LP3988 [TI]
具有电源正常指示和使能功能的 150mA、低压降稳压器;型号: | LP3988 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电源正常指示和使能功能的 150mA、低压降稳压器 稳压器 |
文件: | 总12页 (文件大小:323K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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August 2004
LP3988
Micropower, 150mA Ultra Low-Dropout CMOS Voltage
Regulator With Power Good
n 40dB PSRR at 10kHz
General Description
n ≤1 µA quiescent current when shut down
The LP3988 is a 150mA low dropout regulator designed
n Fast Turn-On time: 100 µs (typ.)
specially to meet requirements of Portable battery-
applications. The LP3988 is designed to work with a space
saving, small 1µF ceramic capacitor. The LP3988 features
an Error Flag output that indicates a faulty output condition.
n 80 mV typ dropout with 150mA load
n −40 to +125˚C junction temperature range for operation
n 1.85V, 2.5V, 2.6V, 2.85V, 3.0V, and 3.3V
The LP3988’s performance is optimized for battery powered
systems to deliver low noise, extremely low dropout voltage
and low quiescent current. Regulator ground current in-
creases only slightly in dropout, further prolonging the bat-
tery life.
Features
n 5 bump thin micro SMD package
n SOT-23-5 package
n Power-good flag output
Power supply rejection is better than 60 dB at low frequen-
cies and starts to roll off at 10 kHz. High power supply
rejection is maintained down to lower input voltage levels
common to battery operated circuits.
n Logic controlled enable
n Stable with ceramic and high quality tantalum capacitors
n Fast turn-on
n Thermal shutdown and short-circuit current limit
The device is ideal for mobile phone and similar battery
powered wireless applications. It provides up to 150 mA,
from a 2.5V to 6V input, consuming less than 1 µA in disable
mode and has fast turn-on time less than 200µs.
Applications
n CDMA cellular handsets
n Wideband CDMA cellular handsets
n GSM cellular handsets
n Portable information appliances
n Tiny 3.3V 5% to 2.85V, 150mA converter
The LP3988 is available 5 pin SOT-23 package and 5 bump
thin micro SMD package. Performance is specified for −40˚C
to +125˚C temperature range and is available in 1.85, 2.5,
2.6, 2.85, 3.0 and 3.3V output voltages.
Key Specifications
n 2.5 to 6.0V input range
n 150mA guaranteed output
Typical Application Circuit
20020502
© 2004 National Semiconductor Corporation
DS200205
www.national.com
Block Diagram
20020501
Pin Descriptions
Name
VEN
micro SMD SOT
Function
A1
B2
C1
C3
A3
3
2
5
1
4
Enable Input Logic, Enable High
Common Ground
GND
VOUT
Output Voltage of the LDO
Input Voltage of the LDO
Power Good Flag (output):
open-drain output, connected to
an external pull-up resistor.
Active low indicates an output
voltage out of tolerance
condition.
VIN
Power Good
Connection Diagrams
SOT-23-5 Package (MF)
5 Bump micro SMD Package (TLA)
20020507
Top View
See NS Package Number MF05A
20020530
Top View
See NS Package Number TLA05
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2
Ordering Information
SOT23-5 Package
LP3988 Supplied as 1000
Units, Tape and Reel
LP3988IMF-2.5
Output
Grade
LP3988 Supplied as 3000
Units, Tape and Reel
LP3988IMFX-2.5
Package Marking
Voltage (V)
2.5
2.6
STD
STD
STD
STD
STD
LFSB
LDJB
LDLB
LFAB
LH5B
LP3988IMF-2.6
LP3988IMFX-2.6
2.85
3.0
LP3988IMF-2.85
LP3988IMF-3.0
LP3988IMFX-2.85
LP3988IMFX-3.0
3.3
LP3988IMF-3.3
LP3988IMFX-3.3
5 Bump Thin Micro SMD Package
Output
Voltage (V)
1.85
Grade
LP3988 Supplied as 250
Units, Tape and Reel
LP3988ITL-1.85
LP3988 Supplied as 3000
Units, Tape and Reel
LP3988ITLX-1.85
STD
STD
STD
2.6
LP3988ITL-2.6
LP3988ITLX-2.6
2.85
LP3988ITL-2.85
LP3988ITLX-2.85
3
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Absolute Maximum Ratings (Notes 1, 2)
ESD Rating (Note 4)
Human Body Model
Machine Model
2kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
SOT23-5 (Note 13)
micro SMD
150V
200V
VIN
−0.3 to 6.5V
−0.3V to (VIN+0.3V),
with 6V max
V
OUT, VEN, PowerGood(applies
only to micro SMD)
Junction Temperature
Storage Temperature
Lead Temp, Pad Temp.
Power Dissipation (Note 3)
SOT23-5
Operating Ratings (Notes 1, 2)
150˚C
V
IN(Note 15)
2.5V to 6V
0 to VIN
−65˚C to +150˚C
235˚C
VOUT, VEN
Junction Temperature
−40˚C to +125˚C
Junction-to-Ambient Thermal
364mW
355mW
Resistance (θJA
)
micro SMD
SOT23-5
220oC/W
255oC/W
micro SMD
Maximum Power Dissipation (Note 5)
SOT23-5
250mW
244mW
micro SMD
Electrical Characteristics
Unless otherwise specified: VEN = 1.8V, VIN = VOUT + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical values and limits
appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40˚C to +125˚C. (Note 6) (Note 7)
Limit
Symbol
Parameter
Output Voltage
Conditions
Typ
Units
Min
−2
Max
2
Tolerance
−20˚C % TJ % 125˚C, SOT23-5
−40˚C % TJ % 125˚C, SOT23-5
−40˚C % TJ % 125˚C, micro SMD
−3
−3.5
-3
3
3.5
3
% of
VOUT(nom)
∆VOUT
Line Regulation Error
−0.15
−0.2
0.15
0.2
0.005
0.007
VIN = VOUT (NOM) + 0.5V to 6.0V
IOUT = 1 mA to 150 mA
%/V
Load Regulation Error
(Note 8)
%/mA
VIN = VOUT(nom) + 1V,
f = 1 kHz,
65
45
IOUT = 50 mA (Figure 3)
VIN = VOUT(nom) + 1V,
f = 10 kHz,
PSRR
Power Supply Rejection Ratio
dB
IOUT = 50 mA (Figure 3)
VEN = 1.4V, IOUT = 0 mA
VEN = 1.4V, IOUT = 0 to 150 mA
VEN = 0.4V
IQ
Quiescent Current
85
140
0.003
1
120
200
1.0
5
µA
Dropout Voltage (Note 9)
IOUT = 1 mA
mV
IOUT = 150 mA
80
115
150
ISC
en
Short Circuit Current Limit
Output Noise Voltage
(Note 10)
600
220
mA
BW = 10 Hz to 100 kHz,
COUT = 1µF
µVrms
Output Capacitor
Capacitance (Note 11)
ESR (Note 11)
1
5
20
µF
mΩ
˚C
COUT
TSD
500
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
160
20
˚C
Enable Control Characteristics (Note 12)
IEN
Maximum Input Current at EN
VEN = 0 and VIN = 6.0V
0.1
µA
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4
Electrical Characteristics (Continued)
Unless otherwise specified: VEN = 1.8V, VIN = VOUT + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical values and limits
appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40˚C to +125˚C. (Note 6) (Note 7)
Limit
Symbol
VIL
Parameter
Conditions
VIN = 2.5V to 6.0V
Typ
Units
Min
1.2
Max
0.5
Logic Low Input threshold
Logic High Input threshold
V
V
VIH
VIN = 2.5V to 6.0V
Power Good
Power Good
% of VOUT (PG ON) Figure 2
% of VOUT (PG OFF) Figure 2 (Note
14)
VTHL
VTHH
VOL
Low threshold
93
95
90
92
95
98
%
High Threshold
PG Output Logic Low Voltage
PG Output Leakage Current
Power Good Turn On time,
(Note 9)
IPULL-UP = 100µA, fault condition
PG Off, VPG = 6V
0.02
0.02
10
0.1
V
IPGL
µA
µs
VIN = 4.2V
TON
Power Good Turn Off time,
(Note 9)
VIN = 4.2V
10
µs
TOFF
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:
PD = (TJ - TA)/θJA
where T is the junction temperature, T is the ambient temperature, and θ is the junction-to-ambient thermal resistance. The 364mW rating appearing under
J
A
JA
Absolute Maximum Ratings for the SOT23-5 package results from substituting the Absolute Maximum junction temperature, 150˚C, for T , 70˚C for T , and 220˚C/W
J
A
for θ . More power can be dissipated safely at ambient temperatures below 70˚C . Less power can be dissipated safely at ambient temperatures above 70˚C. The
JA
Absolute Maximum power dissipation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C. Same
principle applies to the micro SMD package.
Note 4: The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each
pin.
Note 5: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating
appearing under Operating Ratings for the SOT23-5 package results from substituting the maximum junction temperature for operation, 125˚C, for T , 70˚C for T ,
J
A
and 220˚C/W for θ into (Note 3) above. More power can be dissipated at ambient temperatures below 70˚C . Less power can be dissipated at ambient
JA
temperatures above 70˚C. The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW
for each degree above 70˚C. Same principle applies to the micro SMD package.
Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with T = 25˚C or correlated using
J
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
Note 7: The target output voltage, which is labeled V
, is the desired voltage option.
OUT(nom)
Note 8: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 9: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value.
Note 10: Short circuit current is measured on input supply line after pulling down V
to 95% V
.
OUT(nom)
OUT
Note 11: Guaranteed by design. The capacitor tolerance should be 30% or better over the full temperature range. The full range of operating conditions such as
temperature, DC bias and even capacitor case size for the capacitor in the application should be considered during device selection to ensure this minimum
capacitance specification is met. X7R capacitor types are recommended to meet the full device temperature range.
Note 12: Turn-on time is time measured between the enable input just exceeding V and the output voltage just reaching 95% of its nominal value.
IH
Note 13: 100V machine model for Power-good flag, pin 4.
Note 14: The low and high thresholds are generated together. Typically a 2.6% difference is seen between these thresholds.
Note 15: The minimum V is dependant on the device output option.
IN
<
>
= 2.5V, V
For Vout
2.5V, V
will equal 2.5V. For Vout
will equal Vout
+ 200mV.
(NOM)
(NOM)
IN(MIN)
(NOM)
IN(MIN)
5
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20020522
FIGURE 1. Power Good Flag Timing
20020508
FIGURE 2. Line Transient response Input Perturbation
20020509
FIGURE 3. PSRR Input Perturbation
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
= VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VIN
.
Ripple Rejection Ratio (LP3988-2.6)
Ripple Rejection Ratio (LM3988-2.6)
20020510
20020511
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6
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VIN. (Continued)
Power-Good Response Time (LP3988-2.85)
Power-Good Response Time (LP3988-2.85)
(flag pin pulled to VOUT through a 100KΩ resistor)
(flag pin pulled to VIN through a 100KΩ resistor)
20020512
20020513
Power-Good Response Time (LP3988-2.85)
(flag pin pulled to VOUT through a 100KΩ resistor)
Line Transient Response (LP3988-2.85)
20020514
20020515
Line Transient Response (LP3988-2.85)
Power-Up Response
20020516
20020517
7
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VIN. (Continued)
Enable Response
Enable Response
20020518
20020519
Load Transient Response
Load Transient Response
20020520
20020521
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8
CAPACITOR CHARACTERISTICS
Application Hints
The LP3988 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 1µF to 4.7µF range,
ceramic capacitors are the smallest, least expensive and
have the lowest ESR values (which makes them best for
eliminating high frequency noise). The ESR of a typical 1µF
ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which
easily meets the ESR requirement for stability by the
LP3988.
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3988 requires external
capacitors for regulator stability. The LP3988 is specifically
designed for portable applications requiring minimum board
space and smallest components. These capacitors must be
correctly selected for good performance.
INPUT CAPACITOR
The ceramic capacitor’s capacitance can vary with tempera-
ture. Most large value ceramic capacitors () 2.2µF) are
manufactured with Z5U or Y5V temperature characteristics,
which results in the capacitance dropping by more than 50%
as the temperature goes from 25˚C to 85˚C.
An input capacitance of ) 1µF is required between the
LP3988 input pin and ground (the amount of the capacitance
may be increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
A better choice for temperature coefficient in a ceramic
capacitor is X7R, which holds the capacitance within 15%.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
There are no requirements for the ESR on the input capaci-
tor, but tolerance and temperature coefficient must be con-
sidered when selecting the capacitor to ensure the capaci-
tance will be ) 1µF over the entire operating temperature
range.
OUTPUT CAPACITOR
The LP3988 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (dielectric
types Z5U, Y5V or X7R) in 1 to 22 µF range with 5mΩ to
500mΩ ESR range is suitable in the LP3988 application
circuit.
ON/OFF INPUT OPERATION
The LP3988 is turned off by pulling the VEN pin low, and
turned on by pulling it high. If this feature is not used, the VEN
pin should be tied to VIN to keep the regulator output on at all
time. To assure proper operation, the signal source used to
drive the VEN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Elec-
It may also be possible to use tantalum or film capacitors at
the output, but these are not as attractive for reasons of size
and cost (see next section Capacitor Characteristics).
The output capacitor must meet the requirement for mini-
mum amount of capacitance and also have an ESR (Equiva-
lent Series Resistance) value which is within a stable range
(5 mΩ to 500 mΩ).
trical Characteristics section under VIL and VIH
.
FAST ON-TIME
The LP3988 utilizes a speed up circuitry to ramp up the
internal VREF voltage to its final value to achieve a fast
output turn on time.
NO-LOAD STABILITY
The LP3988 will remain stable and in regulation with no
external load. This is specially important in CMOS RAM
keep-alive applications.
9
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Physical Dimensions inches (millimeters)
unless otherwise noted
5-Lead Small Outline Package (MF)
NS Package Number MF05A
Thin micro SMD, 5 bump Package (TLA05)
NS Package Number TLA05AEA
The dimensions for X1, X2 and X3 are as given:
X1 = 1.006mm +/- 0.03mm
X2 = 1.463mm +/- 0.03mm
X3 = 0.6mm +/- 0.075mm
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10
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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