LP3982ILDX-2.82/NOPB

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March 2006

LP3982

Micropower, Ultra Low-Dropout, Low-Noise, 300mA

CMOS Regulator

General Description

Features

n MAX8860 pin, package and spec. compatible

n LLP space saving package

n 300mA guaranteed output current

The LP3982 low-dropout (LDO) CMOS linear regulator is

available in 1.8V, 2.5V, 2.77V, 2.82V, 3.0V, 3.3V, and adjust-

able versions. They deliver 300mA of output current. Pack-

aged in an 8-Pin MSOP, the LP3982 is pin and package

compatible with Maxim’s MAX8860. The LM3982 is also

available in the small footprint LLP package.

@

n 120mV typical dropout 300mA

n 90µA typical quiescent current

n 1nA typical shutdown mode

n 60dB typical PSRR

n 2.5V to 6V input range

n 120µs typical turn-on time

n Stable with small ceramic output capacitors

The LP3982 suits battery powered applications because of

its shutdown mode (1nA typ), low quiescent current (90µA

typ), and LDO voltage (120mV typ). The low dropout voltage

allows for more utilization of a battery’s available energy by

operating closer to its end-of-life voltage. The LP3982’s

PMOS output transistor consumes relatively no drive current

compared to PNP LDO regulators.

n 37µV RMS output voltage noise (10Hz to 100kHz)

n Over temperature/over current protection

n

2% output voltage tolerance

This PMOS regulator is stable with small ceramic capacitive

loads (2.2µF typ).

Applications

These devices also include regulation fault detection, a

bandgap voltage reference, constant current limiting and

thermal overload protection.

n Wireless handsets

n DSP core power

n Battery powered electronics

n Portable information appliances

Application Circuit

20036931

DS200369

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Rating

Human Body Model (Note 6)

Machine Model

2kV

200V

Thermal Resistance (θ_JA

)

V_IN, V_OUT, V_SHDN, V_SET, V_CC

,

8-Pin MSOP

223˚C/W

(Note 3)

V_FAULT

−0.3V to 6.5V

20mA

8-Pin LLP

Fault Sink Current

Power Dissipation

(Note 3)

Operating Ratings(Note 1), (Note 2)

Storage Temperature Range

Junction Temperature (T_J)

Lead Temperature (10 sec.)

−65˚C to 160˚C

150˚C

Temperature Range

−40˚C to 85˚C

Supply Voltage

2.5V to 6.0V

260˚C

Electrical Characteristics

Unless otherwise specified, all limits guaranteed for V_IN= V_O+0.5V (Note 7), V_SHDN= V_IN, C_IN= C_OUT= 2.2µF, C_CC= 33nF,

T_J= 25˚C. Boldface limits apply for the operating temperature extremes: −40˚C and 85˚C.

Symbol

Parameter

Conditions

Min

(Note 5)

2.5

Typ

(Note 4)

Max

(Note 5)

6.0

Units

V_IN

Input Voltage

V

∆V_O

Output Voltage Tolerance

100µA ≤ I_OUT≤ 300mA

V_IN= V_O+0.5V, (Note 7)

SET = OUT for the Adjust

Versions

−2

+2

% of

V_{OUT (NOM)}

−3

+3

6

V_O

I_O

Output Adjust Range

Maximum Output Current

Output Current Limit

Supply Current

Adjust Version Only

Average DC Current Rating

1.25

300

330

V

mA

I_LIMIT

I_Q

770

90

I_OUT= 0mA

270

1

µA

I_OUT= 300mA

225

0.001

0.4

Shutdown Supply Current

Dropout Voltage

V_O= 0V, SHDN = GND

I_OUT= 1mA

V_DO

(Note 7), (Note 8)

I_OUT= 200mA

80

220

0.1

mV

I_OUT= 300mA

120

0.01

∆V_O

Line Regulation

I_OUT= 1mA, (V_O+ 0.5V) ≤ V_I≤ 6V

(Note 7)

−0.1

%/V

Load Regulation

100µA ≤ I_OUT≤ 300mA

I_OUT= 10mA, 10Hz ≤ f ≤ 100kHz

10Hz ≤ f ≤ 100kHz, C_OUT= 10µF

V_IH, (V_O+ 0.5V) ≤ V_I≤ 6V

(Note 7)

0.002

37

%/mA

µV_RMS

nV/

e_n

Output Voltage Noise

Output Voltage Noise Density

SHDN Input Threshold

190

V_SHDN

2

V

V_IL, (V_O+ 0.5V) ≤ V_I≤ 6V

(Note 7)

0.4

I_SHDN

I_SET

SHDN Input Bias Current

SET Input Leakage

SHDN = GND or IN

SET = 1.3V, Adjust Version Only

(Note 9)

0.1

100

2.5

nA

V_FAULT

FAULTDetection Voltage

V_O≥ 2.5V, I_OUT= 200mA

(Note 10)

120

280

mV

FAULT Output Low Voltage

FAULT Off-Leakage Current

Thermal Shutdown

I_SINK= 2mA

0.115

0.1

0.25

V

I_FAULT

T_SD

FAULT = 3.6V, SHDN = 0V

100

nA

160

Temperature

˚C

µs

Thermal Shutdown Hysteresis

Start-Up Time

10

T_ON

C_OUT= 10µF, V_Oat 90% of Final

Value

120

Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its

rated operating conditions.

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2

Electrical Characteristics (Continued)

Note 2: All voltages are with respect to the potential at the ground pin.

Note 3: Maximum Power dissipation for the device is calculated using the following equations:

where T

is the maximum junction temperature, T is the ambient temperature, and θ is the junction-to-ambient thermal resistance. E.g. for the MSOP-8

A JA

J(MAX)

package θ = 223˚C/W, T

= 150˚C and using T = 25˚C, the maximum power dissipation is found to be 561mW. The derating factor (−1/θ ) = −4.5mW/˚C,

JA

J(MAX)

A

J

A

thus below 25˚C the power dissipation figure can be increased by 4.5mW per degree, and similarity decreased by this factor for temperatures above 25˚C. The value

of the θ for the LLP package is specifically dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal

JA

resistance and power dissipation for the LLP package, refer to Application Note AN-1187.

Note 4: Typical Values represent the most likely parametric norm.

Note 5: All limits are guaranteed by testing or statistical analysis.

Note 6: Human body model: 1.5kΩ in series with 100pF.

Note 7: Condition does not apply to input voltages below 2.5V since this is the minimum input operating voltage.

Note 8: Dropout voltage is measured by reducing V until V drops 100mV from its nominal value at V -V = 0.5V. Dropout Voltage does not apply to the 1.8

IN

O

IN

O

version.

Note 9: The SET pin is not externally connected for the fixed versions.

Note 10: The FAULT detection voltage is specified for the input to output voltage differential at which the FAULT pin goes active low.

Functional Block Diagram

20036913

3

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Typical Performance Characteristics Unless otherwise specified, V_IN= V_O+ 0.5V, C_IN= C_OUT

=

2.2µF, C_CC= 33nF, T_J= 25˚C, V_SHDN= V_IN

.

Dropout Voltage vs. Load Current

(For Different Output Voltages)

Dropout Voltage vs. Load Current

(For Different Output Temperatures)

20036903

20036927

FAULT Detect Threshold vs. Load Current

Supply Current vs. Input Voltage

20036928

20036929

Supply Current vs. Load Current

Power Supply Rejection Ratio vs. Frequency

20036930

20036904

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4

Typical Performance Characteristics Unless otherwise specified, V_IN= V_O+ 0.5V, C_IN= C_OUT

=

2.2µF, C_CC= 33nF, T_J= 25˚C, V_SHDN= V_IN. (Continued)

Output Noise Spectral Density

Output Noise (10Hz to 100kHz)

20036906

20036905

Output Impedance vs. Frequency

Line Transient Response

20036908

20036907

Load Transient

Shutdown Response

20036910

20036909

5

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Typical Performance Characteristics Unless otherwise specified, V_IN= V_O+ 0.5V, C_IN= C_OUT

=

2.2µF, C_CC= 33nF, T_J= 25˚C, V_SHDN= V_IN. (Continued)

Power-Up Response

Power-Down Response

20036912

20036911

Application Information

OUTPUT VOLTAGE SETTING (ADJ VERSION ONLY)

The output voltage is set according to the amount of nega-

tive feedback (Note that the pass transistor inverts the feed-

back signal.) Figure 2 simplifies the topology of the LP3982.

This type of regulator can be represented as an op amp

configured as non-inverting amplifier and a fixed DC Voltage

(V_REF) for its input signal. The special characteristic of this

op amp is its extra-large output transistor that only sources

current. In terms of its non-inverting configuration, the output

voltage equals V_REFtimes the closed loop gain:

GENERAL INFORMATION

LP3982 is package, pin and performance compatible with

Maxim’s MAX8860 excluding reverse battery protection and

™

Dual Mode function (fixed and adjustable combined).

Figure 1 shows the functional block diagram for the LP3982.

A 1.25V bandgap reference, an error amplifier and a PMOS

pass transistor perform voltage regulation while being sup-

ported by shutdown, fault, and the usual Temperature and

current protection circuitry

The regulator’s topology is the classic type with negative

feedback from the output to one of the inputs of the error

amplifier. Feedback resistors R₁and R₂are either internal or

external to the IC, depending on whether it is the fixed

voltage version or the adjustable version. The negative feed-

back and high open loop gain of the error amplifier cause the

two inputs of the error amplifier to be virtually equal in

voltage. If the output voltage changes due to load changes,

the error amplifier provides the appropriate drive to the pass

transistor to maintain the error amplifier’s inputs as virtually

equal. In short, the error amplifier keeps the output voltage

constant in order to keep its inputs equal.

Utilize the following equation for adjusting the output to a

particular voltage:

Choose R₂= 100k to optimize accuracy, power supply re-

jection, noise and power consumption.

20036913

FIGURE 1. Functional Block Diagram for the LP3982

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20036916

FIGURE 2. Regulator Topology Simplified

6

Application Information (Continued)

Similarity in the output capabilities exists between op amps

and linear regulators. Just as rail-to-rail output op amps

allow their output voltage to approach the supply voltage,

low dropout regulators (LDOs) allow their output voltage to

operate close to the input voltage. Both achieve this by the

configuration of their output transistors. Standard op amps

and regulator outputs are at the source (or emitter) of the

output transistor. Rail-to-rail op amp and LDO regulator out-

puts are at the drain (or collector) of the output transistor.

This replaces the threshold (or diode drop) limitations on the

output with the less restrictive source-to-drain (or V_SAT) limi-

tations. There is a trade-off, of course. The output imped-

ance become significantly higher, thus providing a critically

lower pole when combined with the capacitive load. That’s

why rail-to-rail op amps are usually poor at driving capacitive

loads and recommend a series output resistor when doing

so. LDOs require the same series resistance except that the

internal resistance of the output capacitor will usually suffice.

Refer to the output capacitance section for more information.

20036917

FIGURE 3. Simplified Model of Regulator

Loop Gain Components

OUTPUT CAPACITANCE

Figure 3 shows a basic model for the linear regulator that

helps describe what happens to the output signal as it is

processed through its feedback loop; that is, describe its

loop gain (LG). The LG includes two main transfer functions:

the error amplifier and the load. The error amplifier provides

voltage gain and a dominant pole, while the load provides a

zero and a pole. The LG of the model in Figure 3 is described

by the following equation:

The LP3982 is specifically designed to employ ceramic out-

put capacitors as low as 2.2µF. Ceramic capacitors below

10µF offer significant cost and space savings, along with

high frequency noise filtering. Higher values and other types

and of capacitor may be used, but their equivalent series

resistance (ESR) should be maintained below 0.5Ω

Ceramic capacitor of the value required by the LP3982 are

available in the following dielectric types: Z5U, Y5V, X5R and

X7R. The Z5U and Y5V types exhibit a 50% or more drop in

capacitance value as their temperature increases from 25˚C,

an important consideration. The X5R generally maintain their

capacitance value within 20%. The X7R type are desirable

for their tighter tolerance of 10% over temperature.

The first term of the above equation expresses the voltage

gain (numerator) and a single pole role-off (denominator) of

the error amplifier. The second term expresses the zero

(numerator) and pole (denominator) of the load in combina-

tion with the R_Oof the regulator.

Ceramic capacitors pose a challenge because of their rela-

tively low ESR. Like most other LDOs, the LP3982 relies on

a zero in the frequency response to compensate against

excessive phase shift in the regulator’s feedback loop. If the

phase shift reaches 360˚ (i.e.; becomes positive), the regu-

lator will oscillate. This compensation usually resides in the

zero generated by the combination of the output capacitor

with its equivalent series resistance (ESR). The zero is

intended to cancel the effects of the pole generated by the

load capacitance (C_L) combined with the parallel combina-

tion of the load resistance (R_L) and the output resistance

(R_O) of the regulator. The challenge posed by low ESR

capacitors is that the zero it generates can be too high in

frequency for the pole that it’s intended to compensate. The

LP3982 overcomes this challenge by internally generating a

strategically placed zero.

Figure 4 shows a Bode plot that represents a case where the

zero contributed by the load is too high to cancel the effect of

the pole contributed by the load and R_O. The solid line

illustrates the loop gain while the dashed line illustrates the

corresponding phase shift. Notice that the phase shift at

unity gain is a total 360˚ -the criteria for oscillation.

7

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POWER DISSIPATION

Application Information (Continued)

Power dissipation refers to the part’s ability to radiate heat

away from the silicon, with packaging being a key factor. A

reasonable analogy is the packaging a human being might

wear, a jacket for example. A jacket keeps a person comfort-

able on a cold day, but not so comfortable on a hot day. It

would be even worse if the person was exerting power

(exercising). This is because the jacket has resistance to

heat flow to the outside ambient air, like the IC package has

a thermal resistance from its junctions to the ambient (θ_JA).

θ

_JAhas a unit of temperature per power and can be used to

calculate the IC’s junction temperature as follows:

T_J= θ_JA(PD) + T_A

T_Jis the junction temperature of the IC. θ_JAis the thermal

resistance from the junction to the ambient air outside the

package. PD is the power exerted by the IC, and T_Ais the

ambient temperature.

PD is calculated as follows:

PD = I_OUT(V_IN-V_O)

20036919

θ_JAfor the LP3982 package (MSOP-8) is 223˚C/W with no

forced air flow, 182˚C/W with 225 linear feet per minute

(LFPM) of air flow, 163˚C/W with 500 LFPM of air flow, and

149˚C/W with 900 LFPM of air flow.

FIGURE 4. Loop Gain Bode Plot Illustrating

Inadequately High Zero for Stability Compensation

θ_JAcan also be decreased (improved) by considering the

layout of the PC board: heavy traces (particularly at V_INand

the two V_OUTpins), large planes, through-holes, etc.

The LP3982 generates an internal zero that makes up for the

inadequately high zero of the low ESR ceramic output ca-

pacitor. This internally generated zero is strategically placed

to provide positive phase shift near unity gain, thus providing

a stable phase margin.

Improvements and absolute measurements of the θ_JAcan

be estimated by utilizing the thermal shutdown circuitry that

is internal to the IC. The thermal shutdown turns off the pass

transistor of the device when its junction temperature

reaches 160˚C (Typical). The pass transistor doesn’t turn on

again until the junction temperature drops about 10˚C (hys-

teresis).

NO-LOAD STABILITY

The LP3982 remains stable during no-load conditions, a

necessary feature for CMOS RAM keep-alive applications.

Using the thermal shutdown circuit to estimate , θ_JAcan be

done as follows: With a low input to output voltage differen-

tial, set the load current to 300mA. Increase the input voltage

until the thermal shutdown begins to cycle on and off. Then

slowly decrease V_IN(100mV increments) until the part stays

on. Record the resulting voltage differential (V_D) and use it in

the following equation:

INPUT CAPACITOR

The LP3982 requires a minimum input capacitance of about

1µF. The value may be increased indefinitely. The type is not

critical to stability. However, instability may occur with bench

set-ups where long supply leads are used, particularly at

near dropout and high current conditions. This is attributed to

the lead inductance coupling to the output through the gate

oxide of the pass transistor; thus, forming a pseudo LCR

network within the Loop-gain. A 10µF tantalum input capaci-

tor remedies this non-situ condition; its larger ESR acts to

dampen the pseudo LCR network. This may only be neces-

sary for some bench setups. 1µF ceramic input capacitor are

fine for most end-use applications.

FAULT DETECTION

If a tantalum input capacitor is intended for the final applica-

tion, it is important to consider their tendency to fail in short

circuit mode, thus potentially damaging the part.

The LP3982 provides a FAULT pin that goes low during out

of regulation conditions like current limit and thermal shut-

down, or when it approaches dropout. The latter monitors

the input-to-output voltage differential and compares it

against a threshold that is slightly above the dropout voltage.

This threshold also tracks the dropout voltage as it varies

with load current. Refer to Fault Detect vs. Load Current

curve in the typical characteristics section.

NOISE BYPASS CAPACITOR

The noise bypass capacitor (CC) significantly reduces output

noise of the LP3982. It connects between pin 6 and ground.

The optimum value for CC is 33nF.

The FAULT pin requires a pull-up resistor since it is an

open-drain output. This resistor should be large in value to

reduce energy drain. A 100kΩ pull-up resistor works well for

most applications.

Pin 6 directly connects to the high impedance output of the

bandgap. The DC leakage of the CC capacitor should be

considered; loading down the reference will reduce the out-

put voltage. NPO and COG ceramic capacitors typically offer

very low leakage. Polypropylene and polycarbonate film car-

bonate capacitor offer even lower leakage currents.

Figure 5 shows the LP3985 with delay added to the FAULT

pin for the reset pin of a microprocessor. The output of the

comparator stays low for a preset amount of time after the

regulator comes out of a fault condition.

CC does not affect the transient response; however, it does

affect turn-on time. The smaller the CC value, the quicker the

turn-on time.

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8

age. The upper threshold (V_UT) is set for 4.6V in order to

exceed the recovery voltage of the battery.

Application Information (Continued)

20036902

FIGURE 6. Minimum Battery Detector that Disconnects

the Load Via the SHDN Pin of the LP3982

Resistor value for V_UTand V_LTare determined as follows:

20036921

FIGURE 5. Power on Delayed Reset Application

The delay time for the application of Figure 5 is set as

follows:

(The application of figure 6 used a G_Tof 5µ mho)

The application is set for a reset delay time of 8.8ms. Note

that the comparator should have high impedance inputs so

as to not load down the V_REFat the CC pin of the LP3982.

SHUTDOWN

The LP3982 goes into sleep mode when the SHDN pin is in

a logic low condition. During this condition, the pass transis-

tor, error amplifier, and bandgap are turned off, reducing the

supply current to 1nA typical. The maximum guaranteed

voltage for a logic low at the SHDN pin is 0.4V. A minimum

guaranteed voltage of 2V at the SHDN pin will turn the

LP3982 back on. The SHDN pin may be directly tied to V_INto

keep the part on. The SHDN pin may exceed V_INbut not the

ABS MAX of 6.5V.

The above procedure assumes a rail-to-rail output compara-

tor. Essentially, R₂is in parallel with R₁prior to reaching the

lower threshold, then R₂becomes parallel with R₃for the

upper threshold. Note that the application requires rail-to-rail

input as well.

Figure 6 shows an application that uses the SHDN pin. It

detects when the battery is too low and disconnects the load

by turning off the regulator. A micropower comparator

(LMC7215) and reference (LM385) are combined with resis-

tors to set the minimum battery voltage. At the minimum

battery voltage, the comparator output goes low and tuns off

the LP3982 and corresponding load. Hysteresis is added to

the minimum battery threshold to prevent the battery’s re-

covery voltage from falsely indicating an above minimum

condition. When the load is disconnected from the battery, it

automatically increases in terminal voltage because of the

reduced IR drop across its internal resistance. The Minimum

battery detector of figure 6 has a low detection threshold

(V_LT) of 3.6V that corresponds to the minimum battery volt-

The resistor values shown in Figure 6 are the closest prac-

tical to calculated values.

FAST START-UP

The LP3982 provides fast start-up time for better system

efficiency. The start-up speed is maintained when using the

optional noise bypass capacitor. An internal 500µA current

source charges the capacitor until it reaches about 90% of its

final value.

9

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Connection Diagrams

8-Pin MSOP

8-Pin LLP Surface Mount

20036933

Top View

20036901

Top View

Note: The SET pin is internally disconnected for the fixed versions.

Ordering Information

Package

Part Number

LP3982IMM-ADJ

LP3982IMMX-ADJ

LP3982IMM-1.8

LP3982IMMX-1.8

LP3982IMM-2.5

LP3982IMMX-2.5

LP3982IMM-2.77

LP3982IMMX-2.77

LP3982IMM-2.82

LP3982IMMX-2.82

LP3982IMM-3.0

LP3982IMMX-3.0

LP3982IMM-3.3

LP3982IMMX-3.3

LP3982ILD-1.8

Package Marking

Transport Media

NSC Drawing

8-Pin MSOP

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

3.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

1k Units Tape and Reel

4.5k Units Tape and Reel

MUA08A

LEVB

LENB

LEPB

LERB

LESB

LETB

LEUB

LNB

8-Pin LLP

LDA08C

LP3982ILDX-1.8

LP3982ILD-2.5

LPB

LP3982ILDX-2.5

LP3982ILD-2.77

LP3982ILDX-2.77

LP3982ILD-2.82

LP3982ILDX-2.82

LP3982ILD-3.0

LRB

LSB

LTB

LP3982ILDX-3.0

LP3982ILD-3.3

LUB

LP3982ILDX-3.3

LP3982ILD-ADJ

LP3982ILDX-ADJ

LVB

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10

Physical Dimensions inches (millimeters) unless otherwise noted

8-Pin MSOP

NS Package Number MUA08A

8-Lead LLP Surface Mount

NS Package Number LDA08C

11

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Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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型号：	LP3982ILDX-2.82/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	2.82 V FIXED POSITIVE LDO REGULATOR, 0.22 V DROPOUT, DSO8 输出元件调节器
文件：	总13页 (文件大小：775K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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