LMZM33604RLXR [TI]
3.5V 至 36V 输入、1V 至 20V 输出、4A 电源模块 | RLX | 41 | -40 to 105;
| 型号： | LMZM33604RLXR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.5V 至 36V 输入、1V 至 20V 输出、4A 电源模块 | RLX | 41 | -40 to 105 开关 输出元件 电源电路 |
| 文件： | 总44页 (文件大小：1843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMZM33604
ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
LMZM33604 3.5V 至 36V 输入、1V 至 20V 输出、4A 电源模块
1 特性
3 说明
•
较小的总体解决方案尺寸：< 250mm2
LMZM33604 电源模块是一款易于使用的集成式电源解
决方案，它在一个低厚度的封装内整合了一个带有功率
MOSFET 的 4A 直流/直流转换器、一个屏蔽式电感器
和多个无源器件。此电源解决方案仅需四个外部组件，
并且省去了设计流程中的环路补偿和电感器元件选择过
程。
1
–
–
所需的外部组件数低至 4 个
16mm × 10mm × 4mm QFN 封装
•
支持 5V、12V、24V、28V 输入电压轨
–
–
1V 至 20V 的输出电压范围
引脚与 6A LMZM33606 兼容
•
•
•
符合 EN55011 辐射发射标准
可配置为负输出电压
该器件采用 16mm × 10mm × 4mm、41 引脚 QFN 封
装，可轻松焊接到印刷电路板上，并可实现紧凑的低厚
度负载点设计。LMZM33604 的全套功能包括电源正常
指示、可调节软启动、跟踪、同步、可编程 UVLO、
预偏置启动、可选自动或 FPWM 模式以及过流和过热
保护。可针对反相应用将 LMZM33604 配置为负输出
电压。
设计灵活性 的 可调节功能
–
–
–
开关频率（350kHz 至 2.2MHz）
可与外部时钟保持同步
可选自动模式或 FPWM 模式
–
–
自动：提升轻负载下的效率
FPWM：在整个负载上具有固定频率
器件信息
–
–
可调软启动和跟踪输入
器件型号
封装
QFN (41)
封装尺寸（标称值）
通过精密使能功能对系统 UVLO 进行编程
LMZM33604
16.00mm × 10.00mm
•
•
保护 功能
–
–
–
断续模式电流限制
空白
过热保护
最小解决方案尺寸
电源正常输出
可在恶劣环境中运行
–
在 85°C 且无气流的情况下具有高达 50W 的输
出功率
–
–
–
工作结温范围：–40°C 至 +125°C
工作环境温度范围：–40°C 至 +105°C
通过了 Mil-STD-883D 冲击和振动测试
2 应用
•
•
•
工业、医疗和测试设备
通用宽输入电压调节
反相输出 应用
空白
典型效率（自动模式）
100
95
90
85
80
75
70
65
60
55
50
简化电路原理图
PGOOD
VIN
VIN
EN
VOUT
VOUT
CIN
LMZM33604
RFBT
SYNC/
MODE
COUT
SS/TRK
RT
VOUT = 5 V
FB
fSW = 500 kHz
AGND
PGND
VIN = 12 V
VIN = 24 V
RFBB
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Current (A)
DFPE
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSB57
LMZM33604
ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics (VIN = 12 V).......................... 9
6.8 Typical Characteristics (VIN = 24 V)........................ 11
6.9 Typical Characteristics (VIN = 36 V)........................ 13
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 26
8
9
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Examples................................................... 30
10.3 Theta JA vs PCB Area.......................................... 31
10.4 Package Specifications......................................... 31
10.5 EMI........................................................................ 32
11 器件和文档支持 ..................................................... 34
11.1 器件支持................................................................ 34
11.2 接收文档更新通知 ................................................. 34
11.3 社区资源................................................................ 34
11.4 商标....................................................................... 34
11.5 静电放电警告......................................................... 34
11.6 Glossary................................................................ 34
12 机械、封装和可订购信息....................................... 35
12.1 Tape and Reel Information ................................... 39
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (October 2018) to Revision A
Page
•
已添加 information on internal LDO and BIAS_SEL............................................................................................................. 22
2
Copyright © 2018–2019, Texas Instruments Incorporated
LMZM33604
www.ti.com.cn
ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
5 Pin Configuration and Functions
RLX Package
41-Pin QFN
Top View
31
30
29
1
2
28
27
SW
SW
VOUT
VOUT
32
34
36
SW
PGND
VOUT
SW
SW
3
26
25
24
VOUT
VOUT
4
5
33
35
37
SW
PGND
VOUT
SW
VOUT
23
SW
6
7
38
39
PGND
VIN
PGND
VIN
DNC
PGND
40
41
22
PGND
VCC
8
9
PGND
AGND
21
BIAS_SEL
PGND
10
11
EN
20
19
SYNC/MODE
12 13 14 15
16
17 18
Copyright © 2018–2019, Texas Instruments Incorporated
3
LMZM33604
ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Analog ground. Zero voltage reference for internal references and logic. These pins are not
connected to one another internal to the device and must be connected to one another externally.
Do not connect these pins to PGND; the AGND to PGND connection is made internal to the device.
See the Layout section of the datasheet for a recommended layout.
AGND
16, 21
G
I
Optional BIAS LDO supply input. An internal 470 nF capacitor is placed between this pin and
PGND. Do not float; tie to PGND if not used. Tie to VOUT if 3.3 V ≤ VOUT ≤ 18 V, or tie to an
external 3.3-V or 5-V rail if available to improve efficiency.
BIAS_SEL
10
Do not connect. This pin is connected to internal circuitry. Do not connect this pin to AGND, PGND,
or any other voltage. This pin must be soldered to an isolated pad..
DNC
EN
7
—
I
Precision enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to VIN.
Precision enable input allows adjustable system UVLO using external resistor divider.
20
Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the
upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the
lower resistor (RFBB) of the feedback divider to AGND.
FB
15
14
I
NC
—
Not internally connected.
Power ground. This is the return current path for the power stage of the device. Connect these pins
to the low side of the input source, load, and bypass capacitors associated with VIN and VOUT
using power ground planes on the PCB. Not all pins are connected to PGND internal to the device;
connections must be made externally. Connect pad 40 and 41 to the ground planes using multiple
vias for good thermal performance.
8, 11, 23, 30,
34, 35, 38,
40, 41
PGND
G
Open drain output for power-good flag. Internal to the device, a 100-kΩ pullup resistor is placed
between this pin and the PGOOD_PU pin.
PGOOD
PGOOD_PU
RT
17
18
12
O
I
Power-good pullup supply. Connect to logic rail or other DC voltage no higher than 20 V.
An external timing resistor connected between this pin and AGND adjusts the switching frequency
of the device. If floating, the default switching frequency is 500 kHz. Do not short to ground.
I
Soft start / tracking control pin. Leave this pin floating to use the 5-ms internal soft-start ramp.To
increase the internal soft start ramp time, simply connect a capacitor between this pin and AGND.
This pin sources 2-μA of current to charge this external capacitor. Connect to external voltage ramp
for tracking. Do not connect to ground.
SS/TRK
SW
13
I
O
I
1, 2, 3, 4, 5,
6, 31, 32, 33
Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not
place any external components on these pins or tie them to a pin of another function.
Synchronization input and Mode setting pin. Do not float; tie to AGND or logic high if not used.
Connect to an external clock to synchronize (see Synchronization (SYNC/MODE)). Connect to
AGND to select Auto mode or connect to logic high to select FPWM mode. (see Mode Select (Auto
or FPWM)).
SYNC/MODE
19
Output of internal bias supply. Used to supply internal control circuits and drivers. Do not place any
external component on this pin or tie it to a pin of another function.
VCC
VIN
9
O
I
22, 39
Input supply voltage. Connect external input capacitors between these pins and PGND.
24, 25, 26,
27, 28, 29,
36, 37
Output voltage. These pins are connected to the output of the internal inductor. Connect these pins
to the output load and connect external bypass capacitors between these pins and PGND.
VOUT
O
4
Copyright © 2018–2019, Texas Instruments Incorporated
LMZM33604
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ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.1
-0.3
MAX
UNIT
V
VIN to PGND
42
EN to AGND
VIN + 0.3
V
FB, RT, SS/TRK to AGND
5
20
V
Input voltage
PGOOD to AGND
V
SYNC/MODE to AGND
BIAS_SEL to AGND
AGND to PGND
5.5
V
-0.3 Lower of (VIN+0.3) and 20
V
-0.3
-0.3
-0.3
-3.5
-0.3
-40
0.3
V
VOUT to PGND
VIN
V
SW to PGND
VIN + 0.3
V
Output voltage
Temperature
SW to PGND (<10 ns transients)
VCC to PGND
42
5
V
V
(2)
Maximum junction temperature, TJ
Storage temperature, Tstg
125
150
240
1
°C
°C
°C
-55
Peak Reflow Case Temperature
Maximum Number of Reflows Allowed
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine,
mounted
Mechanical shock
500
20
G
G
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under the
recommended operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2018–2019, Texas Instruments Incorporated
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ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
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6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
3.5(1)
1
MAX
UNIT
V
Input voltage, VIN
36
Output voltage, VOUT
EN voltage, VEN
20
V
0
VIN
V
PGOOD pullup voltage, VPGOOD
PGOOD sink current
BIAS_SEL
0
18
V
0
5
mA
V
3.3
0
Lower of VIN and 18
Output current, IOUT
4
1200
105
A
Switching frequency, FSW
Operating ambient temperature, TA
Input Capacitance, CIN
Output Capacitance, COUT
350
–40
20(2)
min(3)
kHz
°C
µF
µF
700
(1) For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
(2) A minimum of 20 µF ceramic input capacitance is required for proper operation. An additional 100 µF of bulk capacitance is
recommended for applications with transient load requirements. (see Input Capacitor Selection ).
(3) The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ).
6.4 Thermal Information
LMZM33604
THERMAL METRIC(1)
RLX(B2QFN)
UNIT
41 PINS
13.9
1.2
(2)
RθJA
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C
(3)
Junction-to-top characterization parameter
(4)
ψJB
Junction-to-board characterization parameter
Thermal Shutdown Temperature
6.2
160
TSHDN
Thermal Shutdown Hysteresis
25
°C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75 mm x 75 mm double-sided PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6
Copyright © 2018–2019, Texas Instruments Incorporated
LMZM33604
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ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
6.5 Electrical Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 500 kHz, FPWM mode (unless
otherwise noted); CIN1 = 3x 10 µF, 50-V, 1210 ceramic; CIN2 = 2x 4.7 µF, 50-V, 1210 ceramic; COUT = 6x 22 µF, 25-V, 1210
ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most
likely parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN
)
Input voltage range
VIN turn on
Over IOUT range, VOUT = 2.5 V, fSW = 350 kHz
VIN increasing, VOUT = 2.5 V, IOUT = 0 A
VIN decreasing, VOUT = 2.5 V, IOUT = 0 A
VIN = 12 V, VEN = 0 V, IOUT = 0 A
3.5(1)
36
V
V
VIN
3.12
2.62
0.8
VIN turn off
V
ISHDN
Shutdown supply current
10
µA
INTERNAL LDO (VCC, BIAS_SEL)
PWM operation
PFM operation
3.27
3.1
V
V
VCC
Internal VCC voltage
BIAS_SEL quiescent
current (non-switching)
VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VBIAS_SEL
3.3 V
=
IBIAS_SEL
21
50
µA
FEEDBACK
–40°C ≤ TJ = TA ≤ 125°C, IOUT = 0 A, Over VIN
range, VOUT = 2.5 V, fSW = 350 kHz
Feedback voltage(2)
Load regulation
0.987
1.006
1.017
V
VFB
Over IOUT range, TA = 25 °C
0.1%
0.2
IFB
Feedback leakage current VFB = 1 V
65
4
nA
CURRENT
Output current
Natural convection, TA = 25 °C
0
A
A
IOUT
Overcurrent threshold
9
PERFORMANCE
ƞ
Efficiency
IOUT = 3 A, TA = 25 °C
SS pin open
91%
SOFT START
TSS
Internal soft start time
5
2
ms
µA
VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VSS/TRK
0.5 V
=
ISSC
Soft-start charge current
1.8
2.2
ENABLE (EN)
VEN-H
EN rising threshold
1.14
1.2
-100
1.4
1.25
200
V
VEN-HYS
IEN
EN hysteresis voltage
EN Input leakage current
mV
nA
VIN = 12 V, VFB = 1.5 V, VEN = 2 V
POWER GOOD (PGOOD)
Overvoltage
106%
86%
110%
90%
113%
93%
0.3
PGOOD thresholds
VPGOOD
Undervoltage
PGOOD low voltage
0.5-mA pullup, VEN = 0 V
V
V
Minimum VIN for valid
PGOOD
VINPG
50-μA pullup, VEN = 0 V, TJ = TA = 25°C
1.3
2
(1) For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
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6.6 Switching Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, FPWM mode (unless otherwise noted);
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm, and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY (RT) and SYNCHRONIZATION (SYNC)
Default switching frequency
RT pin = open, IOUT = 0 A
IOUT = 0 A
440
350
500
560
2200
2
kHz
kHz
V
fSW
Switching frequency range
High Threshold
VSYNC
Low Threshold
0.4
V
TS-MIN
Minimum SYNC ON/OFF time
80
ns
8
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LMZM33604
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ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
6.7 Typical Characteristics (VIN = 12 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D011
D012
D016
D013
D014
D015
FPWM Mode
Linear Scale
图 1. Efficiency vs Output Current
Auto Mode
Linear Scale
图 2. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
0
0
0.001
0.01
0.1
1
4
0.001
0.01
0.1
1
4
Output Current (A)
Output Current (A)
FPWM Mode
Log Scale
Auto Mode
Log Scale
图 3. Efficiency vs Output Current
图 4. Efficiency vs Output Current
30
25
20
15
10
5
30
25
20
15
10
5
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
0
0
0
0
1
2
3
4
1
2
3
4
Output Current (A)
Output Current (A)
FPWM Mode
COUT = 4 × 47 µF ceramic
图 5. Voltage Ripple vs Output Current
Auto Mode
COUT = 4 × 47 µF ceramic
图 6. Voltage Ripple vs Output Current
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Typical Characteristics (VIN = 12 V) (接下页)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
2.5
115
105
95
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
2
85
1.5
1
75
65
55
45
0.5
0
Airflow
100LFM
Nat Conv
35
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D017
D020
VOUT = 1.8 V
fSW = 400 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 7. Power Dissipation vs Output Current
图 8. Safe Operating Area
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
45
Airflow
Airflow
200LFM
100LFM
Nat Conv
200LFM
100LFM
Nat Conv
35
35
25
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D019
D018
VOUT = 3.3 V
fSW = 500 kHz
VOUT = 5 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 9. Safe Operating Area
图 10. Safe Operating Area
10
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ZHCSIY5A –OCTOBER 2018–REVISED MAY 2019
6.8 Typical Characteristics (VIN = 24 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D001
D002
D006
D003
D004
D005
FPWM Mode
Linear Scale
Auto Mode
Linear Scale
图 11. Efficiency vs Output Current
图 12. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
0
0
0.001
0.01
0.1
1
4
0.001
0.01
0.1
1
4
Output Current (A)
Output Current (A)
FPWM Mode
Log Scale
Auto Mode
Log Scale
图 13. Efficiency vs Output Current
图 14. Efficiency vs Output Current
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
0
0
0
0
1
2
3
4
1
2
3
4
Output Current (A)
Output Current (A)
FPWM Mode
COUT = 4 × 47 µF ceramic
图 15. Output Voltage Ripple
Auto Mode
COUT = 4 × 47 µF ceramic
图 16. Output Voltage Ripple
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Typical Characteristics (VIN = 24 V) (接下页)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
5
4
3
2
1
0
115
105
95
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D007
D010
VOUT = 3.3 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 17. Power Dissipation
图 18. Safe Operating Area
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
45
Airflow
Airflow
400LFM
200LFM
100LFM
Nat conv
400LFM
200LFM
100LFM
Nat conv
35
35
25
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D009
D008
VOUT = 5 V
fSW = 500 kHz
VOUT = 12 V
fSW = 800 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 19. Safe Operating Area
图 20. Safe Operating Area
12
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6.9 Typical Characteristics (VIN = 36 V)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
0
1
2
3
4
4
4
0
1
2
3
4
4
4
Output Current (A)
Output Current (A)
D025
D026
D030
D027
D028
D029
FPWM Mode
Linear Scale
图 21. Efficiency vs Output Current
Auto Mode
Linear Scale
图 22. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
FPWM Mode
Log Scale
Auto Mode
Log Scale
图 23. Efficiency vs Output Current
图 24. Efficiency vs Output Current
40
40
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
30
20
10
30
20
10
0
0
0
0
1
2
3
1
2
3
Output Current (A)
Output Current (A)
FPWM Mode
COUT = 4 × 47 µF ceramic
图 25. Output Voltage Ripple
Auto Mode
COUT = 4 × 47 µF ceramic
图 26. Output Voltage Ripple
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Typical Characteristics (VIN = 36 V) (接下页)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
6
5
4
3
2
1
0
115
105
95
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D031
D032
VOUT = 5 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 27. Power Dissipation
图 28. Safe Operating Area
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
45
Airflow
Airflow
400LFM
200LFM
100LFM
Nat conv
400LFM
200LFM
100LFM
Nat conv
35
35
25
25
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
D033
D034
VOUT = 12 V
fSW = 800 kHz
VOUT = 20 V
fSW = 1 MHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
图 29. Safe Operating Area
图 30. Safe Operating Area
14
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7 Detailed Description
7.1 Overview
The LMZM33604 is a full-featured 36-V input, 4-A, synchronous step-down converter with controller, MOSFETs,
shielded inductor, and control circuitry integrated into a low-profile, overmolded package. The device integration
enables small designs, while providing the ability to adjust key parameters to meet specific design requirements.
The LMZM33604 provides an output voltage range of 1 V to 20 V. An external resistor divider is used to adjust
the output voltage to the desired value. The switching frequency can also be adjusted, by either an external
resistor or a sync signal, which allows the LMZM33604 to optimize efficiency for a wide variety of input and
output voltage conditions. The device provides accurate voltage regulation over a wide load range by using a
precision internal voltage reference. The EN pin can be pulled low to put the device into standby mode to reduce
input quiescent current. The system undervoltage lockout can be adjusted using a resistor divider on the EN pin.
A power-good signal is provided to indicate when the output is within its nominal voltage range. Thermal
shutdown and current limit features protect the device during an overload condition. A 41-pin, QFN package that
includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Thermal
Shutdown
Precision
Enable
EN
Shutdown
Logic
VCC
OCP
2µA
Soft
Start
LDO
BIAS_SEL
PGND
VIN
SS/TRK
FB
UVLO
+
+
VREF
+
Comp
SW
SYNC/MODE
RT
MODE
Power
Stage
and
Control
Logic
Oscillator
6.8µH
VOUT
PGOOD_PU
100 kO
PGOOD
AGND
PGOOD
Logic
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 15) programs the output voltage of the LMZM33604. The output
voltage adjustment range is from 1 V to 20 V. 图 31 shows the feedback resistor connection for setting the output
voltage. The recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using 公式 1.
表 1 lists the standard external RFBT values for several standard output voltages along with the recommended
switching frequency (FSW) and the frequency setting resistor (RRT) for each of the output voltages listed. (See
Voltage Dropout for the allowable output voltage as a function of input voltage.)
space
(kꢀ)
= 10 x VOUT - VFB
RFBT
( )
where
•
VFB (typical) = 1.006 V
(1)
VOUT
RFBT
FB
RFBB
10 kꢀ
AGND
图 31. Setting the Output Voltage
表 1. Standard Component Values
VOUT (V)
1.2
1.8
2.5
3.3
5
RFBT (kΩ)(1)
1.96
fSW (kHz)
400
RRT (kΩ)
100
7.87
400
100
15.0
400
100
22.6
500
78.7 or open
78.7 or open
78.7 or open
47.5
40.2
500
7.5
12
64.9
500
110
800
15
140
800
47.5
18
169
1000
1000
38.3
20
191
38.3
(1) RFBB = 10 kΩ.
16
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7.3.2 Input Capacitor Selection
The LMZM33604 requires a minimum of 20 µF of ceramic type input capacitance. Use only high-quality ceramic
type X5R or X7R capacitors with sufficient voltage rating. TI recommends an additional 33 µF of non-ceramic
capacitance for applications with transient load requirements. The voltage rating of input capacitors must be
greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends
a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. At worst case, when
operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must
be at least 2 ARMS. 表 2 includes a preferred list of capacitors by vendor.
表 2. Recommended Input Capacitors(1)
CAPACITOR CHARACTERISTICS
(2)
(3)
VENDOR
SERIES
PART NUMBER
CAPACITANCE
(µF)
ESR
WORKING VOLTAGE (V)
(mΩ)
TDK
X5R
X7R
X7R
ZA
C3225X5R1H106K
50
50
63
50
63
10
10
3
Murata
GRM32ER71H106K
GRM32ER71J106K
EEHZA1H101P
2
Murata
10
2
Panasonic
Panasonic
100
56
28
30
ZA
EEHZA1J560P
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values.
(3) Maximum ESR at 100 kHz, 25°C.
7.3.3 Output Capacitor Selection
The minimum amount of required output capacitance for the LMZM33604 varies depending on the output
voltage. 表 3 lists the minimum output capacitance for several output voltage ranges. The required output
capacitance must be comprised of all ceramic capacitors.
When adding additional output capacitance, ceramic capacitors or a combination of ceramic and polymer-type
capacitors can be used. The required capacitance above the minimum is determined by actual transient
deviation requirements. See 表 4 for a preferred list of output capacitors by vendor.
表 3. Minimum Required Output Capacitance
(1)
VOUT RANGE (V)
MINIMUM REQUIRED COUT
CAPACITANCE VALUE
MIN
MAX
1
VOLTAGE RATING
1
400 µF
300 µF
200 µF
150 µF
100 µF
100 µF
50 µF
> 1
1.8
2.5
3.3
5
> 1.8
> 2.5
> 3.3
> 5.0
> 12
≥ 6.3 V
12
20
≥ 16 V
≥ 25 V
(1) The minimum required output capacitance must be made up of ceramic type capacitors. Additional capacitance above the minimum can
be either ceramic or low-ESR polymer type.
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表 4. Recommended Output Capacitors(1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
VOLTAGE (V)
CAPACITANCE (µF)(2)
ESR (mΩ)(3)
TDK
X5R
X5R
C3225X5R1C106K
16
16
16
16
25
25
10
16
25
6.3
6.3
10
16
6.3
6.3
10
10
2
2
2
2
2
2
2
2
2
2
2
2
2
9
12
Murata
TDK
GRM32ER61C106K
C3225X5R1C226M
GRM32ER61C226K
GRM31CC81E226K
GRM32ER71E226M
C3225X5R1A476M
GRM32ER61C476K
GRM31CR61E476M
C3225X5R0J107M
GRM32ER60J107M
GRM32ER61A107M
C1210C107M4PAC7800
6TPF220M9L
X5R
22
Murata
Murata
Murata
TDK
X5R
22
X6S
22
X7R
22
X5R
47
Murata
Murata
TDK
X5R
47
X5R
47
X5R
100
100
100
100
220
220
Murata
Murata
Kemet
Panasonic
Panasonic
X5R
X5R
X5R
POSCAP
POSCAP
6TPE220ML
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values.
(3) Maximum ESR at 100 kHz, 25°C.
7.3.4 Transient Response
表 5 shows the voltage deviation for several transient conditions.
表 5. Output Voltage Transient Response
CIN = 2× 10 µF, 50-V Ceramic, 33 µF, 50-V Polymer Electrolytic
VOUT (V)
COUT
VOLTAGE (1) DEVIATION (mV)
300 µF
500 µF
150 µF
400 µF
100 µF
250 µF
100 µF
200 µF
40
30
1.8
45
3.3
5
40
55
45
175
150
12
(1) 50% load step at 1 A/µs.
18
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7.3.5 Feed-Forward Capacitor
The LMZM33604 is internally compensated to be stable over the operating range of the device. However,
depending on the output voltage and amount of output capacitance, a feed-forward capacitor, CFF, may be added
for optimum performance. The feed-forward capacitor should be placed in parallel with the top resistor divider,
RFBT as shown in 图 32. The value for CFF can be calculated using 公式 2. For output voltages < 1.2 V, CFF is
ineffective and is not recommended.
VOUT x COUT
(pF)
= 4.3 x
CFF
RFBT
where
•
•
COUT is in µF
RFBT is in kΩ
(2)
VOUT
RFBT
CFF
FB
RFBB
10 kꢀ
AGND
图 32. Feed-Forward Capacitor
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7.3.6 Switching Frequency (RT)
The recommended switching frequency range of the LMZM33604 is 350 kHz to 1.2 MHz. 表 6 shows the
allowable output voltage range for several switching frequency settings for three common input voltages. Under
some operating conditions, the device can operate at higher switching frequencies (up to 2.2 MHz), however, this
will reduce efficiency and thermal performance. The switching frequency can easily be set by connecting a
resistor (RRT) between the RT pin and AGND. Additionally, the RT pin can be left floating, and the LMZM33604
operates at 500 kHz default switching frequency. Use 公式 3 to calculate the RRT value for a desired frequency
or simply select from 表 6.
The switching frequency must be selected based on the output voltage setting of the device. See 表 6 for RRT
values and the allowable output voltage range for a given switching frequency at several common input voltages.
For the most efficient solution, always select the lowest allowable frequency.
1
(kO)
=
R
RT
fSW (kHz) × (2.675 × 10-5) t 0.0007
(3)
表 6. Switching Frequency vs Output Voltage
VIN = 5 V (±10%)
VOUT RANGE (V)
VIN = 12 V (±10%)
VOUT RANGE (V)
VIN = 24 V (±10%)
VOUT RANGE (V)
SWITCHING
FREQUENCY (kHz)
RRT RESISTOR (kΩ)
MIN
MAX
MIN
1
MAX
8.2
8.8
9.9
9.9
9.7
9.6
9.3
9.1
8.1
7.7
7.5
7.2
MIN
1
MAX
8.4
350
400
115
100
1
4
1
1
4
1
1
9.9
500
78.7 or open
64.9
4
1
1.1
1.3
1.5
1.7
2.1
2.5
3.2
3.9
4.4
4.8
13.9
15.6
16.9
18
600
1
4
1
700
54.9
1
3.5
3.4
3.4
3.3
2.9
2.7
2.5
2.4
1
800
47.5
1
1
1000
1200
1500
1800
2000
2200
38.3
1
1.1
1.3
1.8
2.1
2.5
2.7
20
31.6
1
19.1
18.1
17.2
16.5
15.9
25.5
1
21.0
1.1
1.2
1.3
19.1
17.4
7.3.7 Synchronization (SYNC/MODE)
The LMZM33604 switching frequency can also be synchronized to an external clock from 350 kHz to 2.2 MHz.
Before the external clock is present, the device switches at the frequency programmed by the RRT resistor.
Select RRT to set the frequency to be the same as the external synchronization frequency. Once the external
clock is present, the device transitions to SYNC mode within 1 ms (typical) and overrides the RT mode. If the
external clock is removed, the device continues to switch at the SYNC frequency for 10 µs (typ) before returning
to the switching frequency set by the RT resistor, resulting in minimal disturbance to the output voltage during the
transitions.
Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns.
When synchronizing to an external clock, the device operation mode is FPWM. If synchronization is not needed,
connect this pin to AGND or logic high to select either Auto mode or FPWM mode. Do not leave this pin open.
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. 表 6 and show the allowable frequencies for a given range of output voltages. For the most
efficient solution, always select the lowest allowable frequency.
20
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7.3.8 Output Enable (EN)
The voltage on the EN pin provides electrical ON/OFF control of the device. Once the EN pin voltage exceeds
the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low quiescent current state.
The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZM33604 is to
connect the EN pin to VIN directly as shown in 图 33. This allows self-start-up of the LMZM33604 when VIN
reaches the turn-on threshold.
If an application requires controlling the EN pin, an external logic signal can be used to drive EN pin as shown in
图 34. Applications using an open drain/collector device to interface with this pin require a pullup resistor to a
voltage above the enable threshold.
VIN
VIN
EN
EN
PGND
PGND
图 33. Enabling the Device
图 34. Typical Enable Control
7.3.9 Programmable System UVLO (EN)
Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be
used for sequencing, to satify a system timing requirement, or to reduce the occurrence of deep discharge of a
battery power source. 图 35 shows how to use a resistor divider to set a system UVLO level. An external logic
output can also be used to drive the EN pin for system sequencing.
VIN
VIN
RENT
EN
RENB
PGND
图 35. System UVLO
表 7 lists recommended resistor values for RENT and RENB to adjust the system UVLO voltage. TI recommends to
set the system UVLO turn-on threshold to approximately 80% to 85% of the minimum expected input voltage.
表 7. Resistor Values for Setting System UVLO
UVLO (V)
RENT (kΩ)
RENB (kΩ)
6.5
100
22.6
10
15
20
25
100
13.7
100
8.66
100
6.34
100
4.99
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7.3.10 Internal LDO and BIAS_SEL
The LMZM33604 integrates an internal LDO, generating a typical VCC voltage (3.27 V) for control circuitry and
MOSFET drivers. The LDO generates VCC voltage from VIN unless a sufficient bias voltage, VBIAS, is applied to
BIAS_SEL pin. The BIAS_SEL input provides an option to supply the LDO with a lower voltage than VIN to
reduce the LDO power loss. The smaller the difference between the input applied to the LDO, VIN_LDO, and the
LDO output voltage, VCC, the more efficiently the device will perform. The amount of current supplied through the
LDO will change based on operating conditions. 图 36 demonstrates the typical LDO current, ILDO, for common
input voltages over the recommended switching frequency range.
30
25
20
15
10
5
36 VIN
24 VIN
12 VIN
0
300
400
500
600
700
800
900
1000 1100 1200 1300
Switching Frequency (kHz)
LMZM
VOUT = 5 V
图 36. LDO Current vs Switching Frequency
The amount of power loss in the LDO can be calculated by 公式 4.
PLOSS_LDO ILDO x (VIN_LDO - VCC
)
=
(4)
For example, when the device is operating at VIN = 24 V, VOUT = 5 V, fsw = 500 kHz, BIAS_SEL = PGND, the ILDO
is typical 11 mA, therefore, the PLOSS_LDO = 11 mA × (24 V – 3.27 V) = 228.03 mW. For the same operating
conditions with BIAS_SEL = 5 V, the power loss is equal to 11 mA × (5 V – 3.27 V) = 19.03 mW. The benefits of
applying a bias voltage to reduce power loss are most notable in applications when VIN » VCC or when the device
is operating at a higher switching frequency. The power savings can be calculated by 公式 5.
x (VIN œ VBIAS_SEL
)
Power Savings ILDO
=
(5)
图 37 and 图 38 show efficiency plots of the LMZM33604 operating with different source voltages applied to the
BIAS_SEL pin. 图 39 demonstrates the power dissipation of the device with various source voltages at
BIAS_SEL pin. The plots include BIAS_SEL tied to a 3.3 V external bias, 5 V external bias, VOUT (5 V) and no
bias voltage applied. The efficiency improvements are more significant when the device is operating at light loads
because the LDO loss is a higher percentage of the total loss.
22
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100
95
90
85
80
75
70
65
60
55
50
45
40
35
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
3.3V External Bias
5.0V External Bias
VOUT Bias (5V)
No Bias
3.3V External Bias
5.0V External Bias
VOUT Bias (5V)
No Bias
30
0
0
1
2
3
4
0.001
0.01
0.1
1
4
Output Current (A)
Output Current (A)
LMZM
LMZM
VIN = 24 V
fSW = 500 kHz
FPWM Mode
VIN = 24 V
fSW = 500 kHz
FPWM Mode
图 37. Efficiency Comparison with BIAS_SEL vs Output
图 38. Efficiency Comparison with BIAS_SEL vs Output
Current
Current
3
No Bias
VOUT Bias (5V)
5.0V External Bias
3.3V External Bias
2
1
0
0
1
2
3
4
Output Current (A)
LMZM
VIN = 24 V
fSW = 500 kHz
FPWM Mode
图 39. Power Dissipation Comparison with BIAS_SEL
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7.3.11 Power Good (PGOOD) and Power Good Pullup (PGOOD_PU)
The LMZM33604 has a built-in power-good signal (PGOOD) that indicates whether the output voltage is within its
regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage
source of 15 V or less. The maximum recommended PGOOD sink current is 5 mA. A typical pullup resistor value
is between 10 kΩ and 100 kΩ.
Once the output voltage rises above 90% (typical) of the set voltage, the PGOOD pin rises to the pullup voltage
level. The PGOOD pin is pulled low when the output voltage drops lower than 90% (typical) or rises higher than
110% (typ) of the nominal set voltage.
Internal to the device, a 100-kΩ pullup resistor is placed between the PGOOD pin and the PGOOD_PU pin.
Applying a pullup voltage directly to the PGOOD_PU pin, eliminates the need for an external pullup resistor.
7.3.12 Mode Select (Auto or FPWM)
The LMZM33604 has configurable Auto mode or FPWM mode options. To select Auto mode, connect the
SYNC/MODE pin (pin 19) to AGND, or a logic signal lower than 0.3 V. To select FPWM mode, connect the
SYNC/MODE pin to a bias voltage or logic signal greater than 0.6 V. When synchronizing to an external clock,
the device inherently operates in FPWM mode.
In Auto mode, the device operates in discontinuous conduction mode (DCM) at light loads. In DCM, the inductor
current stops flowing when it reaches 0 A. Additionally, at very light loads, the switching frequency reduces (PFM
operation) to regulate the required load current, thus improving efficiency by reducing switching losses. At
heavier loads, when the inductor current valley is above 0 A, the device operates in continuous conduction mode
(CCM), where the switching frequency is fixed and set by the RT pin.
In forced PWM (FPWM) mode, the device operates in CCM (at a fixed frequency) regardless of load. In this
mode, inductor current can go negative. At light loads, the efficiency in FPWM mode is lower than in Auto mode,
due to higher conduction losses and higher switching losses. The fact that the switching frequency is fixed over
the entire load range is beneficial in noise sensitive applications.
7.3.13 Soft Start and Voltage Tracking
The soft-start and tracking features control the output voltage ramp during start-up. The soft-start feature reduces
inrush current during start-up and improves system performance and reliability. If the SS/TRK pin is floating, the
LMZM33604 starts up following the fixed, 5-ms internal soft-start ramp. Use CSS to extend soft-start time when
there are a large amount of output capacitors, or the output voltage is high, or the output is heavily loaded during
start-up.
If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to AGND. There is a
2 µA (typical) internal current source, ISSC, to charge the external capacitor. For a desired soft-start time tSS
,
capacitance of CSS can be found by 公式 6.
CSS = ISSC × tSS
where
•
•
•
CSS = soft-start capacitor value (F)
ISSC = soft-start charging current (A)
tSS = desired soft-start time(s)
(6)
LMZM33604 can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the internal
soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise interfering
with the reference voltage. 图 40 shows how to use resistor divider to set VOUT to follow an external ramp.
EXT
RAMP
RTRT
SS/TRK
RTRB
PGND
图 40. Soft-Start Tracking External Ramp
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7.3.14 Voltage Dropout
Voltage dropout is the minimum difference between the input voltage and output voltage that is required to
maintain output voltage regulation while providing the rated output current.
To ensure the LMZM33604 maintains output voltage regulation at the recommended switching frequency, over
the operating temperature range, the following requirements apply:
For output voltages ≤ 5 V, the minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater.
For output voltages > 5 V, the minimum VIN is (1.1 × VOUT).
space
However, if fixed switching frequency operation is not required, the LMZM33604 operates in a frequency
foldback mode when the dropout voltage is less than the recommendations above. Frequency foldback reduces
the switching frequency to allow the output voltage to maintain regulation as input voltage decreases. 图 41
through 图 44 show typical dropout voltage and frequency foldback curves for 5 V and 12 V outputs at TA
=
25°C. (As ambient temperature increases, dropout voltage and frequency foldback occur at higher input
voltages.)
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
600
550
500
450
400
350
300
250
200
150
100
Iout
0.1 A
2.0 A
4.0 A
Iout
0.1 A
2.0 A
4.0 A
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
Input Voltage (V)
Input Voltage (V)
D021
D022
VOUT = 5 V
fSW = 500 kHz
图 41. Voltage Dropout
VOUT = 5 V
fSW = 500 kHz
图 42. Frequency Foldback
12.4
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
1000
900
800
700
600
500
400
300
200
100
0
Iout
Iout
0.1 A
2.0 A
4.0 A
0.1 A
2.0 A
4.0 A
11.0
11.2
11.4
11.6
11.8
Input Voltage (V)
12.0
12.2
12.4
12.6
12.8
13.0
D023
11.8
12.0
12.2
12.4
12.6
Input Voltage (V)
12.8
13.0
13.2
13.4
13.6
D024
VOUT = 12 V
fSW = 800 kHz
图 43. Voltage Dropout
VOUT = 12 V
fSW = 800 kHz
图 44. Frequency Foldback
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7.3.15 Overcurrent Protection (OCP)
The LMZM33604 is protected from overcurrent conditions. Hiccup mode is activated if a fault condition persists to
prevent overheating. In hiccup mode, the regulator is shut down and kept off for 10 ms (typical) before the
LMZM33604 tries to start again. If an overcurrent or short-circuit fault condition still exists, hiccup repeats until
the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions and
prevents overheating and potential damage to the device. Once the fault is removed, the module automatically
recovers and returns to normal operation.
7.3.16 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 135°C
(typical).
7.4 Device Functional Modes
7.4.1 Active Mode
The LMZM33604 is in active mode when VIN is above the turnon threshold and the EN pin voltage is above the
EN high threshold. The simplest way to enable the LMZM33604 is to connect the EN pin to VIN. This allows self
start-up of the LMZM33604 when the input voltage is in the operation range of 3.5 V to 36 V.
7.4.2 Auto Mode
In Auto mode, the LMZM33604 operates in discontinuous conduction mode (DCM) at light loads. In DCM, the
inductor current stops flowing when it reaches 0 A. Additionally, at very light loads, the switching frequency
reduces (PFM operation) to regulate the required load current, thus improving efficiency by reducing switching
losses. At heavier loads, when the inductor current valley is above 0 A, the device operates in continuous
conduction mode (CCM), where the switching frequency is fixed and set by the RT pin.
7.4.3 FPWM Mode
In forced PWM (FPWM) mode, the LMZM33604 operates in CCM (at a fixed frequency) regardless of load. In
this mode, inductor current can go negative. At light loads, the efficiency in FPWM mode is lower than in Auto
mode, due to higher conduction losses and higher switching losses.
7.4.4 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMZM33604. When the EN pin voltage is below the
EN low threshold, the device is in shutdown mode. In shutdown mode the standby current is 0.8 μA typical. If VIN
falls below the turn-off threshold, the output of the regulator is turned off.
26
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZM33604 is a synchronous step-down DC-DC power module. It is used to convert a higher DC voltage to
a lower DC voltage with a maximum output current of 4 A. The following design procedure can be used to select
components for the LMZM33604. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes an iterative design procedure and
accesses comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Application
The LMZM33604 only requires a few external components to convert from a wide input-voltage-supply range to a
wide range of output voltages. 图 45 shows a typical LMZM33604 schematic.
VIN = 24 V
VIN
EN
PGOOD
VOUT
VOUT = 5 V
10 µF
50 V
10 µF
50 V
LMZM33604
40.2 kO
RT
100 pF
SS/TRK
100 µF
6.3 V
100 µF
6.3 V
FB
SYNC/MODE
BIAS_SEL
AGND
10 kO
PGND
图 45. LMZM33604 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8 as the input parameters and follow the design
procedures in Detailed Design Procedure.
表 8. Design Example Parameters
DESIGN PARAMETER
Input voltage VIN
VALUE
24 V typical
5 V
Output voltage VOUT
Output current rating
Operating frequency
4 A
500 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Setpoint
The output voltage of the LMZM33604 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. The value for RFBT can be selected from 表 1 or calculated using the 公式 7:
(kꢀ)
= 10 x VOUT - VFB
RFBT
( )
(7)
For the desired output voltage of 5 V, the formula yields a value of 40 kΩ. Choose the closest available value of
40.2 kΩ for RFBT
.
8.2.2.2 Setting the Switching Frequency
The recommended switching frequency for a 5-V application is 500 kHz. To set the switching frequency to
500 kHz, the RT pin can be left open to operate at the default 500-kHz switching frequency.
8.2.2.3 Input Capacitors
The LMZM33604 requires a minimum input capacitance of 20-µF ceramic type. High-quality ceramic type X5R or
X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input capacitors must be
greater than the maximum input voltage.
For this design, 2x 10-µF, 50-V ceramic capacitors are selected.
8.2.2.4 Output Capacitor Selection
The LMZM33604 requires a minimum amount of output capacitance for proper operation. The minimum amount
of required output varies depending on the output voltage. See 表 3 for the required output capacitance.
For this design example, 2 × 100-µF, 6.3-V ceramic capacitors are used.
8.2.2.5 Feed-Forward Capacitor (CFF)
For typical applications, an external feed-forward capacitor, CFF is not required. Applications requiring optimum
transient performance can benefit from placing a CFF capacitor in parallel with the top resistor divider, RFBT. The
value for CFF can be calculated using 公式 2. The recommended CFF value for 5-V application is 100 pF.
8.2.2.6 Application Curves
VIN = 24 V
VOUT = 5 V
IOUT = 4 A
VIN = 24 V
VOUT = 5 V
IOUT = 1 A to 3 A
Slew rate: 1 A/µs
COUT = 200 µF
图 46. Start-up Waveforms
图 47. Transient Response
28
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9 Power Supply Recommendations
The LMZM33604 is designed to operate from an input voltage supply range between 3.5 V and 36 V. This input
supply must be able to withstand maximum input current and maintain a stable voltage. The resistance of the
input supply rail must be low enough that an input current transient does not cause a high enough drop at the
LMZM33604 supply voltage that can cause a turn-off and system reset.
If the input supply is located more than a few inches from the LMZM33604 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 100-µF
electrolytic capacitor.
10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 48 thru 图 51,
shows a typical PCB layout. Some considerations for an optimized layout are:
•
Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
•
•
•
•
•
•
•
Connect all PGND pins together using copper plane or thick copper traces.
Connect the SW pins together using a small copper island under the device for thermal relief.
Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
Locate additional output capacitors between the ceramic capacitor and the load.
Keep AGND and PGND separate from one another. AGND and PGND are connected internal to the device.
Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
Use multiple vias to connect the power planes to internal layers.
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10.2 Layout Examples
图 48. Typical Top-Layer Layout
图 49. Typical Layer-2 Layout
图 50. Typical Layer 3 Layout
图 51. Typical Bottom-Layer Layout
30
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10.3 Theta JA vs PCB Area
The amount of PCB copper effects the thermal performance of the device. 图 52 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the LMZM33604. The junction-to-ambient thermal
resistance is plotted for a 4-layer PCB and a 6-layer PCB with PCB area from 16 cm2 to 100 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in the Typical Characteristics section.
2. Calculate the maximum θJA using 公式 8 and the maximum ambient temperature of the application.
(125˘C œ TA(max)
)
ꢀJA
=
(˘C/W)
PD(max)
(8)
3. Reference 图 52 to determine the minimum required PCB area for the application conditions.
20
4-layer PCB
6-layer PCB
18
16
14
12
10
15
30
45
60
75
90
105
PCB Area (cm²)
D027
图 52. θJA vs PCB Area
10.4 Package Specifications
表 9. Package Specifications Table
LMZM33604
VALUE
UNIT
Weight
2.0
grams
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
85.5
MHrs
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10.5 EMI
The LMZM33604 is compliant with EN55011 radiated emissions. 图 53, 图 54, and 图 55 show typical examples
of radiated emissions plots for the LMZM33604. The graphs include the plots of the antenna in the horizontal and
vertical positions.
10.5.1 EMI Plots
EMI plots were measured using the standard LMZM33604EVM with no input filter.
图 53. Radiated Emissions 12-V Input, 1.2-V Output, 4-A Load
图 54. Radiated Emissions 12-V Input, 3.3-V Output, 4-A Load
32
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EMI (接下页)
图 55. Radiated Emissions 24-V Input, 5-V Output, 4-A Load
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11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
34
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
P1
K0
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
LMZM33604RLXR
B2QFN
RLX
41
500
330.0
32.4
10.45
16.45
4.4
16.0
32.0
Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
RLX 41
SPQ
500
Length (mm) Width (mm)
383.0 353.0
Height (mm)
LMZM33604RLXR
B2QFN
58.0
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39
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMZM33604RLXR
ACTIVE
B3QFN
RLX
41
500
RoHS Exempt
& Green
NIPDAU
Level-3-240C-168 HR
-40 to 105
LMZM33604
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OUTLINE
RLX0041A
B3QFN - 4.1 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
A
10.15
9.85
B
PIN 1
INDEX AREA
16.15
15.85
0.08 C
C
4.1 MAX
SEATING PLANE
0.05
0.00
2X 6.4
2X 3.55
2X 0.335
16X 0.8
(0.27) TYP
2X 1.92 0.05
2X 1.75 0.05
11
19
(0.23) TYP
4X 1.17 0.05
2X 1.1 0.05
41
40
2.32
4X 1
2X 1 0.05
39
2.2
2X 1.2
2.79
38
37
1.6
PKG
2X 13.6
33
2.4
3.2
35
34
6X 1.44 0.05
36
32
28
1
26X 0.8
PIN 1 ID
31
0.6
27X
0.45
0.35
0.1
52X
0.4
6X 1 0.05
2X 2.4
C A B
0.05
PKG
4223882/A 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RLX0041A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
METAL UNDER
SOLDER MASK
4X (1.4)
SOLDER MASK
OPENING
4X (0.43)
31
4X (7.96)
(7.85)
1
28
4X (1.17)
6X (6.5)
3X (5.6)
32
34
36
26X (0.8)
6X (5.5)
6X (4.5)
6X (3.5)
6X (2.5)
3X (2.4)
37
33
35
6X (1.44)
6X (1.5)
2X (1.2)
6X (1)
6X (0.5)
0.000 PKG
2X (1.1)
(0.27) TYP
3X (0.5)
3X (1.5)
4X (0.825)
(1.2)
(1.6)
38
2X (1)
(2)
40
4X (2.375)
3X (2.5)
(2.79)
4X (1)
3X (3.45)
(3.8)
3X (4.15)
3X (3.5)
39
3X (4.5)
41
2X (1.92)
(5.11)
3X (5.5)
2X (1.75)
11
52X (0.4)
4X (7.185)
19
27X (0.7)
(7.85)
(
0.2) TYP
VIA
16X (0.8)
0.05 MIN
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 8X
4223882/A 10/2017
NOTES: (continued)
4. This package designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RLX0041A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.4)
4X (0.43)
4X (1.06)
(0.27) TYP
31
(7.85)
28
1
32
34
36
26X (0.8)
(5.6)
SOLDER MASK
OPENING
TYP
37
33
35
6X (1.3)
(2.4)
METAL UNDER
SOLDER MASK
TYP
6X
(0.95)
0.000 PKG
2X (1.04)
2X (1.2)
38
(1.6)
40
(2.79)
(5.11)
4X (1)
39
(3.8)
41
2X 0.95
1.72
2X (1.56)
11
27X (0.7)
19
(7.85)
52X (0.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
PADS 1,11,19,28,38 & 39: 90%; PADS 32-37: 86%; PADS 40 & 41: 80%
SCALE: 8X
4223882/A 10/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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