LMZM23601SILR_技术文档

LMZM23601

ZHCSHO5C –DECEMBER 2017 –REVISED MARCH 2023

采用3.8mm × 3mm 封装的LMZM23601 36V、1A 降压直流/直流电源模块

1 特性

3 说明

• 4V 至36V 宽工作输入电压范围

• 1.2V 至15V 可调输出电压和3.3V 或5V 固定输出

电压选项

LMZM23601 集成电感器电源模块专为空间受限型工业

应用而设计。该器件提供 5V 和 3.3V 两种固定输出电

压以及支持 1.2V 至 15V 范围的可调 (ADJ) 输出电压

选项。LMZM23601 具有4V 至36V 的输入电压范围，

可提供高达 1000mA 的输出电流。该电源模块使用起

来极其简单，只需 2 个外部组件即可实现 5V 或 3.3V

输出设计。LMZM23601 的所有方面均针对空间受限的

性能驱动型、低 EMI 工业应用进行了优化。漏极开路

电源正常输出提供了系统状态的真实指示，无需使用附

加监控组件，从而节省了成本和布板空间。PWM 和

PFM 模式之间的无缝转换以及仅 28µA 的无负载电源

电流可确保实现整个负载电流范围的高效率和出色的瞬

态响应。为了方便进行输出电流调节，LMZM23601 与

支持 500mA 输出电流的 LMZM23600 之间实现了引脚

对引脚兼容。

• 1A 输出电流

• 5V 和3.3V 输出设计仅需要输入和输出电容器

• 27mm²解决方案尺寸，使用单面布局

• 28µA 无负载电源电流

• 2µA 关断电流

• 电源正常状态标志

• 外部频率同步

• 模式选择引脚

– 强制PWM 模式可实现恒定频率操作

– 在轻负载条件下可实现高效率的自动PFM 模式

• 内置控制环路补偿、软启动、电流限制和UVLO

• 微型3.8mm × 3mm × 1.6mm 封装

• 使用LMZM23601 并借助WEBENCH^®Power

Designer 创建定制设计方案

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

LMZM23601

SIL（MicroSiP^™

10）

，

2 应用

3.80mm × 3.00mm

• 传感器变送器

• 测试和测量

• 电网基础设施

• 空间受限型应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

GND

DC-DC Module

GND

MODE/

SYNC

C_IN

C_OUT

V_IN

VIN

EN

FB

24V 至5V、1A 直流/直流转换器单面布局解决方案尺

寸

VOUT

V_OUT

PGOOD

C_OUT

GND

24V 至5V、1A 直流/直流转换器的固定输出选项原理

图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAQ4

LMZM23601

ZHCSHO5C –DECEMBER 2017 –REVISED MARCH 2023

www.ti.com.cn

Table of Contents

8 Application and Implementation..................................22

8.1 Application Information............................................. 22

8.2 Typical Applications.................................................. 22

8.3 Best Design Practices...............................................34

8.4 Power Supply Recommendations.............................34

8.5 Layout....................................................................... 35

9 Device and Documentation Support............................38

9.1 Device Support......................................................... 38

9.2 Documentation Support............................................ 38

9.3 接收文档更新通知..................................................... 38

9.4 支持资源....................................................................38

9.5 Trademarks...............................................................39

9.6 静电放电警告............................................................ 39

9.7 术语表....................................................................... 39

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 System Characteristics............................................... 9

6.7 Typical Characteristics..............................................10

7 Detailed Description......................................................16

7.1 Overview...................................................................16

7.2 Functional Block Diagram.........................................16

7.3 Feature Description...................................................16

7.4 Device Functional Modes..........................................21

Information.................................................................... 39

10.1 Tape and Reel Information......................................40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (May 2019) to Revision C (March 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 更新的商标信息.................................................................................................................................................. 1

• Changed the VIN to GND MAX from 42 to 40.................................................................................................... 5

• Updated the Functional Block Diagram ........................................................................................................... 16

Changes from Revision A (April 2018) to Revision B (May 2019)

Page

• 将最小可调输出范围从2.5V 更改为 1.2V...........................................................................................................1

• Added Maximum input voltage vs output voltage graph for V_OUT< 2.5 V, Power dissipation and Output

current vs ambient temperature graphs for 1.2-V and 1.8-V outputs................................................................10

• Added information on maximum input voltage for V_OUT< 2.5 V ......................................................................23

• Added output capacitance requirements for 1.2-V and 1.8-V outputs .............................................................24

• Added guidance on feedback resistor values for lower output voltages ..........................................................25

• Added typical application curves for 1.2-V and 1.8-V outputs ......................................................................... 27

Changes from Revision * (December 2017) to Revision A (April 2018)

Page

• 首次发布生产数据数据表；添加WEBENCH 链接..............................................................................................1

English Data Sheet: SNVSAQ4

2

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Device Comparison

表5-1. LMZM23601 Device Options

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY ⁽¹⁾

LMZM23601SILR

LMZM23601V3SILR

LMZM23601V5SILR

LMZM23601SILT

Adjustable

3.3 V

3000

250

5 V

Adjustable

3.3 V

LMZM23601V3SILT

LMZM23601V5SILT

250

5 V

250

(1) See Package Option Addendum for tape and reel details as well as links used to order parts.

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English Data Sheet: SNVSAQ4

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5 Pin Configuration and Functions

GND

MODE/SYNC

VIN

1

2

3

4

5

10

9

DNC

FB

Thermal

Pad

8

EN

7

PGOOD

6

VOUT

Not to scale

图5-1. SIL 10-Pin MicroSiP^™Package Top View

表5-1. Pin Functions

DESCRIPTION

TYPE

NO.

NAME

1

GND

G

Ground for all circuitry. Reference point for all voltages.

This pin is a multifunction mode control input which is tolerant of voltages up to the input voltage.

With this input tied LOW, the device is in Auto PFM mode with automatic transition between PFM and

PWM with diode emulation at light load. TI recommends this mode when the application requires

high efficiency at light load.

MODE/

SYNC

With this input tied HIGH, the device is in forced PWM mode. The device switches at the internal

clock frequency. TI recommends this mode when the application requires constant switching

frequency across the entire load current.

2

I

With a valid synchronization signal at this pin, the device switches in forced PWM mode at the

external clock frequency and synchronized with it at the rising edge of the clock.

Do not float this pin.

Input supply to the regulator. Connect a high-quality bypass capacitors directly to this pin and the

GND pin (pin 1).

3

4

5

VIN

EN

P

I

Enable input to the regulator. HIGH = ON, LOW = OFF. This pin can be connected to VIN. Do not

float.

Open-drain, power-good output. Connect to a suitable voltage supply through a current limiting

resistor. HIGH = power is good, LOW = fault. This output terminal is LOW when EN is LOW.

PGOOD

O

Output voltage terminal. This pin is internally connected to one terminal of the integrated inductor.

Connect an output filter capacitor from VOUT to GND and place the capacitor as close as possible to

the VOUT pin.

6

7

VOUT

FB

O

I

Feedback input to the regulator.

If using the fixed 3.3-V or 5-V options of the device, connect this pin to the positive end of the output

filter capacitor (the VOUT node).

If using the adjustable output option of the device connect this to the feedback voltage divider and

keep this node as small as possible on the board layout.

8

DNC

—

O

G

Do not connect. Leave floating. This pin provides access to the internal VCC voltage of the device.

Do not connect. Leave floating. This pin provides access to the internal BOOT voltage for the high

side MOSFET driver.

9

10

Do not connect. Leave floating. This pin provides access to the internal SW voltage of the device.

This terminal is internally connected to GND and provides a wide thermal connection from the IC to

the PCB. Connect to electrical ground plane for adequate heat sinking.

Thermal Pad

G = Ground, I = Input, O = Output, P = Power

English Data Sheet: SNVSAQ4

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

MAX

40

UNIT

V

VIN to GND

SW to GND

V_IN+ 0.3

3.6

V

BOOT to SW

V

EN to GND

42

V

VOUT to GND

16

V

FB to GND (3.3-V and 5-V options)

FB to GND (ADJ option)

PGOOD to GND

16

V

–0.3

5.5

V

16

V

PGOOD sink current

MODE/SYNC to GND

VCC to GND

8

mA

V

42

–0.3

-0.3

3.6

V

Operating junction temperature, T_J

Storage temperature, T_stg

125

150

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4

NOM

MAX

36

UNIT

V_IN

Input voltage

V

Output voltage (5 V)

Output voltage (3.3 V)

Output voltage (ADJ)

Output current (1 A)

Operating junction temperature

0

5

V_OUT

0

3.3

15

V

1.2

0

V

I_OUT

T_J

1

A

125

°C

–40

6.4 Thermal Information

LMZM2360x

SIL (μSIP)

10 PINS

45

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-top characterization parameter

°C/W

3

Ψ_JT

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LMZM2360x

SIL (μSIP)

10 PINS

20

THERMAL METRIC⁽¹⁾

UNIT

Junction-to-board characterization parameter

°C/W

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FEEDBACK

V_FB

Initial output voltage accuracy

(3.3-V and 5-V fixed output)

V_IN= 4 V to 36 V, open loop

FB = 1 V

1.5%

1.015

–1.5%

V_FB

Reference voltage (ADJ option)

0.985

1

V

Input current from FB to GND

(ADJ option)

I_FB

20

nA

CURRENT

V_IN= 12 V, V_FB= +10%, V_OUT= 5 V

7

µA

V_IN= 12 V, V_FB= +10%, V_OUT= 5 V, T_J=

85°C

16

18

V_IN= 12 V, V_FB= +10%, V_OUT= 5 V, T_J=

125°C

Operating quiescent current;

measured at VIN pin

I_Q

V_IN= 24 V, V_FB= +10%, V_OUT= 5 V

12

V_IN= 24 V, V_FB= +10%, V_OUT= 5 V, T_J=

85°C

24

26

80

V_IN= 24 V, V_FB= +10%, V_OUT= 5 V, T_J=

125°C

V_IN= 24 V, V_FB= +10%, V_OUT= 5 V,

Mode = 0 V

I_B

Bias current into the VOUT pin

48

µA

EN = 0 V, V_IN= 12 V, T_J= 25°C

EN = 0 V, V_IN= 12 V, T_J= 85°C

EN = 0 V, V_IN= 24 V, T_J= 25°C

EN = 0 V, V_IN= 24 V, T_J= 85°C

1.8

3

Shutdown quiescent current;

measured at VIN pin

I_SD

5

10

UNDERVOLTAGE LOCKOUT (UVLO)

V_{IN_UVLO}

Minimum input voltage to operate Rising

UVLO hysteresis

3.1

0.2

3.5

3.85

0.3

V

V_{IN_UVLO_HYST}

0.25

English Data Sheet: SNVSAQ4

6

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6.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER GOOD FLAG (PGOOD)

V_{PGOOD_OV}

V_{PGOOD_UV}

PGOOD upper threshold voltage Rising, % of Vout

PGOOD lower threshold voltage Falling, % of Vout

103.5% 106.7%

109%

97%

92%

94.7%

Magnitude of PGOOD lower

V_{PGOOD_GUARD}threshold difference from steady

state output voltage.

Steady state output voltage PGOOD

threshold read at the same T_Jand V_IN

4%

PGOOD hysteresis as a percent

V_{PGOOD_HYST}

1.4%

1.0

of output voltage set point

Minimum input voltage for proper 50-µA pullup to PGOOD pin, EN = 0 V, T_J

V_{PGOOD_VALID}

t_{RESET_FILTER}

1.5

V

PGOOD function

= 25°C

Glitch filter time constant for

PGOOD function

190

µs

50-µA pullup to PGOOD pin, V_IN= 1.5 V,

EN = 0 V

0.4

110

Low-level PGOOD function output 0.5-mA pullup to PGOOD pin, V_IN= 12 V,

V_OL

V

voltage

EN = 0 V

1-mA pullup to PGOOD pin, V_IN= 12 V,

EN = 3.3 V

RDSON of the PGOOD output

pull down

R_{PGOOD_RDSON}

50

Ω

SWITCHING FREQUENCY

V_IN= 24 V, 5-V and 3.3-V fixed output

options

675

890

750

1000

750

825

V_IN= 24 V, ADJ output options

1090

f_SW

Switching frequency

kHz

V_IN= 36 V, 5-V and 3.3-V fixed output

options

V_IN= 36 V, ADJ output options

800

FREQUENCY SYNCHRONIZATION AND MODE

5-V and 3.3-V fixed output options V_OUT

V_DROPOUT< V_IN< 36 V

+

500

825

f_SYNC

Sync frequency range

ADJ output options V_OUT+ V_DROPOUT

V_IN< 28 V

<

700

25%

1.5

1100

75%

D_SYNC

Sync input duty cycle range

2.3 V < HIGH state input < 5.5 V

MODE/SYNC input logic HIGH

voltage to enter FPWM mode

V_{MODE_HIGH}

V

MODE/SYNC input logic LOW

voltage to enter AUTO PFM mode

V_{MODE_LOW}

0.4

V_IN= 12 V, V_MODE/SYNC= 3.3 V

V_IN= 12 V, V_MODE/SYNC= 12V

V_IN= 12 V, V_OUT= 5 V, I_OUT= 20 mA

1

5

I_MODE

MODE/SYNC leakage current

µA

µs

MODE transition time to FPWM

300

t_MODE

MODE transition time to AUTO

PFM

V_IN= 12 V, V_OUT= 5 V, I_OUT= 20 mA

300

CURRENT LIMIT PROTECTION

I_L-HS

I_L-LS

I_L-ZC

high-side switch current limit

Duty cycle approaches 0%

MODE/SYNC = logic LOW

1.45

1

1.81

1.2

2.2

A

low-side switch current limit

Zero-cross current limit

1.43

–0.01

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6.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low-side reverse current limit

I_L-NEG

(positive current ino the SW pin to MODE/SYNC = logic HIGH

GND)

0.5

0.8

A

POWER STAGE CHARACTERISTICS

HS R_DS-ON

LS R_DS-ON

t_ON-MIN

High-side MOSFET on-resistance

220

200

50

mΩ

ns

Low-side MOSFET on-resistance

Minimum high-side on-time

Minimum high-side off-time

I_OUT= 500 mA

80

t_OFF-MIN

I_OUT= 500 mA, ADJ

5-V and 3.3-V fixed output options

ADJ option

62

100

ns

93%

91%

97%

10

D_MAX

Maximum switch duty cycle

While in frequency foldback

L

Integrated inductor - inductance

Integrated inductor - DCR

µH

L_DCR

390

mΩ

ENABLE

V_EN

Enable input threshold voltage

Enable input threshold hysteresis

Enable input wake-up threshold

Enable pin input current

Rising

1.7

0.42

0.4

1.92

0.52

V

V_{EN_HYST}

V_{EN_WAKE}

I_EN

V

V_IN= V_EN= 12 V

2.7

µA

VCC REGULATOR

V_IN= 12 V, V_OUT< 3.3 V

3.05

3.15

2.73

V_CC

Internal V_CCvoltage

V

V_IN= 12 V, V_OUT≥3.3V

V_{CC_UVLO}

Internal V_CCvoltage input UVLO V_INrising

2.23

150

3.25

240

V

Internal V_CCvoltage input UVLO

hysteresis

V_{CC_UVLO_HYST}

Hysteresis below VCC_UVLO

mV

SOFT START

t_SS

Soft-start time

Time for V_REFto ramp from 0% to 90%

1.8

3.5

4

5.5

ms

t_{EN_LV}

t_EN

Turnon delay with low V_IN

Turnon delay

V_IN< 4.2 V

V_IN= 12 V

0.7

Short circuit wait time (hiccup

time)

t_W

8.0

ms

THERMAL PROTECTION

T_SD

Thermal shutdown

Thermal shutdown hysteresis

Rising threshold

155

15

°C

T_{SD_HYST}

English Data Sheet: SNVSAQ4

8

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6.6 System Characteristics

The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 125°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 0 A,

fixed output option, EN connected

to V_IN

25

32

24

28

V_IN=12 V, V_OUT= 5 V, I_OUT= 0 A,

fixed output option, EN connected

to V_IN

Input current to the DC-DC converter

while in regulation

I_Q-VIN

µA

V_IN=24 V, V_OUT= 3.3 V, I_OUT= 0 A,

fixed output option, EN connected

to V_IN

V_IN= 24 V, V_OUT= 5 V, I_OUT= 0 A,

fixed output option, EN connected

to V_IN

EFFICIENCY

Efficiency

Typical efficiency 12-V input

Typical efficiency 24-V input

V_IN=12 V, V_OUT= 5 V, I_OUT= 1 A

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 1 A

V_IN= 24 V, V_OUT= 5 V, I_OUT= 1 A

V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 1 A

V_IN= 24 V, V_OUT= 12 V, I_OUT= 1 A

87%

81%

85%

79%

92%

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6.7 Typical Characteristics

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

30

28

26

24

22

20

18

16

14

12

10

70

65

60

55

50

45

40

35

30

25

20

15

10

VOUT = 3.3 V

VOUT = 5.0 V

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

Output Voltage (V)

2

2.1 2.2 2.3 2.4

0

4

8

12

16 20

Input Voltage (V)

24

28

32

36

D099

D041

图6-1. Maximum Input Voltage for V_OUT< 2.5V

Fixed output voltage options

Output voltage in regulation

EN = VIN

Load = Open

图6-2. Input Supply Current

3.5

3.4

3.3

3.2

3.1

3

5.1

5

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4

2.9

2.8

2.7

2.6

2.5

IOUT = 1.0 A

IOUT = 0.75 A

IOUT = 0.5 A

IOUT = 0.25 A

IOUT = 1.0 A

IOUT = 0.75 A

IOUT = 0.5 A

IOUT = 0.25 A

3.9

3.8

3.7

3.3

3.5

3.7

3.9

4.1

4.3

Input Voltage (V)

4.5

4.7

4.9

4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5

Input Voltage (V)

D033

D035

V_OUT= 3.3 V

图6-3. Dropout Voltage

V_OUT= 5 V

图6-4. Dropout Voltage

12.2

12

15.2

15

11.8

11.6

11.4

11.2

11

14.8

14.6

14.4

14.2

14

10.8

10.6

10.4

10.2

10

13.8

13.6

13.4

13.2

13

IOUT = 1.0 A

IOUT = 0.75 A

IOUT = 0.5 A

IOUT = 0.25 A

IOUT = 1.0 A

IOUT = 0.75 A

IOUT = 0.5 A

IOUT = 0.25 A

11

11.4

11.8

12.2 12.6

Input Voltage (V)

13

13.4

13.8

14

14.4

14.8

15.2 15.6

Input Voltage (V)

16

16.4

16.8

D037

D039

V_OUT= 12 V

图6-5. Dropout Voltage

V_OUT= 15 V

图6-6. Dropout Voltage

English Data Sheet: SNVSAQ4

10

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6.7 Typical Characteristics (continued)

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

50

40

30

20

10

0

50

40

30

20

10

0

CISPR11 Class A Limit

CISPR11 Class B Limit

Evaluation Board

CISPR11 Class A Limit

CISPR11 Class B Limit

Evaluation Board

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D042

D044

V_IN= 24 V

_OUT= 5 V

I_OUT= 1 A

V_IN= 24 V

I_OUT= 1 A

V_OUT= 5 V

Default EVM Layout with added 3 × 100pF 0603 C_IN

Default EVM BOM with GND Plane as Top Layer

图6-7. Radiated EMI

图6-8. Radiated EMI

75

1.5

VIN = 18 V PFM

VIN = 18 V FPWM

VIN = 22 V PFM

VIN = 22 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

1.4

1.3

1.2

1.1

1

70

65

60

55

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2-Layer

4-Layer

50

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

5

10

15

20

25

30

35

40

Board Area (cm²)

D020

D032

V_OUT= 15 V

图6-9. Package Thermal Resistance vs Board Copper Area, No

Air Flow

图6-10. Power Dissipation

1.5

1.4

1.3

1.2

1.1

1

VIN = 15 V PFM

VIN = 15 V FPWM

VIN = 18 V PFM

VIN = 18 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

VIN = 6.5 V PFM

VIN = 6.5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D018

D014

V_OUT= 12 V

V_OUT= 5 V

图6-11. Power Dissipation

图6-12. Power Dissipation

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6.7 Typical Characteristics (continued)

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

1.5

1.4

1.3

1.2

1.1

1

1.5

1.4

1.3

1.2

1.1

1

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D016

D012

V_OUT= 3.3 V

V_OUT= 2.5 V

图6-13. Power Dissipation

图6-14. Power Dissipation

1.5

1.4

1.3

1.2

1.1

1

1.5

1.4

1.3

1.2

1.1

1

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 15 V PFM

VIN = 15 V FPWM

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D094

D092

V_OUT= 1.8 V

V_OUT= 1.2 V

图6-15. Power Dissipation

图6-16. Power Dissipation

1.1

1

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 5 V

VIN = 12 V

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

D085

D086

V_OUT= 1.2 V

R_θ= 58°C/W

V_OUT= 1.8V

R_θ= 58°C/W

图6-17. Ambient Temperature vs Output Current

图6-18. Ambient Temperature vs Output Current

English Data Sheet: SNVSAQ4

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6.7 Typical Characteristics (continued)

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

1.1

1

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VIN = 5 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 5 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

D022

D026

D030

D024

V_OUT= 2.5 V

R_θ= 58°C/W

V_OUT= 3.3 V

R_θ= 58°C/W

图6-19. Ambient Temperature vs Output Current

图6-20. Ambient Temperature vs Output Current

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 18 V

VIN = 24 V

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

30

40

50

60

Ambient Temperature (degrees C)

70

80

90 100 110 120 130

D028

V_OUT= 5 V

R_θ= 58°C/W

V_OUT= 12 V

R_θ= 58°C/W

图6-21. Ambient Temperature vs Output Current

图6-22. Ambient Temperature vs Output Current

1.1

1100

1000

900

800

700

600

500

400

300

200

100

0

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VIN = 5V

VIN = 12V

VIN = 24 V

VIN = 18 V

VIN = 24 V

VIN = 36 V

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

30

40

50

60

70

Ambient Temperature (degrees C)

80

90 100 110 120 130

D045

V_OUT= 2.5 V

V_OUT= 15 V

R_θ= 58°C/W

图6-24. Auto PFM Mode Switching Frequency vs Output

图6-23. Ambient Temperature vs Output Current

Current

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6.7 Typical Characteristics (continued)

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

1100

1000

900

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

VIN = 5V

VIN = 12V

VIN = 24 V

VIN = 5V

VIN = 12V

VIN = 24 V

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D047

D057

V_OUT= 3.3 V Adjustable Option

V_OUT= 3.3 V Fixed Option

图6-25. Auto PFM Mode Switching Frequency vs Output

图6-26. Auto PFM Mode Switching Frequency vs Output

Current

1100

1000

900

800

700

600

500

400

300

200

900

800

700

600

500

400

300

200

VIN = 12V

VIN = 24V

VIN = 12V

VIN = 24V

100

0

100

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D049

D059

V_OUT= 5 V Adjustable Option

V_OUT= 5 V Fixed Option

图6-27. Auto PFM Mode Switching Frequency vs Output

图6-28. Auto PFM Mode Switching Frequency vs Output

Current

1100

1000

900

800

700

600

500

400

300

200

1100

1000

900

800

700

600

500

400

300

200

100

VIN = 24V

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D053

D051

V_OUT= 15 V

V_OUT= 12 V

图6-30. Auto PFM Mode Switching Frequency vs Output

图6-29. Auto PFM Mode Switching Frequency vs Output

Current

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6.7 Typical Characteristics (continued)

V_IN= 24 V, T_A= 25°C (unless otherwise noted). Refer to default evaluation board layout and bill of materials.

1100

1000

900

800

700

600

500

400

300

200

100

0

1100

1000

900

800

700

600

500

400

300

200

100

0

VOUT = 2.5V

VOUT = 3.3V

VOUT = 5.0V

VOUT = 12V

VOUT = 15V

VOUT = 5.0 V FIXED

VOUT = 3.3V FIXED

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36

Input Voltage (V)

0

5

10

15

20

25

Input Voltage (V)

30

35

40

D055

D061

图6-31. Switching Frequency vs Input Voltage for Adjustable

图6-32. Switching Frequency vs Input Voltage for Fixed Output

Output Options at Full Load

Options at Full Load

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7 Detailed Description

7.1 Overview

The LMZM23601 is a 4-V to 36-V wide-input voltage range, low quiescent current, high-performance DC/DC

module designed specifically for space-constrained industrial applications. The device is available in an

adjustable output voltage option with 1.2-V to 15-V output range, as well as fixed 5-V and 3.3-V output options.

The high level of integration and innovative packaging technology utilized in this power module makes it possible

to design a 5-V or a 3.3-V 1-A DC/DC converter with only an input capacitor and an output capacitor in just 27

mm² of available board space.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Control Scheme

The LMZM23601 power module utilizes peak-current-mode-control architecture. This enables the use of wide

range of input voltages while maintaining constant switching frequency and good input and output transient

response. The device can be used with 5-V, 12-V, or 24-V typical industrial input voltage rail. The short minimum

on- and off-times ensure constant frequency regulation over a wide range of input to output voltage conversion

ratios. The adjustable (ADJ) output voltage option operates at 1000-kHz switching frequency. The minimum on-

and off- times allow for a duty factor window of 5% to 91% at 1000-kHz switching frequency. If the input voltage

exceeds approximately 28 V on the ADJ version, the frequency is smoothly reduced from 1000 kHz as a function

of input voltage. The switching frequency reduction allows output voltage regulation and the current mode

control to operate with a duty factor below 5%. The fixed 5-V and 3.3-V output options operate at 750 kHz

nominal switching frequency and the frequency foldback at high input voltage is not active or needed.

English Data Sheet: SNVSAQ4

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The control architecture also uses frequency foldback at low input voltage to achieve low dropout voltage,

maintaining output regulation as the input voltage falls close to output voltage. The frequency foldback at low

input voltage is active for the ADJ as well as the 5-V and 3.3-V output options. The reduction in frequency is

smooth and continuous and is activated as the off-time approaches the minimum value. Under these conditions,

the LMZM23601 device operates much like a constant off-time converter allowing the maximum duty cycle to

reach 97%. This feature allows output voltage regulation with very low dropout.

The LMZM23601 features exceptional conversion efficiency at light load. As the load current is reduced, the

LMZM23601 transitions to light-load mode if the MODE/SYNC terminal is pulled low. In light-load mode the

device uses diode emulation to reduce the RMS inductor current and the switching frequency is reduced. The

fixed voltage versions (3.3-V and 5-V) do not need an external voltage divider connected to FB, which results in

saving two components and lower standby current when the load is in standby. As a result, the consumed supply

current is only 24 µA (typical) with 24-V to 3.3-V conversion and 28 µA (typical) with 24-V to 5-V conversion,

while the output is regulated with no load.

7.3.2 Soft-Start Function

The LMZM23601 features an internally programmed soft-start time. The soft-start time is fixed internally at about

4 ms and is achieved by ramping the internal reference. The device starts up properly even if there is a voltage

present on output before the activation of the LMZM23601. In such cases, there is no switching until the output

voltage value programmed by the ramping reference voltage is above the pre-biased output value. After the

prebiased voltage level is reached by the reference ramp, the switching starts, and the output ramps up

smoothly from the pre-biased value up to the final output voltage.

7.3.3 Enable and External UVLO Function

Some applications can require a precision enable or custom input voltage lockout (UVLO) functionality. Setting

up external UVLO based on the application needs prevents the converter from trying to regulate the output

voltage until after the input voltage has reached a desired minimum level. Such function can be used to lower

the current demand from the input supply as the supply is still starting up.

The LMZM23601 features a precision enable (EN) input terminal. The EN input logic has two internal thresholds.

The first rising threshold is at 0.9V typical. Its purpose is to wake up the internal VCC regulator to bias the

internal circuitry. The EN rising threshold to start switching is 1.8V (typical) with 0.5V (typical) hysteresis. A

voltage divider from VIN to EN can be used to set the VIN voltage at which the regulator starts the voltage

conversion. The EN terminal is rated for up to the input voltage and can be connected directly to VIN for an

always-on operation. Pulling the EN pin below 0.4 V puts the LMZM23601 in shutdown mode. In shutdown mode

and 12-V input voltage the LMZM23601 only consumes 1.8 µA (typical) of input current.

7.3.4 Current Limit

The LMZM23601 devices features two current limits inside the IC. A coarse high side or peak current limit is

provided to protect against faults. The high-side current limit limits the duration of the on-period of the high-side

power MOSFET during a given clock cycle. A precision cycle-by-cycle valley current limit prevents excessive

average output current. A new switching cycle is not initiated until the inductor current drops below the valley

current limit.

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Vout

Peak

Valley

图7-1. Current Limit Operation During Output Short Circuit

图 7-1 shows the response of the LMZM23601 device to a short circuit on the output: The peak current limit

prevents excessive peak current while the valley current limit prevents excessive average inductor current. After

a small number of cycles, hiccup mode is activated.

7.3.5 Hiccup Mode

To prevent excessive heating and power consumption under sustained output short-circuit conditions, a hiccup

mode operation is included in the control logic. If an over current condition is maintained on the output, the

LMZM23601 device shuts off both power MOSFETs and waits for a hiccup interval, t_W, of approximately 8 ms.

After the wait period, the device restarts operation beginning with a soft-start time interval.

Vout

图7-2. Hiccup Operation

图 7-2 shows hiccup mode operation: The LMZM23601 attempts to restart periodically, following a hiccup wait

interval. If the fault at the output is still present, another hiccup wait interval is initiated, followed by another

restart attempt. This sequence continues until the output short circuit is removed. When the output short circuit is

removed, the output ramps up during the next restart sequence.

7.3.6 Power Good (PGOOD) Function

The LMZM23601 has a built-in power-good signal presented at the PGOOD terminal. This signal indicates

whether the output voltage is within the regulation window. The PGOOD terminal is an open-drain output that

requires a pullup resistor to a nominal voltage source of 15 V or less. The absolute maximum PGOOD sink

current is 8 mA. Typically, TI recommends a pullup resistor value between 10 kΩ and 100 kΩ. Refer to

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Electrical Characteristics for the power-good thresholds and hysteresis for undervoltage and overvoltage

detection.

7.3.7 MODE/SYNC Function

7.3.7.1 Forced PWM Mode

When constant frequency operation is more important than light load efficiency, the MODE/SYNC input of the

LMZM23601 device must be pulled high or a valid synchronization input must be provided. This activates forced-

PWM-mode operation. After activated, this feature ensures that the switching frequency stays constant across

the entire load current range, while operating between the minimum and maximum duty cycle limits. The diode

emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. The

switching frequency in forced PWM mode is only reduced when the input voltage-to-output voltage ratio results

in minimum on-time limitation (ADJ version only) or minimum off-time limitation near dropout.

This feature can be activated and deactivated while the part is regulating without removing the load. This feature

activates and deactivates gradually, preventing perturbation of output voltage. When in FPWM mode, a limited

reverse current is allowed through the inductor allowing power to pass from the regulators output to its input.

7.3.7.2 Auto PFM Mode

If the MODE/SYNC terminal is held low the LMZM23601 device enables automatic power-saving-mode transition

at light load. With high load the LMZM23601 regulates the output using normal PWM operation. When the load is

light, the control logic smoothly transitions to PFM operation and diode emulation. In this mode, the high side

MOSFET is turned on for one or more pulses to provide energy to the load. The on-time of the high side in this

mode depends on the input voltage level and a pre-programmed internal I_PEAK-MINcurrent level. The higher the

input voltage is, the shorter the on-time is. At this point, there is a longer off-time during which the output is still in

the regulation window because the load is light, and the output is not getting discharged as quickly. The duration

of the off-time depends on the load current level. Lighter load results in longer off-time. This mode of operation

results in excellent conversion efficiency at very light load. When auto-PFM mode is used, the output voltage at

no load is approximately 1% higher than FPWM operation.

7.3.7.3 Dropout Mode

When the input voltage level decreases and approaches the output voltage level, the buck regulator reaches its

maximum duty cycle or minimum off-time requirement for each switching cycle. At this point the output is no

longer regulated and follows the input voltage minus the voltage drops from V_INto V_OUT

.

To maximize the input voltage range for which the output is still regulated, the LMZM23601 features frequency

foldback at low input voltage. This operation extends the switching period and, for a given fixed minimum off-

time, it prolongs the maximum duty cycle of the regulator. As a result, the output voltage can still be well

regulated even as the input voltage level is very close to the output voltage. This feature can be useful for

battery applications (maximizing the useful battery range) or in applications where large input voltage variations

can be expected.

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7.3.7.4 SYNC Operation

Synchronizing the switching frequency of multiple regulators in a single system is often desirable. This technique

results in better defined EMI behavior and can reduce the need for capacitance on some power rails. The

LMZM23601 MODE/SYNC input allows synchronization to an external clock. The LMZM23601 implements an

in-phase locking scheme – the rising edge of the clock signal provided to the input of the LMZM23601 device

corresponds to turning on the high-side MOSFET device. This function is implemented using phase locking over

a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into

the LMZM23601 device replaces the internal free-running clock but does not affect frequency foldback operation.

The foldback function takes over and the output voltage continues to be well regulated using frequency reduction

when duty factors outside of the normal duty cycle range are reached. When the device is synchronized to the

lower end of the synchronization range the internal inductor sees higher peak currents. For high current ripple

designs (for example, high input voltage and 12-V and 15-V output designs), the maximum current capability of

the device can be derated.

The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.

The MODE/SYNC function logic always prioritizes the proper regulation of the output voltage. 表7-1 summarizes

the MODE/SYNC function and the operating switching frequency with various conditions. See 节 6.7 for

frequency foldback vs input voltage behavior.

表7-1. Switching Frequency and MODE/SYNC Function

SWITCHING FREQUENCY

DEVICE

MODE/SYNC

LIGHT LOAD

FULL LOAD

VIN > 28 V

IN DROPOUT MODE

Reduced

(save power)

Fixed

1000 kHz

Reduced

(maintain regulation)

Reduced

(maintain regulation)

Logic LOW = Auto PFM

Fixed

1000 kHz

Fixed

1000 kHz

Reduced

(maintain regulation)

Reduced

(maintain regulation)

ADJ Output

Logic HIGH = FPWM

Valid F_SYNCInput

Reduced

(maintain regulation)

Reduced

(maintain regulation)

F_SYNC

Reduced

(save power)

Fixed

750 kHz

Fixed

750 kHz

Reduced

(maintain regulation)

Logic LOW = Auto PFM

Logic HIGH = FPWM

Valid F_SYNCInput

Fixed

3.3-V Output

or 5-V

Fixed

750 kHz

Fixed

750 kHz

Fixed

750 kHz

Reduced

(maintain regulation)

Output

Reduced

(maintain regulation)

F_SYNC

7.3.8 Thermal Protection

The LMZM23601 monitors its junction temperature (T_J) and shuts off if the it gets too hot. The thermal shutdown

threshold for the junction is typically 155°C. Both, high-side and low-side power MOSFETs are turned off until the

junction temperature has decreased under the hysteresis level, typically 15°C below the shutdown temperature.

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7.4 Device Functional Modes

7.4.1 Shutdown

The LMZM23601 device shuts down most internal circuitry and high-side and low-side power MOSFETs under

any of the following conditions:

1. EN is low

2. VIN is below the falling UVLO threshold

3. Junction temperature exceeds T_SDthreshold

The PGOOD flag remains operational with input voltage as low as 1.5 V.

7.4.2 FPWM Operation

If MODE/SYNC is above the V_MODE/SYNChigh threshold or a valid synchronizing is applied to MODE/SYNC,

constant frequency operation is maintained across load. The ADJ option of the device folds back the frequency

when V_INexceeds 28 V typical so that the output voltage can be properly regulated. See 表 7-1 for all use cases

and options. FPWM mode requires negative current be allowed in the inductor if the load is light. If a large

negative load is present, operation is halted by a reverse current limit, I_L-NEG

.

7.4.3 Auto PFM Mode Operation

If MODE/SYNC is below the V_MODE/SYNClow threshold, reverse current in the inductor is not allowed. This

feature is called diode emulation. While the load is heavy, the regulator uses PWM mode to control the output. If

the load is light, the control logic transitions to PFM mode. The switching frequency is reduced, resulting in

excellent energy savings while regulation is maintained. Because the frequency is reduced and switching pulses

can come in groups, the output voltage ripple can increase slightly. Under this condition, the output ripple can be

reduced by increasing the output capacitance.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The LMZM23601 device is a step-down power module, typically used to efficiently convert a high DC input

voltage to a lower DC output voltage with a maximum output current of up to 1 A. The following sections

describe a simple design procedure for creating a DC/DC converter design with these modules.

8.2 Typical Applications

The LMZM23601 module requires very few external components for a complete DC/DC converter design. If the

output voltage for the application is 3.3 V or 5 V, the fixed output voltage option of the LMZM23601 device can

be used. In such cases, the design is as simple as adding only an input and an output capacitor. The adjustable

output voltage version of the device allows the user to set the output voltage between 1.2 V and 15 V with the

addition of two feedback resistors to the bill of materials.

GND

MODE/

SYNC

C_IN

V_IN

VIN

EN

FB

VOUT

V_OUT

PGOOD

C_OUT

GND

图8-1. Fixed 5-V or 3.3-V Typical Application Circuit

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GND

MODE/

SYNC

C_IN

V_IN

VIN

EN

R_FBT

R_FBB

FB

VOUT

V_OUT

PGOOD

C_OUT

GND

图8-2. Adjustable 1.2-V to 15-V Output Typical Application Circuit

8.2.1 Design Requirements

8.2.1.1 Maximum Input Voltage for V_OUT< 2.5 V

For designs requiring V_OUTless than 2.5 V the maximum input voltage is limited by the switching frequency and

the minimum on-time. See 图8-3.

30

28

26

24

22

20

18

16

14

12

10

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

Output Voltage (V)

2

2.1 2.2 2.3 2.4

D099

图8-3. Maximum Input Voltage for V_OUT< 2.5 V

For this design example, use the parameters listed in 表8-1 as the input parameters.

表8-1. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

VALUE

8 V to 36 V

5 V

COMMENT

This range covers a typical 12-V or 24-V industrial supply

Fixed or adjustable output voltage can be used

Output current range

No load to 1 A

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZM23601device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

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2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Input Capacitor Selection

The input capacitor selection and placement on the board layout is very important for any buck converter design.

This component provides the pulsing high di/dt current every switching cycle and reduces the input voltage ripple

seen by the buck converter. Use a good-quality 10-µF, 1210 (3225) case size, X5R or X7R ceramic capacitor

with sufficient voltage rating on the input of the device. Alternatively, in applications with strict size constraints

and more stable input voltage it is possible to use a 10-µF, 1206 (3216) case size or a parallel combination of 2 ×

4.7-µF, 0805 (2012), X5R or X7R capacitors. Ceramic capacitors have a DC bias dependence on their effective

capacitance and can de-rate their value significantly when used at higher bias voltage. TI recommends ceramic

capacitors with ≥ 50-V rating when using the device with a 24-V input supply. TI recommends ceramic

capacitors with ≥25-V rating when using the device with a 12-V input supply.

Just like with any buck converter, place the input capacitor as close as possible and next to the LMZM23601.

Connect the capacitor directly to the VIN (pin 3) and GND (pin 1) terminals of the device. This placement

ensures that the area of the high di/dt current loop in the buck converter is kept to a minimum, resulting in the

lowest possible inductance in the switching current path. The proper placement of the input capacitor in any

buck converter helps to keep the output noise of the converter to a minimum. See 表 8-2 for several input

capacitor choices.

表8-2. Input Capacitor Selection

VOLTAGE

RATING

VALUE

CASE SIZE

DIELECTRIC

QUANTITY

VENDOR

PART NUMBER

10 µF

4.7 µF

50 V

1210 (3225)

1206 (3216)

0805 (2012)

X7R

X5R

1

2

TDK

MuRata

TDK

C3225X7R1H106M250AC

GRJ32ER71H106KE11

C3216X5R1H106K160AB

C2012X5R1H475K125AB

50 V

TDK

For this design example a single 10-µF, 50-V 1210 X7R capacitor is used.

8.2.2.3 Output Capacitor Selection

TI recommends low-ESR ceramic capacitors for output capacitors. There is a requirement for minimum

capacitance on the output of the LMZM23601 to ensure stable operation. The minimum output capacitance

requirement depends on the output voltage setting. There is also a maximum capacitance value for stability and

to limit the in-rush supply current. Excessive output capacitance can result in excessive current to be drawn from

the input supply during startup. If the overcurrent condition is persistent during start-up, the over current

protection of the LMZM23601 can activate and affect the normal output voltage ramp up. In extreme cases, the

节7.3.5 operation can be activated during start-up if the maximum output capacitance is exceeded.

Refer to 表 8-3 for the minimum, recommended, and maximum output capacitance values for each output

voltage. For this example with a 5-V output a 22-µF capacitor can be used.

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表8-3. Output Capacitor

MINIMUM

OUTPUT CAPACITANCE

RECOMMENDED

OUTPUT CAPACITANCE

MAXIMUM

OUTPUT CAPACITANCE

OUTPUT VOLTAGE

1.2 V

1.8 V

2.5 V

3.3 V

5 V

82 µF

68 µF

47 µF

22 µF

15 µF

10 µF

100 µF

82 µF

68 µF

33 µF

22 µF

15 µF

470 µF

390 µF

330 µF

220 µF

200 µF

12 V

15 V

8.2.2.4 Feedback Voltage Divider for Adjustable Output Voltage Versions

GND

MODE/

SYNC

C_IN

V_IN

VIN

EN

R_FBT

R_FBB

FB

VOUT

V_OUT

PGOOD

C_OUT

GND

图8-4. Adjustable 1.2-V to 15-V Output Typical Application Circuit

The adjustable version of the LMZM23601 regulates the output voltage such that the FB node voltage is equal to

the internal V_REFvoltage of 1 V. The output voltage is then set by a feedback voltage divider formed by two

external resistors, R_FBTand R_FBB

.

R_FBB+ R_FBT

V_OUT= V_REF

ì

R_FBB

(1)

The range of adjustable output voltage is 1.2 V to 15 V.

Choose a value for R_FBTin the kΩrange, and calculate the bottom resistor R_FBBusing 方程式2:

R_FBT

R_FBB

=

V_OUT

V_REF

- 1

(2)

For V_OUT< 3.0 V, TI recommends to allow 20 µA of static load current on the output. This can be achieved by

limiting the maximum resistance of the feedback divider. For example, for V_OUT= 2 V, the maximum total

feedback resistance (R_FBB+ R_FBT) must be 100 kΩor less.

For this design example the output voltage is set to 5 V. The fixed 5-V output voltage option of the LMZM23601

can be used without any feedback resistors. If the adjustable output option is used for this design condition, the

top feedback resistor R_FBTcan be set to 102 kΩ. The R_FBBvalue results in 25.5 kΩ.

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8.2.2.5 R_PU- PGOOD Pullup Resistor

The PGOOD terminal of the LMZM23601 is an open-drain output. If the application requires a power-good flag,

use a 100-kΩ pullup resistor from the PGOOD terminal to an external voltage rail. If a power-good function is

not necessary, the PGOOD terminal can be left floating.

8.2.2.6 V_INDivider and Enable

If the application requires custom input UVLO level higher than the internal UVLO, a voltage divider can be

connected from V_INto the EN terminal to set the turnon threshold.

V_IN

R_ENT

EN

R_ENB

GND

图8-5. Enable Divider to Set External UVLO Threshold

Choose the top resistor R_ENBbetween 10 kΩand 50 kΩand calculate the R_ENTaccording to 方程式3.

≈

’

V_START

∆

÷

R_ENT

=

-1 ìR_ENB

÷

◊

V_EN

«

V_{EN_HYST}

≈

’

÷

◊

∆

V_STOP= V_STARTì 1-

∆

V_EN

«

(3)

where

• V_STARTis the rising input voltage level at which switching starts. Choose this value based on the application

requirements.

• V_STOPis the input voltage at which switching stops

• V_ENis the rising threshold on EN; see Electrical Characteristics

• V_{EN_HYST}is the hysteresis on the EN threshold; see Electrical Characteristics

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8.2.3 Application Curves

Unless otherwise stated, the following conditions apply: V_IN= 24 V, T_A= 25°C.

8.2.3.1 V_OUT= 5 V

100

90

80

70

60

50

40

30

20

10

I_OUT

(500 mA/DIV)

VIN = 6.5V PFM

VIN = 6.5V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

V_OUT

(50 mV/DIV)

Time (500 µs/DIV)

0

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

D002

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

5-V Adjustable Output

10% to 100% Load Step

MODE = High

图8-6. Efficiency

图8-7. Load Transient

V_OUTRipple

(20 mV/DIV)

(5 mV/DIV)

20MHz BW

250MHz BW

Time (1 µs/DIV)

5-V Adjustable Output

I_OUT= 1 A

5-V Adjustable Output

I_OUT= 1 A

图8-8. Output Ripple 20 MHz BW

图8-9. Output Ripple 250-MHz BW

5.1

5.075

5.05

5.025

5

EN

(2 V/DIV)

V_OUT

(2 V/DIV)

4.975

4.95

4.925

4.9

VIN = 5 V PFM

I_OUT

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

(500 mA/DIV)

PGOOD

4.875

4.85

4.825

(2 V/DIV)

Time (2 ms/DIV)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D008

图8-11. Start-up With 24-V Input

图8-10. Line and Load Regulation

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8.2.3.2 V_OUT= 3.3 V

100

90

80

70

60

50

I_OUT

(500 mA/DIV)

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

40

30

20

10

V_OUT

(50 mV/DIV)

Time (500 µs/DIV)

0

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

D003

3.3-V Adjustable Output

10% to 100% Load Step

MODE = High

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

3.3-V Adjustable Output

图8-13. Load Transient

图8-12. Efficiency

V_OUTRipple

(20 mV/DIV)

(5 mV/DIV)

250MHz BW

20MHz BW

Time (1 µs/DIV)

20MHz BW

Time (1 µs/DIV)

3.3-V Adjustable Output

I_OUT= 1 A

3.3-V Adjustable Output

I_OUT= 1 A

图8-14. Output Ripple 20-MHz BW

图8-15. Output Ripple 250 MHz BW

3.38

3.36

3.34

3.32

3.3

EN

(2 V/DIV)

V_OUT

(2 V/DIV)

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

3.28

3.26

3.24

3.22

3.2

I_OUT

(500 mA/DIV)

PGOOD

(2 V/DIV)

Time (2 ms/DIV)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D009

3.3-V Adjustable Output

Toggle Enable

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

3.3-V Adjustable Output

图8-17. Start-up With 24-V Input

图8-16. Line and Load Regulation

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8.2.3.3 V_OUT= 12 V

100

90

80

70

60

50

40

30

20

10

0

I_OUT

(500 mA/DIV)

VIN = 15V PFM

VIN = 15V FPWM

VIN = 18 V PFM

VIN = 18 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

V_OUT

(100 mV/DIV)

Time (500 µs/DIV)

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

D004

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

12-V Adjustable Output

10% to 100% Load Step

MODE = High

图8-18. Efficiency

图8-19. Load Transient

V_OUTRipple

(20 mV/DIV)

(5 mV/DIV)

20MHz BW

250MHz BW

Time (1 µs/DIV)

12-V Adjustable Output

I_OUT= 1 A

12-V Adjustable Output

I_OUT= 1 A

图8-20. Output Ripple 20-MHz BW

图8-21. Output Ripple 250-MHz BW

12.2

12.15

12.1

EN

(2 V/DIV)

12.05

12

V_OUT

(5 V/DIV)

11.95

11.9

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

I_OUT

11.85

11.8

(500 mA/DIV)

PGOOD

11.75

11.7

(2 V/DIV)

Time (2 ms/DIV)

11.65

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D010

12-V Adjustable Output

Toggle Enable

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

12-V Adjustable Output

图8-23. Start-up With 24-V Input

图8-22. Line and Load Regulation

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8.2.3.4 V_OUT= 15 V

100

90

80

70

60

50

I_OUT

(500 mA/DIV)

VIN = 18V PFM

VIN = 18V FPWM

VIN = 22 V PFM

VIN = 22 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

40

30

20

10

V_OUT

(100 mV/DIV)

Time (500 µs/DIV)

0

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

D006

15-V Adjustable Output

10% to 100% Load Step

MODE = High

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

15-V Adjustable Output

图8-25. Load Transient

图8-24. Efficiency

V_OUTRipple

(20 mV/DIV)

(5 mV/DIV)

20MHz BW

250MHz BW

Time (1 µs/DIV)

15-V Adjustable Output

I_OUT= 1 A

15-V Adjustable Output

I_OUT= 1 A

图8-26. Output Ripple 20-MHz BW

图8-27. Output Ripple 250-MHz BW

15.3

15.25

15.2

15.15

15.1

EN

(2 V/DIV)

15.05

15

V_OUT

14.95

14.9

14.85

14.8

14.75

14.7

14.65

14.6

(10 V/DIV)

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

I_OUT

(500 mA/DIV)

PGOOD

(2 V/DIV)

Time (2 ms/DIV)

14.55

14.5

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D011

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

15-V Adjustable Output

Toggle Enable

图8-29. Start-up with 24-V Input

图8-28. Line and Load Regulation

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8.2.3.5 V_OUT= 2.5 V

100

90

80

70

60

50

40

30

20

10

0

I_OUT

(500 mA/DIV)

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

V_OUT

(20 mV/DIV)

Time (500 µs/DIV)

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

D005

2.5-V Adjustable Output

10% to 100% Load Step

MODE = High

MODE = High for FPWM Mode

MODE = Low for Auto PFM Mode

2.5-V Adjustable Output

图8-31. Load Transient

图8-30. Efficiency

V_OUTRipple

(20 mV/DIV)

(5 mV/DIV)

20MHz BW

250MHz BW

Time (1 µs/DIV)

2.5-V Adjustable Output

I_OUT= 1 A

2.5-V Adjustable Output

I_OUT= 1 A

图8-32. Output Ripple 20-MHz BW

图8-33. Output Ripple 250-MHz BW

2.6

2.575

2.55

EN

(2 V/DIV)

2.525

2.5

V_OUT

(2 V/DIV)

2.475

2.45

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

I_OUT

2.425

2.4

(500 mA/DIV)

PGOOD

2.375

2.35

(2 V/DIV)

Time (2 ms/DIV)

2.325

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D007

图8-35. Start-up with 24-V Input

图8-34. Line and Load Regulation

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8.2.3.6 V_OUT= 1.2 V and V_OUT= 1.8 V

100

90

80

70

60

50

40

100

90

80

70

60

50

40

30

20

10

0

VIN = 5 V PFM

30

20

10

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 15 V PFM

VIN = 15 V FPWM

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

0

0.0001

0.001

0.01

Output Current (A)

0.1 0.2 0.5

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D096

D098

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

1.8-V Adjustable Output

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

1.2-V Adjustable Output

图8-36. Efficiency for V_OUT= 1.8 V

图8-37. Efficiency for V_OUT= 1.2 V

1.88

1.86

1.84

1.82

1.8

1.24

1.22

1.2

1.78

1.76

1.74

1.72

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 15 V PFM

VIN = 15 V FPWM

1.18

1.16

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D090

D088

图8-38. Line and Load Regulation for V_OUT= 1.8 V 图8-39. Line and Load Regulation for V_OUT= 1.2 V

1.5

1.4

1.3

1.2

1.1

1

1.5

1.4

1.3

1.2

1.1

1

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 15 V PFM

VIN = 15 V FPWM

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D094

D092

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

1.8-V Adjustable Output

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

1.2-V Adjustable Output

图8-40. Power Dissipation for V_OUT= 1.8 V

图8-41. Power Dissipation for V_OUT= 1.2 V

32

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8.2.3.7 V_OUT= 5 V and 3.3 V Fixed Output Options

100

90

80

70

60

100

90

80

70

60

50

40

30

20

10

0

50

VIN = 6.5V PFM

VIN = 6.5V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

40

30

20

10

0

0.0001

0.001

0.01

Output Current (A)

0.1 0.2 0.5

1

2 3 5 710

0.0001

0.001

0.01 0.1 0.2 0.5

Output Current (A)

1

2 3 5 710

D063

D065

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

5-V Fixed Output

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

3.3-V Fixed Output

图8-42. Efficiency for V_OUT= 5 V

图8-43. Efficiency for V_OUT= 3.3 V

5.1

5.075

5.05

5.025

5

3.38

3.36

3.34

3.32

3.3

3.28

3.26

3.24

3.22

3.2

4.975

4.95

4.925

4.9

VIN = 5 V PFM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

VIN = 5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

3.18

3.16

3.14

3.12

3.1

4.875

4.85

4.825

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D073

D071

图8-44. Line and Load Regulation for V_OUT= 5 V 图8-45. Line and Load Regulation for V_OUT= 3.3 V

1.5

1.4

1.3

1.2

1.1

1

1.5

1.4

1.3

1.2

1.1

1

VIN = 6.5 V PFM

VIN = 6.5 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

VIN = 5.0 V PFM

VIN = 5.0 V FPWM

VIN = 12 V PFM

VIN = 12 V FPWM

VIN = 24 V PFM

VIN = 24 V FPWM

VIN = 36 V PFM

VIN = 36 V FPWM

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

D067

D069

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

5-V Fixed Output

MODE = Low for Auto PFM Mode

MODE = High for FPWM Mode

3.3-V Fixed Output

图8-46. Power Dissipation for V_OUT= 5 V

图8-47. Power Dissipation for V_OUT= 3.3 V

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8.3 Best Design Practices

• Do not: Exceed the absolute maximum ratings of the device.

• Do not: Exceed the ESD ratings of the device.

• Do not: Exceed the recommended operating conditions.

• Do not: Allow the EN or MODE/SYNC terminals to float.

• Do not: Allow the output voltage to exceed the input voltage, nor go below ground.

• Do: Follow all of the guidelines and suggestions found in this data sheet, before committing your design to

production.

• Do: Review your designs with TI Application Engineers on the E2E forum.

8.4 Power Supply Recommendations

8.4.1 Supply Voltage Range

The voltage of the input supply must not exceed the absolute maximum ratings and the recommended operating

conditions of the LMZM23601.

8.4.2 Supply Current Capability

The input supply must be able to supply the required input current to the LMZM23601 converter. The required

input current depends on the application's minimum input voltage, the required maximum output current, the

output voltage, and the converter efficiency ηfor this condition.

V_OUTìI_OUTMAX

I

í

IN

V_INMINì h

(4)

As an example, assuming that the adjustable output voltage version of the LMZM23601 is used for a 5-V, 1-A

output converter design with 12-V minimum input voltage. The conversion efficiency for this condition is about

85%. The required input current from the supply is 0.49 A, so TI recommends an input power supply with ≥ 0.5

A current capability.

8.4.3 Supply Input Connections

Long input connection cables can cause issues with the normal operation of any buck converter. Some of the

issues can be a voltage drop in the input voltage or stability probes because of the added series input

inductance.

8.4.3.1 Voltage Drops

Using long input wires to connect the supply to the input of any converter adds impedance in series with the

input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the

converter is loaded. If the input voltage is near the minimum input operating voltage for the design, this added

voltage drop can cause the converter to drop out or reset. If long wires are used during testing, TI recommends

adding some bulk (for example, electrolytic) capacitance at the input of the converter.

8.4.3.2 Stability

The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in

an underdamped RLC network at the input of the buck converter. This circuit can cause instability, or overvoltage

transients at the VIN pin each time the input supply is cycled on and off. If long wires are used, TI recommends

adding some electrolytic bulk capacitance in parallel with the ceramic input capacitor. The ESR of the bulk

capacitor improves the damping. Use an electrolytic capacitor with a capacitance at least four times larger than

the ceramic input capacitance.

C_BULKí 4 ìC_CER

(5)

The required ESR from the bulk capacitor depends on the cable inductance.

English Data Sheet: SNVSAQ4

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L_CABLE

ESR_BULK

í

C_CER

(6)

For example, two cables (one for VIN and one for GND), each 1 meter (approximately 3 feet) long with

approximately 1-mm diameter (18 AWG), placed 1 cm (approximately 0.4 inch) apart forms a rectangular loop

resulting in about 1.2 µH of inductance. The inductance in this example can be decreased to almost half if the

input wires are twisted. Based on a 10-µF ceramic input capacitor, the recommended parallel C_BULKis ≥ 40 µF.

Using a 47-µF capacitor is sufficient. Based on about 1.2 µH of inductance and 10 µF of ceramic input

capacitance, the recommended ESR of the bulk capacitor is 0.35 Ω or larger. See TI User Guide, Simple

Success with Conducted EMI for DC/DC Converters for more details on input filter design.

8.5 Layout

8.5.1 Layout Guidelines

Good board layout is essential for the proper operation of any switching regulator. A poor layout can ruin an

otherwise perfect schematic design. The good news is that it is relatively easy to achieve an optimized layout

when using a module because some of the critical nodes for the board layout are internal to the device. To have

a good layout with this module, the designer must follow these main objectives:

1. Minimize the inductance in the switching current path of the converter. The switching current path in the buck

converter is formed by the input capacitor and the power switches (for example, MOSFETs). A common

mistake in many buck converter layouts is placing the input capacitor far from the IC. This introduces

inductance in the switching current path, which leads to high frequency ringing on the switching node, which

results in high frequency noise coupled all the way to the output voltage. The input capacitor placement

affects the amount of noise on the output in a buck converter. Place the input capacitor as close as

possible, right next to the LMZM23601 ensures that the switching current path area is kept to a minimum.

This results in the lowest possible inductance in the path of high di/dt current.

2. Protect any sensitive nodes in the converter design. The feedback node is usually a sensitive area of the

converter and needs to be away from any noise sources. The fixed 5-V and 3.3-V output voltage versions of

the LMZM23601 have the feedback resistors internal to the device, and the sensitive node is inside the

module. However, if the adjustable option is used, then two feedback resistors are required to set the output

voltage. A common mistake in many layouts is placing the divider close to the load, far from the device, and

then using a long feedback trace back to the regulator. A long feedback trace can potentially pick up noise

from other nearby circuits. TI recommends placing the feedback divider as close as possible to the

LMZM23601 device so that the feedback node is as small as possible.

3. Provide enough copper for heat dissipation. The board copper provides a thermal resistance path for the

heat to flow out of the package and dissipate into the environment. Place a dog-bone shape of ground

(GND) copper under the module for proper heat sinking. Also, place thermal vias to provide a heat path to

the other board layers. TI recommends an unbroken GND plane or GND area of copper on the top and

bottom layers.

8.5.1.1 Thermal Design

Thermal design is an important aspect of any power regulator design. Every supply dissipates some power, and

providing sufficient copper area for proper heat dissipation is important. The package thermal resistance curves

vs PCB copper area along with the power dissipation curves in 节 6.7 can be used to estimate the necessary

copper area for the design. Consider 方程式7 and 图8-48.

125 ( F 6

#_/#:

4_àQ

2_&

(7)

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75

70

65

60

55

2-Layer

4-Layer

50

5

10

15

20

25

30

35

40

Board Area (cm²)

D032

图8-48. Package Thermal Resistance vs Board Copper Area

As an example, consider a typical application of 24-V input 5-V output with 0.8 A of output current and estimate

the required heat-sinking area. For this example consider a maximum ambient temperature T_{A_MAX}of 75°C and

no air flow or additional heat sinking besides the PCB layers. Calculate the maximum allowed package thermal

resistance for this design specification.

From 节6.7, it can be seen that the power dissipation for 24-V input, 5-V output, and 0.8A load is 0.75 W. Based

on 方程式 7, for this power dissipation level and 75°C maximum ambient temperature, the maximum package

thermal resistance must be less than 66.7°C/W. To achieve this thermal resistance with a 2-layer board, the

approximate area of the board copper must be at least 9 cm².

8.5.2 Layout Examples

INPUT CAPACITOR

OUTPUT

PLACED NEXT TO

CAPACITOR

THE MODULE

MODULE

GND

MODE

VIN

FB

EN

PG

VOUT

VIN

FEEDBACK

CONNECTION

GND COPPER FOR

HEAT SINKING

=THERMAL VIAS

图8-49. Layout Example With Fixed Output Version

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INPUT CAPACITOR

PLACED NEXT TO

THE MODULE

BOTTOM FB

TOP FB

OUTPUT

CAPACITOR

RESISTOR RESISTOR

MODULE

GND

MODE

VIN

EN

FB

PG

VOUT

VIN

MINIMIZE FB

NODE

GND COPPER FOR

HEAT SINKING

=THERMAL VIAS

图8-50. Layout Example With Adjustable Output Version

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9 Device and Documentation Support

9.1 Device Support

9.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

9.1.2 Development Support

9.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZM23601 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation request the following:

Texas Instruments, Inverting Application for the LMZM23601 and LMZM23600 application report

Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report

Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report

Texas Instruments, Constructing Your Power Supply –Layout Considerations

Texas Instruments, AN-1229 Simple Switcher PCB Layout Guidelines application report

Texas Instruments, Using New Thermal Metrics application report

Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

Texas Instruments, AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

application report

Texas Instruments, AN-2162 Simple Success With Conducted EMI From DCDC Converters application report

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

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9.5 Trademarks

MicroSiP^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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10.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

LMZM23601SILR

LMZM23601SILT

uSiP

SIL

10

3000

250

330.0

12.4

3.27

4.07

1.78

8.0

12.0

Q2

LMZM23601V3SILR

LMZM23601V3SILT

LMZM23601V5SILR

LMZM23601V5SILT

3000

250

3000

250

English Data Sheet: SNVSAQ4

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

uSiP

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

58.0

LMZM23601SILR

LMZM23601SILT

SIL

10

383.0

353.0

uSiP

58.0

LMZM23601V3SILR

LMZM23601V3SILT

LMZM23601V5SILR

LMZM23601V5SILT

uSiP

3000

250

58.0

uSiP

58.0

uSiP

3000

250

58.0

uSiP

58.0

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PACKAGE OUTLINE

SIL0010A

uSiP^TM- 1.578 mm max height

S

C

A

L

E

3

.

5

0

MICRO SYSTEM IN PACKAGE

3.9

3.7

B

A

PIN 1 ID

3.1

2.9

PICK AREA

NOTE 3

NOTE 4

TYP

1.578 MAX

C

SEATING PLANE

0.08 C

3.05 TYP

11

EXPOSED

THERMAL PAD

0.7 0.1

(0.05) TYP

5

6

6X 0.6

2.9 0.1

SYMM

2X

2.4

0.4

10X

0.2

0.1

C A B

C

10

0.05

1

PIN 1 ID

0.175

0.75

0.55

10X

PKG

4222635/D 08/2019

MicroSiP is a trademark of Texas Instruments

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Pick and place nozzle 1.1 mm or smaller recommended.

4. Location, size and quantity of components are for reference only and could vary.

5. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

SIL0010A

uSiP^TM- 1.578 mm max height

MICRO SYSTEM IN PACKAGE

(0.7)

11

SEE SOLDER MASK

DETAILS

10X (0.65)

10

1

10X (0.3)

SYMM

(2.9)

8X (0.6)

(1.03)

(R0.05) TYP

6

5

(

0.2) VIA

TYP

(0.175)

PKG

(3.05)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4222635/D 08/2019

NOTES: (continued)

6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

7. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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EXAMPLE STENCIL DESIGN

SIL0010A

uSiP^TM- 1.578 mm max height

MICRO SYSTEM IN PACKAGE

3X (0.7)

11

(R0.05) TYP

10X (0.65)

1

10X (0.3)

10

3X

(0.833)

SYMM

8X (0.6)

(1.03)

5

6

EXPOSED

METAL

2X

(0.175)

PKG

(3.05)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PAD 11:

86% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4222635/D 08/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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44

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Product Folder Links: LMZM23601

English Data Sheet: SNVSAQ4

GENERIC PACKAGE VIEW

SIL 10

uSIP^TM

MICRO SYSTEM IN PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225402/A

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型号：	LMZM23601SILR
厂家：	TEXAS INSTRUMENTS
描述：	采用 3.8mm × 3mm 封装的 36V、1A 降压直流/直流电源模块 \| SIL \| 10 \| -40 to 125 开关电源电路
文件：	总48页 (文件大小：3163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMZM23601SILR [TI]

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