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LMX2820

SNAS783 –JUNE 2020

LMX2820 22.4-GHz Wideband PLLatinum™ RF Synthesizer

With Phase Synchronization and JESD204B Support

1 Features

3 Description

The LMX2820 is a high-performance, wideband

synthesizer that can generate any frequency in the

range of 43.75 MHz to 22.4 GHz. The high-

performance PLL with figure of merit of –236 dBc/Hz

and high phase detector frequency can attain very

low in-band noise and integrated jitter. The high-

speed N-divider has no pre-divider, thus significantly

reducing the amplitude and number of spurs. There is

also a programmable input multiplier to mitigate

integer boundary spurs.

1

•

Output frequency: 43.75 MHz to 22.4 GHz

< 40-fs rms jitter (12 kHz – 95 MHz)

High-performance PLL

–

Figure of merit: –236 dBc/Hz

Normalized 1/f noise: –134 dBc/Hz

High phase detector frequency

–

400-MHz integer mode

300-MHz fractional mode

The LMX2820 allows users to synchronize the output

of multiple devices and also enables applications that

need deterministic delay between input and output.

The fast calibration algorithm greatly reduces the

VCO calibration time to under 5 µs, enabling systems

requiring fast frequency hopping. The LMX2820 can

generate or repeat SYSREF that is compliant to the

JESD204B standard, allowing for its use as a low-

noise clock source for high-speed data converters.

This synthesizer can also be used with an external

VCO. A direct PFD input pin is provided to support

offset mixing for low spurious transmission.

–

Programmable input multiplier

Direct PFD input for offset mixing support

•

< 5-µs fast VCO calibration time

Mute pin with 200-ns mute/unmute time

–40-dBc VCO leakage with doubler enabled

Support for external VCO up to 22 GHz

Synchronization of output phase across multiple

devices

•

Two differential RF outputs and one differential

SYSREF output for JESD204B support

The device runs from a single 3.3-V supply and has

integrated LDOs that eliminate the need for onboard

low-noise LDOs.

2 Applications

•

Radar and electronic warfare

Device Information⁽¹⁾

5G and mm-Wave wireless infrastructure

Microwave backhaul

PART NUMBER

PACKAGE

BODY SIZE (NOM)

Test and measurement equipment

High-speed data converter clocking

LMX2820

VQFN (48)

7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

OSCIN_P

OSCIN_N

÷1,2,..4095

÷1,2,..255

RFOUTA_P

RFOUTA_N

Charge

Pump

÷2,4,8,..,128

PFD

×2

x3,x4..x7

÷2

×2

MUTE

Lock

Detection

LD

RFOUTB_P

RFOUTB_N

÷2,4,8,..,128

N Divider

MUXOUT

SRREQ_P

SRREQ_N

CS#

SCK

SDI

SYSREF

Generation

Digital

Control

G4

Modulator

SROUT_P

SROUT_N

Phase Sync

CE

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to

change without notice.

LMX2820

SNAS783 –JUNE 2020

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 25

8.1 Application Information............................................ 25

8.2 Typical Application ................................................. 26

8.3 Initialization Setup and Power on Sequencing ....... 29

Power Supply Recommendations...................... 31

1

2

3

4

5

6

Features.................................................................. 1

8

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 8

6.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

9

10 Layout................................................................... 32

10.1 Layout Guidelines ................................................. 32

10.2 Layout Example .................................................... 32

11 Device and Documentation Support ................. 34

11.1 Receiving Notification of Documentation Updates 34

11.2 Support Resources ............................................... 34

11.3 Trademarks........................................................... 34

11.4 Electrostatic Discharge Caution............................ 34

11.5 Glossary................................................................ 34

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

June 2020

*

Initial release.

2

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5 Pin Configuration and Functions

RTC Package

48-Pin VQFN

Top View

CE

GND

1

36

35

34

33

32

31

30

29

28

27

26

25

REFVCO2

NC

2

BIASVCO

GND

3

BIASVCO2

VCCBUF2

GND

4

PSYNC

GND

5

6

RFOUTA_P

RFOUTA_N

GND

DAP

VCCDIG

OSCIN_P

OSCIN_N

REGIN

7

8

9

RFIN

10

11

12

GND

SRREQ_P

SRREQ_N

RFOUTB_P

RFOUTB_N

Not to scale

RTC Package (QFN) Pin Functions

I/O (1)

DESCRIPTION

NO.

NAME

41

BIASVAR

BIASVCO

BIASVCO2

CE

BP

I

VCO varactor bias. Connect a 1-µF decoupling capacitor to ground.

VCO bias. Connect a low ESR 0.47-µF decoupling capacitor to ground. Place close to

pin.

3

34

1

VCO bias. Connect a 1-µF decoupling capacitor to ground. Place close to pin.

Chip Enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on

the device.

14

39

CPOUT

CS#

O

I

Charge pump output. Recommend connecting C1 of loop filter close to this pin.

SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic.

32,2,16,27,40,48,42,29

,6,47,15,4

GND

G

Ground.

38

37

23

35

LD

MUTE

MUXOUT

NC

O

I

Lock detect output. 3.3-V logic.

Buffer mute control. High impedance CMOS input. 1.8-V to 3.3-V logic.

SPI readback output. 3.3-V logic. High impedance when CE = LOW.

Connect to ground.

O

NC

Reference input clock (–). High impedance self-biasing pin. Requires AC coupling. If not

being used, AC-couple it to ground via a 50-Ω resistor.

9

OSCIN_N

OSCIN_P

PFDIN

I

Reference input clock (+). High impedance self-biasing pin. Requires AC coupling. If not

being used, AC-couple it to ground via a 50-Ω resistor.

8

External PFD input. Self-biasing pin. Requires AC coupling and an external 50-Ω resistor

to ground.

20

Phase synchronization input. Configurable input signal level. Connect to ground if not

being used.

5

PSYNC

I

44

REFVCO

BP

VCO supply reference. Connect a 10-µF decoupling capacitor to ground.

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RTC Package (QFN) Pin Functions (continued)

I/O (1)

DESCRIPTION

NO.

NAME

36

REFVCO2

BP

VCO supply reference. Connect a 1-µF decoupling capacitor to ground.

Input reference path regulator decoupling. Connect a 1-µF decoupling capacitor to

ground. Place close to pin. An additional low ESR 0.1-µF decoupling capacitor is

recommended for high frequency noise filtering.

10

REGIN

BP

46

28

30

31

25

26

18

19

22

21

12

11

REGVCO

RFIN

BP

I

VCO regulator node. Connect a 1-µF decoupling capacitor to ground.

External VCO input. Internal 50-Ω terminated. Requires AC coupling.

Differential output A (–). Internal 50-Ω pull-up. Requires AC coupling.

Differential output A (+). Internal 50-Ω pull-up. Requires AC coupling.

Differential output B (–). Internal 50-Ω pull-up. Requires AC coupling.

Differential output B (+). Internal 50-Ω pull-up. Requires AC coupling.

SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.

SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic.

Differential SYSREF output (–). Internal 50-Ω pull-up.

RFOUTA_N

RFOUTA_P

RFOUTB_N

RFOUTB_P

SCK

O

I

SDI

I

SROUT_N

SROUT_P

SRREQ_N

SRREQ_P

O

I

Differential SYSREF output (+). Internal 50-Ω pull-up.

Differential SYSREF input clock (–). Supports AC and DC coupling.

Differential SYSREF input clock (+). Supports AC and DC coupling.

I

Output buffer supply. Connect to 3.3-V with a low ESR 0.1-µF and a 1-µF decoupling

capacitor to ground.

24

VCCBUF

P

Buffer supply. Connect to 3.3-V with a low ESR 0.1-µF and a 1-µF decoupling capacitor

to ground.

33

13

7

VCCBUF2

VCCCP

P

Charge pump supply. Connect to 3.3-V with a 1-µF decoupling capacitor to ground.

Digital supply. Connect to 3.3-V with a low ESR 0.1-µF and a 1-µF decoupling capacitor

to ground.

VCCDIG

Digital supply. Connect to 3.3-V with a low ESR 0.1-µF and a 1-µF decoupling capacitor

to ground.

17

VCCMASH

P

VCO supply. Connect to 3.3-V with a low ESR 0.1-µF and a 1-µF decoupling capacitor to

ground.

45

43

VCCVCO

VTUNE

P

I

VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground.

Connect the GND pin to the exposed thermal pad for correct operation. Connect the

thermal pad to any internal PCB ground plane using multiple vias for good thermal

performance.

—

DAP

—

(1) The definitions below define the I/O type for each pin.

•

I = Input

O = Output

BP = Bypass

G = Ground

NC = No connect. Pin may be grounded or left unconnected.

P = Power supply

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

V_CC

V_IN

T_J

Power supply voltage

IO input voltage

–0.3

3.6

V_CC+0.3

150

V

Junction temperature

Storage temperature

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

85

UNIT

°C

T_A

Ambient temperature

Junction temperature

Suppy voltage

–40

T_J

125

3.45

°C

V_CC

3.15

3.3

V

6.4 Thermal Information

LMX2820

THERMAL METRIC⁽¹⁾

RTC (VQFN)

UNIT

48 PINS

21.5

9.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

6.0

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

Ψ_JB

5.9

R_θJC(bot)

0.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

One direct RF output⁽¹⁾

One divided down RF output⁽²⁾

One RF output with VCO doubler enabled⁽³⁾

PLL mode (external VCO)⁽⁴⁾

PFDin mode (external PFD)⁽⁵⁾

MIN

TYP

488

533

594

360

455

234

9

MAX

UNIT

I_CC

Supply current

mA

I_CCPOR

I_CCPD

Power-On-Reset current

Power down current

INPUT SIGNAL PATH

OSC_2X = 0 (Doubler bypassed)

5

1400

250

f_OSCin

OSCin input frequency

MHz

OSC_2X = 1 (Doubler enabled);

Single-ended input buffer

Differential input buffer

0.3

0.1

30

3.6

1

V_OSCin

OSCin input voltage⁽⁶⁾

V

f_MULTin

f_MULTout

PLL

Multiplier input frequency

Multiplier output frequency

70

MULT ≥ 3

MHz

180

250

Integer channel

Phase detector frequency⁽⁷⁾1^stand 2^ndorder modulator

5

400

300

225

f_PD

MHz

mA

3^rdorder modulator

CPG = 2

5.6

11.2

2.8

CPG = 3

I_CPout

Charge pump current

CPG = 4

CPG = 6

CPG = 7

8.4

14

PN_{PLL_1/f}

Normalized PLL 1/f noise⁽⁸⁾

–134

–236

Integer channel⁽⁹⁾

Fractional channel⁽¹⁰⁾

dBc/Hz

Normalized PLL noise

floor⁽⁸⁾

PN_{PLL_Flat}

f_RFin

RFin input frequency

RFin input power

2000

–5

22000

5

MHz

dBm

dB

P_RFin

RL_RFin

f_PFDin

P_PFDin

VCO

f_VCO

RFin return loss

2 GHz ≤ f_RFin≤ 22 GHz

−8

PFDin input frequency

PFDin input power

20

2000

1

MHz

V

0.1

VCO frequency

5600

11200

MHz

(1) f_OSCin= f_PD= 100 MHz; f_VCO= f_OUT= 11 GHz; P_OUT= 0 dBm; OSC_2X = 0; MULT = 1.

(2) f_OSCin= f_PD= 100 MHz; f_VCO= 11 GHz; f_OUT= 5.5 GHz; P_OUT= 0 dBm; OSC_2X = 0; MULT = 1.

(3) f_OSCin= f_PD= 100 MHz; f_VCO= 11 GHz; f_OUT= 22 GHz; P_OUT= 0 dBm; OSC_2X = 1; MULT = 1.

(4) f_OSCin= f_PD= 100 MHz; f_RFin= 11 GHz; f_OUT= 11 GHz (from external VCO); OSC_2X = 0; MULT = 1.

(5) f_OSCin= f_PD= 100 MHz; f_PFDin= 2 GHz; f_OUT= 11 GHz (from external VCO); OSC_2X = 0; MULT = 1.

(6) See Treatment of Unused Pins for definition of OSCin input voltage.

(7) For lower VCO frequencies, the N-divider minimum value can limit the phase detector frequency.

(8) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an

infinite loop bandwidth as: PLL_Total = 10*log[10^{(PLL_Flat/10)}+10^{(PLL_Flicker/10)}]; PLL_Flat = PN1 Hz + 20*log(N) + 10*log(f_PD); PLL_Flicker

= PN10 kHz - 10*log(Offset/10 kHz) + 20*log(f_OUT/1 GHz).

(9) f_OSCin= f_PD= 100 MHz; f_VCO= f_OUT= 11 GHz.

(10) f_OSCin= f_PD= 100 MHz; f_VCO= f_OUT= 10.999 GHz; Fractional denominator = 1000.

6

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

-84.3

MAX

UNIT

10 kHz

100 kHz

1 MHz

-111.3

-132.6

-151.9

-160.1

-83.5

f_VCO= 5.9 GHz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-109.9

-131.3

-150.6

-159.2

-82.4

f_VCO= 6.7 GHz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-109.3

-130.8

-150.0

-158.8

-81.5

f_VCO= 7.5 GHz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-108.1

-129.5

-149.1

-159.2

-80.0

PN_VCO

Open loop VCO phase noise f_VCO= 8.3 GHz

dBc/Hz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-108.8

-129.2

-148.8

-159.3

-79.2

f_VCO= 8.9 GHz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-108.4

-128.6

-148.1

-160.6

-79.4

f_VCO= 9.9 GHz

10 MHz

100 MHz

10 kHz

100 kHz

1 MHz

-106.3

-127.2

-147.0

-158.9

92

f_VCO= 10.9GHz

10 MHz

100 MHz

f_VCO= 5.9 GHz

f_VCO= 6.7 GHz

f_VCO= 7.5 GHz

96

113

K_VCO

VCO gain

f_VCO= 8.3 GHz

120

MHz/V

f_VCO= 8.9 GHz

113

f_VCO= 9.9 GHz

147

f_VCO= 10.9 GHz

152

f_OSCin= f_PD= 100 MHz;

Switch between 5.6 GHz and 11.2 GHz

t_VCOcal

VCO calibration-time

5

µs

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCO not being re-calibrated;

–40°C ≤ T_A≤ 85°C

Allowable temperature

drift⁽¹¹⁾

|Δ_TCL|

125

°C

RF OUTPUT

f_OUT

RF output frequency

43.75

22400

MHz

dBm

f_OUT= 22 GHz

f_OUT= 11 GHz

0

4

Single-ended output

power⁽¹²⁾

P_OUT

f_OUT≤ 5.5 GHz

6

H_1/2

H_3/2

1/2 harmonic⁽¹³⁾

3/2 harmonic

f_OUT= 2 x f_VCO= 11 GHz to 22 GHz

f_VCO= f_OUT= 11 GHz

−40

−45

−20

−35

−25

−27

−14

−32

−53

200

OUTx_PWR

= 7

H2

Second harmonic

Third harmonic

f_VCO= 11 GHz; f_OUT= 5.5 GHz

f_OUT= 2 x f_VCO= 11 GHz to 22 GHz

f_VCO= f_OUT= 11 GHz

dBc

H3

f_VCO= 11 GHz; f_OUT= 5.5 GHz

f_OUT= 22 GHz

Single-ended output power

when output is muted⁽¹²⁾

P_MUTE

f_OUT= 11 GHz

dBm

f_OUT= 5.5 GHz

t_MUTE

Mute enable time

Mute disable time

f_OUT= 11 GHz

ns

t_unMUTE

f_OUT= 11 GHz

f_OUTA = 11 GHz; f_OUTB = 5.5 GHz;

P_OUTA = P_OUTB = 0 dBm

isoCH

Channel to channel isolation

–50

dBc

PHASE SYNCHRONIZATION

OSCin input frequency with

Category 3

5

200

800

f_OSCinSYNC

MHz

SYNC

Categories 1 and 2

DIGITAL INTERFACE (CE, SCK, SDI, CS#, PSYNC, MUTE)

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.2

V_CC

0.6

25

V

µA

V

CS#, MUTE, CE

I_IH

High-level input current

SCK, SDI, PSYNC

60

I_IL

Low-level input current

High-level output voltage

Low-level output voltage

−1

V_OH

V_OL

Load current = –5 mA

Load current = 5 mA

V_CC–0.4

MUXout, LD

0.4

(11) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial

temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay at lock. This

change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended

operating temperatures of the device.

(12) Measured with one of the RF output differential pair pins, the unused pin is 50-Ω terminated. See Initialization Setup and Power on

Sequencing for details.

(13) One RF output is active. Measured with JSO-51-471/6S balun.

6.6 Timing Requirements

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

SERIAL INTERFACE WRITE TIMING

f_SCK

SCK frequency

1 / (t_CWL+t_CWH

)

50

MHz

8

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Timing Requirements (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ 85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted)

MIN

5

NOM

MAX

UNIT

ns

t_CE

SCK to CSB low time

SDI to SCK setup time

SDI to SCK hold time

SCK pulse width high

SCK pulse width low

CSB to SCK setup time

CSB pulse width high

t_CS

2

ns

t_CH

2

ns

t_CWH

t_CWL

t_CES

t_EWH

Figure 1

10

5

ns

2

ns

SERIAL INTERFACE READ TIMING

f_SCK

t_CE

SCK frequency

1 / (t_CWL+t_CWH

)

50

MHz

ns

SCK to CSB low time

SDI to SCK setup time

SDI to SCK hold time

SCK pulse width high

SCK pulse width low

CSB to SCK setup time

CSB pulse width high

SCK to MUXout delay time

5

2

t_CS

ns

t_CH

2

ns

t_CWH

t_CWL

t_CES

t_EWH

t_OD

10

5

ns

Figure 1

ns

2

ns

8

ns

SYNC AND SYSREFREQ TIMING

t_CS

t_CH

Pin to OSCin setup time

Pin to OSCin hold time

2.5

2

ns

Figure 2

MSB

(R/W)

Address

(7-bit)

LSB

(D0)

SDI

(D15 œ D1)

t_CS

t_CH

SCK

1^st

t_CES

2^nd

3

^rdœ 8^th

9^th

10^thœ 23^rd

24^th

t_CE

t_CWH

t_OD

t_EWH

t_CWL

Read back register value

16-bit

MUXOUT

CS#

Figure 1. Serial Interface Timing Diagram

PSYNC

SRREQ

t_CS

t_CH

OSCIN

Figure 2. Trigger Signals Timing Diagram

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6.7 Typical Characteristics

50

47.5

45

42.5

40

37.5

35

32.5

0

2500

5000

7500 10000 12500 15000 17500 20000 22500

Output Frequency (MHz)

Figure 4. Integrated Jitter From 12k – 95 MHz

Figure 3. Closed Loop Phase Noise at 6 GHz With f_PD= 200

MHz

-147

-150

-153

-156

-159

-162

-165

-168

-101

-103

-105

-107

-109

-111

-113

-115

-117

-119

-121

-123

-125

Measurement

Flicker (Normalized 1/f=-132.5)

Flat (FOM=-237.5 dBc/Hz)

Model

1x10³

2x10³3x10³5x10³

1x10⁴

2x10⁴3x10⁴5x10⁴

1x10⁵

2x10⁵

0

2500

5000

7500 10000 12500 15000 17500 20000 22500

Offset (MHz)

Output Frequency (MHz)

Graph is for Flicker = –132.5 dBc/Hz and Figure of merit = –237.5

dBc/Hz

Figure 6. Noise Floor

Figure 5. PLL Noise Metrics

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Typical Characteristics (continued)

10

-30

-36

-42

-48

-54

-60

-66

Single-Ended

Differential

Single-Ended

Differential

9

8

7

6

5

4

3

2

1

0

-1

-2

0

4000

8000

12000

16000

20000

11000

12500

14000

15500

17000

18500

20000

21500

23000

Frequency (MHz)

Output Frequency (MHz)

Figure 7. Output Power

Figure 8. VCO Leakage in With Doubler Enabled (Half

Harmonic)

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7 Detailed Description

7.1 Overview

The LMX2820 is a high-performance, wideband frequency synthesizer with an integrated VCO and output

divider. The VCO operates from 5.6 GHz to 11.2 GHz, and this can be combined with the output divider and

doubler to produce any frequency in the range of 43.75 MHz to 22.4 GHz. Within the input path, there are two

dividers and a multiplier for flexible frequency planning. The multiplier also allows the reduction of spurs by

moving the frequencies away from the integer boundary. The PLL is fractional-N PLL with a programmable delta-

sigma modulator up to 3^rdorder. The fractional denominator is a programmable 32-bit long, which can easily

provide fine frequency steps below 1-Hz resolution, or be used to do exact fractions like 1/3, 7/1000, and many

others. The phase frequency detector goes up to 300 MHz in fractional mode or 400 MHz in integer mode,

although minimum N-divider values must also be taken into account. For applications where deterministic or

adjustable phase is desired, the PSYNC Pin can be used to get the phase relationship between the OSCIN and

RFOUT pins deterministic. When this is done, the phase can be adjusted in very fine steps of the VCO period

divided by the fractional denominator. The ultra-fast VCO calibration is designed for applications where the

frequency must be swept or abruptly changed. The JESD204B support includes using the RFOUTB output to

create a differential SYSREF output that can be either a single pulse or a series of pulses that occur at a

programmable distance away from the rising edges of the output signal. The LMX2820 device requires only a

single 3.3-V power supply. The internal power supplies are provided by integrated LDOs, eliminating the need for

high-performance external LDOs. The digital logic for the SPI interface and is compatible with voltage levels from

1.8 V to 3.3 V. Table 1 shows the range of several of the dividers, multipliers, and fractional settings.

Table 1. Dividers, Multipliers, and Fractional Settings

BLOCK

SUB-BLOCK

FIELD

MIN

MAX

COMMENTS

The low noise doubler can be used to increase the

phase detector frequency to improve phase noise and

avoid spurs.

0

Doubler

OSC_2X

1 (= 2X)

(= 1X)

Only use the Pre-R divider if the frequency is too high

for the input multiplier or for the Post-R divider.

Pre-R Divider

Input Multiplier

Post-R Divider

PLL_R_PRE

MULT

1

3

1

4095

7

Input Path

The input multiplier is effective for spur avoidance,

increases PLL noise.

The maximum input frequency for the Post-R divider is

250 MHz. Use the Pre-R divider if necessary.

PLL_R

255

The minimum divide depends on the modulator order,

VCO frequency/core, and choice of internal/external

VCO.

N Divider

PLL_N

≥ 12

32767

The fractional denominator is programmable and can

assume any value between 1 and 2³²– 1; it is not a

fixed denominator.

Fractional

numerator

2³²– 1 =

4294967295

PLL_NUM

1

N Divider

Fractional

Denominator

2³²– 1 =

4294967295

PLL_DEN

MASH_ORDER

EXTPFD_DIV

0

1

Order 0 is integer mode and the order can be

programmed.

Fractional Order

PFD Input Divider

3

External

PFD Path

63

If the VCO frequency exceeds 11 GHz, then use divide

by 2, otherwise use divide by 1 (bypass). After this

divide, the signal also goes through the PLL N Divider.

External

VCO

External VCO

Divider

EXTVCO_DIV

1

2

4

Supports 1, 2 and 4 ONLY. There is an additional

divide-by-2 divider in this block, total pre-divider value

is 2 × SYSREF_DIV_PRE.

Pre-Divider

SYSREF_DIV_PRE

SYSREF

Divider

SYSREF_DIV

None

0

4

2047

4

Total divider value is 2 + SYSREF_DIV.

This is a fixed divide-by-4 divider.

Extra Divide

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Overview (continued)

Table 1. Dividers, Multipliers, and Fractional Settings (continued)

BLOCK

SUB-BLOCK

FIELD

MIN

MAX

COMMENTS

This is a power-of-2 divider that supports 2, 4, 8, 16,

32, 64 and 128.

OUTA Divider

CHDIVA

2

128

This is a power-of-2 divider that supports 2, 4, 8, 16,

32, 64 and 128.

OUTB Divider

CHDIVB

n/a

2

128

Outputs

Below 5.6 GHz, the channel divider is used. 5.6 - 11.2

GHz is direct VCO. 11.2 - 22.4 GHz is using the output

doubler.

Output

Frequency

43.75

22400

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7.2 Functional Block Diagram

RFOUTA_P

RFOUTA_N

VCCBUF

÷1,2,..255

PLL_R

Charge

Pump

VCO Bias and LDO

÷2,4,8,..,128

CHDIVA

PFD

LDO

(Input Path)

x3,x4..x7

MULT

REGIN

CPG

÷2

MUTE

OSCIN_P

OSCIN_N

MUTE & Supply

×2

÷1,2,..4095

PLL_R_PRE

VCCBUF

×2

PLL_N

CHDIVB

RFOUTB_P

RFOUTB_N

VCCBUF

N Divider

Lock

Detection

÷2,4,8,..,128

LD

SYSREF_REPEAT

SYSREF_PULSE

G4

Modulator

VCCDIG

SYSREF_DIV_PRE

÷2,4,8

SYSREF_DIV

SRREQ_P

SRREQ_N

SysRef

Generation

÷4,6,8,.. 4098

÷2

PLL_NUM

PLL_DEN

Register

Readback

MUXOUT

MASH_ORDER

CS#

SCK

SDI

SROUT_P

SROUT_N

SPI Interface

Chip Enable

VCCBUF

Re-clocking

Circuit

Programmable

Delay

JESD_DACx_CTRL

Phase Sync

÷2

CE

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCIN pins are used as a frequency reference input to the device. The input is high impedance and

requires AC-coupling caps at the pin. A CMOS clock or XO can drive the single-ended OSCIN pins. Differential

clock input is also supported, making it easier to interface with high-performance system clock devices such as

TI’s LMK series clock devices. As the OSCIN signal is used as a clock for the VCO calibration, a proper

reference signal must be applied at the OSCIN pin at the time of the VCO needs to calibrate.

7.3.2 Input Path

The reference path consists of an OSCIN doubler (OSC_2X), Pre-R divider, multiplier (MULT) and a Post-R

divider. The OSCIN doubler (OSC_2X) can double up low OSCIN frequencies. Pre-R (PLL_R_PRE) and Post-R

(PLL_R) dividers both divide frequency down while the multiplier (MULT) multiplies frequency up. The purposes

of adding a multiplier is to reduce integer boundary spurs or to increase the phase detector frequency. Use

Equation 1 to calculate the phase detector frequency, f_PD

:

f_PD= f_OSC× OSC_2X × MULT / (PLL_R_PRE × PLL_R)

(1)

7.3.2.1 Input Path Doubler (OSC_2X)

The OSCIN doubler allows one to double the input reference frequency up to 500 MHz. This doubler adds

minimal noise and is useful for raising the phase detector frequency for better phase noise and also to avoid

spurs. When the phase-detector frequency is increased, the flat portion of the PLL phase noise improves. There

are a few considerations when using the Input Path Doubler:

•

The doubler works by acting on both the rising and falling edges of the input signal.

The duty cycle needs to be close to 50%, or else the spurs will be very high.

Using the Input Path Doubler degrades the PLL flicker noise and figure of merit by about 1 dB. However, the

benefit of the higher phase detector frequency outweighs this.

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Feature Description (continued)

7.3.2.2 Pre-R Divider (PLL_R_PRE)

The Pre-R divider is useful for reducing the input frequency so that the programmable multiplier (MULT) can be

used to help meet the maximum 250-MHz input frequency limitation to the PLL-R divider. Otherwise, it does not

have to be used.

7.3.2.3 Programmable Input Multipler (MULT)

The MULT is useful for shifting the phase-detector frequency to avoid integer boundary spurs. The multiplier

allows a multiplication of 3, 4, 5, 6, or 7. There are some considerations when using the input multiplier:

•

The programmable input multiplier cannot be used at the same time that the Input Path Doubler is used.

The programmable input multiplier degrades the PLL figure of merit by about 8 dB. It is for spur mitigation, not

PLL noise improvement.

•

The programmable input multiplier is most effective when VCO frequency is not close to a multiple of the

OSCIN frequency.

7.3.2.4 R Divider (PLL_R)

The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is

used (PLL_R > 1), the input frequency to this divider is limited to 250 MHz.

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the R divider and N-divider, and generates a correction current

corresponding to the phase error until the two signals are aligned in-phase. This charge-pump current is software

programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL. See

Application Information for more information. The polarity of the phase detector is configurable in order to suit for

active loop filter application.

7.3.4 N Divider and Fractional Circuitry

The complete N divider divides down the VCO frequency to the phase detector frequency (f_PD) . The output

frequency of the VCO is changed by changing this total N divider value. The total N divider value consists of an

integer portion and a fractional portion as shown in Equation 2:

N_Total= N_Integer+ N_Fractional= PLL_N + (PLL_NUM / PLL_DEN)

(2)

7.3.4.1 Integer N Divide Portion (PLL_N)

Due to the requirements of the total N divider value to handle fractions and high frequency, there are limitations

based the modulator order and VCO frequency.

When using the internal VCO, the true minimum N divide is based on the VCO core. The VCO core frequencies

may shift some with process, so the most reasonable thing to do is based this on worst case assumption for the

VCO Core.

Table 2. Minimum N Divider Value for Internal VCO

f_VCO

WORST CASE CORE

MASH_ORDER = 0

MASH_ORDER = 1

MASH_ORDER = 2

MASH_ORDER = 3

5.6 - 6.3 GHz

6.3 - 7.1 GHz

7.5 - 8.3 GHz

8.3 - 8.8 GHz

9.2 - 9.4 GHz

9.7 - 10 GHz

VCO1

VCO2

VCO3

VCO4

VCO5

VCO6

VCO7

12

14

16

18

20

18

21

23

26

28

30

33

19

22

24

27

29

31

34

24

26

29

31

33

36

10 - 11.2

GHz

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For the external VCO, the minium N divides are slightly different. In cases where the VCO frequency is higher

than 11.5 GHz, the VCO frequency must be divided by 2 by setting EXTVCO_DIV bit.

Table 3. Minimum N Divider for External VCO

f_VCO/ EXTVCO_DIV

2 - 4 GHz

MASH_ORDER = 0 MASH_ORDER = 1 MASH_ORDER = 2 MASH_ORDER = 3

12

14

16

20

12

15

18

23

28

32

14

18

20

24

29

33

20

24

26

35

4 - 5.5 GHz

5.5 - 7 GHz

7 - 8.5 GHz

8.5 - 10 GHz

10 GHz - 11.5 GHz

7.3.4.2 Fractional N Divide Portion (PLL_NUM and PLL_DEN)

The N-divider includes fractional compensation and can achieve any fractional denominator from 1 to (2³²– 1).

The fractional portion of the total N divide value is N_Fractional= PLL_NUM / PLL_DEN. The higher the

denominator, the finer the resolution step of the output. For example, even when using f_PD= 200 MHz, the output

can increment in steps of 200 MHz / (2³²– 1) = 0.047 Hz.

7.3.4.3 Modulator Order (MASH_ORDER)

The fractional modulator order is programmable and has an impact on spurs. Theoretically, the higher order the

fractional modulator order, the more it pushes the lower frequency spur energy to higher frequency. However,

higher order modulators add more noise and increase the minimum N divide ratio. Modulator orders higher than

one can create sub-fractional spurs, depending on the value of FDEN, which is the value of the denominator of

the fraction PLL_NUM / PLL_DEN after it is reduced to the lowest terms.

Table 4. Rough Guidelines for Choosing MASH_ORDER

MASH_ORDER

WHEN TO USE

Integer mode (MASH_ORDER = 0) is good when the fractional circuitry is not needed. It has the

advantage that it allows the lowest N divider value. Be aware that the output phase cannot be

shifted with MASH_SEED in integer mode.

Integer Mode

The first order modulator is good for situations where the fractional denominator is small.

Theoretically, if FDEN < 7, then all the fractional spurs will be lowest with the first order modulator.

If the fraction is divisible by 2, then there will be sub-fractional spurs which one has to trade-off

with the primary spur level. If the primary fractional spur at offset of f_PD/ FDEN is far outside the

loop bandwidth, this is often a good choice.

1st Order Modulator

The second order modulator gives good spurs. If FDEN is odd, then there are no sub-fractional

spurs, so situations where FDEN > 8 and FDEN is odd, this might make sense. If FDEN is very

large, like 1000000, then the fraction is likely well-randomized and one might consider a third order

modulator, if it does not overly restrict the N divider value.

2nd Order Modulator

3rd Order Modulator

The third order modulator is a good general-purpose starting point if FDEN > 9 and FDEN is not

divisible by 3.

7.3.5 LD Pin Lock Detect

Lock detect gives a rough indication of whether or not the PLL is in lock. There are two general types of lock

detect supported: calibration status and Vtune. The calibration status lock detect is low whenever the VCO is

calibrating or the LD_DLY timeout counter is running. The LD_DLY timeout counter counts to 2047 and each

count is 32 state machine cycles. The Vtune lock detect works by creating an indirect internal voltage that is

intended to mimic the actual voltage at the VTUNE pin. When this voltage goes out of range, the Vtune lock

detect is low. The calibration status and Vtune lock detect can be combined as well. In situations where the VCO

calibration is bypassed, such as full assist mode or instant calibration, then this lock detect serves just the Vtune

function.

7.3.6 MUXOUT Pin and Readback

Readback is useful for getting information regarding the device status. Fields that can be read back are:

1. Raw register values to confirm programming.

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2. VCO lock detect status (rb_LD).

3. VCO calibration information (rb_VCO_SEL; rb_VCO_CAPCTRL; rb_VCO_DACISET).

4. Die temperature (rb_TEMP_SENS). To use this feature, set TEMPSENSE = 1. Equation 3 calculates the

readback temperature:

Temperature [°C] = 0.683075 × rb_TEMP_SENSE – 352.147

(3)

Resolution is 0.6 °C per readback code. Measurement accuracy is ± 5 °C.

7.3.7 Internal VCO

The LMX2820 includes a fully integrated VCO. The VCO takes the voltage from the loop filter and converts this

into a frequency. The VCO frequency is related to the other frequencies as f_VCO= f_PD× (PLL_N + PLL_NUM /

PLL_DEN).

7.3.7.1 VCO Calibration

To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency

range is divided into several different frequency bands. The entire range, 5.6 to 11.2 GHz covers an octave that

allows the divider to take care of frequencies below the lower bound. This creates the need for frequency

calibration to determine the correct frequency band given a desired output frequency. The frequency calibration

routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. It is important that a

valid OSCIN signal must present before VCO calibration begins. The VCO also has an internal amplitude

calibration algorithm to optimize the phase noise which is also activated any time the R0 register is programmed.

The optimum internal settings for this are temperature dependent. The maximum allowable drift for continuous

lock, ΔTCL, is stated in the electrical specifications. For this device, a number of 125 °C means the device never

loses lock if the device is operated under the Recommended Operating Conditions.

7.3.7.1.1 Determining the VCO Gain and Ranges

VCO gain can vary based on core, and this can vary over temperature and process, but the following table gives

a rough guideline of what VCO gain to expect

Table 5. Approximate VCO Gain and Ranges

VCO CORE

VCO1

Fmin (MHz)

5600

Fmax (MHz)

6550

KvcoMax

75

KvcoMin

78

VCO2

6550

7600

85

91

VCO3

7600

8450

104

117

VCO4

8450

9300

110

127

VCO5

9300

9850

113

130

VCO6

9850

10500

11200

125

144

VCO7

10500

119

135

7.3.8 Channel Divider

The channel divider is actually a single divider with multiple segments and tap points that is shared between

RFOUTA and RFOUTB. In general, this can operate as independent divider values with the one exception that if

a divide value of 128 is chosen for one output, then this divide must be chosen for the other output (although the

channel divider can still be bypassed). Note that when the output frequencies are not the same, the higher

frequency output will have sub-harmonic spurs at frequency offset equal to other output.

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MUX

RFOUTA

RFOUTB

7

VCO

÷2,4,8,..,128

MUX

Figure 9. Channel Divider

7.3.9 Output Frequency Doubler

The frequency doubler is used to produce an output frequency that is twice the VCO frequency and is selected

when OUTx_MUX = 2. When the VCO frequency is doubled, the fundamental (non-doubled) VCO frequency

does leak to the output and this is the sub-harmonic (0.5X). To minimize these sub-harmonics, there is tunable

filter that tracks the output frequency and filters out this sub-harmonic as well as other undesired harmonics

(1.5X, 2X, 3X, ...). The calibration for this tunable filter is automatically triggered whenever the VCO calibration is

done.

7.3.10 Output Buffer

The output buffer is an open-collector architecture, but the 50-Ω pullup resistor is integrated within the device. At

lower frequencies, it is fair to assume the output impedance is 50 Ω, but at higher frequencies, parasitic can

cause the output impedance to be different. The OUTx_PWR programming fields set the emitter current and

adjust the power level.

VCCBUF

LMX2820

50 W

RFOUTA_P

OUTA_PWR

Figure 10. Output Buffer Structure

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7.3.11 Power-Down Modes

The LMX2820 can be powered up and down using the CE pin or the POWERDOWN bit. In power-down mode,

the majority of the device is shut down. However, in power-down mode, the device retains its programming

information and can still be programmed, provided that the supply pins still have power applied to them. As this

also powers down the internal LDOs, be aware that programming register R0 with POWERDOWN will re-

calibrate the VCO if FCAL_EN = 1. In this case, one should re-program register R0 with FCAL_EN = 1 to ensure

that this happens with the LDOs at their proper bias level. If the instant calibration is used, then this extra

programming of register R0 is unnecessary.

7.3.12 Phase Synchronization for Multiple Devices

In many situations, a synchronization pulse is needed to ensure that the device has deterministic phase. The

requirements for phase synchronization depend on certain setup conditions. In cases that the timing of the

synchronization pulse is not critical, it can be done through software by toggling the PHASE_SYNC_EN bit from

0 to 1. When it is timing critical, then it must be done through the pin and the setup and hold times for the OSCIN

pin are critical. The following section gives categories for phase sync based on the input and output frequencies.

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7.3.12.1 SYNC Categories

Start

CHDIV Bypassed?

This means the channel divider after the

VCO is bypassed.

M=1?

NO

Category 4

Device can NOT be reliably

used in SYNC mode

This means the input

multiplier is not used.

In other words

NO

M=1

?

CHDIV Bypassed?

f_OSC% f_OUT= 0?

OSC_2X=0 and MULT=1

This means that the input f_OSC

is an integer multiple of the

output f_OUT

.

f_OUT% f_OSC= 0?

This means that the

output f_OUTis an

integer multiple of

NO

f_OSCG 200 MHz

f_OUT% f_OSC= 0

?

f_OSC% f_OUT= 0

?

f_OSC

.

Only 1 Device?

Category 3

ñ SYNC Required

ñ SYNC Timing Critical

ñ Limitations on f_OSC

This means only one

device is involved and

one is not trying to

align clocks between

multiple devices.

Only 1 Device

?

NO

f_OUT%(a| (_OSC)=0

CHDIV Bypassed?

This means the channel

divider after the VCO is

bypassed.

Category 2

ñ SYNC Required

ñ SYNC Timing NOT critical

ñ No limitations on f_OSC

NO

CHDIV Bypassed?

NO

Integer Mode

?

Integer Mode

This is asking if the device is in integer

mode, which would mean the fractional

numerator is zero.

Category 1

ñ SYNC Mode Not required at all

ñ No limitations on f_OSC

Figure 11. Synchronization Flowchart

7.3.12.2 Phase Adjust

7.3.12.2.1 Length of Phase Adjust

The MASH_SEED word can use the sigma-delta modulator to shift output signal phase with respect to the input

reference. If a SYNC pulse is sent (software or pin) or the MASH is reset with MASH_RST_N, then this phase

shift is from the initial phase of zero. The phase shift can be calculated based on the MASH_SEED.

Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN / CHDIV )

(4)

There are a few considerations with MASH_SEED:

•

Phase shift can be done with a PLL_NUM = 0, but MASH_ORDER must be greater than zero.

For MASH_ORDER = 1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN.

Setting MASH_SEED > 0 can impact fractional spurs. If used with a PLL_NUM = 0, it can create fractional

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spurs. If used with a non-zero numerator, it can either help or hurt spurs and this effect can be simulated with

the TI PLLatinum Sim tool.

7.3.12.2.2 Static vs. Dynamic Phase Adjust

The programming of the MASH_SEED word is cumulative. By that it means that the programmed value is added

to the current value. Whenever the MASH_RST_N bit or the VCO is re-calibrated, the current value is set to

MASH_SEED. Static phase adjust would involve setting the MASH_SEED word to the desired value and toggling

the MASH_RST_N bit to force this value. Dynamic phase adjust involves setting MASH_SEED to a smaller value

and repetitively program the MASH_SEED word to add to the cumulative value for MASH_SEED.

7.3.12.2.3 Fine Adjustments to Phase Adjust

Phase SYNC refers to the process of getting the same phase relationship for every power-up cycle and each

time assuming that a given programming procedure is followed. However, there are some adjustments that can

be made to get the most accurate results. As for the consistency of the phase SYNC, the only source of variation

could be if the VCO calibration chooses a different VCO core and capacitor, which can introduce a bimodal

distribution with about 10 ps of variation. If this 10 ps is not desirable, then it can be eliminated by either using

the instant calibration based VCO calibration or Full assist VCO calibration.

The delay through the device varies from part to part and can be on the order of 60 ps. This part to part variation

can be calibrated out with the MASH_SEED. The variation in delay through the device also changes on the order

of +2.5 ps/°C, but devices on the same board likely have similar temperatures, so this will somewhat track. In

summary, the device can be made to have consistent delay through the part and there are means to adjust out

any remaining errors with the MASH_SEED. This tends only to be an issue at higher output frequencies when

the period is shorter.

7.3.13 SYSREF

The LMX2820 can generate a SYSREF output signal that is synchronized to f_OUTwith a programmable delay.

This output can be a single pulse, series of pulses, or a continuous stream of pulses. To use the SYSREF

capability, the PLL must first be placed in SYNC mode with PHASE_SYNC_EN = 1.

SRREQ_N

SRREQ_P

SYSREF_PULSE_CNT

SysRef Pulse

Generator

SROUT_P

SROUT_N

VCCBUF

Re-clocking

Circuit

SYSREF_DIV_PRE

÷2,4,8

SYSREF_DIV

÷4,6,8,.. 4098

From VCO

÷2

SYSREF_REPEAT

SYSREF_PULSE

Programmable

Delay

JESD_DACx_CTRL

÷2

Figure 12. SYSREF Functional Diagram

The SYSREF feature uses SYSREF_DIV_PRE divider to generate f_INTERPOLATOR. This frequency is used for

reclocking of the rising and falling edges at the SRREQ pin. In master mode, the f_INTERPOLATORis further divided

by 2 × SYSREF_DIV to generate finite series or continuous stream of pulses.

7.3.14 Fast VCO Calibration

The time that it takes the VCO to calibrate can be reduced. Table 6 shows the general methods of VCO

calibration:

Table 6. Types of VCO Calibration

CALIBRATION TYPE DESCRIPTION

User does nothing to improve VCO calibration speed, but the user-specified VCO_SEL, VCO_DACISET and

VCO_CAPCTRL values do affect the starting point of VCO calibration.

No Assist

Upon every frequency change, before the FCAL_EN bit is checked, the user provides the initial starting point for the

Partial Assist

VCO core (VCO_SEL), band (VCO_CAPCTRL), and amplitude (VCO_DACISET) based on values specified in the

datasheet.

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Table 6. Types of VCO Calibration (continued)

CALIBRATION TYPE DESCRIPTION

The user forces the VCO core (VCO_SEL), amplitude settings (VCO_DACISET), and frequency band

(VCO_CAPCTRL) and manually sets the value. If the two frequency points are no more than 5 MHz apart and on

the same VCO core, the user can set the VCO amplitude and capcode for any frequency between those two points

using linear interpolation.

Full Assist

The user initializes the device to generate a instant calibration. For as long as power is applied to the device, the

instant calibration can be used to make ultra-fast VCO Calibration

Instant Calibration

7.3.15 Double Buffering (Shadow Registers)

Double buffering—also known as "shadow registers"—allows the user to program multiple registers without

having them actually take effect. Then when the R0 register is programmed, then these registers take effect. This

is especially useful if one wants to change frequencies quickly and multiple register writes are required. When

DBLBUF_EN = 1, the double buffering is enabled for the following registers: PLL_N, PLL_NUM, PLL_DEN,

MULT, PLL_R, PLL_R_PRE, MASH_ORDER, and PFD_DLY.

7.3.16 Output Mute Pin and Ping Pong Approaches

The output buffer can be muted or unmuted using the MUTE pin. The polarity of this pin is programmable with

the PINMUTE_POL bit. When the output is muted, the PLL stays in lock, so this can be used to combine multiple

synthesizers for faster lock time. The PLL with the muted output can be accepting programming commands or

even locking to a new frequency. As the output is muted, the unwanted signal is greatly attenuated and can be

further attenuated with an RF switch.

MUTE

LMX2820

(PINMUTE_POL=0)

SPI1

Output

MUTE

LMX2820

(PINMUTE_POL=1)

RF Switch

SPI2

f_OSCIN

Figure 13. TITLE NEEDED

7.4 Device Functional Modes

There are four basic modes of the LMX2820 that allow the choice of Internal vs. External VCO and Internal PFD

vs. External PFD.

Table 7. Summary of Device Functional Modes

VCO Mode

PFD Choice

Comment

Internal VCO and Phase Detector

Internal

The internal VCO and phase detector provide excellent performance. This mode is the assumed mode of

operation unless otherwise stated.

Internal

Internal VCO with External Phase Detector

External

Using an external mixer and very low noise source, the PLL phase noise can be substantially improved

by lowering the PLL feedback divider value.

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Device Functional Modes (continued)

Table 7. Summary of Device Functional Modes (continued)

VCO Mode

PFD Choice

Comment

External VCO with Internal Phase Detector

For some applications, especially if it is narrowband, an external VCO may be able to provide better

phase noise performance than the internal VCO. There could be an advantage in phase noise and

harmonics if the output divider or doubler can be avoided by using external VCO.

Internal

External

External VCO with External Phase Detector

Theoretically, an external VCO can be used with the external phase detector for the ultimate in phase

noise. This does require a high-performance source, mixer, and VCO to fully take advantage of this

mode.

External

7.4.1 External VCO Mode

An external VCO can also be used with the LMX2820, but note that the output buffers cannot be used while the

SYSREF feature can. The charge pump voltage maximum output voltage is about 2.5 V, but this is not sufficient

for most VCOs. For this reason, an active filter is recommended which can keep the charge pump voltage biased

around 1.2 V and provide the higher output voltage. If the VCO frequency is higher than 11.2 GHz, the FIN_EN

bit must be enabled, otherwise, it should be zero.

Vtune

18 W

Þ

Output

1.2V

+

OSCIN_P

OSCIN_N

÷1,2,..4095

÷1,2,..255

RFOUTA_P

RFOUTA_N

Charge

Pump

÷2,4,8,..,128

PFD

×2

x3,x4..x7

÷2

×2

MUTE

Lock

LD

Detection

RFOUTB_P

RFOUTB_N

N Divider

MUXOUT

SRREQ_P

SRREQ_N

CS#

SCK

SDI

SYSREF

Generation

Digital

Control

G4

Modulator

SROUT_P

SROUT_N

Phase Sync

CE

Figure 14. External VCO Mode

When using the external VCO, the PFD_DLY word must be set manually as shown in Table 8. For the case of an

integrated VCO, it is not necessary to program this word. PFD_DLY_MANUAL = 1 is required to manually set the

PFD_DLY.

Table 8. PFD_DLY_SEL Settings for External VCO Mode

VCO FREQUENCY

2 - 4 GHz

MASH_ORDER = 0

MASH_ORDER = 1

MASH_ORDER = 2

MASH_ORDER = 3

1

2

3

4

5

1

2

3

4

5

2

3

4

5

6

4

5

6

7

8

4 - 5.5 GHz

5.5 - 7 GHz

7 - 8.5 GHz

8.5 - 10 GHz

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Table 8. PFD_DLY_SEL Settings for External VCO Mode (continued)

VCO FREQUENCY

MASH_ORDER = 0

MASH_ORDER = 1

MASH_ORDER = 2

MASH_ORDER = 3

> 10 GHz

6

7

9

7.4.2 External PFD Input

The LMX2820 gives the user the option to mix down the VCO frequency using an external mixer and clean

source for improved PLL noise.

7.4.2.1 External PFD Input Using PFDIN Pin

When doing this, the single PFD mode must be enabled by setting PFD_SINGLE = 3. The figure of merit in

single PFD mode is about 3 dB worse than dual PFD mode, but still there is a net improvement in phase noise

when this is mixed down. Set the PFDIN_PD pin to 0 to use this feature, otherwise, set the pin to 1.

x2

Loop

Filter

PFD

10 GHz

100 MHz

10 GHz

N Divider

200 MHz

1/8

8400 MHz

1600 MHz

Figure 15. External PFD Mode Using PFDIN Input

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Treatment of Unused Pins

In some applications, not all pins are needed. Table 9 discusses how to treat these unused pins.

Table 9. Treatment of Unused Pins

SITUATION

PINS APPLYING TO

COMMENT

AC-couple this pin to GND through a 50-Ω

resistor. For optimal spurs, the impedance

seen looking out of OSCIN_P and OSCIN_N

should be similar

Single-Ended Input

OSCIN_N

Terminate this pin to a load that looks similar

to the output that is used. This is typically a

50-Ω resistor AC-coupled to ground to

minimize harmonics.

Single-Ended Output

Unused Input

RFOUTA_N, RFOUTB_N

RFIN, PFDIN, SRREQ Pins

This pin may be left floating. This feature can

be powered down in software.

This pin may be left floating. This feature can

be powered down in software.

Unused Output

RFOUT Pins, SROUT pins

GND

Unused Digital Pin

Ground this pin.

8.1.2 External Loop Filter

The LMX2820 requires an external loop filter that is application-specific and can be configured by PLLatinum

Sim. For the LMX2820, it matters what impedance is seen from the VTUNE pin looking outwards. This

impedance is dominated by the component C3 for a third order filter or C1 for a second order filter. If there is at

least 1.5 nF for the capacitance that is shunt with this pin, the VCO phase noise will be as close to the best it can

be. If the capacitance is less, the VCO phase noise in the 100-kHz to 1-MHz region will degrade. This capacitor

should be placed close to the VTUNE pin.

8.1.3 Using Instant Calibration

Instant calibration allows the device to very quickly calibrate the VCO in under 5 µs and choose the same

calibration settings (rb_VCO_SEL, rb_VCO_DACISET, rb_VCO_CAPCTRL). Once this feature is initialized, then

there is no overhead in changing the VCO frequency. This initialization is required when the device is initially

powered up, but the settings are retained, provided power is not removed from the supply pins. The following

procedure details how this is done:

1. Power up device Normally.

2. Program INSTCAL_DLY = 1.9 × f_OSC(in MHz)/ 2^CAL_CLK_DIVfor a 1.9-µs wait time, which gives a 5-µs total

calibration time. Although a smaller delay may work, this value is to ensure the best VCO phase noise and to

prevent frequency glitches.

3. Program register R1 for Instant Calibration.

–

Set INSTCAL_EN = 1. The action of toggling INSTCAL_EN from 0 to 1 resets the instant calibration

settings and sets the part up to generate settings the next tiime that register R0 is programmed with

FCAL_EN = 1.

–

If the output doubler is used set INSTCAL_DBLR_EN = 1, otherwise set it to 0

4. Program the device to output 5.6 GHz.

5. Program INSTCAL_PLL_NUM = 2³²× (PLL_NUM / PLL_DEN).

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6. Write R0 with FCAL_EN = 1 to generate the calibration settings.

7. Write R0 with FCAL_EN = 0 to have the device lock to 5.6 GHz

8. Wait for Lock Detect to go high.

Now the device is initialized for the particular phase detector frequency that this was done at. Provided that

power is not removed from the device and then phase detector frequency does not change, subsequent

frequency changes an be done using the instant cal. To change frequencies after the instant calibration is

initialized:

1. Write the values for INSTCAL_PLL_NUM, PLL_N, PLL_NUM, PLL_DEN.

2. Write R0 to trigger Calibration (with DBLR_CAL_EN = 0, FCAL_EN = 0).

8.2 Typical Application

Figure 16. Typical Application Schematic

8.2.1 Design Requirements

The design of the loop filter is complex and is typically done with software. The PLLATINUM Sim software is an

excellent resource for doing this and the design and simulation. In this case, an integer design is assumed and

this is being designed for optimal jitter, as would be the case for many clocking applications. For this example, it

will be assumed that a 6-GHz output will be generated from a 100-MHz clock. From this, the engineer must

choose a VCO frequency and phase detector before proceeding to the loop filter design.

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Typical Application (continued)

The VCO frequency must be in the range of 5.6 to 11.2 GHz, the output frequency must either divide into this or

double the VCO frequency selected (in the case that it is higher than 11.2 GHz). In this case, this implies the

VCO frequency is 6 GHz. The next step is to choose the phase detector frequency. The phase detector

frequency must either divide the input frequency, or it can be double this if the OSC_2X feature is used. Also, if

the phase detector frequency divides the VCO frequency, the spur performance is much better. So by choosing a

200-MHz phase detector frequency and using the OSC_2X doubler, the device can be used in integer mode and

the best phase noise performance can be achieved.

Table 10. Design Parameters

SYMBOL

DESCRIPTION

VALUE

100

UNITS

MHz

f_OSC

f_OUT

This is the input frequency that was given.

This is the output frequency that was given.

6000

MHz

This is the VCO frequency that was chosen to

generate the output frequency.

f_VCO

f_PD

6000

200

MHz

This is the phase detector frequency that was

chosen for the best noise performance.

8.2.2 Detailed Design Procedure

When the frequencies are known, the loop filter must be designed. The integration of phase noise over a certain

bandwidth (jitter) is an performance specification that translates to signal-to-noise ratio. Phase noise inside the

loop bandwidth is dominated by the PLL, while the phase noise outside the loop bandwidth is dominated by the

VCO.

Generally, jitter is lowest if the loop bandwidth is designed to the point where the two intersect. A higher phase

margin loop filter design has less peaking at the loop bandwidth and thus lower jitter. The trade-off with this is

that longer lock times and spurs must be considered in design as well. In Figure 17, the red comparison trace

that represents the actual measured data matches the simulation very closely.

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Figure 17. Loop Filter Design With PLLatinum Sim Tool

8.2.3 Application Curves

The actual phase noise result shows the outstanding result of 36 fs of jitter.

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Figure 18. Typical Application Result

8.3 Initialization Setup and Power on Sequencing

To ensure the proper operation of the device, proper power on sequencing needs to be followed.

1. When power is initially applied, the Power-on Reset (POR) circuitry will reset the registers and state

machines to a default state.

2. Although the POR circuitry does initialize the device, it is good practice to toggle the RESET bit from 1 to 0 to

manually do a software reset. This is necessary to ensure that the internal state machines, bias levels, and

overall device current reset to a stable and consistent condition.

3. Program the registers in descending order. This loads the device to the desired state.

4. Wait 10 ms to allow the internal LDOs to power up.

5. Program the R0 register one more time to activate the VCO calibration with the LDOs in a stable state. Even

if this was done before, the calibration is not valid if it was done before the LDOs in the chip are at the proper

levels. Also, it is important to have a stable and accurate input reference as the VCO calibration is based off

of this. An input reference may be applied earlier to the device without damaging it. This applies to both the

calibration methods with and without instant calibration.

6. After the VCO has calibrated, the frequency will be closer but not exact. The frequency must settle out with

the analog lock time, which adds to the VCO digital calibration.

7. After the analog PLL lock is done, the output is valid. There may be a signal that comes out of the output

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Initialization Setup and Power on Sequencing (continued)

before this, but the frequency may not be valid.

VCC

V_POR

Internal LDOs

Power Up

Vcc

Pins

Dt

GND

Program

Registers

SPI

Interface

VCO/

Output

VCO

Calibration

Valid Output

May have an output, but not necessarily Valid

OSCIN Pin

May apply a signal, but it does not impact device

Valid signal required

Figure 19. Power On Sequencing

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9 Power Supply Recommendations

If fractional spurs are a large concern, using a ferrite bead to each of these power supply pins can reduce spurs

to a small degree. This device has integrated LDOs, which improves the resistance to power supply noise. This

device can be powered by an external DC-DC buck converter, such as the TPS62150. Note that although Rtps,

Rtps1, and Rtps2 are 0 Ω in the schematic, they could be potentially replaced with a larger resistor value or

inductor value for better power supply filtering.

Figure 20. Power Supply Schematic

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10 Layout

10.1 Layout Guidelines

In general, the layout guidelines are similar to most other PLL devices. Here are some specific guidelines.

•

GND pins may be routed on the package back to the DAP.

The OSCIN pins, these are internally biased and must be AC-coupled.

If not used, the SRREQ pins may be grounded to the DAP.

For optimal VCO phase noise in the 200-kHz to 1-MHz range, it is ideal that the capacitor closest to the

VTUNE pin be at least 1.5 nF. As requiring this larger capacitor may restrict the loop bandwidth, this value

can be reduced (to say 1 nF) at the expense of VCO phase noise.

•

If a single-ended output is needed, the other side must have the same loading. However, the routing for the

used side can be optimized by routing the complementary side through a via to the other side of the board.

On this side, make the load look equivalent to the side that is used.

•

Ensure DAP on device is well-grounded with many vias, preferably copper filled.

Have a thermal pad that is as large as the LMX2820 exposed pad. Add vias to the thermal pad to maximize

thermal performance.

•

Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.

10.2 Layout Example

For this layout, all of the loop filter (C1LF, C2LF, C3LF, R2LF and R3LF) are on the top side of the board. C3LF

is located right next to the VTUNE pin. In the event that this C3LF capacitor would be open, TI recommends to

move one of loop capacitors in this spot. For instance, if a 2nd order loop filter was used, technically C3LF would

be open. However, for this layout example that is designed for a 3rd order loop filter, it would be optimal to make

C1LF = open, and C3LF to be whatever C1LF would have been.

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Layout Example (continued)

Figure 21. Layout Example

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

PLLatinum, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RTC0048G

VQFNP - 0.9 mm max height

SCALE 2.100

PLASTIC QUAD FLATPACK - NO LEAD

7.1

6.9

B

A

PIN 1 ID

7.1

6.9

(

6.75)

0.9

0.8

C

SEATING PLANE

0.08 C

(0.2)

0.60

4X 45 X

0.24

EXPOSED

THERMAL PAD

13

24

12

25

SYMM

4X

49

5.7 0.1

5.5

36

1

0.30

0.18

44X 0.5

48X

48

37

SYMM

0.5

0.3

0.1

C B A

C

PIN 1 ID

(R0.2)

48X

0.05

4224759/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTC0048G

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.7)

(1.35)

(1.25)

37

48

48X (0.6)

48X (0.24)

1

36

(1.25)

44X (0.5)

SYMM

(1.35)

49

(6.8)

(

0.2) VIA

TYP

25

12

(R0.05) TYP

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224759/A 01/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTC0048G

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.675)

(1.35)

48

37

48X (0.6)

48X (0.24)

1

36

44X (0.5)

SYMM

(1.35)

(0.675)

(6.8)

49

METAL

TYP

16X ( 1.15)

25

12

(R0.05) TYP

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49:

65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4224759/A 01/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMX2820
厂家：	TEXAS INSTRUMENTS
描述：	LMX2820 22.4-GHz Wideband PLLatinumâ¢ RF Synthesizer With Phase Synchronization and JESD204B Support
文件：	总40页 (文件大小：1534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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