LMX2592RHAT [TI]
具有集成 VCO 的 9.8GHz 宽带频率合成器 | RHA | 40 | -40 to 85;型号: | LMX2592RHAT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成 VCO 的 9.8GHz 宽带频率合成器 | RHA | 40 | -40 to 85 |
文件: | 总49页 (文件大小:2866K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMX2592
ZHCSEK3G –DECEMBER 2015 –REVISED AUGUST 2022
集成了VCO 的LMX2592 高性能宽带PLLatinum™ 射频合成器
1 特性
3 说明
• 输出频率范围为20 至9800MHz
• 相位噪声性能行业领先
LMX2592 是一款集成了 VCO 的低噪声宽带射频
PLL,支持的频率范围为 20MHz 至 9.8GHz。该器件
支持分数 N 和整数 N 模式,具有一个 32 位分数分频
器,支持选择合适的频率。其积分噪声为 49fs(对于
6GHz 输出),是理想的低噪声源。该器件融入了一流
的 PLL 和 VCO 积分噪声与集成的低压线性稳压器
(LDO),从而无需高性能系统中的多个分立器件。
– VCO 相位噪声:在输出为6GHz 且偏移为
1MHz 时为–134.5dBc/Hz
– 归一化PLL 本底噪声:-231dBc/Hz
– 归一化PLL 闪烁噪声:-126dBc/Hz
– 49fs RMS 抖动(12kHz 至20MHz)(对于
6GHz 输出)
该器件可接受高达 1.4GHz 的输入频率,与分频器及可
编程低噪声乘法器相结合,可灵活设置频率。附加的可
编程低噪声乘法器可帮助用户减轻整数边界杂散的影
响。在分数N 模式下,该器件可将输出相位调整 32 位
分辨率。对于需要快速频率变化的应用,该器件支持耗
时小于25µs 的快速校准选项。
• 输入时钟频率高达1400MHz
• 相位检测器频率高达200MHz,
且在整数N 模式中高达400MHz
• 支持分数N 和整数N 模式
• 双差分输出
• 减少毛刺的创新型解决方案
• 可编程相位调整
• 可编程电荷泵电流
使用一个 3.3V 电源即可能实现此性能。该器件支持 2
个差分输出,这两个输出也可灵活配置为单端输出。用
户可选择将其中一个编程为从 VCO (或倍压器)输
出,另一个从通道分配器输出。若不想使用,可分别禁
用每个输出。
• 可编程输出功率水平
• 串行外设接口(SPI) 或uWire(4 线制串行接口)
• 单电源运行:3.3V
封装信息(1)
2 应用
封装尺寸(标称值)
器件型号
说明
• 测试和测量设备
• 国防和雷达
• 微波回程
LMX2592RHAT
LMX2592RHAR
VQFN (40)
6.00mm × 6.00mm
• 高速数据转换器的高性能时钟源
• 卫星通信
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
External Loop Filter
Cpout
(pin 12)
Vtune
(pin 35)
OSCinP
(pin 8)
OSCin
Buffer
Phase
Detector
RFoutAP
RFoutAM
RFoutBM
RFoutBP
MUX
MUX
Vcc
Vcc
Input
Signal
OSCin
Douber
Pre-R
Divider
Post-R
Divider
Multiplier
Charge
Pump
Channel
Divider
ϕ
MUX
OSCinM
(pin 9)
VCO
doubler
Sigma-Delta
Modulator
CSB (pin 24)
Output
Buffer
SCK (pin 16)
SDI (pin 17)
Serial Interface
Control
N Divider
Prescaler
SDO / LD (pin 20)
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS646
LMX2592
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ZHCSEK3G –DECEMBER 2015 –REVISED AUGUST 2022
Table of Contents
7.5 Programming............................................................ 18
7.6 Register Maps...........................................................19
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 37
8.3 Power Supply Recommendations.............................38
8.4 Layout....................................................................... 39
9 Device and Documentation Support............................40
9.1 Device Support......................................................... 40
9.2 Documentation Support............................................ 40
9.3 接收文档更新通知..................................................... 40
9.4 支持资源....................................................................40
9.5 Trademarks...............................................................40
9.6 Electrostatic Discharge Caution................................40
9.7 术语表....................................................................... 40
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements..................................................8
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Functional Description.............................................. 13
7.4 Device Functional Modes..........................................17
Information.................................................................... 40
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision F (October 2017) to Revision G (August 2022)
Page
• 将封装说明从WQFN 更改为VQFN................................................................................................................... 1
• Added a new requirement to Vtune pin description............................................................................................4
• Added HD2 and HD3 information to the Electrical Characteristics table............................................................7
• Removed sentence: The CLK signal should not be high when LE transitions to low.........................................8
• Changed the Channel Divider requirement...................................................................................................... 16
• Added a new register field, VTUNE_ADJ, in register R30................................................................................19
• Changed the position of register field, PFD_CTL, in register R13....................................................................19
• Added read only register R68, R69 and R70....................................................................................................19
• Added additional requirement for register CP_ICOARSE in 表7-16 ...............................................................20
• Added additional information for register MUXOUT_HDRV in 表7-44 ............................................................20
• Added a new register field, VTUNE_ADJ, in 表7-25 .......................................................................................20
• Changed the register R0 FCAL_LPFD_ADJ configurable values.................................................................... 20
• Changed the register R13 PFD_CTL position.................................................................................................. 20
• Added the R68, R69 and R70 register field descriptions..................................................................................20
• Added External Loop Filter section...................................................................................................................36
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 38
Changes from Revision E (July 2017) to Revision F (October 2017)
Page
• Switched the RFoutBP and RFoutBM pins in the pinout diagram...................................................................... 4
• Changed register 7 and the register descriptions of 4, 20 and 46....................................................................19
Changes from Revision D (February 2017) to Revision E (July 2017)
Page
• Changed Channel Divider Setting as a Function of the Desired Output Frequency table................................16
Changes from Revision C (October 2016) to Revision D (January 2017)
Page
• 从特性中删除了< 25µs 快速校准模式项目........................................................................................................1
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• Changed the high level input voltage minimum value of from: 1.8 to: 1.4 ......................................................... 7
• Changed text from: the rising edge of the LE signal to: the rising edge of the last CLK signal.......................... 8
• Changed text from: the shift registers to an actual counter to: the shift registers to a register bank..................8
• Added content to the Voltage Controlled Oscillator section..............................................................................15
• Changed Channel Divider Setting as a Function of the Desired Output Frequency table................................16
• Changed register 0, 22, and 64 descriptions....................................................................................................19
Changes from Revision B (July 2016) to Revision C (September 2016)
Page
• 根据最新文档和翻译标准更新了数据表文本....................................................................................................... 1
• Changed pin 30 name from: Rext to: NC............................................................................................................4
• Changed CDM value from: ±1250 V to: ±750 V................................................................................................. 6
• Changed parameter name from: Maximum reference input frequency to: reference input frequency............... 7
• Removed the charge pump current TYP range '0 to 12' and split range into MIN (0) and MAX (12) columns....
7
• Moved all typical values in the Timing Requirements table to minimum column ...............................................8
• Changed output frequency units from: MHz to: Hz in graphic ......................................................................... 10
• Changed high input value from: 700 to: 200 ....................................................................................................14
• Changed high input value from: 1400 to: 400 ..................................................................................................14
• Changed minimum output frequency step from: Fpd / PLL_DEN to: Fpd × PLL_N_PRE / PLL_DEN / [Channel
divider value].....................................................................................................................................................14
• Changed text from: output dividers to: channel dividers ..................................................................................15
• Changed output frequency from: 3600 to: 3550 .............................................................................................. 16
• Changed VCO frequency from: 7200 to: 7100 ................................................................................................ 16
• Changed Phase shift (degrees) from: 360 × MASH_SEED / PLL_N_DEN / [Channel divider value] to: 360 x
MASH_SEED x PLL_N_PRE / PLL_N_DEN / [Channel divider value]" ..........................................................17
• Changed register 7, 8, 19, 23, 32, 33, 34, 46, and 64 descriptions .................................................................19
• Added registers 20, 22, 25, 59, and 61 ............................................................................................................19
• Changed register descriptions from: Program to default to: Program to Register Map default values.............20
• Updated content in the Decreasing Lock Time section.................................................................................... 35
• Changed typical application image ..................................................................................................................37
• Changed charge pump value from: 4.8 to: 20.................................................................................................. 38
• Changed R2 value from: 0.068 to: 68...............................................................................................................38
Changes from Revision A (December 2015) to Revision B (July 2016)
Page
• Added VCO Calibration Time to Electrical Characteristics ................................................................................ 7
• Added registers 2, 4, and 62 to Register Table ................................................................................................19
• Changed register 38 in Register Table ............................................................................................................ 19
• Added R2 Register Field Descriptions .............................................................................................................20
• Added R4 Register Field Descriptions .............................................................................................................20
• Added R62 Register Field Descriptions ...........................................................................................................20
Changes from Revision * (December 2015) to Revision A (December 2015)
Page
• 将器件状态从“产品预发布”更新至“量产数据”并发布了完整数据表............................................................ 1
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ZHCSEK3G –DECEMBER 2015 –REVISED AUGUST 2022
5 Pin Configuration and Functions
CE
GND
1
2
3
4
5
6
7
8
9
30 NC
29 VrefVCO2
28 NC
VbiasVCO
GND
27 VbiasVCO2
26 VccVCO2
25 GND
NC
GND
GND
VccDIG
OSCinP
OSCinM
24 CSB
23 RFoutAP
22 RFoutAM
21 VccBUF
VregIN 10
图5-1. RHA Package 40-Pin VQFN Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
CE
NO.
1
Input
Chip Enable input. Active high powers on the device.
CPout
12
Output
Charge pump output. Recommend connecting C1 of loop filter close to pin.
SPI chip select bar or uWire latch enable (abbreviated as LE in 图6-1). High
impedance CMOS input. 1.8 to 3.3-V logic.
CSB
DAP
GND
24
Input
GND
Ground
Ground
RFout ground.
VCO ground.
2, 4, 6, 13, 14, 25,
31, 34, 39, 40
Programmable with register MUXOUT_SEL to be readback SDO or lock detect
indicator (active high).
MUXout
NC
20
5, 28, 30, 32
8
Output
Not connected.
—
Differential reference input clock (+). High input impedance. Requires connecting
series capacitor (0.1-µF recommended).
OSCinP
Input
Differential reference input clock (–). High input impedance. Requires connecting
series capacitor (0.1-µF recommended).
OSCinM
RFoutAM
RFoutAP
RFoutBP
RFoutBM
SCK
9
Input
Output
Output
Output
Output
Input
Differential output A (–). This output requires a pullup component for proper biasing.
A 50-Ωresistor or inductor may be used. Place as close to output as possible.
22
23
19
18
16
Differential output A (+). This output requires a pullup component for proper biasing.
A 50-Ωresistor or inductor may be used. Place as close to output as possible.
Differential output B (+). This output requires a pullup component for proper biasing.
A 50-Ωresistor or inductor may be used. Place as close to output as possible.
Differential output B (–). This output requires a pullup component for proper biasing.
A 50-Ωresistor or inductor may be used. Place as close to output as possible.
SPI or uWire clock (abbreviated as CLK in 图6-1). High impedance CMOS input. 1.8
to 3.3-V logic.
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
SPI or uWire data (abbreviated as DATA in 图6-1). High impedance CMOS input.
1.8 to 3.3-V logic.
SDI
17
Input
VCO varactor internal voltage, access for bypass. Requires connecting 10-µF
capacitor to VCO ground.
VbiasVARAC
VbiasVCO
33
3
Bypass
Bypass
VCO bias internal voltage, access for bypass. Requires connecting 10-µF capacitor
to VCO ground. Place close to pin.
VCO bias internal voltage, access for bypass. Requires connecting 1-µF capacitor to
VCO ground.
VbiasVCO2
VCCBUF
VCCCP
27
21
11
Bypass
Supply
Supply
Output buffer supply. Requires connecting 0.1-µF capacitor to RFout ground.
Charge pump supply. Recommend connecting 0.1-µF capacitor to charge pump
ground.
VCCDIG
7
Supply
Supply
Supply
Supply
Digital supply. Recommend connecting 0.1-µF capacitor to digital ground.
Digital supply. Recommend connecting 0.1-µF and 10-µF capacitor to digital ground.
VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to VCO ground.
VCCMASH
VCCVCO
VCCVCO2
15
37
26
VCO supply internal voltage, access for bypass. Requires connecting 10-µF
capacitor to ground.
VrefVCO
VrefVCO2
VregIN
36
29
10
38
35
Bypass
Bypass
Bypass
Bypass
Input
VCO supply internal voltage, access for bypass. Requires connecting 10-µF
capacitor to VCO ground.
Input reference path internal voltage, access for bypass. Requires connecting 1-µF
capacitor to ground. Place close to pin.
VCO supply internal voltage, access for bypass. Requires connecting 1-µF capacitor
to ground.
VregVCO
Vtune
VCO tuning voltage input. This signal should be kept away from noise sources.
Connect a 3.3-nF or more capacitor to VCO ground.
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ZHCSEK3G –DECEMBER 2015 –REVISED AUGUST 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
3.6
UNIT
V
VCC
VIN
Power supply voltage
Input voltage to pins other than VCC pins
VCC + 0.3
V
≤1.8 with VCC ≤1 with VCC
=
VOSCin
Voltage on OSCin (pin 8 and pin 9)
Vpp
Applied
0
TL
Lead temperature (solder 4 s)
Junction temperature
260
150
150
°C
°C
°C
TJ
–40
–65
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Machine model (MM) ESD stress voltage
V(ESD)
V
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2500 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1250 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.15
–40
NOM
MAX
3.45
85
UNIT
V
VCC
TA
Power supply voltage
Ambient temperature
Junction temperature
°C
TJ
125
°C
6.4 Thermal Information
LMX2592
THERMAL METRIC(1)
RHA (VQFN)
40 PINS
30.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.3
5.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
5.3
ψJB
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
3.15 V ≤VCC ≤3.45 V, –40°C ≤TA ≤85°C.
Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
VCC
ICC
IPD
Supply voltage
Supply current
Powerdown current
3.3
250
3.7
V
Single 6-GHz, 0-dBm output(1)
mA
mA
OUTPUT CHARACTERISTICS
Fout
Output frequency
20
9800
800
MHz
dBm
Output = 3 GHz, 50-Ωpullup, single-
Pout
Typical high output power
8
ended(2)
Reference input = 100 MHz, 7-GHz
desired output(8)
Tcal
VCO calibration time
590
µs
INPUT SIGNAL PATH
REFin
REFv
Reference input frequency
5
1400
2
MHz
Reference input voltage
AC-coupled, differential(3)
0.2
Vppd
Input signal path multiplier input
frequency
MULin
40
70
MHz
MHz
Input signal path multiplier output
frequency
MULout
180
250
PHASE DETECTOR AND CHARGE PUMP
5
0.25
0
200
400
12
MHz
MHz
mA
PDF
Phase detector frequency
Extended range mode(4)
Programmable
CPI
Charge pump current
PLL PHASE NOISE
PLL_flicker_Nor
Normalized PLL Flicker Noise(5)
dBc/Hz
dBc/Hz
–126
–231
m
Normalized PLL Noise Floor (PLL
Figure of Merit)(5)
PLL_FOM
VCO
Allowable temperature drift(6)
Output = 3 GHz
VCO not being recalibrated
100 kHz
125
°C
|ΔTCL
|
–118.8
–140.3
–155.1
–156.3
–112.6
–134.2
–152.6
–156.2
–108.2
–129.1
–140.5
–141.1
1 MHz
10 MHz
100 MHz
100 kHz
1 MHz
PNopen loop
Output = 6 GHz
dBc/Hz
10 MHz
100 MHz
100 kHz
1 MHz
Output = 9.8 GHz
10 MHz
100 MHz
HARMONIC DISTORTION(7)
HD_fund
8 GHz,
Harmonic Distortion fundamental feed- VCO
Fundamental (4 GHz)
–26
through with doubler enabled
doubler
enabled
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3.15 V ≤VCC ≤3.45 V, –40°C ≤TA ≤85°C.
Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Testing output A, output at 5 GHz, output
power level at 8.5-dBm, single-ended
output, other end terminated with 50 Ω.
HD2
HD3
2nd Order Harmonic Distortion(9)
dBc
–27
3rd Order Harmonic Distortion(9)
dBc
–25
DIGITAL INTERFACE
VIH
VIL
IIH
High level input voltage
1.4
0
VCC
0.4
25
V
V
Low level input voltage
High level input current
Low level input current
µA
µA
–25
–25
IIL
25
VCC –
VOH
High level output voltage
V
Load/Source Current of –350 µA
0.4
VOL
Low level output voltage
Highest SPI write speed
SPI read speed
Load/Sink Current of 500 µA
0.4
75
50
V
SPIW
SPIR
MHz
MHz
(1) For typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, pre-R divider bypassed,
multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off,
one output on, 6GHz output frequency, 50-Ωoutput pullup, 0-dBm output power (differential). See the Application and Implementation
section for more information.
(2) For a typical high output power for a single-ended output, with 50-Ωpullup on both M and P side, register OUTx_POW = 63. Un-used
side terminated with 50-Ωload.
(3) There is internal voltage biasing so the OSCinM and OSCinP pins must always be AC-coupled (capacitor in series). Vppd is differential
peak-to-peak voltage swing. If there is a differential signal (two are negative polarity of each other), the total swing is one subtracted by
the other, each should be 0.1 to 1-Vppd. If there is a single-ended signal, it can have 0.2 to 2 Vppd. See the Application and
Implementation section for more information.
(4) To use phase detector frequencies lower than 5-MHz set register FCAL_LPFD_ADJ = 3. To use phase detector frequencies higher
than 200 MHz, you must be in integer mode, set register PFD_CTL = 3 (to use single PFD mode), set FCAL_HPFD_ADJ = 3. For
more information, see the Detailed Description section.
(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat
components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 ×
log(Fvco / 1GHz) –10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as
PLL_Noise = 10 × log(10PLL_Flat / 10 + 10PLL_flicker / 10).
(6) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial
temperature and allowing this temperature to drift without reprogramming the device, and still have the device stay in lock. This change
could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating
temperatures of the device.
(7) Not tested in production. Typical numbers from characterization with output settings: 50-Ωpullup, OUTA_POW = 15, channel divider
off.
(8) The is the calibration time from the time of FCAL_EN = 1 is triggered to the calibration algorithm completing and output at 7 GHz. A
reference input signal of 100 MHz is used and register CAL_CLK_DIV = 0 for state machine clock to be 100 MHz. Faster calibration
times can be achieve through changes of other register settings. See the Application and Implementation section for more information.
This parameter is ensured by bench.
(9) This parameter is verified by characterization on evaluation board, not tested in production.
6.6 Timing Requirements
3.15 V ≤VCC ≤3.45 V, –40°C ≤TA ≤85°C, except as specified. Typical values are at VCC = 3.3 V, TA = 25°C
MIN
TYP
MAX UNIT
MICROWIRE TIMING
tES
Clock to enable low time
5
2
2
5
5
5
2
ns
ns
ns
ns
ns
ns
ns
tCS
Data to clock setup time
Data to clock hold time
Clock pulse width high
Clock pulse width low
Enable to clock setup time
Enable pulse width high
tCH
tCWH
tCWL
tCES
tEWH
See 图6-1
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DATA
MSB
LSB
tt
CS
t
tt
t
CH
CLK
t
tt
CWL
t
tt
CWH
t
tt
ES
t
CES
LE
t
EWH
图6-1. Serial Data Input Timing Diagram
There are several considerations for programming:
• A slew rate of at least 30 V/µs is recommended for the CLK, DATA, LE
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the last
CLK signal, the data is sent from the shift registers to a register bank
• The LE pin may be held high after programming and clock pulses are ignored
• When CLK and DATA lines are shared between devices, TI recommends diving down the voltage to the CLK,
DATA, and LE pins closer to the minimum voltage. This provides better noise immunity
• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines
are shared with other parts, the phase noise may be degraded during the time of this programming
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6.7 Typical Characteristics
TA = 25°C (unless otherwise noted)
-50
-50
-60
Output = 3 GHz
Output = 3 GHz
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Offset (Hz)
1M
10M
1k
10k
100k
Offset (Hz)
1M
10M
D002
D004
D005
D001
D003
D005
图6-3. 3-GHz Output - Open-Loop Phase Noise
图6-2. 3-GHz Output - Closed-Loop Phase Noise
-50
-50
Output = 6 GHz
Output = 6 GHz
-60
-70
-60
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Offset (Hz)
1M
10M
1k
10k
100k
Offset (Hz)
1M
10M
图6-4. 6-GHz Output - Closed-Loop Phase Noise
图6-5. 6-GHz Output - Open-Loop Phase Noise
-40
0
Output = 9.8 GHz
VCO direct = 4900 MHz
VCO doubler enabled = 9800 MHz
-50
-60
-20
-40
-70
-80
-60
-90
-80
-100
-110
-120
-130
-140
-150
-160
-100
-120
-140
-160
-180
1k
10k
100k
Offset (Hz)
1M
10M
100
1k
10k
100k
Offset (Hz)
1M
10M
图6-6. 9.8-GHz Output - Closed-Loop Phase Noise
图6-7. 9.8-GHz Output - Open-Loop Phase Noise
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6.7 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
-50
-90
-95
49 fs jitter for 6-GHz output
(integrate 12k to 20 MHz)
Data
-60
-70
Flicker
Flat
Model
-80
-100
-105
-110
-115
-120
-125
-90
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Offset (Hz)
1M
10M
1k
10k
100k
1M
Offset (Hz)
D007
D008
图6-8. Integrated Jitter (49 fs) - 6-GHz Output
图6-9. 6-GHz Output Wide Loop Bandwidth –Showing PLL
Performance
-70
-80
-50
Output = 6000 M (at -40°C)
Output = 6000 M (at 25°C)
Output = 6000 M (at 85°C)
3.3 V on VCC
3.3 V + 10-mVpp (830-kHz)
ripple on VCC
-60
-70
-90
-80
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Offset (Hz)
1M
10M
1k
10k
100k
Offset (Hz)
1M
10M
D009
D010
图6-10. Variation of Phase Noise Across Temperature
图6-11. Impact of Supply Ripple on 6-GHz Output Phase Noise
10
14
18-nH pull-up - 5400
50-W pull-up - 5400
13
12
11
10
9
8
6
4
2
8
7
6
5
4
3
-40°C
25°C
85°C
0
2
1
-2
0
100M
1G
Output Frequency (Hz)
10G
2 4 6 8 10121416182022242628304850525456586062
Output Power Code (OUTx_POW)
D011
D012
图6-12. High Output Power (50-ΩPullup, Single-Ended) vs
图6-13. Output Power at 5.4-GHz Output vs OUTx_POW Code (1
Output Frequency
- 31, 48 - 63)
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6.7 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
-50
5.4-GHz output with 20-MHz PFD spur
-60
8
7
6
5
4
Calibrating to 6G (GHz)
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Offset (Hz)
1M
10M
0
10
20
30
40
50
D013
Time (µs)
D014
图6-14. Typical PFD Spur for 5.4-GHz Output
图6-15. 20-µs Frequency Change Time to 6 GHz With Fast
Calibration
-60
-70
-140
5400-MHz VCO direct
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Approximate Noise Floor (dBc/Hz)
Approximate VCO Doubler Noise
Floor (dBc/Hz)
-80
-145
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-150
-155
-160
-165
100
1k
10k
100k
Offset (Hz)
1M
10M
0
2000
4000 6000
Output Frequency (MHz)
8000
10000
D015
D016
图6-16. Impact of Channel Divider Settings on Phase Noise
图6-17. Noise Floor Variation With Output Frequency
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7 Detailed Description
7.1 Overview
The LMX2592 is a high performance wideband synthesizer (PLL with integrated VCO). The output frequency
range is from 20 MHz to 9.5 GHz. The VCO core covers an octave from 3.55 to 7.1 GHz. The output channel
divider covers the frequency range from 20 MHz to the low bound of the VCO core. The VCO-doubler covers the
frequency range from the upper bound of the VCO to 9800MHz.
The input signal frequency has a wide range from 5 to 1400 MHz. Following the input, there is an programmable
OSCin doubler, a pre-R divider (previous to multiplier), a multiplier, and then a post-R divider (after multiplier) for
flexible frequency planning between the input (OSCin) and the phase detector.
The phase detector (PFD) can take frequencies from 5 to 200 MHz, but also has extended modes down to 0.25
MHz and up to 400 MHz. The phase-lock loop (PLL) contains a Sigma-Delta modulator (1st to 4th order) for
fractional N-divider values. The fractional denominator is programmable to 32-bit long, allowing a very fine
resolution of frequency step. There is a phase adjust feature that allows shifting of the output phase in relation to
the input (OSCin) by a fraction of the size of the fractional denominator.
The output power is programmable and can be designed for high power at a specific frequency by the pullup
component at the output pin.
The digital logic is a standard 4-wire SPI or uWire interface and is 1.8-V and 3.3-V compatible.
7.2 Functional Block Diagram
CP_ICOARSE
CP_IUP
CP_IDN
MUX
OSCin
Douber
Pre-R
Divider
Post-R
Divider
Multiplier
MULT
Charge
Pump
Channel
Divider
MUX
OSC_2X
PLL_R_PRE
PLL_R
VCO
doubler
REF_EN
MUX
VCO_2X_EN
Sigma-Delta
Modulator
PFD_DLY
MASH_ORDER
CHDIV_SEG1
CHDIV_SEG2
CHDIV_SEG3
CHDIV_SEG_SEL
OUTx_MUX OUTx_PD
OUTx_POW
N Divider
PLL_N
Prescaler
PLL_N_PRE
7.3 Functional Description
7.3.1 Input Signal
An input signal is required for the PLL to lock. The input signal is also used for the VCO calibration, so a proper
signal needs to be applied before the start of programming. The input signal goes to the OSCinP and OSCinM
pins of the device (there is internal biasing which requires AC-coupling caps in series before the pin). This is a
differential buffer so the total swing is the OSCinM signal subtracted by the OSCinP signal. Both differential
signals and single-ended signal can be used. Below is an example of the max signal level in each mode. It is
important to have proper termination and matching on both sides (see Application and Implementation).
Single-ended Input
Differential Input
OSCinP (pin 8) OSCin Buffer
1 V
0.5 V
Vbias
-0.5 V
-1 V
OSCinP (pin 8) OSCin Buffer
+0.5 V
Vbias
1 V
0.5 V
Vbias
-0.5 V
-1 V
1 V
0.5 V
Vbias
-0.5 V
-1 V
-0.5 V
+0.5 V
Vbias
-0.5 V
OSCinM
(pin 9)
OSCinM
(pin 9)
图7-1. Differential vs. Single-Ended Mode
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7.3.2 Input Signal Path
The input signal path contains the components between the input (OSCin) buffer and the phase detector. The
best PLL noise floor is achieved with a 200-MHz input signal for the highest dual-phase detector frequency. To
address a wide range of applications, the input signal path contains the below components for flexible
configuration before the phase detector. Each component can be bypassed. See 表 7-1 for usage boundaries if
engaging a component.
• OSCin doubler: This is low noise frequency doubler which can be used to multiply input frequencies by two.
The doubler uses both the rising and falling edge of the input signal so the input signal must have 50% duty
cycle if enabling the doubler. The best PLL noise floor is achieved with 200-MHz PFD, thus the doubler is
useful if, for example, a very low-noise, 100-MHz input signal is available instead.
• Pre-R divider: This is a frequency divider capable of very high frequency inputs. Use this to divide any input
frequency up to 1400-MHz, and then the post-R divider if lower frequencies are needed.
• Multiplier: This is a programmable, low noise multiplier. In combination with the Pre-R and Post-R dividers,
the multiplier offers the flexibility to set a PFD away from frequencies that may create critical integer boundary
spurs with the VCO and output frequencies. See the Application and Implementation section for an example.
The user should not use the doubler while using the low noise programmable multiplier.
• Post-R divider: Use this divider to divide down to frequencies below 5 MHz in extended PFD mode.
表7-1. Boundaries for Input Path Components
INPUT
OUTPUT
LOW (MHz)
HIGH (MHz)
1400
200
LOW (MHz)
HIGH (MHz)
Input signal
OSCin doubler
Pre-R divider
Multiplier
5
5
10
5
400
700
250
125
10
40
5
1400
70
180
0.25
Post-R divider
PFD
250
0.25
400
7.3.3 PLL Phase Detector and Charge Pump
The PLL phase detector, also known as phase frequency detector (PFD), compares the outputs of the post-R
divider and N divider and generates a correction current with the charge pump corresponding to the phase error
until the two signals are aligned in phase (the PLL is locked). The charge pump output goes through external
components (loop filter) which turns the correction current pulses into a DC voltage applied to the tuning voltage
(Vtune) of the VCO. The charge pump gain level is programmable and allow to modify the loop bandwidth of the
PLL.
The default architecture is a dual-loop PFD which can operate between 5 to 200 MHz. To use it in extended
range mode the PFD has to be configured differently:
• Extended low phase detector frequency mode: For frequencies between 250 kHz and 5 MHz, low PFD mode
can be activated (FCAL_LPFD_ADJ = 3). PLL_N_PRE also needs to be set to 4.
• Extended high phase detector frequency mode: For frequencies between 200 and 400 MHz, high PFD mode
can be activated (FCAL_HPFD_ADJ = 3). The PFD also has to be set to single-loop PFD mode (PFD_CTL =
3). This mode only works if using integer-N, and PLL noise floor will be about 6-dB higher than in dual-loop
PFD mode.
7.3.4 N Divider and Fractional Circuitry
The N divider (12 bits) includes a multi-stage noise shaping (MASH) sigma-delta modulator with programmable
order from 1st to 4th order, which performs fractional compensation and can achieve any fractional denominator
from 1 to (232 – 1). Using programmable registers, PLL_N is the integer portion and PLL_NUM / PLL_DEN is
the fractional portion, thus the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows
the output frequency to be a fractional multiplication of the phase detector frequency. The higher the
denominator the finer the resolution step of the output. There is a N divider prescaler (PLL_N_PRE) between the
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VCO and the N divider which performs a division of 2 or 4. 2 is selected typically for higher performance in
fractional mode and 4 may be desirable for lower power operation and when N is approaching max value.
Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)
Minimum output frequency step = Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]
Typically, higher modulator order pushes the noise out in frequency and may be filtered out with the PLL.
However, several tradeoff needs to be made. 表 7-2 shows the suggested minimum N value while in fractional
mode as a function of the sigma-delta modulator order. It also describe the recommended register setting for the
PFD delay (register PFD_DLY_SEL).
表7-2. MASH Order and N Divider
INTEGER-N
1st ORDER
2nd ORDER
3rd ORDER
4th ORDER
Minimum N divider (low bound)
9
1
11
1
16
2
18
2
30
8
PFD delay recommended setting (PFD_DLY_SEL)
7.3.5 Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) is fully integrated. The frequency range of the VCO is from 3.55 to 7.1
GHz so it covers one octave. Channel dividers allow the generation of all other lower frequencies. The VCO-
doubler allow the generation of all other higher frequencies. The output frequency of the VCO is inverse
proportional to the DC voltage present at the tuning voltage point on pin Vtune. The tuning range is 0 V to 2.5 V.
0 V generates the maximum frequency and 2.5 V generates the minimum frequency. This VCO requires a
calibration procedure for each frequency selected to lock on. Each VCO calibration will force the tuning voltage
to mid value and calibrate the VCO circuit. Any frequency setting in fast calibration occurs in the range of Vtune
pin 0 V to 2.5 V. The VCO is designed to remained locked over the entire temperature range the device can
support. 表7-3 shows the VCO gain as a function of frequency.
表7-3. Typical kVCO
VCO FREQUENCY (MHz)
kVCO (MHz/V)
3700
4200
4700
5200
5700
6200
6800
28
30
33
36
41
47
51
7.3.6 VCO Calibration
The VCO calibration is responsible of setting the VCO circuit to the target frequency. The frequency calibration
routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. A valid input (OSCin)
signal to the device must present before the VCO calibration begins. To see how to reduce the calibration time,
refer to the Application and Implementation section.
7.3.7 VCO Doubler
To go above the VCO upper bound, the VCO-doubler must be used (VCO_2X_EN=1). The doubling block can
be enabled while the VCO is between 3.55 GHz (lowest VCO frequency) and 4.9 GHz. When VCO doubler is
enabled, the N divider prescalar is automatically forced to divide by 4.
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7.3.8 Channel Divider
1
2
MUX
Divide by
2 or 3
Divide by
2,4,6, or 8
Divide by
2,4,6, or 8
4
CHDIV_SEG_SEL
CHDIV_SEG1
CHDIV_SEG2
CHDIV_SEG3
图7-2. Channel Divider Diagram
To go below the VCO lower bound, the channel divider must be used. The channel divider consists of three
programmable dividers controlled by the registers CHDIV_SEG1, CHDIV_SEG2, CHDIV_SEG3. The Multiplexer
(programmed with register CHDIV_SEG_SEL) selects which divider is included in the path. The minimum
division is 2 while the maximum division is 192. Un-used dividers can be powered down to save current
consumption. The entire channel divider can be powered down with register CHDIV_EN = 0 or selectively setting
registers CHDIV_SEG1_EN = 0, CHDIV_SEG2_EN = 0 ,CHDIV_SEG3_EN = 0. Unused buffers may also be
powered down with registers CHDIV_DISTA_EN and CHDIV_DIST_EN. There are restrictions on the maximum
VCO frequency when channel divider is engaged.
表7-4. Channel Divider vs VCO Frequency
OUTPUT FREQUENCY (MHz)
CHDIV SEGMENT
TOTAL
VCO FREQUENCY (MHz)
DIVISION
MIN
1775
1184
888
592
444
296
222
148
111
99
MAX
3550
2200
1184
888
592
444
296
222
148
111
99
SEG1
SEG2
SEG3
MIN
3550
3552
3552
3552
3552
3552
3552
3552
3552
3564
3552
3584
3552
3584
3840
MAX
7100
6600
4736
5328
4736
5328
4736
5328
4736
3996
4752
4736
5376
4736
5376
2
3
2
3
2
2
2
3
2
3
3
2
2
2
3
1
1
2
2
4
6
8
8
8
6
8
8
8
8
8
1
1
1
1
1
1
1
1
2
2
2
4
6
8
8
2
3
4
6
8
12
16
24
32
36
48
64
96
128
192
74
56
74
37
56
28
37
20
28
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7.3.9 Output Distribution
VCO_DISTA_PD
1
OUTA_MUXSEL
MUX
CHDIV_DISTA_EN
Output Buffer A
0
0
Channel
Divider
VCO
CHDIV_DIST_PD
CHDIV_DISTB_EN
VCO_DISTB_PD
MUX
Output Buffer B
OUTB_MUXSEL
1
图7-3. Output Distribution Diagram
For each output A or B, there is a mux which select the VCO output directly or the channel divider output. Before
these selection MUX there are several buffers in the distribution path which can be configured depending on the
route selected. By disabling unused buffers, unwanted signals can be isolated and unneeded current
consumption can be eliminated.
7.3.10 Output Buffer
Each output buffer (A and B) have programmable gain with register OUTA_POW and OUTB_POW. The RF
output buffer configuration is open-collector and requires an external pullup from RFout pin to VCC. There are
two pullup options that can be used with either resistor or inductor. Refer to the Application and Implementation
section for design considerations.
1. Resistor pullup: placing a 50-Ωresistor pullup matches the output impedance to 50-Ω. However, maximum
output power is limited. Output buffer current settings should be set to a value before output power is
saturated (output power increases less for every step increase in output current value).
2. Inductor pullup: placing an inductor pullup creates a resonance at the frequency of interest. This offers
higher output power for the same current and higher maximum output power. However, the output
impedance is higher and additional matching may be required..
7.3.11 Phase Adjust
In fractional mode, the phase relationship between the output and the input can be changed with very fine
resolution. Every time MASH_SEED register is written, it will trigger a phase shift of the amount described in 方
程式1. The seed value should be less then the fractional-N denominator register PLL_N_DEN. The actual phase
shift can be obtained with the following equation:
Phase shift (degrees) = 360 × MASH_SEED × PLL_N_PRE / PLL_N_DEN / [Channel divider value]
(1)
7.4 Device Functional Modes
7.4.1 Power Down
Power up and down can be achieved using the CE pin (logic HIGH or LOW voltage) or the POWERDOWN
register bit (0 or 1). When the device comes out of the powered-down state, either by pulling back CE pin HIGH
(if it was powered down by CE pin) or by resuming the POWERDOWN bit to 0 (if it was powered down by
register write), it is required that register R0 be programmed again to re-calibrate the device.
7.4.2 Lock Detect
The MUXout pin can be configured to output a signal that gives an indication for the PLL being locked. If lock
detect is enabled (LD_EN = 1) and the MUXout pin is configured as lock detect output (MUXOUT_SEL = 1),
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when the device is locked, the MUXout pin output is a logic HIGH voltage, and when the device is unlocked,
MUXout output is a logic LOW voltage.
7.4.3 Register Readback
The MUXout pin can be programmed (MUXOUT_SEL = 0) to use register readback serial data output. Timing
requirements for MUXout to CLK follow the same specifications as Data to CLK in Timing Requirements. To read
back a certain register value, use the following steps:
1. Set the R/W bit to 1; the data field contents are ignored.
2. Program this register to the device, readback serial data will be output starting at the 9th clock.
R/W
= 1
Address
7-bit
Data
= Ignored
DATA
CLK
1st
2nd - 8th
9th - 24th
Read back register value
16-bit
MUXout
LE
图7-4. Register Readback Timing Diagram
7.5 Programming
The programming using 24-bit shift registers. The shift register consists of a R/W bit (MSB), followed by a 7-bit
address field and a 16-bit data field. For the R/W (bit 23), 1 is read and 0 is write. The address field ADDRESS
(bits 22:16) is used to decode the internal register address. The remaining 16 bits form the data field DATA (bits
15:0). While CSB is low, serial data is clocked into the shift register upon the rising edge of clock (data is
programmed MSB first). When CSB goes high, data is transferred from the data field into the selected register
bank.
7.5.1 Recommended Initial Power on Programming Sequence
When the device is first powered up, the device needs to be initialized and the ordering of this programming is
very important. After this sequence is completed, the device should be running and locked to the proper
frequency.
1. Apply power to the device and ensure the VCC pins are at the proper levels
2. Ensure that a valid reference is applied to the OSCin pin
3. Soft reset the device (write R0[1] = 1)
4. Program the remaining registers
5. Frequency calibrate (write R0[3] = 1)
7.5.2 Recommended Sequence for Changing Frequencies
The recommended sequence for changing frequencies is as follows:
1. Set the new N divider value (write R38[12:1])
2. Set the new PLL numerator (R45 and R44) and denominator (R41 and R40)
3. Frequency calibrate (write R0[3] = 1)
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7.6 Register Maps
7.6.1 LMX2592 Register Map –Default Values
图7-5. Register Table
REG 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/
W
ADDRESS[6:0]
DATA [15:0]
0
R/
W
0
0
0
0
0
0
0
0
0
LD_EN
0
0
0
1
FCAL_HPFD FCAL_LPFD_ ACA FCAL_EN MUXO RES POWE
_ADJ
ADJ
L_E
N
UT_S
EL
ET
RDOW
N
1
2
4
7
8
R/
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
CAL_CLK_DIV
R/
W
0
0
0
1
0
1
1
0
0
R/
W
ACAL_CMP_DLY
1
0
0
R/
W
0
0
0
0
1
0
1
1
0
0
0
0
0
0
R/
W
VCO_ID
AC_OV
R
VCO_
CAPC
TRL_
OVR
9
R/
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
OSC
_2X
0
REF_E
N
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
10
11
12
13
14
19
20
22
23
R/
W
MULT
R/
W
PLL_R
R/
W
PLL_R_PRE
R/
W
CP_E
N
0
0
0
0
0
0
0
0
0
0
1
PFD_CTL
R/
W
0
0
0
0
CP_IDN
CP_IUP
CP_ICOARSE
R/
W
VCO_IDAC
0
1
R/
W
0
0
0
0
0
1
0
ACAL_VCO_IDAC_STRT
VCO_CAPCTRL
R/
W
1
0
R/
W
FCAL
_VC
O_S
EL_S
TRT
VCO_SEL
VCO_
SEL_
FORC
E
0
1
0
0
0
0
1
0
24
25
28
29
30
R/
W
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
R/
W
R/
W
R/
W
R/
W
MASH
_DITH
ER
VTUNE_ADJ
VCO_2
X_EN
31
R/
W
0
0
1
1
1
1
1
0
0
0
0
0
VCO_ VCO_D
DIST ISTA_P
0
CHDIV
_DIST
_PD
0
0
0
0
0
0
1
B_PD
D
32
33
34
35
R/
W
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
R/
W
0
0
1
1
R/
W
CHDIV
_EN
R/
W
CHDIV_SEG2
CHD CHDIV
IV_S _SEG
EG3 2_EN
_EN
0
CHDIV CHD
_SEG IV_S
1
EG1
_EN
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图7-5. Register Table (continued)
REG 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/
W
ADDRESS[6:0]
DATA [15:0]
36
R/
W
0
1
0
0
1
0
0
0
0
0
0
CHDI CHDI
V_DI V_DIS
STB_ TA_E
0
0
0
0
0
CHDIV_SEG_SEL
CHDIV_SEG3
EN
N
37
38
39
40
41
42
43
44
45
46
R/
W
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0
PLL_N
_PRE
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
R/
W
PLL_N
R/
W
PFD_DLY
0
0
R/
W
PLL_DEN[31:16]
PLL_DEN[15:0]
R/
W
R/
W
MASH_SEED[31:16]
MASH_SEED[15:0]
PLL_NUM[31:16]
PLL_NUM[15:0]
OUTB OUT
R/
W
R/
W
R/
W
R/
W
0
0
OUTA_POW
1
1
0
0
MASH_ORDER
_PD
A_P
D
47
48
59
R/
W
0
0
0
1
1
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
OUTA_MUX
0
0
0
0
1
0
0
1
0
1
1
0
1
1
0
OUTB_POW
R/
W
0
0
0
0
1
0
1
0
1
OUTB_MUX
R/
W
MUXO
UT_HD
RV
0
0
0
61
62
64
R/
W
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
LD_TY
PE
R/
W
0
0
R/
W
ACAL_ FCA
FAST L_FA
ST
AJUMP_SIZE
rb_VCO_SEL
FJUMP_SIZE
68
69
70
R
R
R
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rb_LD_VTUNE
0
0
0
0
0
0
0
0
0
0
0
rb_VCO_CAPCTRL
rb_VCO_DACISET
7.6.1.1 Register Descriptions
表7-5. R0 Register Field Descriptions
BIT
15:14
13
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
LD_EN
R/W
1
Lock detect enable
1: enable
0: disable
12:9
8:7
R/W
R/W
Program to Register Map default values
FCAL_HPFD_ADJ
FCAL_LPFD_ADJ
0
0
Used for when PFD freq is high
3: PFD > 200 MHz
2: PFD > 150 MHz
1: PFD > 100 MHz
0: not used
6:5
R/W
Used for when PFD freq is low
3: PFD < 2.5 MHz
2: 2.5 MHz ≤PFD < 5 MHz
1: 5 MHz ≤PFD < 10 MHz
0: PFD ≥10 MHz
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表7-5. R0 Register Field Descriptions (continued)
FIELD
TYPE
DEFAULT
DESCRIPTION
4
ACAL_EN
R/W
1
Enable amplitude calibration
1: enable (calibration algorithm will set VCO amplitude. For
manual mode set register VCO_IDAC_OVR=1, and then set the
VCO amplitude by register VCO_IDAC)
0: disable
3
FCAL_EN
R/W
1
Enable frequency calibration
1: enable (writing 1 to this register triggers the calibration
sequence)
0: disable
2
1
0
MUXOUT_SEL
RESET
R/W
R/W
R/W
1
0
0
Signal at MUXOUT pin
1: Lock Detect (3.3 V if locked, 0 V if unlocked)
0: Readback (3.3-V digital output)
Reset
Write with a value of 1 to reset device (this register will self-
switch back to 0)
POWERDOWN
Powerdown whole device
1: power down
0: power up
表7-6. R1 Register Field Descriptions
BIT
15:3
2:0
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
CAL_CLK_DIV
R/W
3
Divides down the OSCin signal for calibration clock
Calibration Clock = OSCin / 2^CAL_CLK_DIV
Set this value so that calibration clock is less than but as close
to 200MHz as possible if fast calibration time is desired.
表7-7. R2 Register Field Descriptions
BIT
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-8. R4 Register Field Descriptions
BIT
TYPE
DEFAULT
DESCRIPTION
15:8
ACAL_CMP_DLY
R/W
25
VCO amplitude calibration delay. Lowering this value can speed
calibration time. The guideline for this register is 2 x
[ACAL_CMP_DLY value] x [calibration clock period] > 200ns. As
described in CAL_CLK_DIV, the calibration clock is defined as
OSCin / 2^CAL_CLK_DIV. For example, with the fastest
calibration clock of 200MHz (OSCin=200MHz and
CAL_CLK_DIV=0), the period is 5ns. So ACAL_CMP_DLY
should be > 20. With the same derivation, an example of a
OSCin=100MHz, ACAL_CMP_DLY should be > 10. This register
is left at a default value of 25 if there is no need to shorten
calibration time.
7:0
R/W
Program to Register Map default values
表7-9. R7 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-10. R8 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:14
R/W
Program to Register Map default values
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表7-10. R8 Register Field Descriptions (continued)
BIT
FIELD
VCO_IDAC_OVR
TYPE
DEFAULT
DESCRIPTION
13
R/W
0
This is the override bit for VCO amplitude (or IDAC value).
When this is enabled, the VCO amplitude calibration function
(ACAL_EN) is not used. VCO_IDAC register can be
programmed to set the amplitude. Keep the VCO_IDAC value
within 250 and 450.
12:11
10
R/W
R/W
Program to Register Map default values
VCO_CAPCTRL_OVR
0
This is the override bit for VCO capacitor bank code (or
CAPCTRL value). When this is enabled, the VCO frequency
calibration function (FCAL_EN) is not used. the VCO_CAPCTRL
register can be programmed to set the VCO frequency within the
selected VCO core. The VCO core is selected by setting
VCO_SEL_FORCE=1 and then selecting the core with
VCO_SEL=1,2,3,4,5,6, or 7
9:0
R/W
Program to Register Map default values
表7-11. R9 Register Field Descriptions
BIT
15:12
11
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
OSC_2X
R/W
0
Reference path doubler
1: enable
0: disable
10
9
R/W
R/W
Program to Register Map default values
REF_EN
1
Enable reference path
1: enable
0: disable
8:0
R/W
Program to Register Map default values
表7-12. R10 Register Field Descriptions
BIT
15:12
11:7
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
MULT
R/W
1
Input signal path multiplier (input range from 40 - 70 MHz, output
range from 180 - 250 MHz)
6:0
R/W
Program to Register Map default values
表7-13. R11 Register Field Descriptions
BIT
15:12
11:4
3:0
FIELD
TYPE
R/W
R/W
R/W
DEFAULT
DESCRIPTION
Program to Register Map default values
R divider after multiplier and before PFD
Program to Register Map default values
PLL_R
1
表7-14. R12 Register Field Descriptions
BIT
15:12
11:0
FIELD
TYPE
DEFAULT
DESCRIPTION
Program to Register Map default values
R divider after OSCin doubler and before multiplier
R/W
PLL_R_PRE
R/W
1
表7-15. R13 Register Field Descriptions
BIT
15
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
14
CP_EN
R/W
1
Enable charge pump
1: enable
0: disable
13:2
R/W
Program to Register Map default values
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表7-15. R13 Register Field Descriptions (continued)
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
1:0
PFD_CTL
R/W
0
PFD mode
0: Dual PFD (default)
3: Single PFD (ONLY use if PFD freq is higher than 200MHz)
表7-16. R14 Register Field Descriptions
BIT
15:12
11:7
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
CP_IDN
R/W
3
Charge pump current (DN) –must equal to charge pump
current (UP). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
6:2
1:0
CP_IUP
R/W
R/W
3
1
Charge pump current (UP) –must equal to charge pump
current (DN). Can activate any combination of bits.
<bit 4>: 1.25 mA
<bit 3>: 2.5 mA
<bit 2>: 0.625 mA
<bit 1>: 0.312 mA
<bit 0>: 0.156 mA
CP_ICOARSE
Charge pump gain multiplier - multiplies charge pump current by
a given factor:
3: multiply by 2.5
2: multiply by 1.5
1: multiply by 2
0: no multiplication
For optimal accuracy of the lock detect circuit over temperature,
it is recommended that only set this register to either 0 or 2.
表7-17. R19 Register Field Descriptions
BIT
15:12
11:3
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
VCO_IDAC
R/W
300
This is the VCO amplitude (or IDAC value). When VCO_IDAC is
overridden with VCO_IDAC_OVR=1, VCO amplitude calibration
function (ACAL_EN) is not used. VCO_IDAC register can be
programmed to set the amplitude. VCO_IDAC value must be
kept within 250 and 450.
2:0
R/W
Program to Register Map default values
表7-18. R20 Register Field Descriptions
BIT
15:9
8:0
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
ACAL_VCO_IDAC_STRT
R/W
300
This register is used to aid the VCO amplitude calibration
function (ACAL_EN). By default the amplitude calibration
function searches from the low end of VCO_IDAC until it
reaches the target value. Like the VCO_IDAC, this must be kept
within 250 and 450. This can be set to a value closer to the
target value, then the amplitude calibration time can be
shortened typically final VCO_IDAC is somewhere around 300.
表7-19. R22 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:8
R/W
Program to Register Map default values
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表7-19. R22 Register Field Descriptions (continued)
BIT
FIELD
VCO_CAPCTRL
TYPE
DEFAULT
DESCRIPTION
7:0
R/W
0
This is the VCO capacitor bank code (or CAPCTRL value).
When VCO_CAPCTRL is overridden with
VCO_CAPCTRL_OVR=1, VCO frequency calibration function
(FCAL_EN) is not used. VCO_CAPCTRL register can be
programmed to set the frequency in that core.
VCO_SEL_FORCE=1 has to be set and VCO_SEL to select the
VCO core, then CAPCTRL values between 0 to 183 will produce
frequencies within this core (0 being the highest frequency and
183 the lowest).
表7-20. R23 Register Field Descriptions
BIT
15
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
14
FCAL_VCO_SEL_STRT
R/W
0
This is a register that aids the frequency calibration function.
When this is enabled, a VCO core can be selected for the
frequency calibration to start at, set by register VCO_SEL. By
default the frequency calibration starts from VCO core 7 and
works its way down. If you want for example to lock to a
frequency in VCO core 1, you can set VCO_SEL to 2, so the
calibration will start at VCO core 2 and end at target frequency
at VCO core 1 faster.
13:11
VCO_SEL
R/W
1
0
This is the register used to select VCO cores. It works for
VCO_CAPCTRL when VCO_CAPCTRL_OVR=1 and
VCO_SEL_FORCE=1. It also aids the frequency calibration
function with FCAL_VCO_SEL_STRT.
10
VCO_SEL_FORCE
R/W
R/W
This register works to force selection of VCO cores. If
VCO_CAPTRL_OVR=1 and this register is enabled, you can
select the VCO core to use with VCO_SEL.
9:0
Program to Register Map default values
表7-21. R24 Register Field Descriptions
BIT
FIELD
FIELD
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to default
表7-22. R25 Register Field Descriptions
BIT
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-23. R28 Register Field Descriptions
BIT
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-24. R29 Register Field Descriptions
BIT
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-25. R30 Register Field Descriptions
BIT
15:11
10
FIELD
MASH_DITHER
VTUNE_ADJ
TYPE
R/W
R/W
R/W
R/W
DEFAULT
DESCRIPTION
Program to Register Map default values
MASH dithering: toggle on/off to randomize
Program to Register Map default values
0
9:8
7:6
Change this register field according to the VCO frequency
0: fVCO < 6500 MHz
3: fVCO ≥6500 MHz
5:1
R/W
Program to Register Map default values
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表7-25. R30 Register Field Descriptions (continued)
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
0
VCO_2X_EN
R/W
0
Enable VCO doubler
1: enable
0: disable
表7-26. R31 Register Field Descriptions
BIT
15:11
10
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
VCO_DISTB_PD
R/W
1
Power down buffer between VCO and output B
1: power down
0: power up
9
VCO_DISTA_PD
CHDIV_DIST_PD
R/W
0
0
Power down buffer between VCO and output A
1: power down
0: power up
8
7
R/W
R/W
R/W
Program to Register Map default values
Power down buffer between VCO and channel divider
Program to Register Map default values
6:0
表7-27. R32 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-28. R33 Register Field Descriptions
BIT
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-29. R34 Register Field Descriptions
BIT
15:6
5
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
CHDIV_EN
R/W
1
Enable entire channel divider
1: enable
0: power down
4:0
R/W
Program to Register Map default values
表7-30. R35 Register Field Descriptions
BIT
15:13
12:9
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
CHDIV_SEG2
R/W
1
Channel divider segment 2
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD
8
7
CHDIV_SEG3_EN
CHDIV_SEG2_EN
R/W
R/W
0
0
Channel divider segment 3
1: enable
0: power down (power down if not needed)
Channel divider segment 2
1: enable
0: power down (power down if not needed)
6:3
2
R/W
R/W
Program to Register Map default values
CHDIV_SEG1
1
Channel divider segment 1
1: divide-by-3
0: divide-by-2
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表7-30. R35 Register Field Descriptions (continued)
BIT
FIELD
CHDIV_SEG1_EN
TYPE
DEFAULT
DESCRIPTION
1
R/W
0
Channel divider segment 1
1: enable
0: power down (power down if not needed)
0
R/W
Program to Register Map default values
表7-31. R36 Register Field Descriptions
BIT
15:12
11
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
CHDIV_DISTB_EN
R/W
0
Enable buffer between channel divider and output B
1: enable
0: disable
10
CHDIV_DISTA_EN
CHDIV_SEG_SEL
R/W
1
1
Enable buffer between channel divider and output A
1: enable
0: disable
9:7
6:4
R/W
R/W
Program to Register Map default values
Channel divider segment select
4: includes channel divider segment 1,2 and 3
2: includes channel divider segment 1 and 2
1: includes channel divider segment 1
0: PD
3:0
CHDIV_SEG3
R/W
1
Channel divider segment 3
8: divide-by-8
4: divide-by-6
2: divide-by-4
1: divide-by-2
0: PD
表7-32. R37 Register Field Descriptions
BIT
15:13
12
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
PLL_N_PRE
R/W
0
N-divider pre-scalar
1: divide-by-4
0: divide-by-2
11:0
R/W
Program to Register Map default values
表7-33. R38 Register Field Descriptions
BIT
15:13
12:1
0
FIELD
FIELD
TYPE
R/W
R/W
R/W
DEFAULT
DESCRIPTION
Program to Register Map default values
Integer part of N-divider
PLL_N
27
Program to Register Map default values
表7-34. R39 Register Field Descriptions
BIT
15:14
13:8
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
PFD_DLY
R/W
2
PFD Delay
32: Not used
16: 16 clock cycle delay
8: 12 clock cycle delay
4: 8 clock cycle delay
2: 6 clock cycle delay
1: 4 clock cycle delay
7:0
R/W
Program to Register Map default values
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BIT
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表7-35. R40 Register Field Descriptions
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
PLL_DEN[31:16]
R/W
1000
Denominator MSB of N-divider fraction
表7-36. R41 Register Field Descriptions
BIT
TYPE
DEFAULT
DESCRIPTION
15:0
PLL_DEN[15:0]
R/W
1000
Denominator LSB of N-divider fraction
表7-37. R42 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
DESCRIPTION
15:0
MASH_SEED[31:16]
R/W
0
MASH seed MSB
表7-38. R43 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
15:0
MASH_SEED[15:0]
R/W
0
MASH seed LSB
表7-39. R44 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
PLL_NUM[31:16]
R/W
0
Numerator MSB of N-divider fraction
表7-40. R45 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
PLL_NUM[15:0]
R/W
0
Numerator LSB of N-divider fraction
表7-41. R46 Register Field Descriptions
BIT
15
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
13:8
OUTA_POW
R/W
15
Output buffer A power
increase power from 0 to 31
extra boost from 48 to 63
7
6
OUTB_PD
OUTA_PD
R/W
R/W
1
0
Output buffer B power down
1: power down
0: power up
Output buffer A power down
1: power down
0: power up
5:3
2:0
R/W
R/W
Program to Register Map default values
MASH_ORDER
3
Sigma-delta modulator order
4: fourth order
3: third order
2: second order
1: first order
0: integer mode
表7-42. R47 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
15:13
12:11
R/W
Program to Register Map default values
OUTA_MUX
R/W
0
Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output
10:6
5:0
R/W
R/W
Program to Register Map default values
OUTB_POW
0
Output buffer B power
increase power from 0 to 31
extra boost from 48 to 63
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表7-43. R48 Register Field Descriptions
BIT
15:2
1:0
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
OUTB_MUX
R/W
0
Selects signal to the output buffer
2,3: reserved
1: Selects output from VCO
0: Selects the channel divider output
表7-44. R59 Register Field Descriptions
BIT
15:6
5
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
MUXOUT_HDRV
R/W
0
This bit enables higher current output (approximately 3 mA) at
MUXOUT pin if value is 1.
4:0
R/W
Program to Register Map default values
表7-45. R61 Register Field Descriptions
BIT
15:1
0
FIELD
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
LD_TYPE
R/W
1
To use lock detect, set MUXOUT_SEL=1. Use this register to
select type of lock detect:
0: Calibration status detect (this indicates if the auto-calibration
process has completed successfully and will output from
MUXout pin a logic HIGH when successful). 1: vtune detect (this
checks if vtune is in the expected range of voltages and outputs
from MUXout pin a logic HIGH if device is locked and LOW if
unlocked).
表7-46. R62 Register Field Descriptions
BIT
FIELD
FIELD
TYPE
DEFAULT
DESCRIPTION
15:0
R/W
Program to Register Map default values
表7-47. R64 Register Field Descriptions
BIT
15:10
9
TYPE
DEFAULT
DESCRIPTION
R/W
Program to Register Map default values
ACAL_FAST
FCAL_FAST
AJUMP_SIZE
R/W
0
Enable fast amplitude calibration
1: enable
0: disable
8
R/W
R/W
0
3
Enable fast frequency calibration
1: enable
0: disable
7:5
When ACAL_FAST=1, use this register to select the jump
increment
4
R/W
R/W
Program to Register Map default values
3:0
FJUMP_SIZE
rb_LD_VTUNE
15
When FCAL_FAST=1, use this register to select the jump
increment
表7-48. R68 Register Field Descriptions
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
10:9
R
Readback of Vtune detect (LD_TYPE = 1).
–
0: Unlocked
1: Invalid
2: Locked
3: Unlocked
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BIT
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表7-48. R68 Register Field Descriptions (continued)
FIELD
TYPE
DEFAULT
DESCRIPTION
7:5
rb_VCO_SEL
R
Reads back the actual VCO that the calibration has selected.
–
1: VCO1
2: VCO2
……
7: VCO7
表7-49. R69 Register Field Descriptions
BIT
FIELD
rb_VCO_CAPCTRL
TYPE
DEFAULT
DESCRIPTION
7:0
R
Reads back the actual CAPCTRL value that the VCO calibration
has chosen.
–
表7-50. R70 Register Field Descriptions
BIT
FIELD
rb_VCO_DACISET
TYPE
DEFAULT
DESCRIPTION
8:0
R
-
Reads back the actual DACISET value that the VCO calibration
has chosen.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
8.1.1 Optimization of Spurs
8.1.1.1 Understanding Spurs by Offsets
The first step in optimizing spurs is to be able to identify them by offset. 图8-1 gives a good example that can be
used to isolate the following spur types.
x6
1/2
Phase
Detector
f
f
OUT
PD
1/8
606.25 MHz
120 MHz
f
OSC
40 MHz
f
VCO
4850 MHz
20 + 50/240
1/2
PLL_N_PRE = 2
Fnum = 5
Fden = 24
图8-1. Spur Offset Frequency Example
Based on 图 8-1, the most common spurs can be calculated from the frequencies. Note that the % is the
modulus operator and is meant to mean the difference to the closest integer multiple. Some examples of how to
use this operator are: 36 % 11 = 3, 1000.1 % 50 = 0.1, and 5023.7 % 122.88 = 14.38. Applying this concept, the
spurs at various offsets can be identified from 图8-1.
表8-1. Spur Definition Table
SPUR TYPE
OFFSET
fOSC
COMMENTS
OFFSET IN 图8-1
OSCin
40 MHz
This spur occurs at harmonics of the OSCin frequency.
The phase detector spur has many possible mechanisms
and occurs at multiples of the phase detector frequency.
Fpd
fPD
fOUT % fOSC
fVCO % fOSC
120 MHz
This spur is caused by mixing between the output and
input frequencies.
fOUT % fOSC
fVCO% fOSC
606.25 % 40 = 6.25 MHz
4850 % 40 = 10 MHz
This spur is caused by mixing between the VCO and input
frequencies.
This spur would be the same offset as the integer
boundary spur if PLL_N_PRE=1, but can be different if
this value is greater than one.
fVCO% fPD
fVCO % fPD
4850 % 120 = 50 MHz
Integer
Boundary
fPD *(Fnum%Fden)/
Fden)
120 × (5%24)/24 = 25 MHz
120 / 24 = 5 MHz
This is a single spur
The primary fractional
Primary
Fractional
fPD / Fden
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SPUR TYPE
ZHCSEK3G –DECEMBER 2015 –REVISED AUGUST 2022
表8-1. Spur Definition Table (continued)
OFFSET
COMMENTS
OFFSET IN 图8-1
To Calculate k:
1st Order Modulator: k=1
First Order Modulator: None
2nd Order Modulator: 120/24/2 = 2.5
MHz
3rd Order Modulator: 120/24/6 =
0.83333 MHz
2nd Order Modulator: k=1 if Fden is odd, k=2 if Fden is
even
3rd Order Modulator: k=1 if Fden not divisible by 2 or 3,
k=2 if Fden divisible by 2 not 3, k=3 if Fden divisible by 3
but not 2, Fden = 6 if Fden divisible by 2 and 3
4th Order Modulator: k=1 if Fden not divisible by 2 or 3.
k=3 if Fden divisible by 3 but not 2, k=4 if Fden divisible by
2 but not 3, k=12 if Fden divisible by 2 and 3
Sub-Fractional Spurs exist if k>1
fPD / Fden / k
k=2,3, or 6
Sub-Fractional
4th Order Modulator: 120/24/12 =
0.416666 MHz
In the case that two different spur types occur at the same offset, either name would be correct. Some may
name this by the more dominant cause, while others would simply name by choosing the name that is near the
top of 表8-1.
8.1.1.2 Spur Mitigation Techniques
Once the spur is identified and understood, there will likely be a desire to try to minimize them. Spurs and
Mitigation Techniques gives some common methods.
Spurs and Mitigation Techniques
SPUR TYPE
WAYS TO REDUCE
TRADE-OFF
1. Use PLL_N_PRE = 2
2. Use an OSCin signal with low amplitude and high slew rate (like
LVDS).
OSCin
1. Decrease PFD_DLY
2. To pin 11, use a series ferrite bead and a shunt 0.1-µF
capacitor.
Phase Detector
fOUT % fOSC
Use an OSCin signal with low amplitude and high slew rate (like
LVDS)
1. To pin 7, use a series ferrite bead and a shunt 0.1-µF capacitor.
2. Increase the offset of this spur by shifting the VCO frequency
3. If multiple VCO frequencies are possible that yield the same
spur offset, choose the higher VCO frequency.
fVCO% fOSC
.
Avoid this spur by shifting the phase detector frequency (with the
programmable input multiplier or R divider) or shifting the VCO
frequency. This spur is better at higher VCO frequency.
fVCO% fPD
Methods for PLL Dominated Spurs
1. Avoid the worst case VCO frequencies if possible.
2. Strategically choose which VCO core to use if possible.
3. Ensure good slew rate and signal integrity at the OSCin pin
4. Reduce the loop bandwidth or add more filter poles for out of
band spurs
Reducing the loop bandwidth may degrade
the total integrated noise if the bandwidth is
too narrow.
5. Experiment with modulator order and PFD_DLY
Integer Boundary
Methods for VCO Dominated Spurs
1. Avoid the worst case VCO frequencies if possible.
2. Reduce Phase Detector Frequency
Reducing the phase detector may degrade
the phase noise and also reduce the
capacitance at the Vtune pin.
3. Ensure good slew rate and signal integrity at the OSCin pin
4. Make the impedance looking outwards from the OSCin pin
close to 50 Ω.
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Spurs and Mitigation Techniques (continued)
SPUR TYPE
WAYS TO REDUCE
TRADE-OFF
Decreasing the loop bandwidth too much
may degrade in-band phase noise. Also,
larger unequivalent fractions only sometimes
work
1. Decrease Loop Bandwidth
2. Change Modulator Order
Primary Fractional
3. Use Larger Unequivalent Fractions
1. Use Dithering
Dithering and larger fractions may increase
phase noise. MASH_SEED can be set
between values 0 and Fden, which changes
the sub-fractional spur behavior. This is a
deterministic relationship and there will be
one seed value that will give best result for
this spur.
2. Use MASH seed
3. Use Larger Equivalent Fractions
4. Use Larger Unequivalent Fractions
5. Reduce Modulator Order
Sub-Fractional
6. Eliminate factors of 2 or 3 in denominator (see AN-1879
Fractional N Frequency Synthesis (SNAA062)
8.1.2 Configuring the Input Signal Path
The input path is considered the portion of the device between the OSCin pin and the phase detector, which
includes the input buffer, R dividers, and programmable multipliers. The way that these are configured can have
a large impact on phase noise and fractional spurs.
8.1.2.1 Input Signal Noise Scaling
The input signal noise scales by 20 × log(output frequency / input signal frequency), so always check this to see
if the noise of the input signal scaled to the output frequency is close to the PLL in-band noise level. When that
happens, the input signal noise is the dominant noise source, not the PLL noise floor.
0
-20
0
-20
5400 MHz output phase noise
100 MHz input signal phase noise
100 MHz input signal phase noise
scaled to 5400 MHz
5400 MHz output phase noise
100 MHz input signal phase noise
100 MHz input signal phase noise
scaled to 5400 MHz
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
100
1k
10k
100k
Offset (Hz)
1M
10M
100
1k
10k
100k
Offset (Hz)
1M
10M
D002
D001
图8-3. Phase Noise of 5.4-GHz Output With High-
图8-2. Phase Noise of 5.4-GHz Output With Low-
Noise Input Signal
Noise Input Signal
8.1.3 Input Pin Configuration
The OSCinM and OSCinP can be used to support both a single-ended or differential clock. In either
configuration, the termination on both sides should match for best common-mode noise rejection. The slew rate
and signal integrity of this signal can have an impact on both the phase noise and fractional spurs. Standard
clocking types, LVDS, LVPECL, HCSL, and CMOS can all be used.
8.1.4 Using the OSCin Doubler
The lowest PLL flat noise is achieved with a low-noise 200-MHz input signal. If only a low-noise input signal with
lower frequency is available (for example a 100-MHz source), you can use the low noise OSCin doubler to attain
200-MHz phase detector frequency. Because PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz),
doubling Fpd theoretically gets –6 dB from the 20 × log(Fvco/Fpd) component, +3 dB from the 10 × log(Fpd /
1Hz) component, and cumulatively a –3-dB improvement.
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-80
-85
Input = 100M_PFD = 100M_VCO = 6000M
Input = 100M_osc2x = 2_PFD = 200M
_VCO = 6000M
-90
-95
-100
-105
-110
-115
-120
100
1k
10k
Offset (Hz)
100k
1M
D008
图8-4. 100-MHz Input With OSCin Doubler
8.1.5 Using the Input Signal Path Components
The ideal input is a low-noise, 200-MHz (or multiples of it) signal and 200-MHz phase detector frequency
(highest dual PFD frequency). However, if spur mechanisms are understood, certain combinations of the R-
divider and Multiplier can help. Refer to the Optimization of Spurs section for understanding spur types and their
mechanisms first, then try this section for these specific spurs.
8.1.5.1 Moving Phase Detector Frequency
Engaging the multiplier in the reference path allows more flexibility in setting the PFD frequency. One example
use case of this is if Fvco % Fpd is the dominant spur. This method can move the PFD frequency and thus the
Fvco % Fpd.
Example: Fvco = 3720.12 MHz, Fosc = 300 MHz, Pre-R divider = 5, Fpd = 60 MHz, Fvco%Fosc = 120.12 MHz
(Far out), Fvco%Fpd = 120 kHz (dominant). There is a Fvco%Fpd spur at 120 kHz (refer to 图8-5).
图8-5. Fvco % Fpd Spur
Then second case, using divider and multiplier, is Fpd = 53.57 MHz away from 120-kHz spur. Fvco =
3720.12MHz, Fosc = 300MHz, Pre-R divider = 7, Multiplier = 5, Post-R divider = 4, Fpd = 53.57 MHz,
Fvco%Fosc = 120.12 MHz (Far out). Fvco % Fpd = 23.79 MHz (far out). There is a 20–dB reduction for the
Fvco % Fpd spur at 120 kHz (refer to 图8-6).
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图8-6. Moving Away From Fvco % Fpd Spur
8.1.5.2 Multiplying and Dividing by the Same Value
Although it may not seem like the first thing to try, the Fvco%Fosc and Fout%Fosc spur can sometimes be
improved engaging the OSC_2X bit and then dividing by 2. Although this gives the same phase detector
frequency, the spur can be improved.
8.1.6 Designing for Output Power
If there is a desired frequency for highest power, use an inductor pullup and design for the value so that the
resonance is at that frequency. Use the formula SRF = 1 / (2π× sqrt[L × C]).
Example: C = 1.4 pF (characteristic). If maximum power is targeted at 1 GHz, L = 18 nH. If maximum power is
targeted at 3.3 GHz, L = 1.6 nH
25
1.6 nH pull-up
18 nH pull-up
50 W pull-up
20
15
10
5
0
-5
-10
100
200
500
1000
2000
Output Frequency (MHz)
5000
9500
D006
图8-7. Output Power vs Pullup Type
8.1.7 Current Consumption Management
The starting point is the typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler
bypassed, Pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector
frequency, 0.468-mA charge pump current, channel divider off, one output on, 6000-MHz output frequency, 50-
Ωoutput pullup, 0-dBm output power (differential). To understand current consumption changes due to engaging
different functional blocks , refer to 表8-2.
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表8-2. Typical Current Consumption Impact By Function
ACTION
STEPS
PROGRAMMING
INCREASE IN CURRENT (mA)
Use input signal path
Enable OSCin doubler
Enable multiplier
OSC_2X = 1
7
MULT = 3,4,5, or 6
VCO_DISTB_PD = 0
OUTB_PD = 0
10
8
Add an output
Route VCO to output B
Enable output B buffer
54
53
Increase output power from 0 to Set highest output buffer current
+10dBm (differential)
OUTA_POW = 63
Use channel divider
Route channel divider to output
Enable channel divider
Enable chdiv_seg1
CHDIV_DISTA_EN = 1
CHDIV_EN = 1
5
18
2
CHDIV_SEG1_EN = 1
CHDIV_SEG2_EN = 1
CHDIV_SEG3_EN = 1
VCO2X_EN
Enable chdiv_seg2
5
Enable chdiv_seg3
5
Using VCO doubler
Enable VCO doubler
16
8.1.8 Decreasing Lock Time
A calibration time of 590 µs typically to lock to 7-GHz VCO can be achieved with default settings as specified in
the Electrical Characteristics table. There are several registers that can be programmed to speed up this time.
Lock time consists of the calibration time (time required to calibrate the VCO to the correct frequency range) plus
the analog settling time (time lock the PLL in phase and frequency). For fast calibration set registers
FCAL_FAST = 1 and ACAL_FAST = 1. Also set the calibration clock frequency [input reference frequency] /
2^CAL_CLK_DIV) to 200 MHz. The 20-µs range lock time can be achieved if the amplitude comparator delay is
low, set by register ACAL_CMP_DLY (5 in this example). If this is too low there is not enough time to make the
decision of VCO amplitude to use and may result in non-optimal phase noise. The other approach is to turn off
amplitude calibration with ACAL_EN=0, then manually choose the amplitude with VCO_IDAC (350 for example).
This will also result in 20-µs range calibration time. There are many other registers that can aid calibration time,
for example ACAL_VCO_IDAC_STRT lets the user choose what VCO amplitude to start with during amplitude
calibration. Setting this value to around 350 will give faster times because it is close to the final amplitude for
most final frequencies. FCAL_VCO_SEL_START allows you to choose the VCO core to start with for the
calibration instead of starting from core 7 by default. If you know you are locking to a frequency around VCO
core 1, you can start from VCO 2 by setting VCO_SEL=2, which should give faster lock times. Go to the Register
Maps section for detailed information of these registers and their related registers. For fast analog settling time,
design loop filter for very wide loop bandwidth (MHz range).
图8-8. Lock Time Screenshot
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The calibration example as shown in 图8-8 sweeps from the top of the VCO frequency range to the bottom. This
example does a calibration to lock at 3.7 GHz (which is longest lock time scenario). For the left screenshot
(Wideband Frequency view), see the sweeping from top to bottom of the VCO range. On the right screenshot
(Narrowband Frequency view), see the analog settling time to the precise target frequency.
8.1.9 Modeling and Understanding PLL FOM and Flicker Noise
Follow these recommended settings to design for wide loop bandwidth and extract FOM and flicker noise. The
flat model is the PLL noise floor modeled by: PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1 Hz).
The flicker noise (also known as 1/f noise) which changes by –10dB / decade, is modeled by: PLL_flicker
(offset) = PLL_flicker_Norm + 20 × log(Fvco / 1 GHz) – 10 × log(offset / 10k Hz). The cumulative model is the
addition of both components: PLL_Noise = 10*log(10PLL_Flat / 10 + 10PLL_flicker / 10). This is adjusted to fit
the measured data to extract the PLL_FOM and PLL_flicker_Norm spec numbers.
表8-3. Wide Loop Filter Design
PARAMETER
VALUE
PFD (MHz)
200
12
Charge pump (mA)
VCO frequency (MHz)
Loop bandwidth (kHz)
Phase margin (degrees)
Gamma
5400
2000
30
1.4
Loop filter (2nd order)
C1 (nF)
0.01
0.022
4.7
C2 (nF)
R2 (kΩ)
-90
-95
Data
Flicker
Flat
Model
-100
-105
-110
-115
-120
-125
1k
10k
100k
1M
Offset (Hz)
D003
图8-9. FOM and Flicker Noise Modeling
8.1.10 External Loop Filter
The LMX2592 requires an external loop filter that is application-specific and can be configured by the PLLatinum
™ simulation tool found here. For the LMX2592, it matters what impedance is seen from the Vtune pin looking
outwards. This impedance is dominated by the component C3 for a third order filter or C1 for a second order
filter. If there is at least 3.3 nF for the capacitance that is shunt with this pin, the VCO phase noise will be close to
the best it can be. If there is less, the VCO phase noise in the 100-kHz to 1-MHz region will degrade. This
capacitor should be placed close to the Vtune pin.
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C3
3
0
1
2
3
4
5
6
7
8
9
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
1
0
2
1
R3
C1
R2
C2
图8-10. External Loop Filter
8.2 Typical Application
8.2.1 Design for Low Jitter
图8-11. Typical Application Schematic
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8.2.1.1 Design Requirements
Refer to the design parameters shown in 表8-4.
表8-4. Design Information
PARAMETER
VALUE
200
20
PFD (MHz)
Charge pump (mA)
VCO frequency (MHz)
Loop bandwidth (kHz)
Phase margin (degrees)
Gamma
6000
210
70
3.8
Loop filter (2nd order)
C1 (nF)
4.7
100
68
C2 (nF)
R2 (Ω)
8.2.1.2 Detailed Design Procedure
The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to
signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise
outside the loop bandwidth is dominated by the VCO. As a rule of thumb, jitter is lowest if loop bandwidth is
designed to the point where the two intersect. A higher phase margin loop filter design has less peaking at the
loop bandwidth and thus lower jitter. The tradeoff with this as longer lock times and spurs should be considered
in design as well.
8.2.1.3 Application Curve
图8-12. Typical Jitter
8.3 Power Supply Recommendations
TI recommends placing 100-nF spurs close to each of the power supply pins. If fractional spurs are a large
concern, using a ferrite bead to each of these power supply pins can reduce spurs to a small degree.
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8.4 Layout
8.4.1 Layout Guidelines
See EVM instructions for details. In general, the layout guidelines are similar to most other PLL devices. The
followings are some outstanding guidelines.
• Place output pull up components close to the pin.
• Place capacitors close to the pins.
• Make sure input signal trace is well matched.
• Do not route any traces that carrying switching signal close to the charge pump traces and external VCO.
8.4.2 Layout Example
图8-13. Recommended Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
Texas Instruments has several software tools to aid in the development at www.ti.com. Among these tools are:
• Codeloader to understand how to program the EVM board.
• Clock Design Tool for designing loop filters, simulating phase noise, and simulating spurs.
• EVM board instructions for seeing typical measured data with detailed measurement conditions and a
complete design.
• Clock Architect for designing and simulating the device and understanding how it might work with other
devices.
9.2 Documentation Support
9.2.1 Related Documentation
The following are recommended reading.
• AN-1879 Fractional N Frequency Synthesis (SNAA062)
• PLL Performance, Simulation, and Design Handbook (SNAA106)
• 9.8 GHz RF High Performance Synthesizer Operating From a Buck Converter Reference Design (TIDUC22)
• RF Sampling S-Band Radar Receiver Reference Design (TIDUBS6)
• 9.8GHz RF CW Signal Generator Using Integrated Synthesizer With Spur Reduction Reference Design
(TIDUBM1)
• 2-GHz Complex Bandwidth DC-Coupled 14-bit Digitizer Reference Design (TIDRLM6)
9.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.5 Trademarks
PLLatinum™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMX2592RHAR
LMX2592RHAT
ACTIVE
ACTIVE
VQFN
VQFN
RHA
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LMX2592
LMX2592
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2592RHAR
LMX2592RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
178.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMX2592RHAR
LMX2592RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040H
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
0.5
0.3
A
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
PIN 1 INDEX AREA
6.1
5.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
2X 4.5
EXPOSED
THERMAL PAD
11
20
36X 0.5
10
21
SEE SIDE WALL
DETAIL
2X
41
SYMM
4.5
4.5 0.1
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219055/B 08/22/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.5)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.27)
(
0.2) TYP
VIA
(0.73)
(5.8)
TYP
4X
41
SYMM
(1.46)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.73) TYP
4X (1.46)
20
4X (1.27)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219055/B 08/22/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.46) TYP
9X ( 1.26)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.46)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219055/B 08/22/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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