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LMX2581E

ZHCSDY3 –MAY 2015

LMX2581E 具有集成 VCO 的宽带频率合成器

1 特性

3 说明

1

•

输出频率：50MHz 至 3800MHz

LMX2581E 是一款低噪声宽带频率合成器，其集成有

Δ-Σ 分数 N 锁相环 (PLL)、多核 VCO、可编程输出分

频器以及两个差动输出缓冲器。 VCO 的频率范围为

1880MHz 至 3800MHz，既可以直接发送至输出缓冲

器，也可以进行 2 至 38 范围内的分频。每个缓冲器

在 2700MHz 频率下都能够提供 -3dBm 至 +12dBm 范

围内的输出功率。该器件集成有低噪声、低压降稳压

器 (LDO)，用于实现出色的抗扰度和稳定性能。

输入时钟频率高达 900MHz

相位检测器速率高达 200MHz

支持分数和整数两种模式

标准化锁相环 (PLL) 相位噪声为 –229dBc/Hz

标准化 PLL 1/f 噪声为 –120.8dBc/Hz

对于 2.5GHz 载波，1MHz 偏移时的压控振荡器

(VCO) 相位噪声为 –137dBc/Hz

•

整数模式下的抖动为 100fs（均方根 (RMS)）

可编程的分数调制器阶数

该合成器是一款高度可编程的器件，用户可通过编程来

优化其性能。在分数模式下，分母和调制器阶数均可

编程，并且还可以配置抖动。用户还能够直接指定

VCO 内核或者完全旁路掉内部 VCO。最后，该器件

还包含许多便捷功能，例如断电、快速锁定、自动静音

以及锁定检测。所有寄存器均可通过简单的 3 线接口

进行编程，并且还提供读回功能。

可编程的分数分母

高达 12dBm 的可编程输出功率

可编程的 32 级电荷泵电流

提供相应的可编程选项以使用外部 VCO

数字锁定检测

3 线串行接口和读回功能

LMX2581E 通过 3.3V 单电源供电运行，并且采用 32

引脚 5.0mm × 5.0mm 超薄型四方扁平无引线 (WQFN)

封装。

单电源电压范围：3.15V 至 3.45V

支持最低至 1.6V 的逻辑电平

2 应用

器件信息⁽¹⁾

•

无线基础设施（通用移动通信系统 (UMTS)、长期

器件型号

LMX2581E

封装

封装尺寸（标称值）

演进技术 (LTE)、全球微波互联接入 (WiMax)、多

标准基站）

WQFN (32) DAP

5.00mm x 5.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

•

无线宽带

测试和测量

时钟发生

4 简化电路原理图

Vtune

Multiple

Core VCO

RFin

MUX

Fractional

CPout

Charge

Pump

Vcc

N Divider

Iꢀ

LD

Output

Divider

RFoutA

MUX

MUXout

RFoutB

OSCin

Vcc

2X

DATA

R

MUX

CLK

LE

Serial Interface

Control

Divider

CE

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS665

LMX2581E

ZHCSDY3 –MAY 2015

www.ti.com.cn

8.6 Register Maps......................................................... 28

Application and Implementation ........................ 42

9.1 Application Information............................................ 42

9.2 Typical Applications ................................................ 42

9.3 Do's and Don'ts....................................................... 46

1

2

3

4

5

6

7

特性.......................................................................... 1

9

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements, MICROWIRE Timing............. 8

7.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 11

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 25

8.5 Programming........................................................... 26

10 Power Supply Recommendations ..................... 46

10.1 Supply Recommendations .................................... 46

10.2 Regulator Output Pins........................................... 47

11 Layout................................................................... 48

11.1 Layout Guidelines ................................................. 48

11.2 Layout Example .................................................... 48

12 器件和文档支持 ..................................................... 49

12.1 器件支持 ............................................................... 49

12.2 文档支持 ............................................................... 49

12.3 社区资源................................................................ 49

12.4 商标....................................................................... 49

12.5 静电放电警告......................................................... 49

12.6 Glossary................................................................ 49

13 机械、封装和可订购信息....................................... 49

8

5 修订历史记录

日期

修订版本

注释

2015 年 7 月

*

首次发布。

2

LMX2581E

www.ti.com.cn

ZHCSDY3 –MAY 2015

6 Pin Configuration and Functions

DAP Package

32-Pin WQFN with Thermal Pad

Top View

VregVCO

VbiasCOMP

VrefVCO

GND

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CLK

DATA

LE

Top Down View

0 (DAP)

CE

Vtune

FLout

VccCP

CPout

GND

VbiasVCO

GND

VccVCO

Pin Functions

TYPE

DESCRIPTION

NUMBER

NAME

DAP

CLK

DATA

LE

0

1

2

3

4

GND

Input

The DAP should be grounded.

MICROWIRE Clock Input. High Impedance CMOS input.

MICROWIRE Data. High Impedance CMOS input.

MICROWIRE Latch Enable. High Impedance CMOS input.

Chip Enable Pin.

CE

Fastlock Output. This can switch in an external resistor to the loop filter during locking to

improve lock time.

5

FLout

Output

6

7

VccCP

CPout

GND

Supply Charge Pump Supply.

Output Charge Pump Output.

8

GND

Ground for the Charge Pump.

Ground for the N and R divider.

9

GND

10

11

VccPLL

Fin

Supply Supply for the PLL.

Input

High frequency input pin for an external VCO. Leave Open or Ground if not used.

Differential divided output. For single-ended operation, terminate the complimentary side

with a load equivalent to the load at this Pin.

12

13

14

15

RFoutA+

RFoutA-

RFoutB+

RFoutB-

Output

Differential divided output. For single-ended operation, terminate the complimentary side

with a load equivalent to the load at this pin.

Output

Differential divided output. For single-ended operation, terminate the complimentary side

with a load equivalent to the load at this pin.

Differential divided output. For single-ended operation, terminate the complimentary side

with a load equivalent to the load at this pin.

16

17

VccBUF

VccVCO

Supply Supply for the Output Buffer.

Supply Supply for the VCO.

Ground Pin for the VCO. This can be attached to the regular ground. Ensure a solid trace

connects this pin to the bypass capacitors on pins 19, 23, and 24.

18

GND

3

LMX2581E

ZHCSDY3 –MAY 2015

www.ti.com.cn

Pin Functions (continued)

NUMBER

19

TYPE

DESCRIPTION

NAME

VbiasVCO

Output Bias circuitry for the VCO. Place a 2.2 µF capacitor to GND (Preferably close to Pin 18).

VCO tuning voltage input. See the functional description regarding the minimum

capacitance to put at this pin.

20

21

22

Vtune

GND

Input

GND

VCO ground.

VCO capacitance. Place a capacitor to GND (Preferably close to Pin 18). This value should

be between 5% and 10% of the capacitance at pin 24. Recommended value is 1 µF.

VrefVCO

Output

VCO bias voltage temperature compensation circuit. Place a minimum 10 µF capacitor to

23

VbiasCOMP

Output GND (Preferably close to Pin 18). If it is possible, use more capacitance to slightly improve

VCO phase noise.

VCO regulator output. Place a minimum 10 µF capacitor to GND (Preferably close to Pin

Output

24

25

VregVCO

LD

18). If it is possible, use more capacitance to slightly improve VCO phase noise.

Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback,

Output

and other diagnostic functions.

26

27

28

29

BUFEN

GND

Input

GND

Enable pin for the RF output buffer. If not used, this can be overwritten in software.

Digital Ground.

VccDIG

OSCin

Supply Digital Supply.

Input

Output

GND

Reference input clock.

Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback,

and other diagnostic functions..

30

MUXout

31

32

GND

Ground for the fractional circuitry.

VccFRAC

Supply Supply for the fractional circuitry.

4

LMX2581E

www.ti.com.cn

ZHCSDY3 –MAY 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V

Vcc

V_IN

T_L

Power supply voltage

3.6

(Vcc + 0.3)

260

Input voltage to pins other than Vcc pins

Lead temperature (solder 4 sec.)

Junction temperature

V

°C

T_J

150

≤1.8 with Vcc Applied

≤1 with Vcc = 0

V_OSCin

Voltage on OSCin (Pin29)

Vpp

°C

Storage Temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

3.45

125

85

UNIT

V

Vcc

T_J

Power Supply Voltage

Junction Temperature

Ambient Temperature

3.15

3.3

°C

T_A

-40

°C

7.4 Thermal Information

LMX2581E

DAP (WQFN)

32 PINS

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

30

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

R_θJC(bot)

4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

LMX2581E

ZHCSDY3 –MAY 2015

www.ti.com.cn

7.5 Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ T_A≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.)

PARAMETER

CURRENT CONSUMPTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

One Output Enabled

OUTx_PWR = 15

I_CC

Entire chip supply current

178

134

44

20

7

mA

Supply current except for

output buffers

I_CCCore

I_CCRFout

I_CCVCO_DIV

I_CCPD

Output Buffers and VCO Divider Disabled.

Additive current for each

output buffer

OUTx_PWR = 15

Additive VCO divider

current

VCO Divider Enabled

Device Powered Down

(CE Pin = LOW)

Power down current

OSCin REFERENCE INPUT

Doubler Enabled

5

250

900

1.7

f_OSCin

OSCin frequency range

MHz

Doubler Disabled

v_OSCin

Spur_Foscin

PLL

OSCin input voltage

Oscin spur

AC Coupled

0.4

Vpp

dBc

Foscin = 100 MHz, Offset = 100 MHz

-81

f_PD

Phase detector frequency

Charge-pump gain

200

MHz

µA

Gain = 1X

Gain = 2X

...

110

220

...

K_PD

Gain = 31X

3410

Normalized PLL 1/f noise

Gain =31X

PN_{PLL_1/f_Norm}

–120.8

dBc/Hz

(1)

Normalized to 1 GHz carrier and 10 kHz Offset

PLL figure of merit

Gain =31X.

Normalized to PLL1 and f_PD=1Hz

PN_{PLL_FOM}

(Normalized Noise Floor)

–229

(1)

External VCO input pin

frequency

Internal VCOs Bypassed

(OUTA_PD=OUTB_PD=1)

f_RFin

0.5

0

2.2

+8

GHz

dBm

External VCO input pin

power

Internal VCOs Bypassed

(OUTA_PD=OUTB_PD=1)

p_RFin

Fpd = 25 MHz

Fpd = 100 MHz

–85

–81

Phase detector spurs

Spur_Fpd

dBc

(2)

OUTPUTS

OUTx_PWR=15

OUTx_PWR=45

7.3

12

p_RFoutA+/-

p_RFoutB+/-

Inductor Pullup

F_OUT= 2.7 GHz

Output power level^{(3) (3)}

dBm

dBc

Second harmonic

H2_RFoutX+/-

F_OUT= 2.7 GHz

OUTx_PWR=15

–25

(4)

(1) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into 1/f and flat

components. PLL_Flat = PLL_FOM + 20*log(Fvco/Fpd)+10*log(Fpd / 1Hz). PLL_1/f = PLL_1/f_Norm + 20*log(Fvco / 1GHz) -

10*log(Offset/10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10*log(

10^PLL_Flat/10)+ 10^{PLL_1/f / 10}

)

(2) The spurs at the offset of the phase detector frequency are dependent on many factors, such as he phase detector frequency.

(3) The output power is dependent of the setup and is also programmable. Consult Application and Implementation for more information.

(4) The harmonics vary as a function of frequency, output termination, board layout, and output power setting.

6

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www.ti.com.cn

ZHCSDY3 –MAY 2015

Electrical Characteristics (continued)

(3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ T_A≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCO

All VCO Cores

Combined

f_VCO

Before the VCO Divider

Vtune = 1.3 Volts

1880

3800

MHz

Core 1

12 to 24

15 to 30

20 to 37

21 to 37

Core 2

K_VCO

VCO gain

MHz/V

Core 3

Core 4

Fvco ≥2.5 GHz

Fvco < 2.5 GHz

–125

–100

+125

Allowable temperature drift

ΔT_CL

VCO not being re-calibrated

°C

µs

(5)

No Pre-

programming

f_OSCin= 100 MHz

f_PD= 100 MHz

Full Band Change 1880 —

3800 MHz

140

10

VCO calibration time

t_VCOCal

(6)

With Pre-

programming

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

40 MHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

40 MHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

40 MHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

40 MHz Offset

–85.4

–114.5

–137.0

–154.2

–156.7

–84.6

f_VCO= 1.9 GHz

Core 1

dBc/Hz

–114.1

–137.5

–154.5

–156.1

–81.7

f_VCO= 2.2 GHz

Core 2

VCO phase noise

(OUTx_PWR =15)

PN_VCO

–112.2

–136.0

–153.1

–155.0

–79.0

f_VCO= 2.7 GHz

Core 3

–108.6

–132.6

–152.0

–155.0

f_VCO= 3.3 GHz

Core 4

(5) Continuous tuning range over temperature refers to programming the device at an initial temperature and allowing this temperature to

drift WITHOUT reprogramming the device. This change could be up or down in temperature and the specification does not apply to

temperatures that go outside the recommended operating temperatures of the device.

(6) VCO digital calibration time is the amount of time it takes for the VCO to find the correct frequency band when switching to a new

frequency. After the correct frequency band is found , the remaining error is typically less than 1 MHz and then the PLL settles the rest

of the error in an analog manner. Pre-programming refers to specifying a band that is close to the final (< 20 MHz), which greatly

improves the VCO calibration time.

7

LMX2581E

ZHCSDY3 –MAY 2015

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ T_A≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INTERFACE (DATA, CLK, LE, CE, MUXout, BUFEN, LD)

V_IH

V_IL

I_IH

High-level input voltage

Low level input voltage

High-level input current

Low-level input current

High-level output voltage

Low-Level output voltage

1.4

Vcc

0.4

5

V

V_IH= 1.75 V

V_IL= 0 V

–5

2

µA

V

I_IL

5

V_OH

V_OL

I_OH= –500 µA

I_OL= –500 µA

0

0.4

V

7.6 Timing Requirements, MICROWIRE Timing

See Figure 1

MIN

35

10

25

10

NOM

MAX

UNIT

ns

t_ES

Clock-to-enable low time

Data-to-clock set up time

Data-to-clock hold time

Clock pulse width high

Clock pulse width low

t_CS

ns

t_CH

ns

t_CWH

t_CWL

t_CES

t_EWH

ns

Enable-to-clock setup time

Enable pulse width high

ns

MSB

LSB

A0

DATA

CLK

LE

D27

D26

D25

D24

D23

D0

A3

A2

A1

t

CWH

CS

t

ES

t

CH

CES

t

CWL

t

EWH

Figure 1. Serial Data Input Timing

8

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ZHCSDY3 –MAY 2015

7.7 Typical Characteristics

8

7

6

5

4

3

2

1

0

-85

-90

Relative Normalized Flicker Noise

Relative Figure of Merit

Modeled Flat Noise

Actual Measurement

Modeled Flicker Noise

Modeled Total Noise

-95

-100

-105

-110

-115

-120

-125

-130

-135

1x10^-1

1x10⁰

1x10¹

1x10²

1x10³

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31

Offset (kHz)

Charge Pump Gain Setting (CPG)

D001

Figure 2. Measurement of PLL Figure of Merit and

Figure 3. K_PDImpact on PLL Noise Metrics

Normalized 1/f Noise

-80

Fvco = 2000 MHz, VCO 1

Fvco = 2200 MHz, VCO 2

Fvco = 2700 MHz, VCO 3

Fvco = 3300 MHz, VCO 4

-84

-88

-92

-96

-100

-120

-100

-104

-108

-112

-116

-120

-124

-128

-132

-136

-140

-144

-148

-152

-156

-160

Fvco = 2000 MHz, VCO 1

-140

Fvco = 2200 MHz, VCO 2

Fvco = 2700 MHz, VCO 3

Fvco = 3300 MHz, VCO 4

-160

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10⁸

D001

1x10³

1x10⁴

1x10⁵

Offset (Hz)

1x10⁶

1x10⁷

1x10⁸

D001

Offset (Hz)

Figure 4. Closed Loop Noise for Narrower Bandwidth Filter

Figure 5. Closed Loop Noise for Wider Bandwidth

-150

4000

3750

3500

3250

3000

2750

2500

2250

-152

-154

-156

-158

-160

-162

-164

2000

VCO_SEL=VCO3, VCO_CAPCODE=127

VCO_SEL=VCO4, VCO_CAPCODE=15

1750

0

200 400 600 800 1000 1200 1400 1600 1800 2000

0

20

40

60

80

100

120

140

160

Output Frequency (MHz)

Time (us)

D001

Figure 6. VCO Output Divider Noise Floor vs. Frequency

Figure 7. VCO Digital Calibration Time

9

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ZHCSDY3 –MAY 2015

www.ti.com.cn

Typical Characteristics (continued)

10

1000

700

50 ohm Resistor

18 nH Inductor

500

400

8

6

300

200

4

100

70

50

40

2

30

Pull-Up Component

None

51 ohm Resistor

18 nH Inductor

0

20

-2

10

0

500 1000 1500 2000 2500 3000 3500 4000

1E+8

2E+8 3E+8 5E+87E+8 1E+9

Frequency (Hz)

2E+9 3E+94E+9

Output Frequency (MHz)

D001

Figure 8. Single-Ended Output Power vs. Frequency

Figure 9. Impedance of RFoutX Pins

5

400

350

300

250

200

150

100

50

Real

Magnitude

Imaginary

0

-5

-10

-15

-20

0

-50

-25

-100

-150

-200

-250

25C, Buffer On

25C, Buffer Off

-40 C Buffer Off

85C, Buffer Off

-30

-35

0

500 1000 1500 2000 2500 3000 3500 4000

0

1E+9

2E+9

Frequency (Hz)

3E+9

4E+9

D001

Frequency (MHz)

D001

Figure 10. Sensitivity for External VCO Input (Fin) Pin

Figure 11. Impedance of External VCO Input (Fin) Pin

-7.5

700

Real

Magnitude

Imag

-10

-12.5

-15

600

500

400

300

200

100

0

-17.5

-20

-22.5

-25

-27.5

-100

-200

-300

-400

-30

OSCin Doubler Enabled

OSCin Doubler Disabled

-32.5

-35

100 200 300 400 500 600 700 800 900 1000

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D001

Figure 12. OSCin Input Sensitivity

Figure 13. OSCin Input Impedance

10

LMX2581E

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ZHCSDY3 –MAY 2015

8 Detailed Description

8.1 Overview

The LMX2581E is a synthesizer, consisting of a reference input and R divider, phase detector and charge pump,

VCO and high frequency fractional (N) divider, and two programmable output buffers. The device requires

external components for the loop filter and output buffers, which are application dependent.

Based on the oscillator input frequency (f_OSC), PLL R divider value (PLL_R), PLL N Divider Value (PLL_N),

Fractional Numerator (PLL_NUM), Fractional Denominator (PLL_DEN), and VCO divider value (VCO_DIV), the

output frequency of the LMX2581E (f_OUT) can be determined as follows:

f_OUT= f_OSC× OSC_2X / PLL_R × (PLL_N + PLL_NUM / PLL_DEN) / VCO_DIV

(1)

8.2 Functional Block Diagram

Multiple Core VCO

Programmable

Varactor

Capacitor Array

Diode

(256 Values)

Vtune

Digital

Control

4 Switchable VCO Cores

RFin

N Divider

MUX

CPout

Charge

Pump

4/5 Prescaler

Iꢀ

LD

Output

Divider

Compensation

RFoutA

RFoutB

MUX

MUXout

MUX

2X

DATA

OSCin

R

Divider

MUX

CLK

LE

Serial Interface

Control

CE

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8.3 Feature Description

8.3.1 Typical Performance Characteristics

8.3.1.1 Phase Noise Typical Performance Plot Explanations

Figure 2 shows 2700 MHz output and a 100 MHz phase detector frequency. The modeled noises (Flat, Flicker,

and Total) are calculated from the normalized –229 dBc/Hz figure of merit and the -120.8 dBc/Hz normalized 1/f

noise from the electrical table. After 200 kHz, the loop filter dynamics cause the noise to increase sharply.

Figure 3 shows the relative changes with the normalized PLL noise and figure of merit as a function of charge

pump gain. The PLL phase noise changes as a function of the charge pump gain.

Figure 4 shows the phase noise for a filter optimized for spurs with a 20 MHz phase detector and running in

fractional mode with strong dithering. Due to the narrower loop bandwidth, the impact of the VCO phase noise

inside the loop bandwidth is in the 1 to 10 kHz region.

In Figure 5, the loop filter was optimized for RMS jitter. This was in fractional mode with a phase detector of 200

MHz and uses the First Order Modulator.

In Figure 6, the output divider noise floor only applies when the output divider is not bypassed and depends

mainly on output frequency, not the actual divide value.

8.3.1.2 Other Typical Performance Plot Characteristics Explanations

Figure 7 shows a frequency change of 1880 MHz to 3760 MHz with Fosc = Fpd = 100 MHz. If the VCO3 is

selected as the starting VCO with VCO_CAPCODE=127, digital calibration time is closer to 115 µs. If VCO4 is

selected as the starting VCO with VCO_CAPCODE=15, the calibration time is greatly shortened to something of

the order of 5 µs.

Figure 8 was measured with a board with very short traces. Only one of the differential outputs is routed.

In Figure 9, the output impedance is mainly determined by the pullup component used at lower frequencies. For

the resistor, it is 51 Ω up to about 2 GHz, where the impedance of the device starts to dominate. For the inductor

it increases with frequency and then reaches a resonance frequency before coming down. These behaviors are

specific to the pullup component. These impedance plots match the conditions that were used to measure output

power.

In Figure 12, the OSCin input sensitivity for a sine wave. The voltage has no impact and the temperature only

has a slight impact. Enabling the doubler limits the performance

In Figure 13, For lower frequencies, the magnitude of the OSCin input impedance can be considered high

relative to 50 Ω. At higher frequencies, it is not as high and a resistive pad may be better than a simple shunt 50

Ω resistor for matching.

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Feature Description (continued)

8.3.2 Impact of Temperature on VCO Phase Noise

The phase noise specifications for the VCO in Electrical Characteristics are for a narrow loop bandwidth at room

temperature. If the temperature is changed, Table 1 gives an approximation on how the VCO phase noise is

impacted. For instance, if one was to lock the PLL at -40°C and then measure the phase noise at 1 MHz offset,

the phase noise would typically be of the order of 2 dB better than if it was locked and measured at 25°C. If the

PLL is locked at -40°C and then the temperature was to drift to 85°C, then the phase noise at 1 MHz offset would

typically be about 2 dB worse than it would be if it was locked and measured at 25°C. These numbers are only

approximations and may change between devices and over VCO cores slightly.

Table 1. Approximate Change in VCO Phase Noise vs. Temperature and Temperature Drift in dB

OFFSET

STARTING

FINAL

TEMPERATURE TEMPERATURE

10 kHz

100 kHz

1 MHz

10 MHz

40 MHz

-40°C

-2

-1

-3

-1

0

-2

0

-2

-1

-0

-1

0

-40°C

25°C

85°C

25°C

85°C

-40°C

25°C

85°C

-40°C

25°C

85°C

2

-1

0

These are all zero because all measurements are relative to this row.

-3

-4

-1

-2

2

-2

0

2

-2

0

-2

0

2

8.3.3 OSCin INPUT and OSCin Doubler

The OSCin pin is driven with a single-ended signal which is used as a frequency reference. Before the OSCin

frequency reaches the phase detector, it may be doubled with the OSCin doubler and/or divided with the PLL R

divider.

Because the OSCin signal is used as a clock for the VCO calibration, the OSC_FREQ word needs to be

programmed correctly and a proper signal needs to be applied at the OSCin pin at the time of programming the

R0 register in order for the VCO calibration to properly work. Higher slew rates tend to yield the best fractional

spurs and phase noise, so a square wave signal is best for OSCin. If using a sine wave, higher frequencies tend

to yield better phase noise and fractional spurs due to their higher slew rates. The OSCin pin has high

impedance, so for optimal performance, it is recommended to use either a shunt resistor or resistive pad to make

sure that the impedances looking towards and away from the device input are both close to 50 Ω.

8.3.4 R Divider

The R divider divides the OSCin frequency down to the phase detector frequency. With this device, it is possible

to use both the doubler and the R divider at the same time.

8.3.5 PLL N Divider And Fractional Circuitry

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to

4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion,

PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programmable.

So in general, the total N divider value, N, is determined by: N = PLL_N + PLL_NUM / PLL_DEN. The order of

the delta sigma modulator is programmable from integer mode to third order. There are also several dithering

modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any

time that the R0 register is programmed.

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8.3.5.1 Programmable Dithering Levels

If used appropriately, dithering may be used to reduce sub-fractional spurs, but if used inappropriately, it can

actually create spurs and increase phase noise. Table 2 provides guidelines for the use of dithering based on the

fractional denominator, after the fraction is reduced to lowest terms.

Table 2. Dithering Recommendations

DITHERING

RECOMMENDATION

FRACTION

COMMENTS

This is often the worst case for spurs, which can actually be turned into

the best case by simply disabling dithering. This will have performance

that is similar to integer mode.

Fractional Numerator = 0

Disable Dithering

These fractions are not well randomized and dithering will likely create

phase noise and spurs.

Equivalent Denominator < 20

Disable Dithering

Consider Dithering

Equivalent Denominator is not

divisible by 2 or 3

There will be no sub-fractional spurs, so dithering is likely not to be very

effective

Equivalent Denominator > 200

and is divisible by 2 or 3

Dithering may help reduce the sub-fractional spurs, but understand it may

degrade the PLL phase noise.

In general, dithering is likely to cause more harm than good for poorly randomized fractions like 1/2. There are

situations when dithering does make sense and when it is used, it is recommended to adjust the PFD_DLY word

accordingly to compensate for this.

8.3.5.2 Programmable Delta Sigma Modulator Order

The fractional modulator order is programmable, which gives the opportunity to better optimize phase noise and

spurs. Theoretically, higher order modulators push out phase noise to farther offsets, as described in Table 3.

Table 3. Choosing the Fractional Modulator Order

MODULATOR ORDER

APPLICATIONS

Integer Mode

(Order = 0)

If the fractional numerator is zero, it is best to run the device in integer mode to minimize phase noise

and spurs.

When the equivalent fractional denominator is 6 or less, the first order modulator theoretically has lower

phase noise and spurs, so it always makes sense in these situations. When the fractional denominator

is between 6 and about 20, consider using the first order modulator because the spurs might be far

enough outside the loop bandwidth that they will be filtered. The first order modulator also does not

create any sub-fractional spurs or phase noise.

First Order Modulator

The choice between 2nd and 3rd order modulator tends to be a little more application specific. If the

fractional denominator is not divisible by 3, then the 2nd and 3rd order modulators will have spurs in the

same offsets, so the 3rd is generally better for spurs. However, if stronger levels of dithering is used, the

3rd order modulator will create more close-in phase noise than the 2nd order modulator

2nd and 3rd Order Modulators

Figure 14 and Figure 15 give an idea of the theoretical impact of the delta sigma modulator order on the shaping

of the phase noise and spurs. In terms of phase noise, this is what one would theoretically expect if strong

dithering was used for a well-randomized fraction. Dithering can be set to different levels or even shut off and the

noise can be eliminated. In terms of spurs, they can change based on fraction, but they will theoretically pushed

out to higher phase detector frequencies. However, one must be aware that these are just THEORETICAL

graphs and for offsets that on the order of less than 5% of the phase detector frequency, other factors can

impact the noise and spurs. In Figure 14, the curves all cross at 1/6th of the phase detector frequency and that

this transfer function peaks at half of the phase detector frequency, which is assumed to be well outside the loop

bandwidth. Figure 15 shows the impact of the phase detector frequency on the modulator noise.

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-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

1st Order Modulator

2nd Order Modulator

3rd Order Modulator

1x10⁶2x10⁶

5x10⁶1x10⁷2x10⁷

Offset (Hz)

5x10⁷1x10⁸2x10⁸

D001

Figure 14. Theoretical Delta Sigma Noise Shaping for a 100 MHz Phase Detector Frequency

-50

-60

-70

-80

-90

-100

-110

-120

-130

Fpd=10MHz

Fpd=100 MHz

Fpd=200 MHz

-140

-150

1x10⁶2x10⁶

5x10⁶1x10⁷2x10⁷

Offset (Hz)

5x10⁷1x10⁸2x10⁸

D001

Figure 15. Theoretical Delta Sigma Noise Shaping for 3rd Order Modulator

For lower offsets, the actual noise added by the delta sigma modulator may be higher than the theoretical values

shown due to nonlinearity of the phase detector. This noise floor can vary with the modulator order, phase

detector frequency, and PFD_DLY word setting as shown in the following table, which shows the phase noise at

10 kHz offset for a frequency close to 2801 MHz with a well randomized fraction and strong dithering. The phase

noise in integer mode is also shown for comparison purposes.

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Table 4. Impact of PFD_DLY, Modulator Order, and Phase Detector Frequency on Modulator Noise Floor

INTEGER

Fpd= Fpd=

50MHz 100 MHz 200 MHz 25 MHz

2nd ORDER MODULATOR

Fpd= Fpd= Fpd= Fpd=

50MHz 100 MHz 200 MHz 25 MHz

3rd ORDER MODULATOR

Fpd= Fpd= Fpd= Fpd=

50MHz 100 MHz 200 MHz

PFD_

DLY

Fpd=

25 MHz

Fpd=

0

1

2

3

4

5

6

7

-106.7

-106.2

-106.0

-105.6

-105.5

-105.1

-104.8

-109.5

-108.8

-108.3

-108.2

-107.7

-107.6

-107.3

-106.8

-111.4

-110.6

-109.7

-109.4

-108.8

-108.5

-108.2

-111.0

-110.9

-110.1

-109.9

-110.0

-110.1

-109.3

-105.9

-106.3

-106.5

-105.6

-105.3

-105.1

-105.6

-104.6

-108.8

-108.4

-108.3

-107.9

-107.5

-107.4

-107.0

-106.2

-110.6

-110.1

-109.2

-108.7

-108.6

-107.8

-107.4

-111.0

-110.0

-110.1

-109.8

-109.3

-109.0

-109.1

-108.7

-84.4

-88.3

-92.9

-99.2

-103.0

-101.4

-98.4

-97.1

-87.5

-91.3

-90.1

-93.6

-93.8

-98.5

-96.1

-98.1

-102.8

-105.4

-106.2

-105.5

-102.9

-100.2

-101.8

-105.4

-104.0

-101.6

-100.6

-102.6

-105.8

-103.7

-102.7

-102.1

8.3.6 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the R and N dividers and generates a correction current

corresponding to the phase error. This charge pump current is software programmable to many different levels.

The phase detector frequency, f_PD, can be calculated as follows:

f_PD= f_OSCin× OSC_2X / R

(2)

The charge pump outputs a correction current into the loop filter, which is implemented with external

components. The gain of the charge pump is programmable to 32 different levels with the CPG word and the

PFD_DLY word can adjust the minimum on time that the charge pump comes on for.

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8.3.7 External Loop Filter

The LMX2581E requires an external loop filter which is application-specific and can be configured by consulting

LMX2581E Tools and Software. For the LMX2581E, it matters what impedance is seen from the Vtune pin

looking outwards. This impedance is dominated by the component C3_LF for a third order filter or C1_LF for a

second order filter (R3_LF = C3_LF = 0). If there is at least 3.3 nF for the capacitance that is shunt with this pin,

the VCO phase noise will be close to the best it can be. If there is less, the VCO phase noise in the 100 k to

1MHz region. In cases where 3.3 nF might restrict the loop bandwidth to be too narrow, it might make sense to

violate this restriction a little and sacrifice some VCO phase noise in order to get a wider loop bandwidth.

R3_LF

Vtune

C3_LF

LMX2581

CPout

C2_LF

C1_LF

R2_LF

Figure 16. Typical Loop Filter

10

Component

1 nF

3.3 nF

330 pF

8

6

4

2

0

-2

1x10³

1x10⁴

1x10⁵

Offset (Hz)

1x10⁶

1x10⁷5x10⁷

D001

Figure 17. Vtune Capacitor Impact on VCO Phase Noise

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8.3.8 Low Noise, Fully Integrated VCO

The VCO takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related

to the other frequencies and divider values as follows: f_VCO= f_PD× N = f_OSCin× OSC_2X × N / R. The VCO is

fully integrated, including the tank circuitry.

In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the

internal VCO is actually made of VCO cores working as one. These cores starting from lowest frequency to

highest frequency are VCO 1, VCO 2, VCO 3, and VCO 4. Each VCO core has 256 different frequency bands.

Band 255 is the lowest frequency and Band 0 is the highest This creates the need for frequency calibration in

order to determine the correct VCO core and correct frequency band in that VCO core. The frequency calibration

routine is activated any time that the R0 register is programmed with the NO_FCAL bit equal to zero. In order for

this frequency calibration to work properly, the OSC_FREQ word needs to be set to the correct setting. The

VCO_SEL word allows the user to suggest a particular VCO core for the device to choose, which is useful for

optimizing fractional spurs and minimizing lock time.

Table 5. Approximate (NOT Ensured) VCO Core Frequency Ranges

VCO CORE

VCO 1

APPROXIMATE FREQUENCY RANGE

1800 to 2270 MHz

VCO 2

2135 to 2720 MHz

VCO 3

2610 to 3220 MHz

VCO 4

3075 to 3880 MHz

8.3.8.1 VCO Digital Calibration

When the frequency is changed, the digital VCO goes through the following VCO calibration:

1. Depending on the status of the VCO_SEL word, the starting VCO core is selected.

2. The algorithm starts counting at the default band in this core as determined by the VCO_CAPCODE value.

3. The VCO increments or decrements the CAPCODE based on the what the actual VCO output is compared

to the target VCO output.

4. Repeat step 3 until either the VCO is locked or the VCO is at VCO_CAPCODE = 0 or 255

5. If not locked, then choose the next appropriate VCO if possible and return to step 3. If not possible, the

calibration is terminated.

A good starting point is to set VCO_SEL = 2 for VCO 3 and set VCO_SEL_MODE = 1 to start at the selected

core. If there is the potential of switching the VCO from a frequency above 3 GHz directly to a frequency below

2.2 GHz, VCO_SEL_MODE can not be set to 0. In this case, VCO_SEL_MODE can still be set to 1 to select a

starting core, but the starting core specified by VCO_SEL can not be VCO 4.

The digital calibration time can be improved dramatically by giving the VCO guidance regarding which VCO core

and which VCO_CAPCODE to start using. Even if the wrong VCO core is chosen, which could happen near the

boundary of two cores, the calibration time is improved. For situations where the frequency change is small, the

device can be programmed to automatically start at the last VCO core used. For applications where the

frequency change is relatively small, the best VCO calibration time can often be achieved by setting the

VCO_SEL_MODE to choose the last VCO core that was used.

8.3.9 Programmable VCO Divider

The VCO divider can be programmed to even values from 2 to 38 as well as bypassed by either one or both of

the RFout outputs. When the zero delay mode is not enabled, the VCO divider is not in the feedback path

between the VCO and the PLL and therefore has no impact on the PLL loop dynamics. After this programmable

divider is changed, it may be beneficial to reprogram the R0 register to re-calibrate the VCO. The frequency at

the RFout pin is related to the VCO frequency and divider value, VCO_DIV, as follows:

f_RFout= f_VCO/ VCO_DIV

(3)

When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise.

When changing to a VCO_DIV value of 4, either from a state of VCO_DIV=2 or OUTx_MUX = 0, it is necessary

to program VCO_DIV first to a value of 6, then to a value of 4. This holds for no other VCO_DIV value and is not

necessary if the VCO frequency (but not VCO_DIV) is changing.

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8.3.10 0–Delay Mode

When the VCO divider is used, an ambiguous phase relationship is created between the OSCin and RFout pins.

0–Delay mode can be enabled to eliminate this ambiguity.

When this mode is used, special care needs to be taken because it does interfere with the VCO calibration if not

done correctly. The correct way to use 0–Delay mode is as follows:

1. If N is not divisible by VCO_DIV, reduce the phase detector frequency to make it so.

2. Program as normal and lock the PLL.

3. Program the NO_FCAL =1.

4. Program 0_DLY = 1. This will cause the PLL to lose lock.

5. Program the PLL_N value with PLL_N* / VCO_DIV, where PLL_N* is the original value.

6. The PLL should now be locked in zero delay mode.

8.3.11 Programmable RF Output Buffers

The output states of the RFoutA and RFoutB pins are controlled by the BUFEN pin as well as the BUFEN_DIS

programming bit. If the pin is powered up, then output power can be programmed to various levels with the

OUTx_PWR words.

Table 6. Output States of the RFoutA and RFoutB Pins

OUTA_PD

OUTB_PD

BUFEN_DIS

BUFEN PIN

OUTPUT STATE

1

X

0

X

Powered Down

Powered Up

0

Low

High

Powered Down

Powered Up

1

8.3.11.1 Choosing the Proper Pullup Component

The first decision is to whether to use a resistor or inductor for a pullup.

•

The resistor pullup involves placing a 50 Ω resistor to the power supply on each side, which makes the output

impedance easy to match and close to 50 Ω. However, it is a higher current for the same output power, and

the maximum possible output power is more limited. For this method, the OUTx_PWR setting should be kept

about 30 or less (for a 3.3-V supply) to avoid saturation. The resistive pullup is also sometimes more

desirable when the output frequency is lower.

•

The inductor pullup involves placing an inductor to the power supply. This inductor should look like high

impedance at the frequency of interest. This method offers higher output power for the same current and

higher maximum output power. The output power is about 3 dB higher for the same OUTx_PWR setting than

the resistor pullup. Since the output impedance will be very high and poorly matched, it is recommended to

either keep traces short or to AC couple this into a pad for better impedance matching.

If an output is partially used or unused:

•

If the output is unused, then power it down in software. No external components are necessary.

If only one side of the differential output is used, include the pullup component and terminate the unused side,

such that the impedance as seen by this pin looks similar to the impedance as seen by the used side.

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8.3.11.2 Choosing the Best Setting for the RFoutA_PWR and RFoutB_PWR Words

Table 7 shows the impact of the RFoutX_PWR word on the output power and current RELATIVE to a setting of

RFoutX_PWR = 15. The choice of pullup component has an impact on the output power, but not much impact on

the output current. The relative noise floor measurements are made without the VCO divider engaged.

Table 7. Impact of the RFoutX_PWR Word on the Output Power and Current

OUTx_PWR

RELATIVE

CURRENT

(mA)

RESISTIVE PULLUP

INDUCTOR PULLUP

RELATIVE OUTPUT

RELATIVE NOISE

FLOOR (dB)

RELATIVE OUTPUT

RELATIVE NOISE

FLOOR (dB)

POWER (dB)

− 9.0

− 4.6

−2.0

POWER (dB)

− 9.0

− 4.6

−2.0

0

−16

− 11

− 5

0

+ 4.0

+ 0.7

+ 0.9

0

+ 2.5

+ 0.5

- 0.1

0

5

10

15

20

25

30

35

40

45

0

+ 5

+10

+15

+20

+25

+30

+ 1.4

+ 2.1

+ 2.4

+ 2.2

+ 1.9

+ 1.4

+ 0.7

+ 1.6

+ 3.2

+ 5.6

+ 1.5

+ 2.8

+ 3.9

+ 4.8

+ 5.4

+6.0

- 0.6

- 1.1

- 1.0

- 0.9

+ 0.2

+ 2.0

For a resistive pullup, a setting of 15 is optimal for noise floor and a setting if 30 is optimal for output power.

Settings above 30 are generally not recommended for a resistive pullup. For an inductor pullup, a setting of 30 is

optimal for noise floor and a setting of 45 is optimal for output power. These settings may vary a little based on

output frequency, supply voltage, and loading of the output, but the above table gives a fairly close indication of

what performance to expect.

8.3.12 Fastlock

The LMX2581E includes the Fastlock feature that can be used to improve the lock times. When the frequency is

changed, a timeout counter is used to engage the Fastlock for a programmable amount of time. During the time

the device is in Fastlock, the FLout pin changes from high impedance to low, thus switching in the external

resistor R2pLF in parallel with R2_LF.

Vtune

Charge

CPout

Pump

C2_LF

Fastlock

FLout

Control

C1_LF

R2_LF

R2pLF

Table 8. Normal Operation vs. Fastlock

PARAMETER

Charge Pump Gain

FLout Pin

NORMAL OPERATION

CPG

FASTLOCK

FL_CPG

High Impedance

Grounded

Once the loop filter values and charge pump gain are known for normal operation, they can be determined for

Fastlock operation as well. In normal operation, one can not use the highest charge pump gain and still use

Fastlock because there will be no larger current to switch in. The resistor and the charge pump current are

changed simultaneously so that the phase margin remains the same while the loop bandwidth is multiplied by a

factor of K as shown in Table 9:

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Table 9. Fastlock Configuration

PARAMETER

SYMBOL

FL_CPG

K

CALCULATION

Charge Pump Gain in Fastlock

Loop Bandwidth Multiplier

External Resistor

Typically use the highest value.

K=sqrt(FL_CPG/CPG)

R2 / (K-1)

R2pLF

8.3.13 Lock Detect

The LMX2581E offers two circuits to detect lock, Vtune and Digital Lock Detect, which may be used separately

or in conjunction. Digital Lock Detect gives a reliable indication of lock/unlock if programmed correctly with the

one exception, which occurs when the PLL is locked to a valid OSCin signal and then the OSCin signal is

abruptly removed. In this case, digital lock detect can sometimes still indicate a locked state, but Vtune Lock

detect will correctly indicate an unlocked state. Therefore, for the most reliable lock detect, it is recommended to

use these in conjunction, because each technique's drawback is covered by the other one. Note that because

the powerdown mode powers down the lock detect circuitry, it is possible to get a high lock detect indication

when the device is powered down. The details of the two respective methods are described below in the Vtune

Lock Detect and Digital Lock Detect (DLD) sections.

8.3.13.1 Vtune Lock Detect

This style of lock detect only works with the internal VCO. Whenever the tuning voltage goes below the threshold

of about 0.5 V, or above the threshold of about 2.2 V, the internal VCO will become unlocked and the Vtune lock

detect will indicate that the device is unlocked. For this reason, when the Vtune lock detect says the PLL is

unlocked, one can be certain that it is unlocked.

8.3.13.2 Digital Lock Detect (DLD)

This lock detect works by comparing the phase error as presented to the phase detector. If the phase error plus

the delay as specified by the PFD_DLY word outside the tolerance as specified by DLD_TOL, then this

comparison would be considered to be an error, otherwise passing. At higher phase detector frequencies, it may

be necessary to adjust the DLD_ERR_CNT and DLD_PASS_CNT. The DLD_ERR_CNT specifies how may

errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT multiplied by

8 specifies how many passing comparisons are necessary to cause the PLL to be considered to be locked and

also resets the count for the errors. The DLD_ERR_CNT and DLD_PASS_CNT values may be decreased to

make the circuit more sensitive, but if lock detect is made too sensitive, chattering can occur and these values

should be increased.

8.3.14 Part ID and Register Readback

8.3.14.1 Uses of Readback

The LMX2581E allows any of its registers to be read back, which could be useful for the following applications

below.

•

Register Readback

–

By reading back the register values, it can be confirmed that the correct information was written. In

addition to this, Register R6 has special diagnostic information that could potentially be useful for

debugging problems.

•

Part ID Readback

–

By reading back the part ID, this information may be used by whatever device is programming the

LMX2581E to identify this device and know what programming information to send. In addition to this, the

BUFEN and CE pins may be used to create 4 unique part ID values. Although these pins can impact the

device, they may be overridden in software. It is not necessary to have the device programmed in order to

do part ID Readback.

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The procedure for doing this Readback is in Serial Timing for Readback. Depending on the settings for the

ID(R0[31]) and RDADDR (R6[8:5]), information a different bit stream will be returned as shown in Table 10.

Table 10. Uses of Readback

ID

BUFEN PIN

CE PIN

READBACK CODE

Readback register defined by

RDADDR.

0

X

0

1

0

1

0

1

0x 00000500

0x 00000510

0x 00000520

0x 00000530

1

8.3.14.2 Serial Timing for Readback

Readback is done through the the MUXout (or LD) pin with the same clock that is used to clock in the data.

•

Choose either the MUXout (or LD) pin for reading back data and program the MUXOUT_SELECT (or

LD_SELECT) to readback mode.

•

Bring the LE pin from low to high to start the readback at the MSB.

After the signal to the CLK pin goes high, the data will be ready at the readback pin 10 ns afterwards. It is

recommended to read back the data on the falling edge of the clock. Technically, the first bit actually

becomes ready after the rising edge of LE, but it still needs to be clocked out.

•

The address being clocked out will all be 1's.

Because the CLK pin is both used to clock in data and clock out data, special care needs to be taken to ensure

that erroneous data is not being clocked in during readback. There are two approaches to deal with this. The first

approach is to actually send valid data during readback. For this approach, R6 is a recommended register and

the approach is shown in Figure 18:

MSB

D27

LSB

1

D27

MUXout

DATA

D26

D25

D24

D23

D0

1

LSB

A0

D27

D26

D25

D24

D23

D0

A3

A2

A1

CLK

LE

t

CWH

CS

t

CES

ES

t

CH

t

CWL

t

EWH

Figure 18. Timing for Readback

A second approach is to hold LE high during readback so that the clock pulses do not clock data into the part,

but still function for readback purposes. Figure 19 demonstrates this method:

MSB

LSB

D26

D25

D24

D23

D0

1

D27

MUXout

LSB

CLK

t

CWH

t

CES

t

CWL

LE

Figure 19. Timing for Readback, Holding LE High

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8.3.15 Optimization of Spurs

The LMX2581E offers several programmable features for optimizing fractional spurs. In order to get the best out

of these features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes,

and remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process

more systematic. Texas Instruments offers tools for information and tools for fractional spurs such as Application

Note AN-1879 (

AN-1879 Fractional N Frequency Synthesis), The Clock Design Tool, and this datasheet.

8.3.15.1 Phase Detector Spur

The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, f_PD. To

minimize this spur, considering using a smaller value for PFD_DLY, smaller value for CPG_BLEED, and a lower

phase detector frequency. In some cases where the loop bandwidth is very wide relative to the phase detector

frequency, some benefit might be gained from using a narrower loop bandwidth or adding poles to the loop filter,

but otherwise the loop filter has minimal impact. Bypassing at the supply pins and board layout can also have an

impact on this spur, especially at higher phase detector frequencies.

8.3.15.2 Fractional Spur - Integer Boundary Spur

This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel

for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency was 2703 MHz,

then the integer boundary spur would be at 3 MHz offset. This spur can be either PLL or VCO dominated. If it is

PLL dominated, then the following table shows that decreasing the loop bandwidth and some of the

programmable fractional words may impact this spur. If the spur is VCO dominated, then reducing the loop filter

will not help, but rather reducing the phase detector and having a good slew rate and signal integrity at the

OSCin pin will help. Regardless of whether it is PLL or VCO dominated, the VCO core does impact this spur.

Table 11. Typical Integer Boundary Spur Levels

FRACTIONAL INTEGER BOUNDARY SPURS

PLL DOMINATED

VCO DOMINATED

VCO CORE

InBandSpur

Metric

VCOXtalkSpur

METRIC

FORMULA

VCO 1

VCO 2

VCO 3

VCO 4

-33

–25

–37

–34

-89

–83

–99

–87

VCOXtalkSpur

+VCO_Transfer_Function(Offset)

InBandSpur

+ PLL_Transfer_Function(Offset)

- 20 × log(VCO_DIV)

+ 20 × log(f_PD

)

- 20 × log(Offset / 1MHz)

It is common practice to benchmark a fractional PLL spurs by choosing a worst case VCO frequency and use

this as a metric. However, one should be cautions that this is only a metric for the integer boundary spur. For

instance, suppose that one was to compare two devices by using an 100 MHz phase detector frequency, tune

the VCO to 2000.001 MHz, and measure the integer boundary spur at 1 kHz. If one part was to have better

spurs at this frequency, this does not necessarily mean that the spurs would be better at a channel farther from

an integer boundary, like 2025.001 MHz.

8.3.15.3 Fractional Spur - Primary Fractional Spurs

These spurs occur at multiples of f_PD/ PLL_DEN and are not the integer boundary spur. For instance, if the

phase detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at

1,2,4,5,6,...MHz. These are impacted by the loop filter bandwidth and modulator order. If a small frequency error

is acceptable, then a larger equivalent fraction may improve these spurs. For instance, if the fraction is 53/200,

expressing this as 530,000 / 2,000, 001. This larger un-equivalent fraction pushes the fractional spur energy to

much lower frequencies that hopefully is not so critical.

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8.3.15.4 Fractional Spur - Sub-Fractional Spurs

These spurs appear at a fraction of f_PD/ PLL_DEN and depend on modulator order. With the first order

modulator, there are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if

the denominator is even. A third order modulator can produce sub-fractional spurs at 1/2,1/3, or 1/6 of the offset,

depending if it is divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is

3/100, no sub-fractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a 2nd

or 3rd order modulator would be expected.

Aside from strategically choosing the fractional denominator and using a lower order modulator, another tactic to

eliminate these spurs is to use dithering and express the fraction in larger equivalent terms (that is,

1000000/4000000 instead of 1/4). If a small frequency error is acceptable, also consider a larger un-equivalent

fraction like (1000000,4000000). However, dithering can also add phase noise, so if dithering is used, this needs

to be managed with the various levels it has and the PFD_DLY word to get the best possible performance.

8.3.15.5 Summary of Spurs and Mitigation Techniques

Table 12 gives a summary of the spurs discussed so far and techniques to mitigate them.

Table 12. Spurs and Mitigation Techniques

SPUR TYPE

OFFSET

WAYS to REDUCE

TRADE-OFF

1. Reduce Phase Detector Frequency

2. Decrease PFD_DLY

Although reducing the phase detector

frequency does improve this spur, it

also degrades phase noise.

Phase Detector

f_PD

3. Decrease CPG_BLEED

Methods for PLL Dominated Spurs

1. Avoid the worst case VCO frequencies if possible.

2. Strategically choose which VCO core to use if

possible.

Reducing the loop bandwidth may

degrade the total integrated noise if the

bandwidth is too narrow.

3. Ensure good slew rate and signal integrity at the

OSCin pin

4. Reduce the loop bandwidth or add more filter poles

for out of band spurs

5. Experiment with modulator order, PFD_DLY, and

CPG_BLEED

Integer Boundary

f_VCOmod f_PD

Methods for VCO Dominated Spurs

1. Avoid the worst case VCO frequencies if possible.

2. Strategically choose which VCO core to use if

possible.

Reducing the phase detector may

degrade the phase noise and also

reduce the capacitance at the Vtune

pin.

3. Reduce Phase Detector Frequency

4. Ensure good slew rate and signal integrity at the

OSCin pin

5. Make the impedance looking outwards from the

OSCin pin close to 50 Ω.

Decreasing the loop bandwidth too

much may degrade in-band phase

noise. Also, larger un-equivalent

fractions only sometimes work

1. Decrease Loop Bandwidth

2. Change Modulator Order

Primary

Fractional

f_PD/ PLL_DEN

3. Use Larger Un-equivalent Fractions

1. Use Dithering

2. Use Larger Equivalent Fractions

3. Use Larger Un-equivalent Fractions

4. Reduce Modulator Order

f_PD/ PLL_DEN / k

k=2,3, or 6

Dithering and larger fractions may

increase phase noise.

Sub-Fractional

5. Eliminate factors of 2 or 3 in denominator (see AN-

1879, SNAA062)

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8.4 Device Functional Modes

8.4.1 Full Synthesizer Mode

In this mode, the internal VCO is enabled. When combined with an external reference and loop filter, this mode

provides a complete signal source.

8.4.2 External VCO Mode

The LMX2581E allows the user to use an external VCO by using the Fin pin and selecting the external VCO

mode for the MODE word. Because this is software selectable, the user may have a setup that switches between

the external and internal VCO. Because the Fin pin is close to the RFoutA and RFoutB pins, some care needs to

be taken to minimize board crosstalk when both an external VCO and an output buffer is used. If only one output

buffer is required, it is recommended to use the RFoutB output because it is physically farther from the Fin pin

and therefore will have less board related crosstalk. When using external VCO with a different characteristic, it

may be necessary to change the phase detector polarity (CPP).

8.4.3 Powerdown Modes

The LMX2581E can be powered down either fully or partially with the PWDN_MODE word or the CE pin. The

two types of powerdown are in the following table.

Table 13. LMX2581E Powerdown Modes

POWERDOWN STATE

Partial Powerdown

Full Powerdown

DESCRIPTION

VCO, PLL, and Output buffers are powered down, but the LDOs are kept powered up to

reduce the time it takes to power the device back up.

VCO, PLL, Output Buffers, and LDOs are all powered down.

When coming out of a full powerdown state, it is necessary to do the initial power-on programming sequence

described in later sections. If coming out of a partial powerdown state, it is necessary to do the sequence for

switching frequencies after initialization, that is described in later sections.

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8.5 Programming

The LMX2581E is programmed using several 32-bit registers. A 32-bit shift register is used as a temporary

register to indirectly program the on-chip registers. The shift register consists of a data field and an address field.

The last LSB bits, ADDR[3:0], form the address field, which is used to decode the internal register address. The

remaining 28 bits form the data field DATA[27:0]. While LE is low, serial data is clocked into the shift register

upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the

data field into the selected register bank.

8.5.1 Serial Data Input Timing

There are several programming considerations (see Figure 20):

•

A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE

signal, the data is sent from the shift registers to an actual counter.

•

The LE pin may be held high after programming and this will cause the LMX2581E to ignore clock pulses.

The CLK signal should not be high when LE transitions to low.

When CLK and DATA lines are shared between devices, it is recommended to divide down the voltage to the

CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.

•

If the CLK and DATA lines are toggled while the in VCO is in lock. As is sometimes the case when these lines

are shared with other parts, the phase noise may be degraded during the time of this programming.

MSB

D27

LSB

A0

DATA

CLK

LE

D26

D25

D24

D23

D0

A3

A2

A1

t

CWH

CS

t

ES

t

CH

CES

t

CWL

t

EWH

Figure 20. Serial Data Input Timing

8.5.2 Recommended Initial Power on Programming Sequence

When the device is first powered up, the device needs to be initialized and the ordering of this programming is

very important. After the following sequence is complete, the device should be running and locked to the proper

frequency.

1. Apply power to the device and ensure the Vcc pins are at the proper levels.

2. Ensure that a valid reference is applied to the OSCin pin

3. Program register R5 with RESET (R5[4]) =1

4. Program registers R15,R13,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1, and R0

5. Wait 20 ms

6. Program the R0 register again OR do the recommended sequence for changing frequencies.

8.5.3 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies is as follows:

1. (optional) If the OUTx_MUX State is changing, program Register R5

2. (optional) If the VCO_DIV state is changing, program Register R3. See VCO_DIV[4:0] — VCO Divider Value

if programming a to a value of 4.

3. (optional) If the MSB of the fractional numerator or charge pump gain is changing, program register R1

4. (Required) Program register R0

Although not necessary, it is also acceptable to program the R0 register a second time after this programming

sequence. It is not necessary to program the initial power on sequence to change frequencies.

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Programming (continued)

8.5.4 Triggering Registers

The action of programming certain registers may trigger special actions as shown in Table 14.

Table 14. Triggering Registers

REGISTER

CONDITIONS

ACTIONS TRIGGERED

WHY THIS IS DONE

The registers are reset by the power on reset circuitry

when power is initially applied. The RESET bit allows the

user the option to perform the same functionality of the

power-on reset through software.

All Registers are reset to power on

default values. This takes less than 1

us. The reset bit is self-clearing.

R5

RESET = 1

This activates the frequency calibration, which chooses the

correct VCO core and also the correct frequency band

within that core. This is necessary whenever the frequency

is changed. If it is desired that the R0 register be

programmed without activating this calibration, then the

NO_FCAL bit can be set to zero. If the fastlock timeout

counter is programmed to a nonzero value, then this action

also engages fastlock.

—Starts the Frequency Calibration

—Engages Fastlock (If FL_TOC>0)

R0

NO_FCAL = 0

NO_FCAL = 1

This engages fastlock, which may be used to decrease the

lock time in some circumstances.

—Engages Fastlock (If FL_TOC>0)

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8.6.1 Programming Word Descriptions

8.6.1.1 Register R15

The programming of register R15 is only necessary when one wants to change the default value of

VCO_CAPCODE for improving the VCO calibration time or use the VCO_CAP_MAN bit for diagnostic purposes.

8.6.1.1.1 VCO_CAP_MAN — Manual VCO Band Select

This bit determines if the value of VCO_CAPCODE is just used as a starting point for the initial frequency

calibration or if the VCO is forced to this value. If this is forced, it is only for diagnostic purposes.

VCO_CAP_MAN

IMPACT of VCO_CAPCODE

0

1

VCO_CAPCODE value is initial starting point for VCO digital calibration.

VCO_CAPCODE value is forced all the time. For diagnostic purposes only.

8.6.1.1.2 VCO_CAPCODE[7:0] — Capacitor Value for VCO Band Selection

This word selects the VCO tank capacitor value that is initially used when VCO calibration is run or that is forced

when VCO_CAP_MAN is set to one. The lower values correspond to less capacitance, which corresponds to a

higher VCO frequency for a given VCO Core. If this word is not programmed, it is defaulted to 128.

VCO_CAPCODE

VCO TANK CAPACITANCE

VCO FREQUENCY

0

...

Minimum

...

Highest

...

255

Maximum

Lowest

8.6.1.2 Register R13

Register R13 gives access to words that are used for the digital lock detect circuitry.

8.6.1.2.1 DLD_ERR_CNT[3:0] - Digital Lock Detect Error Count

This is the amount of phase detector comparisons that may exceed the tolerance as specified in DLD_TOL

before digital lock indicates an unlocked state. The recommended default is 4 for phase detector frequencies of

80 MHz or below; higher frequencies may require the user to experiment to optimize this value.

8.6.1.2.2 DLD_PASS_CNT[9:0] - Digital Lock Detect Success Count

This value multiplied by 8 is the amount of phase detector comparison within the tolerance specified by

DLD_TOL and adjusted by DLD_ERR_CNT that are necessary to cause the digital lock to indicate a locked

state. The recommended value is 32 for phase detector frequencies of 80 MHz or below; higher frequencies may

require the user to experiment and optimize this value based on application.

8.6.1.2.3 DLD_TOL[2:0] — Digital Lock Detect

This is the tolerance that is used to compare with each phase error to decide if it is a success or a fail. Larger

settings are generally recommended, but they are limited by several factors such as PFD_DLY, modulator order,

and especially the phase detector frequency.

DLD_TOL

PHASE ERROR TOLERANCE (ns)

TYPICAL PHASE DETECTOR FREQUENCY

Fpd > 130 MHz

0

1

1.7

80 MHz < Fpd ≤ 130 MHz

60 MHz < Fpd ≤ 80 MHz

45 MHz < Fpd ≤ 60 MHz

30 MHz <Fpd ≤ 45 MHz

Fpd ≤ 30 MHz

2

3

6

10

4

5

18

6–7

Reserved

n/a

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8.6.1.3 Registers R10, R9, and R8

These registers control functions that are not disclosed to the user and the power on default values are not

optimal. Therefore these registers need to be programmed to the values specified in the register map for proper

operation.

8.6.1.4 Register R7

This register has words that control status pins, which would be LD, MUXout, and FLout

8.6.1.4.1 FL_PINMODE[2:0], MUXOUT_PINMODE[2:0], and LD_PINMODE[2:0] — Output Format for Status Pins

These words control the state of the output pin.

FL_PINMODE

MUXOUT_PINMODE

LD_PINMODE

OUTPUT TYPE

TRI-STATE

(Default for LD_PINMODE)

0

Push-Pull

(Default for MUXOUT_PINMODE)

1

2

3

Open Drain

High Drive Push-Pull

(Can drive 5 mA for an LED)

4

5

High Drive Open Drain

High Drive Open Source

Reserved

6,7

8.6.1.4.2 FL_INV, MUX_INV, LD_INV - Inversion for Status Pins

The logic for the LD and MUXOUT pins can be inverted with these bits.

FL_INV

MUX_INV

LD_INV

PIN STATUS

0

1

Normal Operation

Inverted

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8.6.1.4.3 FL_SELECT[4:0], MUXOUT_SELECT[4:0], LD_SELECT[4:0] — State for Status Pins

This word controls the output state of the MUXout, LD, and FLout pins. Note that during fastlock, the

FL_SELECT word is ignored.

FL_SELECT

MUXOUT_SELECT

LD_SELECT

OUTPUT

0

1

GND

Digital Lock Detect (Based on Phase Measurement)

Vtune Lock Detect (Based on tuning voltage)

Lock Detect (Based on Phase Measurement AND tuning voltage)

Readback (Default for MUXOUT_SELECT)

PLL_N divided by 2

2

3

4

5

6

PLL_N divided by 4

7

PLL_R divided by 2

8

PLL_R divided by 4

9

Analog Lock Detect

10

11

12

13

14

15

16-31

OSCin Detect

Fin Detect

Calibration Running

Tuning Voltage out of Range

VCO calibration fails in the low frequency direction.

VCO Calibration fails in the high frequency direction.

Reserved

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8.6.1.5 Register R6

8.6.1.5.1 RD_DIAGNOSTICS[19:0] — Readback Diagnostics

This word is contains several pieces of information that may be read back for debug and diagnostic purposes.

RD_DIAGNOISTICS[19:8]

19

18

17

16

15

[14:11]

10

9

8

CAL_

RUNNING

VCO_RAIL_

HIGH

VCO_RAIL_

LOW

VCO_SELECT FIN_DETECT

OSCIN_DETECT VCO_DETECT

Reserved

RD_DIAGNOISTICS[7:0]

7

6

5

4

3

2

1

0

VCO_TUNE_

HIGH

VCO_TUNE_

VALID

LD_PIN

STATE

CE_PIN

STATE

BUFEN_PIN

STATE

Reserved

FLOUT_ON

DLD

WORD NAME

MEANING if VALUE is ONE

This is the VCO that the device chose to use. 0 = VCO 1, 1 = VCO 2, 2 = VCO 3, 3 = VCO 4

VCO_ SELECT

Indicates transitions at the Fin pin have been detected. This could either be the VCO signal or self-oscillation of the

Fin pin in the even that no signal is present. This bit needs to be manually reset by programing register R5 with

R5[30] = 1, and then again with bit R5[30]=0

FIN_DETECT

Indicates transitions at the OSCin pin have been detected. This could either be a signal at the OSCin pin or self-

oscillation at the OSCin pin in the event no signal is present . This bit needs to be manually reset by programming

R5 with R5[29] = 1 and then again with R5[29] = 0.

OSCIN_DETECT

CAL_RUNNING

Indicates that some calibration in the part is currently running.

Indicates that the VCO frequency calibration failed because the VCO would need to be a higher frequency than it

could achieve.

VCO_RAIL_HIGH

Indicates that the VCO frequency calibration failed because the VCO would need to be a lower frequency than it

could achieve.

VCO_RAIL_LOW

VCO_TUNE_HIGH

VCO_TUNE_VALID

FLOUT_ON

Indicates that the VCO tuning voltage is higher than 2.4 volts and outside the allowable range.

Indicates that the VCO tuning voltage is inside then allowable range.

Indicates that the FLout pin is low.

Indicates that the digital lock detect phase measurement indicates a locked state. This does not include any

consideration of the VCO tuning voltage.

DLD

LD_PINSTATE

This is the state of the LD Pin.

This is the state of the CE pin.

This is the state of the BUFEN pin.

CE_PINSTATE

BUFEN_PINSTATE

8.6.1.5.2 RDADDR[3:0] — Readback Address

When the ID bit is set to zero, this word designates which register is read back from. When the ID bit is set to

one, the unique part ID identifying the device as the LMX2581E is read back.

ID

RDADDR

INFORMATION READ BACK

1

Don't Care

Part ID

Register R0

Register R1

...

0

1

...

0

15 (default)

Register R15

8.6.1.5.3 uWIRE_LOCK - Microwire lock

uWIRE_LOCK

MICROWIRE

0

1

Normal Operation

Locked out – All Programming except to the uWIRE_LOCK bit is ignored

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8.6.1.6 Register R5

8.6.1.6.1 OUT_LDEN — Mute Outputs Based on Lock Detect

When this bit is enabled, the RFoutA and RFoutB pins are disabled if the PLL digital lock detect circuitry

indicates that the PLL is in the unlocked state.

OUT_LDEN

PLL DIGITAL LOCK DETECT STATUS

RFoutA / RFoutB PINS

Normal Operation

Powered Down

0

1

Don't Care

Locked

Unlocked

8.6.1.6.2 OSC_FREQ[2:0] — OSCin Frequency for VCO Calibration

This word should be set to in accordance to the OSCin frequency BEFORE the doubler. It is critical for running

internal calibrations for this device.

OSC_FREQ

OSCin FREQUENCY

f_OSCin< 64 MHz

0

1

64 ≤ f_OSCin< 128 MHz

128 ≤ f_OSCin< 256 MHz

256 ≤ f_OSCin< 512 MHz

512 ≤ f_OSCin

2

3

4

≥ 5

Reserved

8.6.1.6.3 BUFEN_DIS - Disable for the BUFEN Pin

This pin allows the BUFEN pin to be disabled. This is useful if one does not want to pull this pin high or use it for

the readback ID.

BUFEN_DIS

BUFEN PIN

Impacts Output buffers

Ignored.

0

1

8.6.1.6.4 VCO_SEL_MODE — Method of Selecting Internal VCO Core

This word allows the user to choose how the VCO selected by the VCO_SEL word is treated. Note setting 0

should not be used if switching from a frequency above 3 GHz to a frequency below 2.2 GHz.

VCO_SEL_MODE

VCO SELECTION

VCO core is automatically selected based on the last one that was used. If none was used before, it chooses

the lowest frequency VCO core.

0

VCO selection starts at the value as specified by the VCO_SEL word. However, if this is invalid, it will choose

another VCO.

1

VCO is forced to the selection as defined by the VCO_SEL word, regardless of whether it is valid or not. Note

that this mode is not ensured and is only included for diagnostic purposes.

2

3

Reserved

8.6.1.6.5 OUTB_MUX — Mux for RFoutB

This word determines whether RFoutB is the VCO frequency, the VCO frequency divided by VCO_DIV, or the fin

frequency.

OUTB_MUX

RFoutB FREQUENCY

0

1

2

3

f_VCO

f_VCO/ VCO_DIV

f_Fin

Reserved

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8.6.1.6.6 OUTA_MUX — Mux for RFoutA

This word determines whether RFoutA is the VCO frequency, the VCO frequency divided by VCO_DIV, or the fin

frequency.

OUTA_MUX

RFoutA FREQUENCY

0

1

2

3

f_VCO

f_VCO/ VCO_DIV

f_Fin

Reserved

8.6.1.6.7 0_DLY - Zero Delay Mode

When this mode is enabled, the VCO divider is put in the feedback path of the PLL so that the delay from input

to output of the device will be deterministic.

0_DLY

PHASE DETECTOR INPUT

Direct VCO or Fin signal.

Channel Divider output.

0

1

8.6.1.6.8 MODE[1:0] — Operating Mode

This word determines in what mode the device is run.

MODE

OPERATIONAL MODE

Full Chip Mode

PLL Only Mode

Reserved

PLL

VCO

FIN PIN

0

1

Powered Up

Reserved

Powered Up

Powered Down

Reserved

Powered Down

Reserved

2,3

8.6.1.6.9 PWDN_MODE - Powerdown Mode

This word powers the device up and down. Aside from the traditional power up and power down, there is the

partial powerdown that powers down the PLL and VCO, but keeps the LDOs powered up to allow the device to

power up faster.

PWDN_MODE

CE Pin

X

DEVICE STATUS

Powered Up

0

1

2

3

X

Full Powerdown

Reserved

X

Partial Powerdown

Full Powerdown

Powered Up

Low

High

X

4

5

6

Reserved

Low

High

Low

High

Partial Powerdown

Powered Up

Full Powerdown

Partial Powerdown

7

8.6.1.6.10 RESET - Register Reset

When this bit is enabled, the action of programming register R5 resets all registers to their default power on reset

status, otherwise the words in register 5 may be programmed without resetting all the registers.

RESET

ACTION of PROGRAMMING REGISTER R5

Registers and state machines are operational.

0

1

Registers and state machines are reset, then this reset is automatically released.

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8.6.1.7 Register R4

8.6.1.7.1 PFD_DLY[2:0] — Phase Detector Delay

This word controls the minimum on time for the charge pump. The minimum setting often yields the best phase

detector spurs and integer mode PLL phase noise. Higher settings may be useful in reducing the delta sigma

noise of the modulator when dithering is enabled. These settings are not generally recommended if the phase

detector frequency exceeds 130 MHz. If unsure, program this word to zero.

PFD_DLY

PULSE WIDTH

WHEN RECOMMENDED

Default

Use with a 2nd order modulator , when

dithering is disabled, or when the phase

detector frequency is >130 MHz.

0

370 ps

1

2

3

4

5

6

7

760 ps

1130 ps

1460 ps

1770 ps

2070 ps

2350 ps

2600 ps

Consider these settings for a 3rd order

modulator when dithering is used.

8.6.1.7.2 FL_FRCE — Force Fastlock Conditions

This bit forces the fastlock conditions on, provided that the FL_TOC word is greater than zero.

FL_FRCE

FASTLOCK TIMEOUT COUNTER

FASTLOCK

0

Disabled

0

Fastlock engaged as long as timeout counter is

counting down

> 0

0

Invalid State

1

> 0

Always Engaged

8.6.1.7.3 FL_TOC[11:0] — Fastlock Timeout Counter

This word controls the timeout counter used for fastlock.

FL_TOC

FASTLOCK TIMEOUT COUNTER

Disabled

COMMENTS

0

1

Fastlock Disabled

2 x Reference Cycles

2 x 2 x Reference cycles

2

Fastlock engaged as long as timeout counter is

counting down

...

4095

2 x 4095 x Reference cycles

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8.6.1.7.4 FL_CPG[4:0] — Fastlock Charge Pump Gain

This word determines the charge pump current that is active during fastlock.

FL_CPG

FASTLOCK CURRENT STATE

0

1

TRI-STATE

1X

2X

...

2

..

31

31X

8.6.1.7.5 CPG_BLEED[5:0]

The CPG bleed word is for advanced users who want to get the lowest possible integer boundary spur. The

impact of this word is on the order of 2 dB. For users who do not care about this, the recommendation is to

default this word to zero.

USER TYPE

FRAC_ORDER

CPG

CPG BLEED RECOMMENDATION

Basic User

X

< 2

X

0

2

4

< 4X

Advanced User

4X ≤ CPG < 12X

12X ≤ CPG

>1

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8.6.1.8 Register R3

8.6.1.8.1 VCO_DIV[4:0] — VCO Divider Value

This word determines the value of the VCO divider. Note that the this divider may be bypassed with the

OUTA_MUX and OUTB_MUX words.

VCO_DIV

VCO DIVIDER VALUE

0

2

1

4

2

6

3

4

8

10

...

38

18

20 - 31

Invalid State

8.6.1.8.2 OUTB_PWR[5:0] — RFoutB Output Power

This word controls the output power for the RFoutB output.

OUTB_PWR

RFoutB POWER

Minimum

...

0

...

47

Maximum

Reserved

48 – 63

8.6.1.8.3 OUTA_PWR[5:0] — RFoutA Output Power

This word controls the output power for the RFoutA output.

OUTA_PWR

RFout POWER

Minimum

...

0

...

47

Maximum

Reserved.

48 – 63

8.6.1.8.4 OUTB_PD — RFoutB Powerdown

This bit powers down the RFoutB output.

OUTB_PD

RFoutB

0

1

Normal Operation

Powered Down

8.6.1.8.5 OUTA_PD — RFoutA Powerdown

This bit powers down the RFoutA output.

OUTA_PD

RFoutA

0

1

Normal Operation

Powered Down

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8.6.1.9 Register R2

8.6.1.9.1 OSC_2X — OSCin Doubler

This bit controls the doubler for the OSCin frequency.

OSC_2X

OSCin DOUBLER

Disabled

0

1

Enabled

8.6.1.9.2 CPP - Charge Pump Polarity

This bit sets the charge pump polarity. Note that the internal VCO has a negative tuning gain, so it should be set

to negative gain with the internal VCO enabled.

CPP

CHARGE PUMP POLARITY

Positive

0

1

Negative (Default)

8.6.1.9.3 PLL_DEN[21:0] — PLL Fractional Denominator

These words control the denominator for the PLL fraction. Note that 0 is only permissible in integer mode.

PLL

_

PLL_DEN[21:0]

DEN

0

1

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

1

.

...

4194

303

1

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8.6.1.10 Register R1

8.6.1.10.1 CPG[4:0] — PLL Charge Pump Gain

This word determines the charge pump current that used during steady state operation.

CPG

0

CHARGE PUMP CURRENT STATE

TRI-STATE

1

1X

2X

...

2

..

31

31X

Note that if the CPG setting is 400 µA or lower, then the CPG_BLEED word needs to be set to 0.

8.6.1.10.2 VCO_SEL[1:0] - VCO Selection

These words allow the user to specify which VCO the frequency calibration starts at. If uncertain, program this

word to 0 to start at the lowest frequency VCO core. A programming setting of 3 (VCO 4) should not be used if

switching to a frequency below 2.2 GHz.

VCO_SEL

VCO SELECTION

VCO 1

(Lowest Frequency)

0

1

2

VCO 2

VCO 3

VCO 4

(Highest Frequency)

3

8.6.1.10.3 FRAC_ORDER[2:0] — PLL Delta Sigma Modulator Order

This word sets the order for the fractional engine.

FRAC_ORDER

MODULATOR ORDER

Integer Mode

0

1

1st Order Modulator

2nd Order Modulator

3rd Order Modulator

Reserved

2

3

4-7

8.6.1.10.4 PLL_R[7:0] — PLL R divider

This word sets the value that divides the OSCin frequency.

PLL_R

PLL_R DIVIDER VALUE

0

1

256

1 (bypass)

...

255

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8.6.1.11 Register R0

Register R0 controls the frequency of the device. Also, unless disabled by setting NO_FCAL = 1, the action of

writing to the R0 register triggers a frequency calibration for the internal VCO.

8.6.1.11.1 ID - Part ID Readback

When this bit is set, the part ID indicating the device is an LMX2581E is read back from the device. Consult the

Feature Description for more details.

ID

0

READBACK MODE

Register

1

Part ID

8.6.1.11.2 FRAC_DITHER[1:0] — PLL Fractional Dithering

This word sets the dithering mode. When the fractional numerator is zero, it is recommended, although not

required, to set the FRAC_DITHER mode to disabled for the best possible spurs. Doing this shuts down the

fractional circuitry and eliminates fractional spurs for these frequencies. This is the reason why the

FRAC_DITHER word is in the R0 register, so that it can be set correctly for every frequency if this setting

changes.

FRAC_DITHER

DITHERING MODE

Weak

0

1

2

3

Medium

Strong

Disabled

8.6.1.11.3 NO_FCAL — Disable Frequency Calibration

Normally, when the R0 register is written to, a frequency calibration for the internal VCO is triggered. However,

this feature may be disabled. If the frequency is changed, then this frequency calibration is necessary for the

internal VCO.

NO_FCAL

VCO FREQUENCY CALIBRATION

Done upon write to R0 Register

Not done on write to R0 Register

0

1

8.6.1.11.4 PLL_N - PLL Feedback Divider Value

This is the feedback divider value for the PLL. There are some restrictions on this depending on the modulator

order.

PLL_N

<7

PLL_N[11:0]

Invalid state

7

Possible only in integer mode or with a 1st order modulator

Possible in integer mode, 1st order modulator, or 2nd order modulator

Possible only in integer mode, 1st order modulator, 2nd order modulator, or 3rd order modulator

8-9

10-13

14

0

...

1

0

...

1

0

...

1

0

...

1

0

...

1

0

...

1

0

...

1

0

...

1

...

1

...

1

...

1

0

...

1

...

4095

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8.6.1.11.5 PLL_NUM[21:12] and PLL_NUM[11:0] — PLL Fractional Numerator

These words control the numerator for the PLL fraction.

PLL

_

PLL_NUM[21:12]

NU

PLL_NUM[11:0]

M

0

1

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

1

.

...

4095

4096

...

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

.

0

1

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

4194

303

1

41

LMX2581E

ZHCSDY3 –MAY 2015

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMX2581E can be used in a broad class of applications. In general, they tend to fall in the categories where

the output frequency is a nicely related input frequency and those that require fractional mode. The following

schematic generally applies to most applications.

9.2 Typical Applications

Figure 21. Typical Schematic

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Typical Applications (continued)

9.2.1 Clocking Application

When the output and input frequencies are nicely related, the LMX2581E can often achieve this in integer mode.

In integer mode, fractional spurs and noise are much less of a concern, so higher phase detector frequency and

wider loop bandwidth are typically used for optimal phase noise performance.

9.2.1.1 Design Requirements

For this example, consider a design for a fixed 1500 MHz output clock to be generated from a 100 MHz input

clock. Good close in phase noise and maximizing the output power are desired in this particular example

9.2.1.2 Detailed Design Procedure

For this kind of application, the design goal is typically to minimize the jitter.

PARAMETER

Fout

VALUE

1500 MHz

100 MHz

REASON for CHOOSING

This parameter was given.

Fosc

Choose a highest possible phase detector frequency. There are no fractional spurs and

this increases the value of C1

Fpd

200 MHz

Fvco

Kpd

3000 MHz

31x

The VCO needs to be a multiple of 1500 MHz, which restricts it to be 3000 MHz.

This maximizes the C1 capacitor and also the phase noise

Loop Bandwidth

256 kHz

Theoretically, optimal jitter is obtained by choosing the loop bandwidth to the frequency

where the open loop PLL and closed loop VCO noise are equal, which would be about

250 kHz. The phase margin is typically chosen around 70 degrees, but is chosen to be

50 degrees to increase the value of the C1 capacitor to be at least 1 nF to reduce VCO

phase noise degradation.

Phase Margin

50 deg

OUT_A_PWR

45

1 nF

This yields the maximum output power.

Calculated with TI clock design software

This gives maximum output power.

C1

C2

R2

6.8 nF

270 Ω

Pullup Component

18 nH Inductor

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9.2.1.3 Application Curves

Figure 22 is an example of the performance that one might see for an application like this. The achieved results

show an output power of about 14 dBm (single-ended) and a jitter from 100 Hz to 10 MHz of 100 fs. Note that

the output power is higher than +12 dBm as claimed in the electrical specifications because this is at a lower

frequency than 2.7 GHz.

-80

PLL Simulation

Measurement

VCO & Output Divider Simulation

Loop Bandwidth

-100

-120

-140

-160

1x10²2x10²5x10²1x10³2x10³5x10³1x10⁴2x10⁴5x10⁴1x10⁵2x10⁵5x10⁵1x10⁶2x10⁶5x10⁶1x10⁷2x10⁷5x10⁷1x10⁸

Offset (Hz)

Figure 23. Measured Plot

Figure 22. Measured Data and Loop Bandwidth Choice

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9.2.2 Fractional PLL Application

For applications where the output frequency is not always related nicely to the input frequency, lowering the loop

bandwidth and reducing the phase detector frequency can often improve spurs at the cost of in-band phase

noise.

9.2.2.1 Design Requirements

Consider generating 1880 to 3800 MHz from a 100 MHz input frequency with a channel spacing of 200 kHz. This

is the situation similar that was used for the EVM board.

9.2.2.2 Detailed Design Procedure

PARAMETER

Fout

VALUE

1880 - 3800 MHz

100 MHz

REASON for CHOOSING

This parameter was given.

Fosc

By trial and error and experimenting with the clock design tool, we see that this

gives a good trade-off between the integer boundary spur and phase noise.

Fpd

25 MHz

Loop Bandwidth

Kpd

28.7 KHz

31x

This is around where the PLL and VCO noise meet. The VCO is at 2700 MHz

Choose the highest charge pump gain to maximize the capacitor next to the VCO.

C1_LF

1.8 nF

56 nF

C2_LF

The loop filter can be calculated with the clock design tool. Note that we need to

keep the loop bandwidth not too wide so that the capacitor next to the VCO is

larger. Also, it is put in C4_LF spot, not C3_LF spot. Both are electrically

equivalent, but layoutwise, C4_LF makes more sense. See the board layout in

sections to come.

C3_LF

Open

C4_LF

3.3 nF

390 Ω

270 Ω

0 Ω

R2_LF

R3_LF

R4_LF

OUT_A_PWR

Pullup Component

30

This combination of pullup component and output power settings yields optimal

noise floor.

18 nH Inductor

9.2.2.3 Application Curves

Figure 25. Fractional Channel 2703 MHz

Figure 24. Integer Channel

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9.3 Do's and Don'ts


型号：	LMX2581E
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 VCO 的 3.8GHz 宽带频率合成器
文件：	总55页 (文件大小：1193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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