LMV7239QM7X/NOPB [TI]
汽车级微功耗 75ns 单路轨至轨比较器 | DCK | 5 | -40 to 125;
| 型号： | LMV7239QM7X/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级微功耗 75ns 单路轨至轨比较器 | DCK | 5 | -40 to 125 比较器 |
| 文件： | 总31页 (文件大小：2009K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
LMV7239-Q1
ZHCSI25 –APRIL 2018
具有开漏和推挽输出的 LMV7239-Q1 75ns、超低功耗、低压、轨至轨输入
比较器
1 特性
3 说明
1
•
•
符合汽车类 标准
具有符合 AEC-Q100 标准的下列特性：
LMV7239-Q1 是 75ns 超低功耗低压比较器。此器件
可在 2.7V 至 5.5V 的完整电源电压范围内正常运行。
该器件可实现 75ns 的传播延迟，而在 5V 电压下仅消
耗 65μA 的电源电流。
–
–
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
1C
LMV7239-Q1 具有更大的轨至轨共模电压范围。输入
共模电压范围可基于地电压向下扩展 200mV 并基于电
源电压向上扩展 200mV，从而允许接地感应和电源感
应。
器件 CDM ESD 分类等级 C5（DBV 封装）
•
•
•
•
•
•
•
VS = 5V，TA = 25°C（典型值，除非另有说明）
传播延迟：75ns
LMV7239-Q1 具有 推挽式输出级。凭借此特性，器件
无需外部上拉电阻器即可运行。
低电源电流：65µA
轨至轨输入
开漏和推挽输出
LMV7239-Q1 采用 5 引脚 SC70 和 5 引脚 SOT-23 封
装，因此非常适合需要小尺寸和低功耗特性的系统。
非常适合 2.7V 和 5V 单电源 应用
采用节省空间的封装：
器件信息(1)
–
–
5 引脚 SOT-23
5 引脚 SC70
器件型号
封装
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
SOT-23 (5)
SC70 (5)
LMV7239-Q1
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
•
便携式和电池供电类系统
机顶盒
高速差分线路接收器
窗口比较器
过零检测器
高速采样电路
电源电流与电源电压间的关系
传播延迟与过驱动
120
100
80
60
40
20
0
90
-40°C
25°C
V = 5V
S
C
=15pF
85°C
LOAD
125°C
85
80
75
70
Rising Edge
Falling Edge
0
1
2
3
4
5
20
40
60
80
100
SUPPLY VOLTAGE (V)
INPUT OVERDRIVE (mV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSD85
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, 2.7 V ............................... 5
6.6 Electrical Characteristics, 5 V .................................. 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 器件支持................................................................ 20
11.2 文档支持 ............................................................... 20
11.3 接收文档更新通知 ................................................. 20
11.4 社区资源................................................................ 20
11.5 商标....................................................................... 20
11.6 静电放电警告......................................................... 20
11.7 术语表 ................................................................... 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
第一版。将汽车器件从 SNOS532 移到独立的数
据表，并更新电气特性，2.7V 和电气特性，5V
表中的输入失调电压参数
2018 年 4 月
*
2
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
5 Pin Configuration and Functions
DBV and DGK Package
5-Pin SC70 and SOT-23
Top View
VOUT
V+
1
2
5
Vœ
Non-Inverting
Input
Inverting
Input
3
4
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
VOUT
V-
1
2
3
4
5
O
P
I
Output
Negative Supply
Noninverting Input
Inverting Input
IN+
IN-
I
V+
P
Positive Supply
Copyright © 2018, Texas Instruments Incorporated
3
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Differential Input Voltage
± Supply Voltage
V
(2)
Output Short Circuit Duration
Supply Voltage (V+ - V−)
See
6
V
SOLDERING INFORMATION
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235
°C
°C
V
260 (lead temp)
(V+) +0.3, (V−) −0.3
Voltage at Input/Output Pins
(3)
Current at Input Pin
±10
150
150
mA
°C
°C
Storage Temperature, Tstg
Junction Temperature,TJ
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
(3) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
6.2 ESD Ratings
VALUE
±1000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011(1)
Machine model (MM)
Electrostatic
discharge
V(ESD)
DBV package only
V
±100
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
MIN
2.7
–40
MAX
5.5
125
UNIT
V
Supply Voltages (V+ - V−)
Temperature Range(1)
°C
(1) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LMV7239-Q1
THERMAL METRIC(1)
DGK (SC70)
5 PINS
DBV (SOT-23)
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
478
265
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
6.5 Electrical Characteristics, 2.7 V
Unless otherwise specified, all limits ensured for TA = 25°C, VCM = V+/2, V+ = 2.7 V, V− = 0 V−.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1) UNIT
–6
±0.8
30
5
+6
+8
mV
VOS
Input Offset Voltage
At temp extremes
–8
400
600
200
400
IB
Input Bias Current
Input Offset Current
nA
nA
At temp extremes
IOS
At temp extremes
Common-Mode Rejection
Ratio
Power Supply Rejection Ratio V+ = 2.7 V to 5 V
0 V < VCM < 2.7 V(3)
CMRR
PSRR
52
65
62
85
dB
dB
V− −0.1 −0.2 to 2.9 V+ +0.1
Input Common-Mode Voltage
CMRR > 50 dB
VCM
VO
IS
V
Range
At temp extremes
V−
V+
350
450
IL = −4 mA,
VID = −500 mV
230
Output Swing Low
Supply Current
At temp extremes
mV
µA
IL = −0.4 mA,
VID = −500 mV
15
52
No load
85
At temp extremes
100
Overdrive = 20 mV
CLOAD = 15 pF
96
87
85
ns
ns
ns
Overdrive = 50 mV
CLOAD = 15 pF
tPD
Propagation Delay
Overdrive = 100 mV
CLOAD = 15 pF
LMV7239/LMV7239Q
10% to 90%
tr
tf
Output Rise Time
Output Fall Time
1.7
1.7
ns
ns
90% to 10%
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
(3) CMRR is not linear over the common mode range. Limits are guaranteed over the worst case from 0 to VCC/2 or VCC/2 to VCC
.
Copyright © 2018, Texas Instruments Incorporated
5
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
6.6 Electrical Characteristics, 5 V
Unless otherwise specified, all limits ensured for TA = 25°C, VCM = V+/2, V+ = 5 V, V− = 0 V.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)
UNIT
–6
±1
30
5
+6
+8
VOS
Input Offset Voltage
mV
At temp extremes
–8
400
600
200
400
IB
Input Bias Current
Input Offset Current
nA
At temp extremes
IOS
nA
dB
At temp extremes
0 V < VCM < 5 V
Common-Mode Rejection
Ratio
Power Supply Rejection Ratio V+ = 2.7 V to 5 V
CMRR
PSRR
52
65
67
85
dB
V
−0.2 to
V− −0.1
V−
V+ +0.1
Input Common-Mode Voltage
CMRR > 50dB
5.2
VCM
Range
At temp extremes
At temp extremes
V+
350
450
IL = −4 mA,
VID = −500 mV
230
VO
Output Swing Low
mV
µA
IL = −0.4 mA,
VID = −500 mV
10
65
95
IS
Supply Current
No load
At temp extremes
110
Overdrive = 20 mV
CLOAD = 15 pF
89
82
ns
ns
Overdrive = 50 mV
CLOAD = 15 pF
tPD
Propagation Delay
Output Fall Time
Overdrive = 100 mV
CLOAD = 15 pF
75
ns
ns
tf
90% to 10%
1.2
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
6
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
6.7 Typical Characteristics
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
100
10
1
120
-40°C
25°C
V
= 5V
S
85°C
125°C
100
80
60
40
20
0
.1
.01
.1
1
10
0
1
2
3
4
5
OUTPUT VOLTAGE REFERENCED TO V+ (V)
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Sourcing Current vs. Output Voltage
100
100
V
= 2.7V
V
= 5V
S
S
10
1
10
1
.1
.1
.01
.1
1
10
.01
.1
1
10
OUTPUT VOLTAGE REFERENCED TO V+ (V)
OUTPUT VOLTAGE REFERENCED TO GND (V)
Figure 3. Sourcing Current vs. Output Voltage
Figure 4. Sinking Current vs. Output Voltage
50
100
40
V
= 2.7V
S
VS = 5V
30
IBIAS+
20
10
10
1
0
-10
-20
-30
-40
-50
IBIAS
-
.1
.01
.1
1
10
-0.2
1
2
3
4
5
OUTPUT VOLTAGE REFERENCED TO GND (V)
VIN (V)
Figure 5. Sinking Current vs. Output Voltage
Figure 6. Input Bias Current vs. Input Voltage
Copyright © 2018, Texas Instruments Incorporated
7
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
Typical Characteristics (continued)
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
70
60
160
150
140
130
120
110
100
90
V
V
=2.7V
S
=20mV
VS = 2.7V
50
40
30
20
10
0
OD
C
=15pF
LOAD
IBIAS
+
Falling Edge
-10
-20
-30
-40
IBIAS
-
Rising Edge
-50
-60
80
2
0
1
2.7
-40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
VIN (V)
Figure 7. Input Bias Current vs. Input Voltage
Figure 8. Propagation Delay vs. Temperature
140
106
V =5V
S
V = 2.7V
S
V
=20mV
OD
V
=20mV
OD
130
120
110
100
90
104
102
100
98
C
LOAD
=15pF
Falling Edge
Falling Edge
96
Rising Edge
Rising Edge
80
94
-40 -20
0
20 40 60 80 100 120 140
0
20
40
60
80
100
TEMPERATURE (°C)
CAPACITANCE (pF)
Figure 9. Propagation Delay vs. Temperature
Figure 10. Propagation Delay vs. Capacitive Load
96
100
V
= 2.7V
LOAD
V
V
= 5V
S
S
C
=15pF
=20mV
OD
94
92
90
88
95
90
85
80
Rising Edge
Falling Edge
Rising Edge
Falling Edge
0
20
40
60
80
100
20 30 40 50 60 70 80 90 100
INPUT OVERDRIVE (mV)
CAPACITANCE (pF)
Figure 11. Propagation Delay vs. Capacitive Load
Figure 12. Propagation Delay vs. Input Overdrive
8
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
Typical Characteristics (continued)
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
90
120
115
110
105
100
95
V
V
= 2.7V
V
= 5V
LOAD
S
S
=20mV
C
=15pF
OD
C
=15pF
LOAD
85
80
75
70
Rising Edge
90
Falling Edge
85
Rising Edge
Falling Edge
80
20
40
60
80
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT OVERDRIVE (mV)
INPUT COMMON MODE VOLTAGE (V)
Figure 13. Propagation Delay vs. Input Overdrive
Figure 14. Propagation Delay vs. Common-Mode Voltage
110
V
V
= 5V
OD
LOAD
S
=20mV
C
=15pF
100
90
Falling Edge
Rising Edge
80
0
1
2
3
4
5
INPUT COMMON MODE VOLTAGE (V)
Figure 15. Propagation Delay vs. Common-Mode Voltage
Copyright © 2018, Texas Instruments Incorporated
9
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LMV7239-Q1 is an ultra low power, low voltage, 75-ns comparator. They are ensured to operate over the full
supply voltage range of 2.7 V to 5.5 V. These devices achieve a 75-ns propagation delay while consuming only
65 µA of supply current at 5 V.
The LMV7239-Q1 has a greater than rail-to-rail common-mode voltage range. The input common-mode voltage
range extends 200 mV below ground and 200 mV above supply, allowing both ground and supply sensing.
7.2 Functional Block Diagram
Figure 16. Simplified Schematic
7.3 Feature Description
7.3.1 Input Stage
The LMV7239-Q1 is a rail-to-rail input and output. The typical input common-mode voltage range of −0.2 V below
the ground to 0.2 V above the supply. The LMV7239-Q1 uses a complimentary PNP and NPN input stage in
which the PNP stage senses common-mode voltage near V− and the NPN stage senses common-mode voltage
near V+. If either of the input signals falls below the negative common mode limit, the parasitic PN junction
formed by the substrate and the base of the PNP will turn on resulting in an increase of input bias current.
If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic
level as long as the other input stays within the common mode range. However, the propagation delay will
increase. When both inputs are outside the common-mode voltage range, current saturation occurs in the input
stage, and the output becomes unpredictable.
The propagation delay does not increase significantly with large differential input voltages. However, large
differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage.
7.3.2 Output Stage: LMV7239-Q1
The LMV7239-Q1 has a push-pull output. When the output switches, there is a low resistance path between VCC
and ground, causing high output sinking or sourcing current during the transition.
10
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
Feature Description (continued)
Figure 17. LMV7239-Q1 Push-Pull Output Stage
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay is not affected by capacitive loads at the output of the LPV7239 or LMV7239-Q1.
However, resistive loads slightly effect the propagation delay on the falling edge depending on the load
resistance value.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to spend time between high and low when the
input signal changes slowly. The result is the output may oscillate between high and low when the differential
input is near zero. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the
input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the
noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
To improve propagation delay when low overdrive is needed hysteresis can be added.
7.4.3.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
V+ of the comparator as shown in Figure 18. When VIN at the inverting input is less than VA, the voltage at the
noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as
high as V+). The three network resistors can be represented as R1//R3 in series with R2.
Copyright © 2018, Texas Instruments Incorporated
11
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
Device Functional Modes (continued)
Figure 18. Inverting Comparator With Hysteresis
The lower input trip voltage VA1 is defined as:
VA1 = VCCR2 / [(R1 // R3) + R2)]
(1)
When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network
resistors can be presented as R2 // R3 in series with R1.
The upper trip voltage VA2 is defined as:
VA2 = VCC (R2 // R3) / [(R1 ) + (R2 // R3)]
(2)
The total hysteresis provided by the network is defined as ΔVA = VA1 - VA2.
+VCCR1R2
DVA
=
R1R2 + R1R3 + R2R3
(3)
7.4.3.2 Non-Inverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up
to VIN1 where VIN1 is calculated by:
VREF(R1 + R2 )
DV
=
IN1
R2
(4)
As soon as VO switches to VCC, VA steps to a value greater than VREF which is given by:
(VCC - VIN1)R1
VA = V
+
IN
R1 + R2
(5)
To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN2
can be calculated by:
12
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
Device Functional Modes (continued)
VREF(R1 + R2 ) - VCC R1
V
=
IN2
R2
(6)
(7)
The hysteresis of this circuit is the difference between VIN1 and VIN2
.
ΔVIN = VCCR1 / R2
V
CC
V
REF
R
-
V
A
V
O
V
IN
+
R
1
L
R
2
Figure 19. Noninverting Comparator With Hysteresis
Figure 20. Noninverting Comparator Thresholds
7.4.4 Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is
connected to a 100 mVPP AC signal. As the signal at the noninverting input crosses 0V, the comparator’s output
changes state.
Figure 21. Simple Zero Crossing Detector
7.4.4.1 Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN
= 0.
The positive feedback resistor, R6, is made very large with respect to R5 || R6 = 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output
voltage transitions.
Diode D1 is used to ensure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to
approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
Copyright © 2018, Texas Instruments Incorporated
13
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
Device Functional Modes (continued)
V
CC
R3
R
4
R
R
2
1
V
-
IN
V
2
V
O
V
1
+
D1
R
6
R
5
Figure 22. Zero Crossing Detector With Hysteresis
7.4.5 Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the noninverting input passes the VREF threshold, the comparator’s output changes state. It is important to use a
stable reference voltage to ensure a consistent switching point.
Figure 23. Threshold Detector
14
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7239-Q1 is a single supply comparator with 75 ns of propagation delay and only 65 µA of supply
current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
R
4
C
R
1
-
V
C
V
O
+
R
3
1
V
A
+
V
+
V
R
2
0
Figure 24. Square Wave Oscillator
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. The circuit in Figure 24 generates a square
wave whose period is set by the RC time constant of the capacitor C1 and resistor R4.
8.2.1.2 Detailed Design Procedure
The maximum frequency is limited by the large signal propagation delay of the comparator and by the capacitive
loading at the output, which limits the output slew rate.
Figure 25. Square Wave Oscillator Timing Thresholds
Consider the output of Figure 24 to be high to analyze the circuit. That implies that the inverted input (VC) is
lower than the noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC
increases until it is equal to the noninverting input. The value of VA at this point is:
VCC ∂R2
VA1
=
R
R2 + R1 R3
(8)
15
If R1 = R2 = R3, then V A1 = 2 Vcc/3
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
Typical Applications (continued)
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is:
R
VCC(R2 R3 )
VA2
=
R
R1 + (R2 R3 )
(9)
If R1 = R2 = R3, then VA2 = VCC/3.
The capacitor C1 now discharges through R4, and the voltage VC decreases until it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1·ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
(10)
The LMV7239 should be used for a symmetrical output. The LMV7235 will require a pullup resistor on the output
to function, and will have a slightly asymmetrical output due to the reduced sourcing current.
8.2.1.3 Application Curves
Figure 26 shows the simulated results of an oscillator using the following values:
1. R1 = R2 = R3 = R4 = 100 kΩ
2. C1 = 100 pF, CL = 20 pF
3. V+ = 5 V, V– = GND
4. CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
V
a
4
3
2
1
V
c
0
-1
0
10
20
30
40
50
TIME (µs)
C001
Figure 26. Square Wave Oscillator Output Waveform
8.2.2 Crystal Oscillator
A simple crystal oscillator using the LMV7239-Q1 is shown in Figure 27. Resistors R1 and R2 set the bias point at
the comparator’s noninverting input. Resistors, R3 and R4 and capacitor C1 set the inverting input node at an
appropriate DC average level based on the output. The crystal’s path provides resonant positive feedback and
stable oscillation occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor
tolerances and to a lesser extent by the comparator
16
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
Typical Applications (continued)
VCC
100K
100K
Crystal
VOUT
100K
0.1uF
Figure 27. Crystal Oscillator
8.2.3 Infrared (IR) Receiver
The LMV7239-Q1 can also be used as an infrared receiver. The infrared photo diode creates a current relative to
the amount of infrared light present. The current creates a voltage across RD. When this voltage level cross the
voltage applied by the voltage divider to the inverting input, the output transitions.
Figure 28. IR Receiver
8.2.4 Window Detector
+
V
R
1
V
+
-
REF2
OUTPUT A
OUTPUT B
A
B
V
IN
R
2
+
-
V
REF1
R
3
Figure 29. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
Copyright © 2018, Texas Instruments Incorporated
17
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
Typical Applications (continued)
OUTPUT B
V
IN
+
V
V
V
REF2
REF1
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 30. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or "within the window", where these are
defined as:
VREF1 = R3/R1+R2+R3) × V+
(11)
(12)
VREF2 = R2+R3)/R1+R2+R3) × V+
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to "ring" due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV7239-Q1 as a high-speed device. Keep the ground paths short and place small (low ESR ceramic)
bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
18
Copyright © 2018, Texas Instruments Incorporated
LMV7239-Q1
www.ti.com.cn
ZHCSI25 –APRIL 2018
10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane will help to ensure the specified performance of the LMV7239-
Q1. Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount components will
also help. Comparators are very sensitive to input noise.
The LMV7239-Q1 requires a high-speed layout. Follow these layout guidelines:
1. Use printed-circuit board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF, ceramic surface-mount capacitor) as close as possible to VCC pin.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from output.
4. Solder the device directly to the printed-circuit board rather than using a socket.
5. For slow moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to tPD when the source impedance is low.
6. The top-side ground plane runs between the output and inputs.
7. Ground trace from the ground pin runs under the device up to the bypass capacitor, shielding the inputs from
the outputs.
10.2 Layout Example
Figure 31. SOT-23 Board Layout Example
版权 © 2018, Texas Instruments Incorporated
19
LMV7239-Q1
ZHCSI25 –APRIL 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
TINA-TI 基于 SPICE 的模拟仿真程序，http://www.ti.com.cn/tool/cn/tina-ti
DIP 适配器评估模块，http://www.ti.com.cn/tool/cn/dip-adapter-evm
TI 通用运行放大器评估模块，http://www.ti.com.cn/tool/cn/opampevm
11.2 文档支持
11.2.1 相关文档
《四个独立运行的比较器》(SNOA654)
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
20
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV7239QDBVRQ1
LMV7239QM7/NOPB
LMV7239QM7X/NOPB
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DCK
5
5
5
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
ZBMX
C42
SN
SN
SC70
C42
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV7239QDBVRQ1
LMV7239QM7/NOPB
LMV7239QM7X/NOPB
SOT-23
SC70
DBV
DCK
DCK
5
5
5
3000
1000
3000
178.0
178.0
178.0
8.4
8.4
8.4
3.2
3.2
1.4
1.2
1.2
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
2.25
2.25
2.45
2.45
SC70
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV7239QDBVRQ1
LMV7239QM7/NOPB
LMV7239QM7X/NOPB
SOT-23
SC70
DBV
DCK
DCK
5
5
5
3000
1000
3000
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明