LMV712LDX [TI]
LMV712-N Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown; LMV712 -N的低功耗，低噪声，高输出， RRIO双带独立的关断运算放大器
| 型号： | LMV712LDX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMV712-N Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown |
| 文件： | 总22页 (文件大小：1111K) |
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LMV712-N
www.ti.com
SNOS534G –MAY 2004–REVISED MARCH 2010
LMV712-N Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with
Independent Shutdown
Check for Samples: LMV712-N
1
FEATURES
2
•
(Typical Unless Otherwise Noted)
•
•
1.5µA Shutdown ICC
2.2µs Turn On
•
•
•
•
•
•
•
•
•
5MHz GBP
Slew Rate 5V/µs
APPLICATIONS
Low Noise 20nV/√Hz
•
•
•
•
•
•
Power Amplifier Control Loop
Cellular Phones
Supply Current 1.22mA/Channel
VOS< 3mV Max
Portable Equipment
Wireless LAN
Guaranteed 2.7V and 5V Specifications
Rail-to-Rail Inputs and Outputs
Unity Gain Stable
Radio Systems
Cordless Phones
Small Package: 10-Pin WSON, 10-Pin VSSOP
and 10-Bump DSBGA
DESCRIPTION
The LMV712-N duals are high performance BiCMOS operational amplifiers intended for applications requiring
Rail-to-Rail inputs combined with speed and low noise. They offer a bandwidth of 5MHz and a slew rate of 5
V/µs and can handle capacitive loads of up to 200pF without oscillation.
The LMV712-N is guaranteed to operate from 2.7V to 5.5V and offers two independent shutdown pins. This
feature allows disabling of each device separately and reduces the supply current to less than 1µA typical. The
output voltage rapidly ramps up smoothly with no glitch as the amplifier comes out of the shutdown mode.
The LMV712-N with the shutdown feature is offered in space saving 10-Bump DSBGA and 10-Pin WSON
packages. It is also offered in 10-Pin VSSOP package. These packages are designed to meet the demands of
small size, low power, and low cost required by cellular phones and similar battery operated portable electronics.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
LMV712-N
SNOS534G –MAY 2004–REVISED MARCH 2010
www.ti.com
Typical Application Circuit
Figure 1. P.A. Control Loop
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
1.5kV
150V
Machine Model
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ - V−)
Output Short Circuit V+
Output Short Circuit V−
Current at Input Pin
±Supply Voltage
(V+) +0.4V to (V−) −0.4V
6V
(4)
(4)
±10mA
±50mA
Current at Output Pin
Storage Temp Range
Junction Temperature TJMAX
−65°C to 150°C
150°C
(5)
Soldering specification for WSON SnPb:
Infrared or Convection (20sec)
235°C
Soldering specification for all other packages:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) Shorting circuit output to either V+ or V− will adversely affect reliability.
(5) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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(1)
Recommended Operating Conditions
Supply Voltage
2.7V to 5.5V
Temperature Range
−40°C ≤ TJ ≤ 85°C
Thermal Resistance
10-Pin VSSOP
235°C/W
53.4°C/W
196°C/W
10-Pin WSON
10-Bump DSBGA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V − = 0V, VCM = 1.35V and TA = 25°C and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
VSSOP
WSON
0.4
3
3
3.2
VCM = 0.85V and
VCM = 1.85V
VOS
Input Offset Voltage
mV
DSBGA
7
9
5.5
75
90
90
115
130
IB
Input Bias Current
pA
dB
dB
dB
50
45
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 2.7V
2.7V ≤ V+ ≤ 5V,
VCM = 0.85V
2.7V ≤ V+ ≤ 5V,
VCM = 1.85V
70
68
PSRR
CMVR
ISC
Power Supply Rejection Ratio
Common Mode Voltage Range
Output Short Circuit Current
70
68
For CMRR ≥ 50dB
−0.3
3
−0.2
V
2.9
Sourcing
VO = 0V
15
12
25
mA
mA
V
Sinking
VO = 2.7V
25
22
50
2.62
2.60
2.68
0.01
2.55
0.05
RL = 10kΩ to 1.35V
RL = 600Ω to 1.35V
0.12
0.15
V
VO
Output Swing
2.52
2.50
V
0.23
0.30
V
VO(SD)
IS
Output Voltage in Shutdown
Supply Current per Channel
10
200
mV
mA
1.22
1.7
1.9
On Mode
0.12
1.5
2.0
Shutdown Mode
uA
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
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2.7V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V − = 0V, VCM = 1.35V and TA = 25°C and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
dB
(1)
(2)
(1)
Sourcing
RL = 10kΩ
80
76
115
113
97
VO = 1.35V to 2.3V
Sinking
RL = 10kΩ
80
76
dB
VO = 0.4V to 1.35V
AVOL
Large Signal Voltage Gain
Sourcing
RL = 600Ω
80
dB
VO = 1.35V to 2.2V
76
Sinking
RL = 600Ω
80
100
dB
VO = 0.5V to 1.35V
76
On Mode
2.4 to 2.7 2.0 to 2.7
V
V
VSD
Shutdown Pin Voltage Range
Shutdown Mode
0 to 0.8
0 to 1
5
GBWP
SR
Gain-Bandwidth Product
Slew Rate
MHz
V/µs
Deg
nV/√Hz
(3)
5
φm
Phase Margin
60
20
2.2
en
Input Referred Voltage Noise
f = 1kHz
4
4.6
Turn-On Time from Shutdown
Turn-On Time from Shutdown
μs
μs
TON
6
8
DSBGA
(3) Number specified is the slower of the positive and negative slew rates.
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+ = 5V, V − = 0V, VCM = 2.5V and TA = 25°C and RL > 1MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
VSSOP
WSON
0.4
3
3
3.2
VCM = 0.85V and
VCM = 1.85V
VOS
Input Offset Voltage
mV
DSBGA
7
9
5.5
80
90
90
115
130
IB
Input Bias Current
pA
dB
dB
dB
0V ≤ VCM ≤ 5V
50
45
CMRR
Common Mode Rejection Ratio
2.7V ≤ V+ ≤ 5V,
VCM = 0.85V
2.7V ≤ V+ ≤ 5V,
VCM = 1.85V
70
68
PSRR
CMVR
ISC
Power Supply Rejection Ratio
Common Mode Voltage Range
Output Short Circuit Current
70
68
For CMRR ≥ 50dB
−0.3
5.3
35
−0.2
V
V
5.2
Sourcing
VO = 0V
20
18
mA
mA
Sinking
VO = 5V
25
21
50
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
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SNOS534G –MAY 2004–REVISED MARCH 2010
5V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for V+ = 5V, V − = 0V, VCM = 2.5V and TA = 25°C and RL > 1MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
(2)
(1)
4.92
4.90
4.98
0.01
4.85
0.05
RL = 10kΩ to 2.5V
V
V
V
0.12
0.15
VO
Output Swing
4.82
4.80
RL = 600Ω to 2.5V
0.23
0.30
V
VO(SD)
IS
Output Voltage in Shutdown
Supply Current per Channel
10
200
mV
mA
1.17
1.7
1.9
On Mode
0.12
130
130
110
107
1.5
2.0
Shutdown Mode
uA
dB
Sourcing
RL = 10kΩ
VO = 2.5V to 4.6V
80
76
Sinking
RL = 10kΩ
VO = 0.4V to 2.5V
80
76
dB
dB
dB
AVOL
Large Signal Voltage Gain
Sourcing
RL = 600Ω
VO = 2.5V to 4.6V
80
76
Sinking
RL = 600Ω
80
VO = 0.4V to 2.5V
76
On Mode
4.5 to 5
0 to 0.8
3.5 to 5
V
V
VSD
Shutdown Pin Voltage Range
Shutdown Mode
0 to 1.5
GBWP
SR
Gain-Bandwidth Product
Slew Rate
5
5
MHz
V/µs
Deg
nV/√Hz
(3)
φm
Phase Margin
60
20
1.6
en
Input Referred Voltage Noise
f = 1kHz
4
4.6
Turn-On Time for Shutdown
Turn-On Time for Shutdown
μs
μs
TON
6
8
DSBGA
(3) Number specified is the slower of the positive and negative slew rates.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Supply Current Per Channel
Supply Current
vs.
vs.
Supply Voltage
Supply Voltage (Shutdown)
1.5
1.3
0.6
0.5
0.4
0.3
0.2
85°C
25°C
1.1
0.9
0.7
0.5
-40°C
2.7 3.0
3.5
4.0
4.5
5.0
2.7 3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 2.
Figure 3.
VOS
vs.
VCM
IB
vs.
VCM Over Temp
100
10
0
+85°C
-200
+70°C
-40°C
-400
-600
-800
+50°C
1
+25°C
25°C
85°C
0°C
-25°C
0.1
-1000
-1200
-40°C
0.01
0
1
2
3
4
5
0
1
2
4
5
3
V
CM
(V)
V
(V)
CM
Figure 4.
Figure 5.
Output Positive Swing
vs.
Supply Voltage, RL = 600Ω
Output Negative Swing
vs.
Supply Voltage, RL = 600Ω
160
100
140
120
90
80
25°C
25°C
85°C
85°C
100
70
80
60
40
60
50
40
-40°C
-40°C
2.7
2.7
3.0
3.5
3.0
3.5
4.0
(V)
4.5
5.0
4.0
(V)
4.5
5.0
V
V
S
S
Figure 6.
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Sourcing Current
Sourcing Current
vs.
Output Voltage, VS = 5V
vs.
Output Voltage, VS = 2.7V
35
30
25
30
85°C
85°C
25
25°C
20
-40°C
25°C
20
15
10
-40°C
15
10
5
5
0
0
0
1
2
3
4
5
-0.3
0.2
0.7
1.2
FROM V (V)
1.7
2.2
2.7
+
V
(V)
V
OUT
OUT
Figure 8.
Figure 9.
Sinking Current
vs.
Output Voltage, VS = 2.7V
Sinking Current
vs.
Output Voltage, VS = 5V
90
80
70
60
50
40
30
20
10
0
70
85°C
85°C
60
50
40
30
20
10
0
25°C
25°C
-40°C
-40°C
-10
-10
0
1
2
3
4
5
-0.3
0.2
0.7
1.7
2.2
2.7
1.2
V
(V)
OUT
V
(V)
OUT
Figure 10.
Figure 11.
PSRR
vs.
Frequency VS = 2.7V
PSRR
vs.
Frequency VS = 5V
100
90
100
90
NEGATIVE
80
80
NEGATIVE
70
60
50
40
30
70
60
50
40
30
POSITIVE
POSITIVE
20
10
0
20
10
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12.
Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
CMRR
CMRR
vs.
Frequency
vs.
Frequency
100
100
90
V
= 2.7V
S
90
80
70
60
50
40
30
dV
= 0.2V TO 1.2V
CM
80
70
60
50
40
30
20
10
0
20
10
0
V
= 5V
S
dV
= 2V TO 3V
CM
10
100
1k
10k
1M
10
100
1k
10k
1M
100k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14.
Figure 15.
Open Loop Frequency Response
Open Loop Frequency Response
vs.
RL
vs.
RL
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= 2.7V
S
V
= 5V
S
R
= 10kW
10kW
L
600W
R
= 600W
600W
L
R
= 600W
L
90
60
30
90
60
30
0
0
R
L
= 10kW
10kW
-10
-10
-20
-20
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16.
Figure 17.
Open Loop Frequency Response
Open Loop Frequency Response
vs.
CL
vs.
CL
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= 2.7V
V = 5V
S
S
C
= 0pF
C
= 0pF
L
L
90
60
30
0
90
60
30
0
C
= 100pF
L
C
= 100pF
L
C
L
= 1000pF
C
= 1000pF
C
L
= 1000pF
L
C
L
= 1000pF
C
L
= 100pF
C
L
= 100pF
-10
-10
C
= 0pF
1M
C
L
= 0pF
1M
L
-20
-20
1k
10k
100k
FREQUENCY (Hz)
10M
1k
10k
100k
10M
FREQUENCY (Hz)
Figure 18.
Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Voltage Noise
vs.
Frequency
Voltage Noise
vs.
Frequency
1000
100
10
1000
V
V
V
= 5V
S
V
V
V
= 2.7V
S
= 2.5V
= 5V
CM
SD
= 1.35V
= 2.7V
CM
SD
100
10
1
1
100k
1
10
100
1k
10k
100k
1
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20.
Figure 21.
Non-Inverting Large Signal Pulse Response, VS = 2.7V
Non-Inverting Large Signal Pulse Response, VS = 5V
TIME (500ns/div)
TIME (500ns/div)
Figure 22.
Figure 23.
Non-Inverting Small Signal Pulse Response, VS = 2.7V
Non-Inverting Small Signal Pulse Response, VS = 5V
TIME (500ns/div)
TIME (500ns/div)
Figure 24.
Figure 25.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.
Inverting Large Signal Pulse Response, VS = 2.7V
Inverting Large Signal Pulse Response, VS = 5V
TIME (500ns/div)
TIME (500ns/div)
Figure 26.
Figure 27.
Inverting Small Signal Pulse Response, VS = 2.7V
Inverting Small Signal Pulse Response VS = 5V
TIME (500ns/div)
TIME (500ns/div)
Figure 28.
Figure 29.
Input Common Mode Capacitance
vs.
Turn on Time Response VS = 5V
VCM VS = 5V
30
C
TO GROUND
CM
28
26
24
22
20
18
16
14
12
10
FMEAS = 1MHz
FOLLOWER CONFIG
V
FOLLOWS V (V )
IN CM
OUT
0
1
2
3
4
5
TIME (2µs/div)
V
(V)
CM
Figure 30.
Figure 31.
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APPLICATION INFORMATION
THEORY OF OPERATION
The LMV712-N dual op amp is derived from the LMV711 single op amp. Figure 32 contains a simplified
schematic of one channel of the LMV712-N.
+
V
V
BIAS
I
P
MP3
MP4
Q2
Q1
MP1
MP2
MN2
-
+
IN
IN
CLASS AB
CONTROL
OUT
MN3
MN1
Q3
Q4
Q6
MN4
Q5
I
N
V
BIAS
-
V
BIAS
CONTROL
SD
Figure 32.
Rail-to-Rail input is achieved by using in parallel, one NMOS differential pair (MN1 and MN2) and one PMOS
differential pair (MP1 and MP2). When the common mode input voltage (VCM) is near V+, the NMOS pair is on
and the PMOS pair is off. When VCM is near V−, the NMOS pair is off and the PMOS pair is on. When VCM is
between V+ and V−, internal logic decides how much current each differential pair will get. This special logic
ensures stable and low distortion amplifier operation within the entire common mode voltage range.
Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LMV712-N
becomes a function of VCM. VOS has a crossover point at 1.4V above V−. Refer to the "VOS vs. VCM" curve in the
Typical Performance Characteristics section. Caution should be taken in situations where input signal amplitude
is comparable to VOS value and/or the design requires high accuracy. In these situations, it is necessary for the
input signal to avoid the crossover point.
The current coming out of the input differential pairs gets mirrored through two folded cascode stages (Q1, Q2,
Q3, Q4) into the "class AB control" block. This circuitry generates voltage gain, defines the op amp's dominant
pole and limits the maximum current flowing at the output stage. MN3 introduces a voltage level shift and acts as
a high impedance to low impedance buffer.
The output stage is composed of a PMOS and a NPN transistor in a common source/emitter configuration,
delivering a rail-to-rail output excursion.
The MN4 transistor ensures that the LMV712-N output remains near V− when the amplifier is in shutdown mode.
SHUTDOWN PIN
The LMV712-N offers independent shutdown pins for the dual amplifiers. When the shutdown pin is tied low, the
respective amplifier shuts down and the supply current is reduced to less than 1µA. In shutdown mode, the
amplifier's output level stays at V−. In a 2.7V operation, when a voltage between 1.5V to 2.7V is applied to the
shutdown pin, the amplifier is enabled. As the amplifier is coming out of the shutdown mode, the output
waveform ramps up without any glitch. This is demonstrated in Figure 33.
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SNOS534G –MAY 2004–REVISED MARCH 2010
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TIME (2µs/div)
Figure 33.
A glitch-free output waveform is highly desirable in many applications, one of which is power amplifier control
loops. In this application, the LMV712-N is used to drive the power amplifier's power control. If the LMV712-N did
not have a smooth output ramp during turn on, it would directly cause the power amplifier to produce a glitch at
its output. This adversely affects the performance of the system.
To enable the amplifier, the shutdown pin must be pulled high. It should not be left floating in the event that any
leakage current may inadvertently turn off the amplifier.
PRINTED CIRCUIT BOARD CONSIDERATION
To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8µF
or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced
onto the board. Another 0.1µF ceramic capacitor should be placed as close as possible to the power supply pin
of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a
0.1µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V− pins need to be bypassed.
It is good practice to use a ground plane on a printed circuit board to provide all components with a low inductive
ground connection.
Surface mount components in 0805 size or smaller are recommended in the LMV712-N application circuits.
Designers can take advantage of the DSBGA, VSSOP and WSON miniature sizes to condense board layout in
order to save space and reduce stray capacitance.
CAPACITIVE LOAD TOLERANCE
The LMV712-N can directly drive 200pF in unity-gain without oscillation. The unity-gain follower is the most
sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers.
The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in
either an under-damped pulse response or oscillation. To drive a heavier capacitive load, Figure 34 can be used.
Figure 34.
In Figure 34, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more
phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO
resistor value, the more stable VOUT will be. But the DC accuracy is degraded when the RISO gets bigger. If there
were a load resistor in Figure 34, the output voltage would be divided by RISO and the load resistor.
12
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Links: LMV712-N
LMV712-N
www.ti.com
SNOS534G –MAY 2004–REVISED MARCH 2010
The circuit in Figure 35 is an improvement to the one in Figure 34 because it provides DC accuracy as well as
AC stability. In this circuit, RF provides the DC accuracy by using feed-forward techniques to connect VIN to RL.
CF and RISO serve to counteract the loss of phase margin by feeding the high frequency component of the output
signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop.
Increased capacitive drive is possible by increasing the value of CF. This in turn will slow down the pulse
response.
Figure 35.
LATCHUP
CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR (silicon controlled rectifier)
effects. The input and output pins look similar to the gate of the SCR. There is a minimum current required to
trigger the SCR gate lead. The LMV712-N is designed to withstand 150mA surge current on all the pins. Some
resistive method should be used to isolate any capacitance from supplying excess current to the pins. In addition,
like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will
also inhibit latchup susceptibility.
Copyright © 2004–2010, Texas Instruments Incorporated
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LMV712-N
SNOS534G –MAY 2004–REVISED MARCH 2010
www.ti.com
CONNECTION DIAGRAMS
*Connect thermal pad to V-or leave floating
1
+
10
9
+
OUT A
-IN A
1
2
3
V
OUT A
-IN A
10
9
V
2
3
OUT B
OUT B
-
-
+
+
8
7
-
-
+
+
+IN A
+IN A
-IN B
+IN B
SD B
8
7
6
-IN B
+IN B
SD B
-
4
5
-
V
V
4
5
-
6
SD A
SD A
Figure 36. 10-Pin VSSOP (Top View)
Figure 37. 10-Pin WSON (Top View)
A2
+
A2
+
V
V
A1
OUT
A
A3
OUTB
A3
OUTB
A1
OUT
A
B
B
B1
-INA
B1
-INA
3
3
-INB
-INB
C
C1
+INA
C1
+INA
C3
+INB
3
+INB
D3
SDB
D1
SDA
D1
SDA
D3
SDB
-
-
V
V
D2
D2
Figure 38. 10-Bump DSBGA (Top View)
Figure 39. 10-Bump DSBGA (Bottom View)
14
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
LMV712LD/NOPB
LMV712LDX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
WSON
WSON
NGY
10
10
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-3-260C-168 HR
A62
A62
ACTIVE
NGY
4500
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
LMV712MM
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
A61
A61
LMV712MM/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LMV712MMX
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
3500
3500
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
A61
A61
LMV712MMX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LMV712TL/NOPB
LMV712TLX/NOPB
ACTIVE
ACTIVE
DSBGA
DSBGA
YPA
YPA
10
10
250
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
AU2A
AU2A
3000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV712LD/NOPB
LMV712LDX/NOPB
LMV712MM
WSON
WSON
VSSOP
VSSOP
VSSOP
VSSOP
DSBGA
DSBGA
NGY
NGY
DGS
DGS
DGS
DGS
YPA
YPA
10
10
10
10
10
10
10
10
1000
4500
1000
1000
3500
3500
250
178.0
330.0
178.0
178.0
330.0
330.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
8.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
5.3
3.4
1.4
LMV712MM/NOPB
LMV712MMX
5.3
3.4
1.4
5.3
3.4
1.4
LMV712MMX/NOPB
LMV712TL/NOPB
LMV712TLX/NOPB
5.3
3.4
1.4
1.68
1.68
2.13
2.13
0.76
0.76
3000
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV712LD/NOPB
LMV712LDX/NOPB
LMV712MM
WSON
WSON
VSSOP
VSSOP
VSSOP
VSSOP
DSBGA
DSBGA
NGY
NGY
DGS
DGS
DGS
DGS
YPA
YPA
10
10
10
10
10
10
10
10
1000
4500
1000
1000
3500
3500
250
213.0
367.0
210.0
210.0
367.0
367.0
210.0
210.0
191.0
367.0
185.0
185.0
367.0
367.0
185.0
185.0
55.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LMV712MM/NOPB
LMV712MMX
LMV712MMX/NOPB
LMV712TL/NOPB
LMV712TLX/NOPB
3000
Pack Materials-Page 2
MECHANICAL DATA
NGY0010A
LDA10A (Rev B)
www.ti.com
MECHANICAL DATA
YPA0010
0.600
±0.075
D
E
TLP10XXX (Rev D)
D: Max = 2.048 mm, Min =1.987 mm
E: Max = 1.565 mm, Min =1.504 mm
4215069/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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