LMR14030SSQDDARQ1 [TI]
具有 40uA IQ 的 SIMPLE SWITCHER®、汽车类 40V、3.5A 2.2MHz 降压转换器 | DDA | 8 | -40 to 125;
| 型号： | LMR14030SSQDDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 40uA IQ 的 SIMPLE SWITCHER®、汽车类 40V、3.5A 2.2MHz 降压转换器 | DDA | 8 | -40 to 125 开关 光电二极管 转换器 |
| 文件： | 总40页 (文件大小：1450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
LMR14030-Q1 SIMPLE SWITCHER® 40V、3.5A 降压转换器（IQ 为
40µA）
1 特性
3 说明
1
•
适用于汽车电子 应用
LMR14030-Q1 器件是一款集成高侧金属氧化物半导体
场效应晶体管 (MOSFET) 的 40V、3.5A 降压稳压器。
该器件的宽输入电压范围为 4V 至 40V，适用于调节从
工业到汽车等各类 应用 中的非稳压电源。其扩展系列
产品能够以引脚到引脚兼容封装提供 2 A 和 5A 电流选
项，其中包括 LMR14020-Q1 和 LMR14050-Q1。该
稳压器在休眠模式下的静态电流为 40µA，非常适合电
池供电类系统。并且在关断模式下具有 1μA 的超低电
流，可进一步延长电池使用寿命。该稳压器的可调开关
频率范围较宽，这使得效率或外部元件尺寸能够得到优
化。内部环路补偿意味着用户不用承担设计环路补偿组
件的枯燥工作。并且还能够以最大限度减少器件的外部
元件数。精密使能输入简化了稳压器控制和系统电源排
序。此外，该器件还内置多种保护 功能： 逐周期限流
保护、应对功耗过大的热感测和热关断保护以及输出过
压保护。
•
具有符合 AEC-Q100 标准的下列结果：
- 器件温度 1 级：-40°C 至 125°C 的环境运行温度
范围
- 器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H1C
- 器件带电器件模型 (CDM) ESD 分类等级 C4A
•
•
•
•
输入电压范围：4V 至 40V
3.5A 持续输出电流
40µA 超低工作静态电流
90mΩ 高侧金属氧化物半导体场效应晶体
(MOSFET)
•
•
•
•
•
•
•
•
•
•
•
•
最短导通时间：75ns
电流模式控制
可调节开关频率范围：200kHz 至 2.5MHz
与外部时钟频率同步
扩展频谱选项，适用于降低电磁干扰 (EMI)
内置补偿功能，便于使用
支持高占空比运行
LMR14030-Q1 采用带有外露焊盘的 8 引脚 HSOIC 或
10 引脚 WSON 封装，用于实现低热阻。
精密使能引脚
器件信息(1)
关断电流：1µA
器件型号
封装
封装尺寸（标称值）
外部软启动
LMR14030SQDDARQ1
HSOIC (8)
4.89mm x 3.90mm
热保护、过压保护和短路保护
LMR14030SSQDDARQ1
（扩展频谱）
HSOIC (8)
WSON (10)
WSON (10)
4.89mm x 3.90mm
4.10mm x 4.10mm
4.10mm x 4.10mm
8 引脚散热增强型小外形集成电路 (HSOIC)
PowerPAD™封装
LMR14030QDPRRQ1
LMR14030SQDPRRQ1
（扩展频谱）
2 应用范围
•
•
•
•
汽车电池稳压
工业用电源
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
电信和数据通信系统
通用宽输入电压稳压
空白
简化电路原理图
VIN up to 40 V
CIN
VIN
BOOT
EN
CBOOT
L
VOUT
RT/SYNC
SW
FB
RT
D
RFBT
COUT
SS
RFBB
CSS
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAG3
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
效率与输出电流间的关系
100
90
80
70
60
50
40
30
20
VOUT = 5 V
VOUT = 3.3 V
10
0
VIN = 12 V, ÖSW = 500 kHz
0.01
0.001
0.1
1
10
IOUT (A)
D001
2
版权 © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 器件支持 ............................................................... 26
11.2 文档支持................................................................ 26
11.3 接收文档更新通知 ................................................. 26
11.4 社区资源................................................................ 26
12 机械、封装和可订购信息....................................... 27
7
4 修订历史记录
注意：前一修订版的页码可能与当前版本的页码不同。
Changes from Original (November 2015) to Revision A
Page
•
•
•
•
已添加 DPR 封装信息............................................................................................................................................................. 1
Added new column for WSON package................................................................................................................................. 4
Added new section for PGOOD.............................................................................................................................................. 6
Added PGOOD section ........................................................................................................................................................ 15
Copyright © 2015–2016, Texas Instruments Incorporated
3
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
5 Pin Configuration and Functions
DDA Package
8-Pin (HSOIC)
Top View
DPR Package
10-Pin (WSON)
Top View
BOOT
VIN
1
2
3
4
5
10
9
SW
BOOT
1
8
SW
GND
VIN
EN
2
3
4
7
6
5
GND
SS
Thermal Pad
(11)
VIN
8
PGOOD
FB
Thermal Pad
(9)
EN
7
RT/SYNC
FB
RT/SYNC
6
SS
Pin Functions
NO.
WSON-10
(1)
NAME
TYPE
DESCRIPTION
SO-8
Bootstrap capacitor connection for high-side MOSFET driver. Connect a high
quality 0.1 μF capacitor from BOOT to SW.
BOOT
VIN
1
2
1
P
P
Connect to power supply and bypass capacitors CIN. Path from VIN pin to high
frequency bypass CIN and GND must be as short as possible.
2, 3
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float
or connect to VIN to enable. Adjust the input under voltage lockout with two
resistors. See the Enable and Adjusting Under voltage lockout section.
EN
3
4
5
A
Resistor Timing or External Clock input. An internal amplifier holds this pin at a
fixed voltage when using an external resistor to ground to set the switching
frequency. If the pin is pulled above the PLL upper threshold, a mode change
occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking
edges stop, the internal amplifier is re-enabled and the operating mode returns to
frequency programming by resistor.
RT/SYNC
4
A
Feedback input pin, connect to the feedback divider to set VOUT. Do not short this
pin to ground during operation.
FB
5
6
7
6
A
A
A
G
P
G
SS
Soft-start control pin. Connect to a capacitor to set soft-start time.
Open drain output for power-good flag. Use a 10 kΩ to 100 kΩ pull-up resistor to
logic rail or other DC voltage no higher than 7V.
PGOOD
GND
N/A
7
8
9
System ground pin.
Switching output of the regulator. Internally connected to high-side power
MOSFET. Connect to power inductor.
SW
8
10
11
Thermal Pad
9
Major heat dissipation path of the die. Must be connected to ground plane on PCB.
(1) A = Analog, P = Power, G = Ground
4
Copyright © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1)
Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted)
PARAMETER
VIN, EN to GND
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
44
49
5
UNIT
BOOT to GND
SS to GND
Input Voltages
V
FB to GND
7
RT/SYNC to GND
PGOOD to GND
BOOT to SW
3.6
7
6.5
44
150
150
Output Voltages
V
SW to GND
-3
TJ
Junction temperature
Storage temperature
-40
-65
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
(1)
Human-body model (HBM), per AEC Q100-002
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted)
(1)
MIN
4
MAX
40
UNIT
VIN
VOUT
0.8
28
Buck Regulator
BOOT
45
V
SW
-1
0
40
FB
5
EN
0
40
RT/SYNC
0
3.3
3
Control
V
SS
0
PGOOD to GND
0
5
Switching frequency range at RT mode
Switching frequency range at SYNC mode
Operating junction temperature, TJ
200
250
-40
2500
2300
125
Frequency
kHz
°C
Temperature
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits.
For guaranteed specifications, see Electrical Characteristics.
Copyright © 2015–2016, Texas Instruments Incorporated
5
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
6.4 Thermal Information
LMR14030-Q1
(1) (2)
THERMAL METRIC
DDA (HSOIC)
DPR (WSON)
10 PINS
36.5
UNIT
8 PINS
42.5
9.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
0.3
ψJB
25.4
56.1
3.8
13.8
RθJC(top)
RθJC(bot)
RθJB
35.2
3.1
25.5
13.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature (TJ) of 125°C, which is
illustrated in Recommended Operating Conditions section.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.0 V to 40 V
PARAMETER
POWER SUPPLY (VIN PIN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Operation input voltage
4
40
V
V
UVLO
Under voltage lockout thresholds
Rising threshold
3.5
3.7
285
1.0
40
3.9
Hysteresis
mV
μA
μA
ISHDN
IQ
Shutdown supply current
VEN = 0 V, TJ = 25 °C, 4.0 V ≤ VIN ≤ 40 V
VFB = 1.0 V, TJ = 25 °C
3.0
Operating quiescent current (non-
switching)
ENABLE (EN PIN)
VEN_TH
EN Threshold Voltage
EN PIN current
1.05
1.20
-4.6
-1.0
-3.6
1.38
V
IEN_PIN
Enable threshold +50 mV
Enable threshold -50 mV
μA
μA
IEN_HYS
EN hysteresis current
EXTERNAL SOFT-START
ISS
SS pin current
TJ = 25 °C
-3
μA
POWER GOOD (PGOOD PIN)
VPG_UV
Power-good flag under voltage tripping
threshold
POWER GOOD (% of FB voltage)
POWER BAD (% of FB voltage)
POWER BAD (% of FB voltage)
POWER GOOD (% of FB voltage)
% of FB voltage
94%
92%
109%
107%
2%
VPG_OV
Power-good flag over voltage tripping
threshold
VPG_HYS
IPG
Power-good flag recovery hysteresis
PGOOD leakage current at high level
output
VPull-Up = 5 V
10
200
nA
VPG_LOW
PGOOD low level output voltage
IPull-Up = 1 mA
0.1
1.6
V
V
VIN_PG_MIN
Minimum VIN for valid PGOOD output
VPull-Up < 5 V at IPull-Up = 100 μA
1.95
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage
TJ = 25°C
0.744 0.750 0.756
0.735 0.750 0.765
V
V
TJ = -40 °C to 125 °C
HIGH-SIDE MOSFET
RDS_ON On-resistance
VIN = 12 V, BOOT to SW = 5.8 V
90
180
mΩ
6
Copyright © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.0 V to 40 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HIGH-SIDE MOSFET CURRENT LIMIT
ILIMT
Current limit
VIN = 12 V, TJ = -40°C to 125°C, Open
Loop
4.1
5.5
7.7
A
THERMAL PERFORMANCE
TSHDN Thermal shutdown threshold
THYS Hysteresis
170
12
°C
6.6 Switching Characteristics
Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RT = 11.5 kΩ
MIN
TYP MAX UNIT
Switching frequency
1758 1912 2066
fSW
kHz
Switching frequency range at SYNC mode
Switching frequency dithering
250
1.7
2300
FDITHER
Spread spectrum option, frequency
dithering over center frequency
±6%
VSYNC_HI
VSYNC_LO
TSYNC_MIN
SYNC clock high level threshold
SYNC clock low level threshold
Minimum SYNC input pulse width
V
0.5
Measured at 500 kHz, VSYNC_HI > 3 V,
VSYNC_LO < 0.3 V
30
ns
TLOCK_IN
TON_MIN
PLL lock in time
Measured at 500 kHz
100
75
µs
ns
Minimum controllable on time
VIN = 12 V, BOOT to SW = 5.8 V, ILoad
1 A
=
DMAX
Maximum duty cycle
fSW = 200 kHz
97%
Copyright © 2015–2016, Texas Instruments Incorporated
7
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
6.7 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 500 kHz, L = 5.6 µH, COUT = 47 µF x 2, TA =
25°C.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 36 V
VIN = 24 V
VIN = 12 V
VIN = 36 V
VIN = 24 V
VIN = 12 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT (A)
IOUT (A)
D002
D003
VOUT = 5 V
fSW = 500 kHz
VOUT = 5 V
fSW = 1 MHz
Figure 1. Efficiency vs. Load Current
Figure 2. Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 24 V
VIN = 12 V
VIN = 5 V
VIN = 20 V
VIN = 12 V
VIN = 5 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT (A)
IOUT (A)
D009
D010
VOUT = 3.3 V
fSW = 1 MHz
VOUT = 3.3 V
fSW = 2.2 MHz
Figure 3. Efficiency vs. Load Current
Figure 4. Efficiency vs. Load Current
125
100
75
50
25
0
0.2
0.15
0.1
VFB Falling
VFB Rising
VIN = 36 V
VIN = 24 V
VIN = 12 V
0.05
0
-0.05
0.001
0.01
0.1
1
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IOUT (A)
VFB (V)
D004
D005
VOUT = 5 V
fSW = 500 kHz
Figure 5. Load Regulation
Figure 6. Frequency vs VFB
8
Copyright © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 500 kHz, L = 5.6 µH, COUT = 47 µF x 2, TA =
25°C.
6
5.5
5
6
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
IOUT = 3.5 A
IOUT = 1.75 A
IOUT = 0.35 A
IOUT = 3.5 A
IOUT = 1.75 A
IOUT = 0.35 A
2.5
2
2.5
2
4
4.5
5
5.5
6
6.5
4
4.5
5
5.5
6
6.5
VIN (V)
VIN (V)
D011
D012
VOUT = 5 V
fSW = 500 kHz
VOUT = 5 V
fSW = 1 MHz
Figure 8. Dropout Curve
Figure 7. Dropout Curve
6
5.5
5
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
4.5
4
3.5
3
IOUT = 3.5 A
IOUT = 1.75 A
IOUT = 0.35 A
IOUT = 3.5 A
IOUT = 1.75 A
IOUT = 0.35 A
2.5
2
4
4.5
5
5.5
6
6.5
3.5
3.75
4
4.25
4.5
4.75
5
VIN (V)
VIN (V)
D013
D014
VOUT = 5 V
fSW = 2.2 MHz
VOUT = 3.3 V
fSW = 2.2 MHz
Figure 10. Dropout Curve
Figure 9. Dropout Curve
45
40
35
30
25
20
15
10
5
3.75
3.7
3.65
3.6
IQ
UVLO_H
3.55
3.5
UVLO_L
ISHDN
3.45
3.4
0
0
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
150
VIN (V)
Temperature (°C)
D006
D007
IOUT = 0 A
Figure 11. Shut-down Current and Quiescent Current
Figure 12. UVLO Threshold
Copyright © 2015–2016, Texas Instruments Incorporated
9
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LMR14030-Q1 SIMPLE SWITCHER® regulator is an easy to use step-down DC-DC converter that operates
from a 4.0 V to 40 V supply voltage. It integrates a 90 mΩ (typical) high-side MOSFET, and is capable of
delivering up to 3.5 A DC load current with exceptional efficiency and thermal performance in a very small
solution size. The operating current is typically 40 μA under no load condition (not switching). When the device is
disabled, the supply current is typically 1 μA. An extended family is available in 2 A and 5 A load options in pin to
pin compatible packages.
The LMR14030-Q1 implements constant frequency peak current mode control with Sleep-mode at light load to
achieve high efficiency. The device is internally compensated, which reduces design time, and requires fewer
external components. The switching frequency is programmable from 200 kHz to 2.5 MHz by an external resistor
RT. The LMR14030-Q1 is also capable of synchronization to an external clock within the 250 kHz to 2.3 MHz
frequency range, which allows the device to be optimized to fit small board space at higher frequency, or high
efficient power conversion at lower frequency.
Other features are included for more comprehensive system requirements, including precision enable, adjustable
soft-start time, and approximate 97% duty cycle by BOOT capacitor recharge circuit. These features provide a
flexible and easy to use platform for a wide range of applications. Protection features include over temperature
shutdown, VOUT over voltage protection (OVP), VIN under-voltage lockout (UVLO), cycle-by-cycle current limit,
and short-circuit protection with frequency fold-back.
7.2 Functional Block Diagram
EN
VIN
Thermal
Shutdown
UVLO
Enable
Comparator
Shutdown
Shutdown
Logic
Voltage
Reference
Enable
Threshold
Boot
Charge
OV
Boot
UVLO
ERROR
AMPLIFIER
PWM
Comparator
FB
BOOT
PWM
Control
Logic
Comp
Components
Shutdown
Slope
Compensation
S
SW
Frequency
Shift
Bootstrap
Control
VIN
Oscillator
with PLL
SS
GND
RT/SYNC
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7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR14030-Q1 will refer to the Functional Block Diagram and to the
waveforms in Figure 13. LMR14030-Q1 output voltage is regulated by turning on the high-side N-MOSFET with
controlled ON time. During high-side switch ON time, the SW pin voltage swings up to approximately VIN, and the
inductor current iL increase with linear slope (VIN – VOUT) / L. When high-side switch is off, inductor current
discharges through freewheel diode with a slope of –VOUT / L. The control parameter of Buck converter is defined
as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the switching period. The
regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal Buck
converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input
voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
ûiL
t
0
Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The LMR14030-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time of
the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency at normal load condition. At very light load, the
LMR14030-Q1 will operate in Sleep-mode to maintain high efficiency and the switching frequency will decrease
with reduced load current.
7.3.2 Slope Compensation
The LMR14030-Q1 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
7.3.3 Sleep-mode
The LMR14030-Q1 operates in Sleep-mode at light load currents to improve efficiency by reducing switching and
gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300 mA, the device enters Sleep-mode. The Sleep-mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.
When in Sleep-mode, the internal COMP voltage is clamped at 400mV and the high-side MOSFET is inhibited,
and the device draws only 40 μA (typical) input quiescent current. Since the device is not switching, the output
voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage
eventually falls below the Sleep-mode threshold at which time the device again enters Sleep-mode.
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Feature Description (continued)
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The LMR14030-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or
greater is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the LMR14030-Q1
will operate at approximate 97% duty cycle. When the high-side MOSFET is continuously on for 5 or 6 switching
cycles (5 or 6 switching cycles for frequency lower than 1 MHz, and 10 or 11 switching cycles for frequency
higher than 1 MHz) and the voltage from BOOT to SW drops below 3.2 V, the high-side MOSFET is turned off
and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor.
Since the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 97%. The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
7.3.5 Adjustable Output Voltage
The internal voltage reference produces a precise 0.75 V (typical) voltage reference over the operating
temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It is
recommended to use 1% tolerance or better and temperature coefficient of 100 ppm or less divider resistors.
Select the low side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT
.
Larger value divider resistors are good for efficiency at light load. However, if the values are too high, the
regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
RFBB in the range from 10 kΩ to 100 kΩ is recommended for most applications.
V
OUT
R
FBT
FBB
FB
R
Figure 14. Output Voltage Setting
VOUT - 0.75
RFBT
=
ìRFBB
0.75
(1)
7.3.6 Enable and Adjustable Under-voltage Lockout
The LMR14030-Q1 is enabled when the VIN pin voltage rises above 3.7 V (typical) and the EN pin voltage
exceeds the enable threshold of 1.2 V (typical). The LMR14030-Q1 is disabled when the VIN pin voltage falls
below 3.42 V (typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pull-up current
source (typically IEN = 1 μA) that enables operation of the LMR14030-Q1 when the EN pin is floating.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 15 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced out
of EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current
facilitates adjustable input voltage UVLO hysteresis. Use Equation 2 and Equation 3 to calculate RENT and RENB
for desired UVLO hysteresis voltage.
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Feature Description (continued)
I
I
EN
EN_HYS
VIN
EN
V
IN
R
R
ENT
V
EN
ENB
Figure 15. System UVLO By Enable Dividers
VSTART - VSTOP
RENT
=
IHYS
(2)
(3)
VEN
VSTART - VEN
RENB
=
+ IEN
RENT
where VSTART is the desired voltage threshold to enable LMR14030-Q1, VSTOP is the desired voltage threshold to
disable device.
7.3.7 External Soft-start
The LMR14030-Q1 has soft-start pin for programmable output ramp up time. The soft-start feature is used to
prevent inrush current impacting the LMR14030-Q1 and its load when power is first applied. The soft-start time
can be programed by connecting an external capacitor CSS from SS pin to GND. An internal current source
(typically ISS = 3 μA) charges CSS and generates a ramp from 0 V to VREF. The soft-start time can be calculated
by Equation 4:
CSS(nF)ì VREF(V)
tSS(ms) =
ISS(mA)
(4)
For LMR14030-Q1 in WSON package, the maximum value of CSS is 4.7 nF.
The soft-start resets while device is disabled or in thermal shutdown.
7.3.8 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LMR14030-Q1 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. The RT/SYNC pin can’t be left floating or shorted to ground. To determine the timing resistance for a
given switching frequency, use Equation 5 or the curve in Figure 16. Table 1 gives typical RT values for a given
fSW
.
RT(kW) = 42904 ì ƒSW (kHz)-1.088
(5)
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Feature Description (continued)
140
120
100
80
60
40
20
0
0
500
1000
1500
2000
2500
Frequency (kHz)
D008
Figure 16. RT vs Frequency Curve
Table 1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
133
200
350
73.2
49.9
32.4
23.2
15.0
11.5
9.76
500
750
1000
1500
1912
2200
The LMR14030-Q1 switching action can also be synchronized to an external clock from 250 kHz to 2.3 MHz.
Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 17. Internal oscillator
is synchronized by the falling edge of external clock. The recommendations for the external clock include: high
level no lower than 1.7 V, low level no higher than 0.5 V and have a pulse width greater than 30 ns. When using
a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling
capacitor CCOUP to a termination resistor RTERM (e.g., 50 Ω). The two resistors in series provide the default
frequency setting resistance when the signal source is turned off. A 10 pF ceramic capacitor can be used for
CCOUP. Figure 18, Figure 19 and Figure 20 show the device synchronized to an external system clock.
C
COUP
PLL
RT/SYNC
PLL
RT/SYNC
R
T
Lo-Z
Clock
Source
Hi-Z
Clock
Source
R
T
R
TERM
Figure 17. Synchronizing to an External Clock
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SYNC (2 V/DIV)
SYNC (2 V/DIV)
SW (5 V/DIV)
iL (1 A/DIV)
SW (5 V/DIV)
iL (500 mA/DIV)
Time (2 µs/DIV)
Time (2 µs/DIV)
Figure 18. Synchronizing in CCM
Figure 19. Synchronizing in DCM
SYNC (2 V/DIV)
SW (5 V/DIV)
iL (500 mA/DIV)
Time (10 µs/DIV)
Figure 20. Synchronizing in Sleep-mode Mode
For spread spectrum option, the internal frequency dithering is diabled if the device is synchronized to an
external clock.
Equation 6 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
≈
’
IOUT ìRIND + VOUT + VD
V -IOUT ìRDS_ON + VD
IN_MAX
1
ƒSW(max)
=
ì
∆
∆
«
÷
÷
◊
tON
(6)
where
•
•
•
•
•
•
•
IOUT = Output current
RIND = Inductor series resistance
VIN_MAX = Maximum input voltage
VOUT = Output voltage
VD = Diode voltage drop
RDS_ON = High-side MOSFET switch on resistance
tON = Minimum on time
7.3.9 Power Good (PGOOD)
The LMR14020-Q1 in WSON-10 package has a built in power-good flag shown on PGOOD pin to indicate
whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing
of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pull-up resistor to an
appropriate DC voltage. Voltage seen by the PGOOD pin should never exceed 7 V. A resistor divider pair can be
used to divide the voltage down from a higher potential. A typical range of pull-up resistor value is 10 kΩ to 100
kΩ.
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Refer to Figure 21. When the FB voltage is within the power-good band, +7% above and -6% below the internal
reference VREF typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the
voltage level defined by the pull-up resistor or divider. When the FB voltage is outside of the tolerance band,
+9% above or -8% below VREF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be
pulled low to indicate power bad.
VREF
109%
107%
94%
92%
PGOOD
High
Low
Figure 21. Power-Good Flag
7.3.10 Over Current and Short Circuit Protection
The LMR14030-Q1 is protected from over current condition by cycle-by-cycle current limiting on the peak current
of the high-side MOSFET. High-side MOSFET over-current protection is implemented by the nature of the Peak
Current Mode control. The high-side switch current is compared to the output of the Error Amplifier (EA) minus
slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak
current of high-side switch is limited by a clamped maximum peak current threshold which is constant. So the
peak current limit of the high-side switch is not affected by the slope compensation and remains constant over
the full duty cycle range.
The LMR14030-Q1 also implements a frequency fold-back to protect the converter in severe over-current or
short conditions. The oscillator frequency is divided by 2, 4, and 8 as the FB pin voltage decrease to 75%, 50%,
25% of VREF. The frequency fold-back increases the off time by increasing the period of the switching cycle, so
that it provides more time for the inductor current to ramp down and leads to a lower average inductor current.
Lower frequency also means lower switching loss. Frequency fold-back reduces power dissipation and prevents
overheating and potential damage to the device.
7.3.11 Overvoltage Protection
The LMR14030-Q1 employs an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. The
OVP feature minimizes output overshoot by turning off high-side switch immediately when FB voltage reaches to
the rising OVP threshold which is nominally 109% of the internal voltage reference VREF. When the FB voltage
drops below the falling OVP threshold which is nominally 107% of VREF, the high-side MOSFET resumes normal
operation.
7.3.12 Thermal Shutdown
The LMR14030-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170 °C (typical). The high-side MOSFET stops switching when thermal shundown activates. Once the
die temperature falls below 158 °C (typical), the device reinitiates the power up sequence controlled by the
internal soft-start circuitry.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR14030-Q1. When VEN is below 1.0 V, the device
is in shutdown mode. The switching regulator is turned off and the quiescent current drops to 1.0 µA typically.
The LMR14030-Q1 also employs under voltage lock out protection. If VIN voltage is below the UVLO level, the
regulator will be turned off.
7.4.2 Active Mode
The LMR14030-Q1 is in Active Mode when VEN is above the precision enable threshold and VIN is above its
UVLO level. The simplest way to enable the LMR14030-Q1 is to connect the EN pin to VIN pin. This allows self
startup when the input voltage is in the operation range: 4.0 V to 40 V. Please refer to Enable and Adjustable
Under-voltage Lockout for details on setting these operating levels.
In Active Mode, depending on the load current, the LMR14030-Q1 will be in one of three modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple.
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation.
3. Sleep-mode when internal COMP voltage drop to 400 mV at very light load.
7.4.3 CCM Mode
CCM operation is employed in the LMR14030-Q1 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum
in this mode and the maximum output current of 3.5 A can be supplied by the LMR14030-Q1.
7.4.4 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR14030-Q1 will
operate in DCM. At even lighter current loads, Sleep-mode is activated to maintain high efficiency operation by
reducing switching and gate drive losses.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMR14030-Q1 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3.5 A. The following design procedure can be used to select
components for the LMR14030-Q1. This section presents a simplified discussion of the design process.
8.2 Typical Application
The LMR14030-Q1 only requires a few external components to convert from wide voltage range supply to a fixed
output voltage. A schematic of 5 V / 3.5 A application circuit based on LMR14030-Q1 in SO-8 package is shown
in Figure 22. The external components have to fulfill the needs of the application, but also the stability criteria of
the device’s control loop.
7 V to 36 V
CBOOT
VIN
CIN
BOOT
L
5 V / 3.5 A
EN
SW
COUT
D
RFBT
RT/SYNC
FB
RFBB
SS
RT
GND
CSS
Figure 22. Application Circuit, 5V Output
8.2.1 Design Requirements
This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level:
Table 2. Design Parameters
Input Voltage, VIN
Output Voltage, VOUT
7 V to 36 V, Typical 12 V
5.0 V
3.5 A
Maximum Output Current IO_MAX
Transient Response 0.35 A to 3.5 A
Output Voltage Ripple
5%
50 mV
400 mV
500 kHz
5 ms
Input Voltage Ripple
Switching Frequency fSW
Soft-start time
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Set-Point
The output voltage of LMR14030-Q1 is externally adjustable using a resistor divider network. The divider network
is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used to determine
the output voltage:
VOUT - 0.75
RFBT
=
ìRFBB
0.75
(7)
Choose the value of RFBT to be 100 kΩ. With the desired output voltage set to 5 V and the VFB = 0.75 V, the RFBB
value can then be calculated using Equation 7. The formula yields to a value 17.65 kΩ. Choose the closest
available value of 17.8 kΩ for RFBB
.
8.2.2.2 Switching Frequency
For desired frequency, use Equation 8 to calculate the required value for RT.
RT(kW) = 42904 ì ƒSW (kHz)-1.088
(8)
For 500 kHz, the calculated RT is 49.66 kΩ and standard value 49.9 kΩ can be used to set the switching
frequency at 500 kHz.
8.2.2.3 Output Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current. A reasonable value of KIND should be
20%-40%. During an instantaneous short or over current operation event, the RMS and peak inductor current
can be high. The inductor current rating should be higher than current limit.
VOUT ì(V
- VOUT
)
IN_MAX
DiL =
VIN_MAX ìL ì ƒSW
(9)
V
- VOUT
VOUT
IN_MAX
LMIN
=
ì
IOUT ìKIND
VIN_MAX ì ƒSW
(10)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss since the RMS current is slightly higher.
Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak
current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current
ripple improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 6.15 µH, and a
nearest standard value is chosen: 6.5 µH. A standard 6.5 μH ferrite inductor with a capability of 4 A RMS current
and 6.5 A saturation current can be used.
8.2.2.4 Output Capacitor Selection
The output capacitor(s), COUT, should be chosen with care since it directly affects the steady state output voltage
ripple, loop stability and the voltage over/undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR) of the output capacitors:
DVOUT_ESR = DiL ìESR = KIND ìIOUT ìESR
(11)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
DiL
KIND ìIOUT
8ì ƒSW ìCOUT 8ì ƒSW ìCOUT
DVOUT_C
=
=
(12)
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The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The regulator’s control loop usually needs three or more clock cycles to respond to the output voltage droop. The
output capacitance must be large enough to supply the current difference for three clock cycles to maintain the
output voltage within the specified range. Equation 13
Equation 13 shows the minimum output capacitance needed for specified output undershoot. When a sudden
large load decrease happens, the output capacitors absorb energy stored in the inductor. The catch diode can’t
sink current so the energy stored in the inductor results in an output voltage overshoot. Equation 14 calculates
the minimum capacitance required to keep the voltage overshoot within a specified range.
3ì(IOH -IOL
ƒSW ì VUS
IO2 H -IO2 L
(VOUT + VOS )2 - VO2UT
)
COUT
>
(13)
(14)
COUT
>
ìL
where
•
•
•
•
•
KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT
IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
)
VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. Equation 11 yields ESR no larger than 35.7 mΩ and Equation 12 yields COUT no smaller than 7
μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be
calculated to be no smaller than 75.6 μF and 30.8 μF by Equation 13 and Equation 14 respectively. In summary,
the most stringent criteria for the output capacitor is 75.6 μF. Two 47 μF, 16 V, X7R ceramic capacitors with 5
mΩ ESR are used in parallel.
8.2.2.5 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. The
current rating for the diode should be equal to the maximum output current for best reliability in most
applications. In cases where the input voltage is much greater than the output voltage the average diode current
is lower. In this case it is possible to use a diode with a lower average current rating, approximately (1-D) × IOUT
however the peak current rating should be higher than the maximum load current. A 4 A to 5 A rated diode is a
good starting point.
8.2.2.6 Input Capacitor Selection
The LMR14030-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended.
To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR14030-Q1 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable or the trace. For this design, two 2.2 μF, X7R ceramic
capacitors rated for 100 V are used. A 0.1 μF for high-frequency filtering and place it as close as possible to the
device pins.
8.2.2.7 Bootstrap Capacitor Selection
Every LMR14030-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
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8.2.2.8 Soft-start Capacitor Selection
Use Equation 15 in order to calculate the soft-start capacitor value:
tSS(ms)ìISS(mA)
CSS(nF) =
VREF(V)
(15)
where
•
•
•
CSS = Soft-start capacitor value
ISS = Soft-start charging current (3 μA)
tSS = Desired soft-start time
For the desired soft-start time of 5 ms and soft-start charging current of 3.0 μA, Equation 15 yields a soft-start
capacitor value of 20 nF, a standard 22 nF ceramic capacitor is used.
For design with LMR14030-Q1 in WSON package, the maximum value of CSS is 4.7 nF.
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8.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 500 kHz, L = 5.6 µH, COUT = 47 µF x 2, TA = 25
°C.
VIN (5 V/DIV)
VIN (5 V/DIV)
EN (1 V/DIV)
VOUT (1 V/DIV)
VOUT (1 V/DIV)
iL (2 A/DIV)
Time (2 ms/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 5 V
IOUT = 2 A
VIN = 12 V
VOUT = 5 V
IOUT = 2 A
Figure 23. Start-up By EN
Figure 24. Start-up By VIN
SW (5 V/DIV)
SW (5 V/DIV)
iL (200 mA/DIV)
iL (200 mA/DIV)
VOUT(ac) (10 mV/DIV)
VOUT(ac) (10 mV/DIV)
Time (2 ms/DIV)
Time (2 µs/DIV)
VIN = 12 V
VOUT = 5 V
IOUT = 0 A
VIN = 12 V
VOUT = 5 V
IOUT = 100 mA
Figure 25. Sleep-mode
Figure 26. DCM Mode
SW (5 V/DIV)
VOUT(ac) (200 mV/DIV)
iL (500 mA/DIV)
IOUT (1 A/DIV)
VOUT(ac) (10 mV/DIV)
Time (2 µs/DIV)
Time (100 µs/DIV)
VIN = 12 V
VOUT = 5 V
IOUT = 1.5 A
IOUT: 20% → 80%
of 3.5 A
Slew rate = 100
mA/μs
Figure 27. CCM Mode
Figure 28. Load Transient
22
Copyright © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 500 kHz, L = 5.6 µH, COUT = 47 µF x 2, TA = 25
°C.
VOUT (1 V/DIV)
VOUT (1 V/DIV)
iL (2 A/DIV)
iL (2 A/DIV)
Time (40 µs/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 5 V
VIN = 12 V
VOUT = 5 V
Figure 29. Output Short
Figure 30. Output Short Recovery
Copyright © 2015–2016, Texas Instruments Incorporated
23
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
9 Power Supply Recommendations
The LMR14030-Q1 is designed to operate from an input voltage supply range between 4 V and 40 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop at
the LMR14030-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the LMR14030-Q1, additional bulk capacitance may be required in
addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47 μF or 100 μF
electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistor RFBT and RFBB, should be kept close to the FB pin. VOUT sense path away
from noisy nodes and preferably through a layer on the other side of a shielding layer.
2. The input bypass capacitor CIN must be placed as close as possible to the VIN pin and ground. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the GND
pin and PAD.
3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor, COUT should be placed close to the junction of L and the diode D. The L, D, and COUT
trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
5. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane
6. For more detail on switching power supply layout considerations see SNVA021 Application Note AN-1149
24
版权 © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
10.2 Layout Example
Output Bypass
Capacitor
Output
Inductor
Rectifier Diode
BOOT
Capacitor
Input Bypass
Capacitor
BOOT
VIN
SW
GND
SS
Soft-Start
Capacitor
EN
RT/SYNC
FB
UVLO Adjust
Resistor
Output Voltage
Set Resistor
Thermal VIA
Signal VIA
Frequency
Set Resistor
Figure 31. Layout
版权 © 2015–2016, Texas Instruments Incorporated
25
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
AN-1149《开关电源布局指南》（文献编号：SNVA021）。
11.2.2 相关产品
部件编号
VIN (V)
IOUT (A)
注释
非同步降压转换器，IQ = 40µA，休眠模式，扩展频谱，SO-8 或 WSON-10
封装
LMR14020-Q1
4.0 - 40
2
非同步降压转换器，IQ = 40µA，休眠模式，扩展频谱，SO-8 或 WSON-10
封装
LMR14050-Q1
4.0 - 40
5
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
26
版权 © 2015–2016, Texas Instruments Incorporated
LMR14030-Q1
www.ti.com.cn
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
27
LMR14030-Q1
ZHCSF91A –NOVEMBER 2015–REVISED JULY 2016
www.ti.com.cn
28
版权 © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR14030QDPRRQ1
LMR14030QDPRTQ1
ACTIVE
WSON
WSON
DPR
10
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LMR
14030Q
ACTIVE
DPR
250
75
RoHS & Green
RoHS & Green
NIPDAU
LMR
14030Q
LMR14030SQDDAQ1
LMR14030SQDDARQ1
LMR14030SQDPRRQ1
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DPR
8
8
NIPDAUAG
NIPDAUAG
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
14030Q
2500 RoHS & Green
3000 RoHS & Green
14030Q
ACTIVE
ACTIVE
WSON
WSON
10
LMR
1403SQ
LMR14030SQDPRTQ1
DPR
10
250
75
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LMR
1403SQ
LMR14030SSQDDAQ1
LMR14030SSQDDARQ1
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
NIPDAUAG
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1403SQ
2500 RoHS & Green
1403SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR14030QDPRRQ1
LMR14030QDPRTQ1
LMR14030SQDDARQ1
WSON
WSON
DPR
DPR
DDA
10
10
8
3000
250
330.0
180.0
330.0
12.4
12.4
12.8
4.25
4.25
6.4
4.25
4.25
5.2
1.15
1.15
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q1
SO
2500
PowerPAD
LMR14030SQDPRRQ1
LMR14030SQDPRTQ1
LMR14030SSQDDARQ1
WSON
WSON
DPR
DPR
DDA
10
10
8
3000
250
330.0
180.0
330.0
12.4
12.4
12.8
4.25
4.25
6.4
4.25
4.25
5.2
1.15
1.15
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q1
SO
2500
PowerPAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR14030QDPRRQ1
LMR14030QDPRTQ1
LMR14030SQDDARQ1
LMR14030SQDPRRQ1
LMR14030SQDPRTQ1
LMR14030SSQDDARQ1
WSON
WSON
DPR
DPR
DDA
DPR
DPR
DDA
10
10
8
3000
250
346.0
210.0
366.0
346.0
210.0
366.0
346.0
185.0
364.0
346.0
185.0
364.0
33.0
35.0
50.0
33.0
35.0
50.0
SO PowerPAD
WSON
2500
3000
250
10
10
8
WSON
SO PowerPAD
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMR14030SQDDAQ1
LMR14030SSQDDAQ1
DDA
DDA
HSOIC
HSOIC
8
8
75
75
517
517
7.87
7.87
635
635
4.25
4.25
Pack Materials-Page 3
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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