LMR14010ADDCT [TI]

具有高效 Eco-Mode 的 SIMPLE SWITCHER® 4V 至 40V、1A 降压转换器 | DDC | 6 | -40 to 125;


型号：	LMR14010ADDCT
厂家：	TEXAS INSTRUMENTS
描述：	具有高效 Eco-Mode 的 SIMPLE SWITCHER® 4V 至 40V、1A 降压转换器 \| DDC \| 6 \| -40 to 125 转换器
文件：	总23页 (文件大小：1078K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMR14010A

ZHCSHV9 –MARCH 2018

LMR14010A 4V 至 40V、1A 降压转换器 - 具有高效 Eco-mode™

1 特性

3 说明

•

输入电压范围为 4V 至 40V，具有高达 45V 的瞬态

保护

LMR14010A 是一款 PWM 直流/直流降压稳压器。该

器件具有 4V 至 40V 的宽输入范围，因此适用于从工

业到汽车的各种应用。1µA 的超低关断电流可延长电

池寿命。工作频率固定在 0.7MHz，从而允许使用小型

外部组件，同时能够最大程度地降低输出纹波电压。在

内部实现了软启动和补偿电路，从而限制了外部组件的

数量。

•

0.7MHz 开关频率

凭借 Eco-mode™，可以在轻负载下实现超高的效

率

•

低压降运行

输出电流高达 1A

精密使能输入

LMR14010A 针对高达 1A 的负载电流进行了优化。它

具有 0.765V 的标称反馈电压。

过流保护

内部补偿

内部软启动

该器件具有内置的保护功能，如逐周期电流限制、热

感应以及在功率耗散过大时关断。LMR14010A 采用薄

型 TSOT-6L 封装 (2.9mm × 1.6mm × 0.85mm)。

小型总体解决方案尺寸（TSOT-6L 封装）

使用 LMR14010A 并借助 WEBENCH^®电源设计器

创建定制设计

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

2 应用

LMR14010A

TSOT-6L

2.9mm x 1.6mm

•

智能仪表

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

电器

升降机和自动扶梯

摄像机

简化原理图

效率与电流间的关系

（ƒ_SW= 0.7MHz，V_IN= 12V，V_OUT= 3.3V）

VIN

Cin

Cboot

100

SHDN

Cout

LMR14010A

GND

0.1

100

1000

Output Current (mA)

C001

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSD87

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

7.4 Device Functional Modes.......................................... 9

Application and Implementation ........................ 10

8.1 Application Information............................................ 10

8.2 Typical Application ................................................. 10

Power Supply Recommendations...................... 15

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration................................................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 7

7.1 Overview ................................................................... 7

7.2 Functional Block Diagram ......................................... 7

7.3 Feature Description................................................... 8

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Example .................................................... 16

11 器件和文档支持 ..................................................... 17

11.1 器件支持 ............................................................... 17

11.2 接收文档更新通知 ................................................. 17

11.3 社区资源................................................................ 17

11.4 商标....................................................................... 17

11.5 静电放电警告......................................................... 17

11.6 Glossary................................................................ 17

12 机械、封装和可订购信息....................................... 17

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 3 月

初始发行版。

LMR14010A

www.ti.com.cn

ZHCSHV9 –MARCH 2018

5 Pin Configuration

DDC Package

(TOP VIEW)

GND

V_IN

PIN 1 ID

SHDN

Pin Functions

I/O

DESCRIPTION

NAME

NO.

SW FET gate bias voltage. Connect C_bootcapacitor between CB and SW.

Feedback Pin. Set feedback voltage divider ratio with V_OUT= V_FB

(1+(R1/R2)).

GND

Ground connection.

Enable and disable input pin(high voltage tolerant). Internal pull-up current

source. Pull below 1.25 V to disable. Float to enable. Adjust the input

undervoltage lockout with two resistors.

SHDN

VIN

Switch node. Connect to inductor, diode and C_bootcapacitor.

Power input voltage pin. Input for internal supply and drain node input for

internal high-side MOSFET.

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

–1

MAX

UNIT

V_INto GND

SHDN to GND

Input Voltages

FB to GND

CB to SW

SW to GND

Output Voltages

SW to GND less than 30ns transients

–2

Storage temperature range, T_stg

Operating junction temperature, T_J

–55

–0

165

150

°C

(1) Stresses at or beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Vin

Buck regulator

CB to SW

–0.7

Control

SHDN

125

Temperature

Operating junction temperature, T_J

–40

°C

6.4 Thermal Information

LMR14010A

THERMAL METRIC⁽¹⁾

SOT (DDC)

6 PINS

102

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

ψ_JB

Junction-to-case (top) thermal resistance

Junction-to-board characterization parameter

36.9

°C/W

28.4

(1) All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to

JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution, number

of thermal vias, board size, ambient temperature, and air flow.

LMR14010A

www.ti.com.cn

ZHCSHV9 –MARCH 2018

6.5 Electrical Characteristics

V_IN= 12V, SHDN = V_IN, T_J= 25°C, unless otherwise noted.

PARAMETER

INPUT POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Operating input voltage

Shutdown supply current

µA

EN = 0 V

Rising

Undervoltage lockout thresholds

I_Q

Falling

ECO mode, no load, V_IN= 12 V, not

switching

µA

SHDN AND UVLO

Rising SHDN Threshold Voltage

1.05

1.25

–4.2

–1

1.38

SHDN = 2.3 V

SHDN = 0.9 V

µA

SHDN PIN current

Hysteresis current

–3

HIGH-SIDE MOSFET

On-resistance

V_IN= 12 V, CB to SW = 5.8 V

500

⁽¹⁾95

mΩ

t_ON-MIN

D_MAX

V_FB

: Maximum duty cycle⁽¹⁾

: Feedback voltage

96%

0.74

550

0.765

0.79

850

CURRENT LIMIT

Current limit threshold

Switching frequency

V_IN= 12 V

Hysteresis

1500

700

ƒ_SW

kHz

THERMAL PERFORMANCE

T_SHUTDOW

Thermal shutdown trip point⁽¹⁾

170

°C

(1)

T_HYS

(1) Specified by design.

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

6.6 Typical Characteristics

Unless otherwise noted, V_IN= 12 V, L = 22 µH, C_OUT= 22 µF, T_A= 25°C

100

Vin=15V

Vin=12V

Vin=18V

Vin=15V

100

1000

100

1000

Output Current (mA)

C001

C002

ƒ_SW= 0.7 MHz

V_OUT= 12 V

ƒ_SW= 0.7 MHz

V_OUT= 5 V

图 1. Efficiency vs Load Current

图 2. Efficiency vs Load Current

1.5%

1.0%

0.5%

0.0%

-0.5%

-1.0%

-1.5%

100

ECO

Shutdown

0.1

200

400

600

800

1000

Load Current (mA)

Input Voltage (V)

C004

C005

V_IN= 18 V

V_OUT= 12 V

V_OUT= 5 V

图 3. Load Regulation

图 4. Supply Current vs Input Voltage (No Load)

LMR14010A

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ZHCSHV9 –MARCH 2018

7 Detailed Description

7.1 Overview

The LMR14010A device is a 40-V, 1-A step-down (buck) regulator. The buck regulator has a very low-quiescent

current during the light load to prolong the battery life.

The LMR14010A improves performance during line and load transients by implementing a constant frequency,

current mode control which reduces output capacitance and simplifies frequency compensation design. The

LMR14010A reduces the external component count by integrating the boot recharge diode. The bias voltage for

the integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The boot capacitor voltage is

monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset

threshold. The LMR14010A can operate at high duty cycles because of the boot UVLO and small refresh FET.

The output voltage can be stepped down to as low as the 0.765-V reference. Internal soft start is featured to

minimize inrush currents.

7.2 Functional Block Diagram

VIN

Leading Edge

Blanking

Bootstrap

Regulator

Logic &

PWM Latch

Driver

Frequency

Shift

0.765V

COMP

Main OSC

∑

Bandgap

Ref

Slope

Compensation

SHDN

GND

LMR14010A

ZHCSHV9 –MARCH 2018

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7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The LMR14010A operates at a fixed frequency, and it implements peak current mode control. The output voltage

is compared through external resistors on the FB pin to an internal voltage reference by an error amplifier which

drives the internal COMP node. An internal oscillator initiates the turn on of the high side power switch. The error

amplifier output is compared to the high side power switch current. When the power switch current reaches the

level set by the internal COMP voltage, the power switch is turned off. The internal COMP node voltage will

increase and decrease as the output current increases and decreases. The device implements a current limit by

clamping the COMP node voltage to a maximum level.

7.3.2 Bootstrap Voltage (CB)

The LMR14010A has an integrated boot regulator, and requires a small ceramic capacitor between the CB and

SW pins to provide the gate drive voltage for the high side MOSFET. The CB capacitor is refreshed when the

high side MOSFET is off and the low side diode conducts.

To improve drop out, the LMR14010A is designed to operate at 96% duty cycle as long as the CB to SW pin

voltage is greater than 3.2 V. When the voltage from CB to SW drops below 3.2 V, the high-side MOSFET is

turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the CB

capacitor. Since the supply current sourced from the CB capacitor is low, the high-side MOSFET can remain on

for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching

regulator is high.

Attention must be taken in maximum duty cycle applications with light load. To ensure SW can be pulled to

ground to refresh the CB capacitor, an internal circuit will charge the CB capacitor when the load is light or the

device is working in dropout condition.

7.3.3 Setting the Output Voltage

The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the

front page schematic. The feedback pin voltage 0.765 V, so the ratio of the feedback resistors sets the output

voltage according to the following equation: V_OUT= 0.765 V (1+(R1/R2)). Typically R2 will be given as 1 kΩ to

100 kΩ for a starting value. To solve for R1 given R2 and V_OUTuses R1 = R2 ((V_OUT/0.765 V) – 1).

7.3.4 Enable (SHDN ) and V_INUndervoltage Lockout

The LMR14010A SHDN pin is a high-voltage tolerant input with an internal pull-up circuit. The device can be

enabled even if the SHDN pin is floating. The regulator can also be turned on using 1.25-V or higher logic

signals. If the use of a higher voltage is desired due to system or other constraints it may be used. A 100-kΩ or

larger resistor is recommended between the applied voltage and the SHDN pin to protect the device. When

SHDN is pulled down to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown

mode the supply current will be decreased to approximately 1 µA. If the shutdown function is not to be used, the

SHDN pin may be tied to V_IN. The maximum voltage to the SHDN pin should not exceed 40 V.

The LMR14010A has an internal UVLO circuit to shutdown the output if the input voltage falls below an internally

fixed UVLO threshold level. This ensures that the regulator is not latched into an unknown state during low input

voltage conditions. The regulator will power up when the input voltage exceeds the UVLO voltage level. If there

is a requirement for a higher UVLO voltage, the SHDN can be used to adjust the input voltage UVLO by using

external resistors.

7.3.5 Current Limit

The LMR14010A implements current mode control which uses the internal COMP voltage to turn off the high

side MOSFET on a cycle by cycle basis. Each cycle the switch current and internal COMP voltage are

compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During

overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP node

high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch

current limit.

LMR14010A

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ZHCSHV9 –MARCH 2018

Feature Description (接下页)

7.3.6 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C

typical. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the

thermal trip threshold. Once the junction temperature decreases below 160°C typical, the device reinitiates the

power-up sequence.

7.4 Device Functional Modes

7.4.1 Continuous Conduction Mode

The LMR14010A steps the input voltage down to a lower output voltage. In continuous conduction mode (when

the inductor current never reaches zero at steady state), the buck regulator operates in two cycles. The power

switch is connected between VIN and SW. In the first cycle of operation the transistor is closed and the diode is

reverse biased. Energy is collected in the inductor, the load current is supplied by C_OUTand the current through

the inductor is rising. During the second cycle the transistor is open and the diode is forward biased due to the

fact that the inductor current cannot instantaneously change direction. The energy stored in the inductor is

transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The

output voltage is defined approximately as: D = V_OUT/V_INand D' = (1-D) where D is the duty cycle of the switch,

D and D' will be required for design calculations.

7.4.2 Eco-mode™

The LMR14010A operates in Eco-mode™ at light-load currents to improve efficiency by reducing switching and

gate drive losses. For Eco-mode™ operation, the LMR14010A senses peak current, not average or load current,

so the load current where the device enters Eco-mode™ is dependent on V_IN, V_OUTand the output inductor

value. When the load current is low and the output voltage is within regulation, the device enters Eco-mode™

(see 图 12) and draws only 28-µA input quiescent current.

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMR14010A is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 1 A. The following design procedure can be used to select

components for the LMR14010A. This section presents a simplified discussion of the design process.

8.2 Typical Application

VIN

Cin

2.2µF/50V

22µH

Cboot

100nF

5V, 1A

SHDN

LMR14010A

Cout

22µF

C1out (optional)

100µF

54.9kꢀ

GND

10kꢀ

图 5. LMR14010A Application Circuit, 5-V Output

8.2.1 Design Requirements

8.2.1.1 Step-By-Step Design Procedure

This example details the design of a high-frequency switching regulator using ceramic output capacitors. A few

parameters must be known in order to start the design process. These parameters are typically determined at the

system level:

PARAMETER

VALUE

Input voltage, V_IN

9 V to 16 V, typical 12 V

Output voltage, V_OUT

5.0 V ± 3%

Maximum output current example I_{O_max}

Minimum output current example I_{O_min}

Transient response 0.03 A to 0.6 A

Output voltage ripple

1 A

0.1 A

Switching frequency f_SW

700 kHz

Target during load transient

Overvoltage peak value

Undervoltage value

106% of output voltage

91% of output voltage

LMR14010A

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ZHCSHV9 –MARCH 2018

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR14010A device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Inductor Selection

The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The

inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages. Since the

ripple current increases with the input voltage, the maximum input voltage is always used to determine the

inductance. 公式 1 is used to calculate the minimum value of the output inductor, where K_INDis ripple current

percentage. A reasonable value is setting the ripple current to be 30% (K_IND) of the DC output current. For this

design example, the minimum inductor value is calculated to be 16.4 µH, and a nearest standard value was

chosen: 22 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings

not be exceeded. The RMS and peak inductor current can be found from 公式 3 and 公式 4. The inductor ripple

current is 0.22 A, and the RMS current is 1 A. As the equation set demonstrates, lower ripple currents will reduce

the output voltage ripple of the regulator but will require a larger value of inductance. A good starting point for

most applications is 22 μH with a 1.6-A current rating. Using a rating near 1.6 A will enable the LMR14010A to

current limit without saturating the inductor. This is preferable to the LMR14010A going into thermal shutdown

mode and the possibility of damaging the inductor if the output is shorted to ground or other long-term overload.

V_{in max}-V_out

V_out

L_{o min}

I_oì K_IND

V_{in max}ì f_sw

(1)

(2)

V_outì(V_{in max}-V_out

V_{in max}ì L_oì f_sw

)

I_ripple

I_L-RMS

I_o

I_ripple

(3)

(4)

I_ripple

I_{L- peak}= I_o+

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ZHCSHV9 –MARCH 2018

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8.2.2.3 Output Capacitor Selection

The selection of C_OUTis mainly driven by three primary considerations. The output capacitor will determine the

modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The

output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The regulator usually needs two or

more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty

cycle to react to the change. The output capacitance must be large enough to supply the difference in current for

2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 5 shows the

minimum output capacitance necessary to accomplish this. For this example, the transient load response is

specified as a 3% change in Vout for a load step from 0.1 A to 1 A (full load). For this example, ΔI_OUT= 1 - 0.1 =

0.9 A and ΔV_OUT= 0.03 × 5 = 0.15 V. Using these numbers gives a minimum capacitance of 17.1 µF. For

ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and

tantalum capacitors have higher ESR that should be taken into account.

The stored energy in the inductor will produce an output voltage overshoot when the load current rapidly

decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning

from a high load current to a lower load current. Equation 6 is used to calculate the minimum capacitance to

keep the output voltage overshoot to a desired value. Where L is the value of the inductor, I_OHis the output

current under heavy load, I_OLis the output under light load, Vf is the final peak output voltage, and Vi is the initial

capacitor voltage. For this example, the worst case load step will be from 1 A to 0.1 A. The output voltage will

increase during this load transition and the stated maximum in our specification is 3 % of the output voltage. This

will make Vo_overshoot = 1.03 × 5 = 5.15 V. Vi is the initial capacitor voltage which is the nominal output voltage

of 5 V. Using these numbers in Equation 6 yields a minimum capacitance of 14.3 µF.

Equation 7 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, Vo_ripple is the maximum allowable output voltage ripple, and IL_ripple is

the inductor ripple current. Equation 7 yields 0.26 µF.

Equation 8 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification. Equation 8 indicates the ESR should be less than 680 mΩ. Additional capacitance de-ratings for

aging, temperature and dc bias should be factored in which will increase this minimum value. For this example,

22 µF ceramic capacitors will be used. Capacitors in the range of 4.7 µF to 100 µF are a good starting point with

an ESR of 0.7 Ω or less.

2ì DI_out

fswì DV_out

C_out

(5)

(6)

(Ioh²- Iol²)

(Vf ²-Vi²)

C_out> L_oì

C_out

V_{o _ ripple}

8ì fsw

I_{L _ ripple}

(7)

(8)

V_{o _ ripple}

R_ESR

I_{L _ ripple}

8.2.2.4 Schottky Diode Selection

The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the

target application, the current rating for the diode should be equal to the maximum output current for best

reliability in most applications. In cases where the input voltage is not much greater than the output voltage the

average diode current is lower. In this case it is possible to use a diode with a lower average current rating,

approximately (1-D) × IOUT, however the peak current rating should be higher than the maximum load current. A

1-A to 2-A rated diode is a good starting point.

LMR14010A

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ZHCSHV9 –MARCH 2018

8.2.2.5 Input Capacitor Selection

A low ESR ceramic capacitor is needed between the VIN pin and ground pin. This capacitor prevents large

voltage transients from appearing at the input. Use a 1-µF to 10-µF value with X5R or X7R dielectric. Depending

on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is

applied. Consult with the capacitor manufactures data sheet for information on capacitor derating over voltage

and temperature. The capacitor must also have a ripple current rating greater than the maximum input current

ripple of the LMR14010A. The input ripple current can be calculated using below Equations.

For this example design, one 2.2-µF, 50-V capacitor is selected. The input capacitance value determines the

input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the

design example values, I_OUTMAX= 1 A, C_IN= 2.2 µF, ƒ_SW= 700 kHz, yields an input voltage ripple of 162 mV and

an rms input ripple current of 0.5 A.

(V_{in min}-V_out

)

V_out

I_cirms= I_out

V_{in min}

(9)

I_{out max}ì 0.25

C_inì fsw

DV_in

(10)

8.2.2.6 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor or larger is recommended for the bootstrap capacitor (C_boot). For applications where

the input voltage is close to output voltage a larger capacitor is recommended, generally 0.1 µF to 1 µF to ensure

plenty of gate drive for the internal switches and a consistently low R_DSON. A ceramic capacitor with an X7R or

X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics

over temperature and voltage.

Below are the recommended typical output voltage inductor/capacitor combinations for optimized total solution

size.

P/N

V_OUT(V)

R1 (kΩ)

54.9 (1%)

64.9 (1%)

147 (1%)

R2 (kΩ)

10 (1%)

L (µH)

C_OUT(µF)

LMR14010A

5.7

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

8.2.3 Application Performance Curves

Unless otherwise noted, V_IN= 12 V, L = 22 µH, C_OUT= 22 µF, T_A= 25°C

V_OUT(50 mV/DIV, AC coupled)

V_OUT(10 mV/DIV, AC coupled)

V_SW(5 V/DIV)

I_INDUCTOR(500 mA/DIV)

Time (1 µs/DIV)

Time (800 µs/DIV)

图 6. Switching Node and Output Voltage

图 7. Load Transient Between 0.1 A and 1 A

Waveform (V_IN= 12 V, V_OUT= 5 V, I_Load= 1 A)

(V_IN= 12 V, V_OUT= 5 V)

V_SHND(5 V/DIV)

V_OUT(10 V/DIV)

V_SHND(5 V/DIV)

V_OUT(10 V/DIV)

V_SW(10 V/DIV)

I_INDUCTOR(1 A/DIV)

Time (400 µs/DIV)

图 8. Start-up Waveform

图 9. Shutdown Waveform

(V_IN= 18 V, V_OUT= 12 V, I_Load= 800 mA)

V_SHND(5 V/DIV)

V_OUT(5 V/DIV)

V_SHND(5 V/DIV)

V_OUT(5 V/DIV)

V_SW(10 V/DIV)

I_INDUCTOR(1 A/DIV)

Time (200 µs/DIV)

Time (100 µs/DIV)

图 10. Start-Up Waveform

图 11. Shutdown Waveform

(V_IN= 12 V, V_OUT= 5 V, I_Load= 800 mA)

LMR14010A

www.ti.com.cn

ZHCSHV9 –MARCH 2018

Unless otherwise noted, V_IN= 12 V, L = 22 µH, C_OUT= 22 µF, T_A= 25°C

V_OUT(20 mV/DIV, AC coupled)

I_INDUCTOR(100 mA/DIV)

V_SW(5 V/DIV)

Time (200 µs/DIV)

图 12. Eco-mode™ Operation (V_IN= 12 V, V_OUT= 5 V, No Load)

9 Power Supply Recommendations

The LMR14010A is designed to operate from an input voltage supply range between 4 V and 40 V. This input

supply should be able to withstand the maximum input current and maintain a voltage above 4 V. The resistance

of the input supply rail should be low enough that an input current transient does not cause a high enough drop

at the LMR14010A supply voltage that can cause a false UVLO fault triggering and system reset. If the input

supply is located more than a few inches from the LMR14010A, additional bulk capacitance may be required in

addition to the ceramic input capacitors.

LMR14010A

ZHCSHV9 –MARCH 2018

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB

with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The feedback network, resistors R1 and R2, should be kept close to the FB pin, and away from the inductor

to minimize coupling noise into the feedback pin.

2. The input capacitor C_INmust be placed close to the V_INpin. This will reduce copper trace inductance which

effects input voltage ripple of the device.

3. The inductor L1 should be placed close to the SW pin to reduce magnetic and electrostatic noise.

4. The output capacitor C_OUTshould be placed close to the junction of L1 and the diode D1. The L1, D1 and

C_OUTtrace should be as short as possible to reduce conducted and radiated noise.

5. The ground connection for the diode, C_INand C_OUTshould be tied to the system ground plane in only one

spot (preferably at the C_OUTground point) to minimize conducted noise in the system ground plane.

10.2 Layout Example

图 13. LMR14010A Layout Example

LMR14010A

www.ti.com.cn

ZHCSHV9 –MARCH 2018

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 使用 WEBENCH® 工具创建定制设计

请单击此处，使用 LMR14010A 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

Eco-mode, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMR14010ADDCR

LMR14010ADDCT

ACTIVE SOT-23-THIN

DDC

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

1N72

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE OUTLINE

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

3.05

2.55

1.1

0.7

1.75

1.45

0.1 C

PIN 1

INDEX AREA

4X 0.95

1.9

3.05

2.75

0.5

0.3

0.1

TYP

0.0

0.2

C A B

0 -8 TYP

0.25

GAGE PLANE

SEATING PLANE

0.20

0.12

TYP

0.6

0.3

TYP

4214841/C 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-193.

www.ti.com

EXAMPLE BOARD LAYOUT

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X (0.95)

(R0.05) TYP

(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN

SCALE:15X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDERMASK DETAILS

4214841/C 04/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X(0.95)

(R0.05) TYP

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

4214841/C 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMR14010ADDCT [TI]

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