LMP7704-SP [TI]
Radiation-hardness-assured (RHA), precision low-input-bias wide-supply-range amplifier with RRIO;
| 型号： | LMP7704-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Radiation-hardness-assured (RHA), precision low-input-bias wide-supply-range amplifier with RRIO |
| 文件： | 总33页 (文件大小：1572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP7704-SP
ZHCSN30C –DECEMBER 2020 –REVISED MARCH 2022
LMP7704-SP 具有低输入偏置和宽电源电压范围的耐辐射加固保障(RHA)、精
密RRIO 放大器
1 特性
3 说明
• QML V 类(QMLV)、RHA、SMD 5962-19206
• 辐射性能
LMP7704-SP 是一款精密放大器，具有低输入偏置、
低失调电压、2.5 MHz 增益带宽积和宽电源电压。该器
件耐辐射，可在 -55°C 至 +125°C 的军用级温度范围
内运行。
– RHA 高达TID = 100krad(Si)
– 无低剂量率辐射损伤增强(ELDRS)，最高TID =
100krad(Si)
该放大器拥有高直流精度等特性，特别是 ±60 µV 的低
失调电压和±500 fA 的超低输入偏置，因此非常适合具
有高输出阻抗的精密传感器接口。该放大器可配置为换
能器/传感器、电桥、应变仪和跨阻放大。
– SEL 对于LET 的抗扰度= 85MeV-cm2/mg
– SEE 对于LET 的额定值= 85MeV cm2/mg
• 超低输入偏置电流：±500fA
• 输入失调电压：±60µV
• 单位带宽增益积：2.5MHz
• 电源电压范围：2.7 V 至12 V
• 轨至轨输入和输出
器件信息
封装(1)
封装尺寸（标称值）
器件型号
5962R1920601VXC，
飞行模型(QMLV)，
RHA 达100 krad
• 军用温度范围-55°C 至+125°C
• 采用14 引线CFP，具有业界通用四路放大器引脚
分配
CFP (14)
9.73mm x 6.47mm
LMP7704HBH/EM，
工程模型(2)
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 卫星运行状况监控和遥测
• 科学勘探有效载荷
• 姿态和轨道控制系统(AOCS)
• 卫星电力系统(EPS)
• 通信负载
(2) 这些器件仅适用于工程评估。按非合规性流程对其进行了处理
（即未进行老化处理等操作）并且仅在25°C 的额定温度下进
行了测试。这些部件不适用于质检、量产、辐射测试或飞行。
这些零件无法在–55°C 至+125°C 的完整MIL 额定温度范围
内或运行寿命中保证其性能。有关工程模型的更多信息，请参
阅德州仪器(TI) 工程评估单元与MIL‑PRF‑38535 QML V 类处
理概述。
• 雷达成像有效载荷
R
R
V
V
1
+
-
R
S
I = (V2 œ V1)
A
1
RS
+
-
V
+
V
Z
LOAD
-
R
R
V
2
A
2
+
-
V
典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDB6
LMP7704-SP
ZHCSN30C –DECEMBER 2020 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................26
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 接收文档更新通知................................................... 27
11.2 支持资源..................................................................27
11.3 Trademarks............................................................. 27
11.4 Electrostatic Discharge Caution..............................27
11.5 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: VS = 5 V............................. 5
6.6 Electrical Characteristics: VS = 10 V........................... 7
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (September 2021) to Revision C (March 2022)
Page
• 将5962R1920601VXC 飞行模型从预发布更改为量产数据（正在供货）...........................................................1
• 删除了器件信息表中已淘汰的5962-1920601VXC 飞行模型.............................................................................1
Changes from Revision A (January 2021) to Revision B (September 2021)
Page
• 将器件状态从“预告信息（预发布）”更改为“量产数据（正在供货）”.........................................................1
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5 Pin Configuration and Functions
图5-1. HBH Package, 14-Pin CFP, Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN A+
IN A–
IN B+
IN B–
IN C+
IN C–
IN D+
IN D–
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input for amplifier A
Inverting input for amplifier A
Noninverting input for amplifier B
Inverting input for amplifier B
Noninverting input for amplifier C
Inverting input for amplifier C
Noninverting input for amplifier D
Inverting input for amplifier D
Output for amplifier A
2
5
I
6
I
10
9
I
I
12
13
1
I
I
O
O
O
O
P
P
—
7
Output for amplifier B
8
Output for amplifier C
14
4
Output for amplifier D
Positive supply
V–
11
—
Negative supply
LID
The metal lid is internally connected to V–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VS
13.2
V
Supply voltage, VS = (V+) –(V–)
Common-mode
Differential
(V+) + 0.3
(V–) –0.3
Voltage
V
(V+) –(V–) + 0.3
Current
±10
Continuous
150
mA
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
Continuous
TA
°C
°C
°C
–55
TJ
150
TSTG
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
12
UNIT
V
VS
TA
Supply voltage, VS = (V+) –(V–)
Specified temperature
125
°C
–55
6.4 Thermal Information
LMP7704-SP
HBH (CFP)
14 PINS
37.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
ºC/W
RθJC(top)
RθJB
20.6
21.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
12.9
ψJT
21.0
ψJB
RθJC(bot)
10.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = 5 V
at TA = +25°C, VS = (V+) –(V–) = 5 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±60
±260
±520
VOS
Input offset voltage
µV
TA = –55°C to +125°C
TA = –55°C to +125°C
Input offset voltage
drift(1)
dVOS/dT
PSRR
±1
±5
µV/°C
86
82
100
dB
dB
Power-supply rejection
ratio
2.7 V < VS < 12 V
TA = –55°C to +125°C
INPUT BIAS CURRENT
±0.5
±40
±10
pA
pA
fA
IB
Input bias current
±400
TA = –55°C to +125°C
IOS
Input offset current
NOISE
Input voltage noise
density
en
in
f = 1 kHz
9
1
nV/√Hz
fA/√Hz
Input current noise
density
f = 100 kHz
INPUT VOLTAGE
(V–) –
VCM
Common-mode voltage
(V+) + 0.2
V
TA = –55°C to +125°C
(V–) < VCM < (V+)
0.2
85
81
130
Common-mode rejection
ratio
TA = –55°C to +125°C
CMRR
dB
Flight model post-HDR exposure,
TA = –55°C to +125°C
76
OPEN-LOOP GAIN
100
94
119
130
(V–) + 0.3 V < VOUT < (V+) –0.3
V,
RL = 2 kΩ
TA = –55°C to +125°C
Flight model post-HDR exposure,
TA = –55°C to +125°C
AOL
Open-loop voltage gain
84
dB
100
96
(V–) + 0.2 V < VOUT < (V+) –0.2
V
TA = –55°C to +125°C
FREQUENCY RESPONSE
GBW
SR
Gain bandwidth
Slew rate
2.5
1
MHz
V/µs
G = 1, 4-V step, 10% to 90% rising
G = 1, f = 1 kHz
Total harmonic distortion
+ noise
THD+N
0.02%
OUTPUT
60
120
200
RL = 2 kΩto VS / 2
RL = 2 kΩto VS / 2,
TA = –55°C to +125°C
Positive rail
40
50
60
120
120
TA = –55°C to +125°C
RL = 2 kΩto VS / 2
Voltage output swing
from rail
VO
mV
mA
RL = 2 kΩto VS / 2,
TA = –55°C to +125°C
190
Negative rail
30
50
100
TA = –55°C to +125°C
ISC
Short-circuit current
VOUT = VS / 2, VIN = ±100 mV
+66 / –76
POWER SUPPLY
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6.5 Electrical Characteristics: VS = 5 V (continued)
at TA = +25°C, VS = (V+) –(V–) = 5 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.9
3.7
IQ
Total quiescent current
IO = 0 A
mA
5.1
TA = –55°C to +125°C
(1) Specification set by device characterization, not tested in final production.
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6.6 Electrical Characteristics: VS = 10 V
at TA = +25°C, VS = (V+) –(V–) = 10 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±60
±260
±520
VOS
Input offset voltage
µV
TA = –55°C to +125°C
TA = –55°C to +125°C
Input offset voltage
drift(1)
dVOS/dT
PSRR
±1
±5
µV/°C
86
82
100
dB
dB
Power-supply rejection
ratio
2.7 V < VS < 12 V
TA = –55°C to +125°C
INPUT BIAS CURRENT
±1
±10
pA
pA
fA
IB
Input bias current
±400
TA = –55°C to +125°C
IOS
Input offset current
±40
NOISE
Input voltage noise
density
en
in
f = 1 kHz
9
1
nV/√Hz
fA/√Hz
Input current noise
density
f = 100 kHz
INPUT VOLTAGE
(V–) –
VCM
Common-mode voltage
(V+) + 0.2
V
0.2
90
86
130
Common-mode rejection
ratio
TA = –55°C to +125°C
CMRR
dB
(V–) < VCM < (V+)
Flight model post-HDR exposure,
TA = –55°C to +125°C
83
OPEN-LOOP GAIN
100
94
121
134
(V–) + 0.3 V < VOUT < (V+) –0.3
V,
RL = 2 kΩ
TA = –55°C to +125°C
TA = –55°C to +125°C
AOL
Open-loop voltage gain
dB
100
97
(V–) + 0.2 V < VOUT < (V+) –0.2
V
FREQUENCY RESPONSE
GBW
SR
Gain bandwidth
Slew rate
2.5
0.8
MHz
V/µs
G = 1, 9-V step, 10% to 90% rising
G = 1, f = 1 kHz
Total harmonic distortion
+ noise
THD+N
0.02%
OUTPUT
60
120
200
RL = 2 kΩto VS / 2
RL = 2 kΩto VS / 2,
TA = –55°C to +125°C
Positive rail
40
50
60
120
120
TA = –55°C to +125°C
RL = 2 kΩto VS / 2
Voltage output swing
from rail
VO
mV
mA
RL = 2 kΩto VS / 2,
TA = –55°C to +125°C
190
Negative rail
30
50
100
TA = –55°C to +125°C
ISC
Short-circuit current
VOUT = VS / 2, VIN = ±100 mV
+86 / –84
POWER SUPPLY
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6.6 Electrical Characteristics: VS = 10 V (continued)
at TA = +25°C, VS = (V+) –(V–) = 10 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.2
4.2
IQ
Total quiescent current
IO = 0 A
mA
5.7
TA = –55°C to +125°C
(1) Specification set by device characterization, not tested in final production.
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6.7 Typical Characteristics
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
25
20
V
= 3V
V
T
= 3V
S
S
-40°C Ç T Ç 125°C
= 25°C
A
A
20
16
12
8
15
10
5
4
0
-200
0
-100
0
100
200
-3
-3
-3
-2
-1
0
1
2
3
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
图6-1. Offset Voltage Distribution
图6-2. TCVOS Distribution
25
20
16
V
T
= 5V
S
V = 5V
S
= 25°C
A
-40°C Ç T Ç 125°C
A
20
15
10
5
12
8
4
0
-200
0
-100
0
100
200
-2
-1
0
1
2
3
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
图6-3. Offset Voltage Distribution
图6-4. TCVOS Distribution
25
20
15
10
5
20
16
V
= 10V
V
T
= 10V
S
S
-40°C Ç T Ç 125°C
= 25°C
A
A
12
8
4
0
-200
0
-100
0
100
200
-2
-1
0
1
2
3
OFFSET VOLTAGE (mV)
TCV
(mV/°C)
OS
图6-5. Offset Voltage Distribution
图6-6. TCVOS Distribution
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
200
150
100
0
-20
V
= 3V
S
-40
V
= 3V
S
V
S
= 5V
50
-60
-80
0
V
= 10V
S
-50
V
S
= 5V
-100
-100
-150
-200
V
= 10V
S
-120
-140
-40 -20
0
20 40 60 80 100 120125
TEMPERATURE (°C)
10k
FREQUENCY (Hz)
10
100
1k
100k
1M
图6-7. Offset Voltage vs Temperature
图6-8. CMRR vs Frequency
200
150
200
150
100
50
V
= 3V
S
-40°C
100
-40°C
50
25°C
0
0
25°C
-50
-50
125°C
-100
-100
-150
-200
125°C
-150
-200
2
4
6
8
10
12
0
0.5
1.5
(V)
2
2.5
3
3.5
-0.5
1
V
CM
SUPPLY VOLTAGE (V)
图6-10. Offset Voltage vs VCM
图6-9. Offset Voltage vs Supply Voltage
200
200
150
100
V
S
= 10V
V
= 5V
S
150
100
-40°C
25°C
-40°C
25°C
50
0
50
0
-50
-50
-100
-150
-200
-100
-150
125°C
125°C
-200
-1
0
1
2
3
4
5
6
5
-1
0
1
2
3
4
6
7
8
9 10 11
V
CM
(V)
V
CM
(V)
图6-11. Offset Voltage vs VCM
图6-12. Offset Voltage vs VCM
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
200
300
V
S
= 3V
V
S
= 3V
200
100
100
0
85°C
-40°C
0
-100
-100
-200
-200
-300
125°C
25°C
1.5
0
0.5
1
1.5
(V)
2
2.5
3
0
0.5
1
2
2.5
3
V
V
(V)
CM
CM
图6-14. Input Bias Current vs VCM
图6-13. Input Bias Current vs VCM
300
300
V
S
= 5V
V
S
= 5V
200
200
100
100
0
85°C
-40°C
0
-100
-100
-200
-300
-200
-300
25°C
125°C
0
1
2
3
4
5
0
1
2
3
4
5
V
CM
(V)
V
CM
(V)
图6-16. Input Bias Current vs VCM
图6-15. Input Bias Current vs VCM
500
300
200
V
S
= 10V
V
S
= 10V
250
0
100
0
85°C
-40°C
-100
-250
-200
-300
25°C
125°C
-500
0
2
4
6
8
10
0
2
4
6
8
10
V
CM
(V)
V
CM
(V)
图6-17. Input Bias Current vs VCM
图6-18. Input Bias Current vs VCM
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
120
1.2
1
V
= 10V
S
V
S
= 5V
100
125°C
-40°C
V
= 3V
S
25°C
+PSRR
0.8
0.6
0.4
80
60
V
= 10V
S
V
= 5V
S
V
= 3V
S
40
20
0.2
0
-PSRR
100k
0
10k
FREQUENCY (Hz)
10
100
1k
1M
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
图6-19. PSRR vs Frequency
图6-20. Supply Current vs Supply Voltage (Per Channel)
120
100
120
-40°C
25°C
-40°C
125°C
100
25°C
80
60
40
80
60
40
125°C
20
0
20
0
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
图6-21. Sinking Current vs Supply Voltage
图6-22. Sourcing Current vs Supply Voltage
+
V
1.5
A
V
= +1
T
A
= -40°C, 25°C, 125C
V
1.4
1.3
1.2
1.1
1
= 2 V
+
(V ) -1
IN
PP
R
C
= 10 kW
L
L
FALLING EDGE
= 10 pF
+
(V ) -2
3V
ö
ö
0.9
0.8
0.7
0.6
0.5
2
1
0
RISING EDGE
V
= 3V, 5V, 10V
S
0
20
40
60
80
100
2
4
6
8
10
12
OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
图6-23. Output Voltage vs Output Current
图6-24. Slew Rate vs Supply Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
100
80
60
40
20
0
225
180
135
90
100
80
60
40
20
0
225
V
= 3V, 5V, 10V
= 20 pF, 50 pF, 100 pF
= 10 kW
S
GAIN
GAIN
180
135
C
R
L
L
V
= 10V
S
-40°C
25°C
C
= 20 pF 90
L
PHASE
PHASE
45
0
45
0
125°C
125°C
25°C
-40°C
-45
-90
-45
-90
-20
-40
-60
-20
-40
-60
V
= 5V
S
C
R
= 20 pF
= 10 kW
V
= 3V
L
L
S
C
= 100 pF
L
-135
100M
-135
10M
100M
100k
10M
100
10k
1M
1k
100k
FREQUENCY (Hz)
100
10k
1M
1k
FREQUENCY (Hz)
图6-25. Open-Loop Frequency Response
图6-26. Open-Loop Frequency Response
V
= 5V
V
= 5V
S
S
f = 10 kHz
f = 10 kHz
A
V
= +1
A
V
= +1
V
V
= 100 mV
= 10 kW
= 10 pF
= 2 V
IN
PP
IN
PP
R
C
R
C
= 10 kW
L
L
L
L
= 10 pF
10 ms/DIV
10 ms/DIV
图6-27. Large Signal Step Response
图6-28. Small Signal Step Response
V
= 5V
V
= 5V
S
S
f = 10 kHz
f = 10 kHz
A
V
= +10
A
V
= +10
V
V
= 100 mV
= 10 kW
= 10 pF
= 400 mV
= 10 kW
= 10 pF
IN
PP
IN
PP
R
C
R
C
L
L
L
L
10 ms/DIV
10 ms/DIV
图6-29. Large Signal Step Response
图6-30. Small Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
120
100
80
150
140
130
120
V
= 10V
S
V
= 5V
S
R
L
= 10 kW
110
100
90
V
= 3V
S
60
40
20
0
V
= 3V
S
V
= 5V
S
80
R
= 2 kW
L
70
V
= 10V
S
60
1k
FREQUENCY (Hz)
10k
1
10
100
100k
500
400
300
200
100
0
OUTPUT SWING FROM RAIL (mV)
图6-31. Input Voltage Noise vs Frequency
图6-32. Open Loop Gain vs Output Voltage Swing
50
50
R
= 10 kW
R
= 10 kW
L
L
25°C
40
30
20
10
0
40
30
20
10
0
125°C
-40°C
125°C
-40°C
25°C
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
图6-33. Output Swing High vs Supply Voltage
图6-34. Output Swing Low vs Supply Voltage
100
100
R
= 2 kW
R
= 2 kW
L
L
25°C
25°C
80
60
40
20
0
80
60
40
20
0
125°C
125°C
-40°C
-40°C
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
图6-35. Output Swing High vs Supply Voltage
图6-36. Output Swing Low vs Supply Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VCM = VS/2, and RL > 10 kΩ (unless otherwise noted)
1
1
V
= 5V
S
V
V
= 5V
S
f = 1 kHz
= 100 kW
= 4.5 V
O
PP
R
L
R
= 100 kW
L
0.1
0.01
0.1
0.01
A
V
= +10
A = +10
V
A
V
= +1
A
V
= +1
0.001
0.001
10
100
1k
10k
100k
0.001
0.01
0.1
1
10
V
OUT
(V)
FREQUENCY (Hz)
图6-37. THD+N vs Frequency
图6-38. THD+N vs Output Voltage
140
V
S
= 12V
120
100
80
V
= 5V
S
V
S
= 3V
60
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
图6-39. Crosstalk Rejection Ratio vs Frequency (LMP7702/LMP7704)
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7 Detailed Description
7.1 Overview
The LMP7704-SP is a radiation-hardened, quad, low offset voltage, rail-to-rail input and output precision
amplifier with a CMOS input stage. The LMP7704-SP has a wide supply voltage range of 2.7 V to 12 V and a
very low input bias current of only ±500 fA at room temperature.
The wide supply voltage range of 2.7 V to 12 V over the extensive temperature range of −55°C to +125°C makes
the LMP7704-SP an excellent choice for low-voltage, precision applications with extensive temperature
requirements.
The LMP7704-SP has only ±60 μV of input-referred offset voltage. This offset voltage allows for more accurate
signal detection and amplification in precision applications.
The low input bias current of only ±500 fA along with the low input-referred voltage noise of 9 nV/√Hz give the
LMP7704-SP superiority for use in sensor applications. Lower levels of noise from the LMP7704-SP mean better
signal fidelity and a higher signal-to-noise ratio.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Radiation Hardened Performance
Total Ionizing Dose (TID)—The LMP7704-SP is a radiation-hardness-assured (RHA) QML class V (QMLV)
product, with a total ionizing dose (TID) level specified in the Device Information table on the front page of this
data sheet. Testing and qualification of these products is done on a wafer level according to MIL-STD-883, Test
Method 1019. Radiation lot acceptance testing (RLAT) is performed at 30-krad, 50-krad, and 100-krad TID
levels.
Group E TID RLAT data are available with lot shipments as part of the QCI summary reports; for information on
finding QCI summary reports, see QML Flow, Its Importance, and Obtaining Lot Information.
Neutron Displacement Damage (NDD)—The LMP7704-SP was irradiated up to 1 × 1012 n/cm2. A sample size
of 15 units was exposed to radiation testing per MILSTD-883, Method 1017 for Neutron Irradiation.
Single-Event Effects (SEE)—One-time SEE characterization was performed according to EIA/JEDEC standard,
EIA/JEDEC57 to linear energy transfer (LET) = 85 MeV⋅cm2/mg. During testing, no single-event latch-up (SEL)
was observed.
7.3.2 Engineering Model (Devices With /EM Suffix)
Engineering evaluation or engineering model (EM) devices are available for order and are identified by the /EM
in the orderable device name (see the Ordering Information table on the front page of the data sheet). These
devices meet the performance specifications of the data sheet at room temperature only and have not received
the full space production flow or testing. Engineering samples may be QCI rejects that failed tests that would not
impact the performance at room temperature, such as radiation or reliability testing.
7.3.3 Capacitive Load
The LMP7704-SP can be connected as a noninverting unity gain follower. This configuration is the most
sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier output
impedance creates a phase lag, which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response is either underdamped or oscillated.
To drive heavier capacitive loads, use an isolation resistor, labeled as RISO in 图 7-1. By using this isolation
resistor, the capacitive load is isolated from the amplifier output, and thus, the pole caused by CL is no longer in
the feedback loop. The larger the value of RISO, the more stable the output voltage. If values of RISO are
sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO
result in reduced output swing and reduced output current drive.
图7-1. Isolating Capacitive Load
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7.3.4 Input Capacitance
CMOS input stages inherently have low input bias current and higher input-referred voltage noise. The
LMP7704-SP enhances this performance by having a low input bias current of only ±500 fA, as well as a very
low input-referred voltage noise of 9 nV/√Hz. To achieve these specifications, a larger input stage is used. This
larger input stage increases the input capacitance of the LMP7704-SP. The typical value of this input
capacitance, CIN, for the LMP7704-SP is 25 pF. The input capacitance interacts with other impedances, such as
gain and feedback resistors, which are seen on the inputs of the amplifier, to form a pole. This pole has little or
no effect on the output of the amplifier at low frequencies and dc conditions, but plays a bigger role as the
frequency increases. At higher frequencies, the presence of this pole decreases phase margin and also causes
gain peaking. To compensate for the input capacitance, choose the feedback resistors carefully. In addition to
being selective in picking values for the feedback resistor, add a capacitor to the feedback path to increase
stability.
The dc gain of the circuit shown in 图7-2 is simply –R2/R1.
C
R
F
2
R
1
-
+
C
IN
V
+
-
IN
+
V
OUT
-
R2
R1
VOUT
-
AV =
-
=
VIN
图7-2. Compensating for Input Capacitance
For the time being, ignore CF. The ac gain of the circuit in 图7-2 can be calculated as follows:
VOUT
VIN
-R2/R1
(s) =
s2
s
«
«
∆
1 +
+
A0 R1
A0
∆
≈
≈
∆
«
≈
≈
∆
«
CIN R2
R1 + R2
(1)
(2)
This equation is rearranged to find the location of the two poles:
2
«
∆
4 A0CIN
≈
1
1
-1
1
1
-
≈
P1,2
=
+
ê
+
∆
R1
R2
R
R2
R2
2CIN
«
1
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方程式 2 shows that as values of R1 and R2 are increased, the magnitude of the poles is reduced, which in turn
decreases the bandwidth of the amplifier. Whenever possible, the best practice is to choose smaller feedback
resistors. 图7-3 shows the effect of the feedback resistor on the bandwidth of the LMP7704-SP.
2
V
= 5V
= 0 pF
= -1
S
C
F
V
0
-2
A
R
= R = 100 kW
2
1
-4
R
= R = 30 kW
2
1
-6
R
= R = 10 kW
2
1
-8
R
= R = 1 kW
1
2
-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
图7-3. Closed-Loop Gain vs Frequency
方程式 2 has two poles. In most cases, the presence of pairs of poles causes gain peaking. To eliminate this
effect, place the poles in a Butterworth position, because poles in a Butterworth position do not cause gain
peaking. To achieve a Butterworth pair, set the quantity under the square root in 方程式 2 to equal −1. Using this
fact and the relation between R1 and R2 (R2 = −AV R1), the optimum value for R1 is found. Use 方程式 3 to
calculate the value of R1. If R1 is larger than this optimum value, gain peaking occurs.
(1 - AV)2
R1
<
2A0AVCIN
(3)
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In 图 7-2, CF is added to compensate for input capacitance and to increase stability. Additionally, CF reduces or
eliminates the gain peaking that can be caused by having a larger feedback resistor. 图 7-4 shows how CF
reduces gain peaking.
2
C
= 0 pF
= 1 pF
F
0
-2
C
F
C
= 5 pF
F
-4
C
= 3 pF
F
-6
V
= 5V
S
-8
R
= R = 100 kW
1
2
A
= -1
V
-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
图7-4. Closed-Loop Gain vs Frequency With Compensation
7.3.5 Diodes Between the Inputs
The LMP7704-SP have a set of anti-parallel diodes between the input pins, as shown in 图 7-5. These diodes
are present to protect the input stage of the amplifier. At the same time, the diodes limit the amount of differential
input voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might
damage the diodes. The differential signal between the inputs must be limited to ±300 mV or the input current
must be limited to ±10 mA.
+
+
V
V
D
1
ESD
IN
ESD
ESD
R
R
2
1
-
+
IN
ESD
D
2
-
-
V
V
图7-5. Input of LMP7704-SP
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7.4 Device Functional Modes
7.4.1 Precision Current Source
The LMP7704-SP can be used as a precision current source in many different applications. 图 7-6 shows a
typical precision current source. This circuit implements a precision, voltage-controlled current source. Amplifier
A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal. Amplifier A2 is a buffer
that eliminates the error current from the load side of the RS resistor. In general, the circuit is stable as long as
the closed-loop bandwidth of amplifier A2 is greater then the closed-loop bandwidth of amplifier A1. If A1 and A2
are the same type of amplifiers, then the feedback around A1 reduces bandwidth compared to A2.
R
R
V
1
+
V
-
R
S
I = (V2 œ V1)
A
1
RS
+
-
V
+
V
Z
LOAD
-
R
R
V
2
A
2
+
-
V
图7-6. Precision Current Source
The equation for output current is derived as shown in 方程式4:
(V0 œ IRS)R
V2R
V1R
+
R + R R + R
V0R
=
+
R + R
R + R
(4)
(5)
Solving for current I results in 方程式5:
V2 œ V1
I =
R
S
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 Low Input Voltage Noise
The LMP7704-SP has a very low input voltage noise of 9 nV/√Hz. This input voltage noise is further reduced by
placing N amplifiers in parallel, as shown in 图 8-1. The total voltage noise on the output of this circuit is divided
by the square root of the number of amplifiers used in this parallel combination. The reason is because each
individual amplifier acts as an independent noise source, and the average noise of independent sources is the
quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers:
1
2
2
+e
n1 n2
2
+....+e
REDUCED INPUT VOLTAGE NOISE =
e
nN
N
N
N
1
Ne2
=
=
=
e
n
n
N
1
e
n
N
(6)
图8-1 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are:
RG = 10 Ω, RF = 1 kΩ, and RO = 1 kΩ.
+
V
V
+
IN
V
OUT
-
R
O
O
O
-
V
R
G
R
F
+
V
+
-
R
-
R
G
V
R
F
+
V
+
-
R
-
R
G
V
R
F
+
V
+
-
R
O
-
R
G
V
R
F
图8-1. Noise Reduction Circuit
8.1.2 Total Noise Contribution
The LMP7704-SP has a very-low input bias current, very-low input current noise, and very-low input voltage
noise. As a result, this amplifier is an excellent choice for circuits with high-impedance sensor applications.
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图8-2 shows the typical input noise of the LMP7704-SP as a function of source resistance where:
• en denotes the input-referred voltage noise.
• ei is the voltage drop across source resistance due to input-referred current noise or ei = RS * in.
• et shows the thermal noise of the source resistance.
• eni shows the total noise on the input, where:
eni = en2+ e2i + et2
1000
100
e
ni
e
n
10
e
t
e
i
1
0.1
10k
(W)
1M
10
1k
100k
10M
100
R
S
图8-2. Total Input Noise
The input current noise of the LMP7704-SP is so low that this noise does not become the dominant factor in the
total noise unless the source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in 图 8-2, at lower RS values, total noise is dominated by the amplifier input voltage noise. If RS is
larger than a few kilo-ohms, then the dominant noise factor becomes the thermal noise of RS. As mentioned
previously, the current noise will not be the dominant noise factor for any practical application.
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8.2 Typical Application
10 kꢀ
240 kꢀ
GND
5 V
Signal Source with
high output impedance
GND
Vout
œ
10 Mꢀ
+
+
Vin = 0.1 V
œ
-5 V
GND
GND
图8-3. LMP7704-SP Configured for 25x Gain With High Signal Source Impedance
8.2.1 Design Requirements
Many precision analog sensors, such as temperature or pressure (bridge) sensors, require a high-precision
amplifier with low input bias to condition the signal before the analog-to-digital converter. The LMP7704-SP is an
excellent amplifier choice for a voltage gain stage thanks to the low offset voltage, offset voltage drift, and ultra-
low input bias current.
8.2.2 Detailed Design Procedure
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors must
often be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier can
load the sensor output and cause a voltage drop across the source resistance, as shown in 图 8-4, where VIN+
VS –IBIAS * RS.
=
SENSOR
+
V
I
B
R
S
V
+
IN
+
-
+
V
S
-
-
V
图8-4. Offset Error Due to IBIAS
The last term, IBIAS * RS, shows the voltage drop across RS. To prevent errors introduced to the system due to
this voltage, an op amp with very low input bias current must be used with high impedance sensors. An amplifier
with low input bias also has low input current noise, further improving the accuracy of systems with high source
resistance.
图 8-3 shows one channel of the LMP7704-SP configured for a gain of 25. A high source impedance is placed
between the input signal and the noninverting input of the amplifier to represent the output impedance of the
sensor.
With the ultra-low input bias current of the LMP7704-SP, even with a signal source that has high output
impedance, the system output maintains very good linearity to the ideal output voltage (that is, the output of an
ideal amplifier in the same configuration). 图 8-5 shows the output voltage vs input voltage of the LMP7704-SP
with a 10-MΩ source impedance. 图 8-6 shows the output voltage vs input voltage for an ideal amplifier with no
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input bias current. Comparing the two graphs shows that the LMP7704-SP maintains high accuracy even with a
large source impedance connected to an input.
8.2.3 Application Curves
图8-5. LMP7704-SP Output Voltage vs Input
图8-6. LMP7704-SP Ideal Output Voltage vs Input
Voltage
Voltage
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9 Power Supply Recommendations
For proper operation, the power supplies must be decoupled. To decouple the supply, place 10‑nF to 1‑µF
capacitors as close as possible to the operational-amplifier power-supply pins. For single-supply configurations,
place a capacitor between the V+ and V– supply pins. For dual-supply configurations, place one capacitor
between V+ and ground, and place a second capacitor between V– and ground. Bypass capacitors must have a
low ESR of less than 0.1 Ω.
10 Layout
10.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. Use a ground plane underneath the device; best practice is for any bypass components to ground to
have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins lowers the power-
supply inductance and provides a more stable power supply.
To minimize stray parasitics, place the feedback components as close as possible to the device.
10.2 Layout Example
+3.3V
GND
+3.3V
+3.3V
5
2
GND
1
+3.3V
VOUT
2
2
2
1
VOUT
GND
VOUT
VOUT
+3.3V
4
3
1
1
V–
V+
V–
V–
2
+3.3V
1
2
1
1
2
V+
GND GND
GND
V–
V+
GND
V+
图10-1. LMP7704-SP Example Layout for a Single Channel
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Product Folder Links: LMP7704-SP
LMP7704-SP
ZHCSN30C –DECEMBER 2020 –REVISED MARCH 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMP7704-SP
LMP7704-SP
ZHCSN30C –DECEMBER 2020 –REVISED MARCH 2022
www.ti.com.cn
PACKAGE OUTLINE
HBH0014A
CFP - 2.874 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
B
(6.09)
4X (R0.76)
6X 1.27
14
1
9.91
(9.27)
9.55
2X 7.62
7
8
0.482
0.382
8X
6.65
6.30
A
0.2
C A B
2.874 MAX
0.18
0.10
0.43 MAX
(4.45)
C
0.18 MIN
8
7
1
14
PIN 1 ID
25 MAX
4225069/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. The lid is not connected to any lead.
4. The leads are gold plated.
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R1920601VXC
LMP7704HBH/EM
ACTIVE
CFP
CFP
HBH
14
14
1
RoHS & Green
RoHS & Green
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962R1920601VXC
LMP7704
Samples
Samples
ACTIVE
HBH
1
NIAU
LMP7704HBH/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
OTHER QUALIFIED VERSIONS OF LMP7704-SP :
Catalog : LMP7704
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R1920601VXC
LMP7704HBH/EM
HBH
HBH
CFP
CFP
14
14
1
1
506.98
506.98
26.16
26.16
6220
6220
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HBH0014A
CFP - 2.861 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
METAL LID
B
(6.09)
4X (R0.76)
6X 1.27
14
1
9.91
(9.27)
9.55
2X 7.62
7
8
0.482
0.382
C A B
8X
6.65
6.30
A
0.2
2.861
2.325
0.18
0.10
0.98
0.80
4.65
4.25
C
0.18 MIN
(4.04)
8
7
(9.32)
1
14
PIN 1 ID
BACKSIDE METALLIZATION
(THERMAL PAD)
25 MAX
4225069/C 07/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. The lid is not connected to any lead.
4. The leads are gold plated.
5. Metal lid is connected to backside metalization.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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