LMK6HA10000BDLFT [TI]
低抖动、高性能、体声波 (BAW) 固定频率 HCSL 振荡器 | DLF | 6 | -40 to 85;
| 型号： | LMK6HA10000BDLFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低抖动、高性能、体声波 (BAW) 固定频率 HCSL 振荡器 | DLF | 6 | -40 to 85 振荡器 |
| 文件： | 总58页 (文件大小：4333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
LMK6x 低抖动高性能BAW 振荡器
1 特性
3 说明
• 高性能差分和单端输出振荡器、支持以下范围内的
任何固定频率：
德州仪器 (TI) 的体声波 (BAW) 是一种微谐振器技术，
能够将高精度 BAW 谐振器直接集成到具有超低抖动时
钟电路的封装中。与其他硅基制造工艺一样，BAW 完
全由TI 工厂设计和制造。
– LMK6D：1 至400MHz、LVDS 输出
– LMK6H：1 至400MHz、HCSL 输出
– LMK6P：1 至400MHz、LVPECL 输出
– LMK6C：1 至200MHz、LVCMOS 输出
• 超低抖动：
LMK6x 器件是一款超低抖动固定频率振荡器，融合了
BAW 作为谐振器源。该器件根据特定运行模式进行出
厂编程，包括频率、电压、输出类型和功能引脚。
LMK6x 带有高性能分数分频器，能够产生指定范围内
的任何频率，提供可满足所有频率需求的单个器件系
列。
– LMK6D/LMK6H/LMK6P：频率为156.25MHz 时
RMS 抖动典型值为100fs，最大值为125fs
（12kHz 至20MHz）
– LMK6C：频率为100MHz 时RMS 抖动典型值
为350fs，最大值为500fs（12kHz 至20MHz）
– LMK6H：符合PCIe 第1 代到第6 代标准
• ±25ppm 的总频率稳定性（考虑10 年老化和所有其
他因素）
凭借高性能时钟、机械稳定性、灵活性和小型封装选
项，此器件非常适用于电信、数据以及企业网络和工业
应用中使用的高速 SERDES 内的参考时钟和核心时
钟。
• 超小型业界通用DLE 和DLF 封装
• 支持扩展工业温度等级：
封装信息
封装(1)
封装尺寸（标称值）
3.20mm x 2.50mm
2.50mm × 2.00mm
器件型号
LMK6C
输出类型
– LMK6P/LMK6D/LMK6H：–40°C 至85°C
– LMK6C：–40°C 至105°C
VSON (DLE-4)
VSON (DLF-4)
LVCMOS
LMK6C
• 集成LDO，具有强大的抗电源噪声能力：
– 在500kHz 纹波下具有-72dBc PSRR
• 启动时间：< 5ms
LMK6D
LMK6H
LMK6P
VSON (DLE-6)
VSON (DLF-6)
3.20mm x 2.50mm
2.50mm × 2.00mm
LVDS、
HCSL、
LVPECL
LMK6D
LMK6H
LMK6P
• 标准频率：
– LVCMOS (MHz)：4、8.192、12, 20、24、
25、33.333、40、50、60、65.53、74.25、
100、125 和156.25
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 差分(MHz)：51.84、100、122.88、125、
148.5、155.52、156.25、161.1328125、200
和312.5
Power
Conditioning
BAW
VDD
Fractional
Output
Divider
CLK
Output
driver
• 器件可支持1MHz 至400MHz 之间的任何频率。如
有任何频率和样片需求，请与TI 代表联系
Output/Chip
Control Logic
OE / ST / NC
Temp
Sensor
Frequency Control
Logic
GND
2 应用
• 56G/112G PAM4 时钟
• 100G/200G/400G/800G 光纤传输网络和相干光学
元件
LMK6x 简化方框图
• 网络设备、交换机、路由器、线路卡、SAN、数据
中心和基带单元(BBU)
• 符合PCIe 第1 代到第6 代标准的参考时钟
• 工业应用
• 测试和测量
• ASIC、FPGA、MCU 参考时钟
• 高性能晶体振荡器替代产品
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS826
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
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Table of Contents
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................22
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................28
10 Application and Implementation................................29
10.1 Application Information........................................... 29
10.2 Typical Application.................................................. 29
10.3 Power Supply Recommendations...........................32
10.4 Layout..................................................................... 32
11 Device and Documentation Support..........................36
11.1 Documentation Support.......................................... 36
11.2 接收文档更新通知................................................... 36
11.3 支持资源..................................................................36
11.4 Trademarks............................................................. 36
11.5 静电放电警告...........................................................36
11.6 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Ordering Information..........................................3
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Environmental Compliance.........................................6
7.4 Recommended Operating Conditions.........................6
7.5 Thermal Information....................................................7
7.6 Thermal Information....................................................7
7.7 Electrical Characteristics.............................................8
7.8 Timing Diagrams.......................................................14
7.9 Typical Characteristics..............................................15
8 Parameter Measurement Information..........................20
8.1 Device Output Configurations...................................20
9 Detailed Description......................................................22
Information.................................................................... 36
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2022) to Revision D (February 2023)
Page
• Changed the NO. column to DLE/DLF in the Pin Functions table for the DLF package release........................5
Changes from Revision B (November 2022) to Revision C (December 2022)
Page
• 将数据表状态从“预告信息”更改为“量产数据”.............................................................................................1
• 从LMK6D、LMK6H 和LMK6P 器件中删除了预发布说明..................................................................................1
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5 Device Ordering Information
Use 图5-1 and 图5-2 to understand the device nomenclature of the LMK6x orderable options.
LMK6 P A
A DLF T
156250
Product Family
Output Type
D: LVDS
H: HCSL
Packaging Method
T: Small Reel
R: Large Reel
P: LVPECL
Package Size
DLE: 3.2 mm x 2.5 mm
DLF: 2.5 mm x 2.0 mm
Sub-Family Options
E: Pin 1 – Output Enable (Active High or NC)
F: Pin 2 – Output Enable (Active High or NC)
A: Pin 1 – Stand By (Active Low)
B: Pin 2 – Stand By (Active Low)
Note: Contact TI for other options for Output Enable
and Stand By.
Voltage/Temperature Rating
A: 2.5 V - 3.3 V ±5%, -40 °C to 85 °C
B: 1.8 V ±5%, -40 °C to 85 °C
Frequency Options
156250 = 156.250 MHz
050000 = 50.000 MHz
008192 = 8.192 MHz
XXX.XXX = Custom Frequency Code;
Note: Contact TI for custom number of digits after
decimal point
图5-1. Part Number Guide: LMK6D, LMK6H, and LMK6P
Note: Contact a TI representative to pre-order specific devices. Email: ti_osc_customer_requirement@list.ti.com
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LMK6 C E
C DLF T
050000
Product Family
Packaging Method
T: Small Reel
R: Large Reel
Output Type
C: LVCMOS
Sub-Family Options
E: Pin 1 – Output Enable (Active High or NC)
Package Size
DLE: 3.2 mm x 2.5 mm
A: Pin 1 – Stand By
(Active Low)
DLF: 2.5 mm x 2.0 mm
Note: Contact TI for other options for Output Enable
and Stand By.
Voltage/Temperature Rating
C: 2.5 V - 3.3 V ±5%, -40 °C to 105 °C
D: 1.8 V ±5%, -40 °C to 105 °C
Frequency Options
125000 = 125.000 MHz
033333 = 33.333 MHz
008192 = 8.192 MHz
XXX.XXX = Custom Frequency Code
Note: Contact TI for custom number of digits after
decimal point
图5-2. Part Number Guide: LMK6C
Note: Contact a TI representative to pre-order specific devices. Email: ti_osc_customer_requirement@list.ti.com
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6 Pin Configuration and Functions
OE / ST / NC
1
2
3
6
5
4
VDD
OE / ST / NC
GND
OUTN
OUTP
图6-1. LMK6P, LMK6D, or LMK6H 6-Pin VSON (Top View)
表6-1. LMK6P, LMK6D, or LMK6H Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
DLE/DLF
Output Enable (OE) or Standby (ST) pin or No Connect (NC). See 表9-1 for
more details.
OE / ST / NC
1
I / NC
NC / I
Output Enable (OE) or Standby (ST) pin or No Connect (NC). See 表9-1 for
more details.
OE / ST / NC
2
GND
3
4
5
6
G
O
O
P
Device ground
OUTP
OUTN
VDD
Positive differential output clock
Negative differential output clock
Device power supply
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect (can be left floating).
OE / ST / NC
1
2
4
3
VDD
OUT
GND
图6-2. LMK6C 4-Pin VSON (Top View)
表6-2. LMK6C Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
DLE/DLF
Output Enable (OE) or Standby (ST) pin or No Connect (NC). See
表9-2 for more details.
OE / ST / NC
1
I / NC
GND
OUT
VDD
2
3
4
G
O
P
Device ground
LVCMOS output clock
Device power supply
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect (can be left floating).
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
3.63
UNIT
Device Supply Voltage(2)
VDD
V
V
V
V
V
Device Supply Voltage(3)
1.98
EN
Logic Input Voltage
VDD + 0.3
VDD + 0.3
VDD + 0.3
125
OUTP, OUTN
Clock Output Voltage(4)
Clock Output Voltage(5)
Junction Temperature
Storage Temperature
OUT
TJ
℃
℃
TSTG
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) For all devices with Recommended Operating Voltage of 2.5 V +/- 5% and 3.3 V +/- 5%
(3) For all devices with Recommended Operating Voltage of 1.8 V +/- 5%
(4) For all differential outputs - LMK6D, LMK6H, and LMK6P.
(5) For single ended outputs - LMK6C.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Environmental Compliance
VALUE
UNIT
Mechanical Shock Resistance
Mechanical Vibration Resistance
Moisture Sensitivity Level (MSL)
MIL-STD-883F, Method 2002, Condition A
MIL-STD-883F, Method 2026, Condition C
MIL-STD-883F, Method 2007, Condition A
1500
10
g
g
g
20
MSL1
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX
UNIT
V
Device Supply Voltage(1)
VDD
1.8
1.9
3.5
85
Device Supply Voltage(2)
2.37
–40
–40
2.5, 3.3
V
Ambient temperature(3)
°C
°C
°C
ms
TA
Ambient temperature(4)
105
125
100
TJ
Junction temperature
tRAMP
VDD power-up ramp time(1) (2)
0.1
(1) For all devices with Recommended Operating Voltage of 1.8V +/- 5%
(2) For all devices with Recommended Operating Voltage of 2.5V +/- 5% and 3.3V +/- 5%
(3) For all differential outputs - LMK6D, LMK6H and LMK6P.
(4) For single-ended output - LMK6C.
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7.5 Thermal Information
LMK6D/H/P
THERMAL METRIC(1)
DLE (VSON)
6 PINS
101.2
58.6
DLF (VSON)
6 PINS
107.9
70.1
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
31.3
39.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
2.3
31.1
39.2
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information
LMK6C
THERMAL METRIC(1)
DLE (VSON)
4 PINS
124.8
61.2
DLF (VSON)
4 PINS
128.1
73.2
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
42.5
39.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.8
2.4
42.3
39.5
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.7 Electrical Characteristics
over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Consumption Characteristics
100 MHz
65
69
67
76
88
61
66
64
73
84
65
69
67
76
88
58
62
60
69
77
54
58
56
65
76
52
56
54
63
74
45
55
61
44
50
56
6
82
87
85
95
108
79
83
82
91
104
82
87
86
96
108
75
80
78
88
97
71
75
74
84
96
68
72
71
80
92
62
71
77
59
65
72
13
67
67
66
56
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
156.25 MHz
200 MHz
Device power consumption
(LVPECL,VDD = 2.5 V/3.3 V, excluding
load current)
312.5 MHz
400 MHz
100 MHz
156.25 MHz
200 MHz
Device power consumption
(LVPECL,VDD = 1.8 V, excluding load
current)
312.5 MHz
400 MHz
100 MHz
156.25 MHz
Device power consumption
(HCSL,VDD = 2.5 V/3.3 V, excluding load 200 MHz
current)
312.5 MHz
400 MHz
100 MHz
156.25 MHz
Device power consumption
(HCSL,VDD = 1.8 V, excluding load
current)
200 MHz
IDD
312.5 MHz
400 MHz
100 MHz
156.25 MHz
Device power consumption
(LVDS,VDD = 2.5 V/3.3 V, excluding load 200 MHz
current)
312.5 MHz
400 MHz
100 MHz
156.25 MHz
Device power consumption
(LVDS,VDD = 1.8 V, excluding load
current)
200 MHz
312.5 MHz
400 MHz
100 MHz
Device power consumption
(LVCMOS,VDD = 2.5 V / 3.3 V, with
load)
156.25 MHz
200 MHz
100 MHz
Device power consumption
(LVCMOS,VDD = 1.8 V, with load)
156.25 MHz
200 MHz
IDD-STBY Device standby current
ST (Standby) = GND
OE = GND, LVPECL mode, VDD = 3.3 V
OE = GND, HCSL mode, VDD = 3.3 V
OE = GND, LVDS mode, VDD = 3.3 V
OE = GND, LVCMOS mode, VDD = 3.3 V
48
49
49
40
Device current with output disabled (100
MHz)
IDD-PD
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL Output Characteristics
Fout
Output frequency
1
525
450
280
650
450
400
765
660
470
950
750
MHz
mV
mV
mV
mV
mV
Vpp
V
AC coupled, VDD = 3.3 V
645
555
375
800
600
AC coupled, VDD = 2.5 V
VOD
AC coupled, VDD = 1.8 V
Output voltage swing (VOH –VOL
)
DC coupled, VDD = 2.5 V/ 3.3 V(1)
DC coupled, VDD = 1.8 V(1)
VOD,DIFF Differential output peak-peak swing
2 × |VOD|
VDD = 3.3 V(1)
VDD = 2.5 V(1)
VDD = 1.8 V(1)
1.5
0.825
0.45
1.6
0.9
0.5
1.7
0.975
0.55
VOS
Output common-mode voltage
Output rise/fall time
V
V
20% to 80% of VOD,DIFF, VDD = 2.5 V/ 3.3
V
120
120
50
200
200
55
ps
ps
%
tR/tF
20% to 80% of VOD,DIFF, VDD = 1.8 V
VDD = 2.5 V/ 3.3 V, measured between
50% points on the waveform
45
45
ODC
Output duty cycle
VDD = 1.8 V, measured between 50%
points on the waveform
50
55
%
LVDS Output Characteristics
Fout
VOD
Output frequency
1
400
450
MHz
mV
Vpp
V
Under LVDS load condition
250
350
Output voltage swing (VOH –VOL
)
VOD,DIFF Differential output peak-peak swing
2 × |VOD|
VDD = 2.5 V/3.3 V
VDD = 1.8 V
1.025
0.80
1.2
0.9
1.375
1.0
VOS
Output common-mode voltage
Output rise/fall time
V
20% to 80% of VOD,DIFF, VDD = 2.5 V/3.3
V
150
150
50
250
250
55
ps
ps
%
tR/tF
20% to 80% of VOD,DIFF, VDD = 1.8 V
VDD = 2.5 V/3.3 V, measured between
50% points on the waveform
45
45
ODC
Output duty cycle
VDD = 1.8 V, measured between 50%
points on the waveform
50
55
%
HCSL Output Characteristics
Fout
Output frequency
1
650
400
850
660
150
150
MHz
mV
mV
mV
mV
V
DC coupled, 50 Ω to ground, VDD = 2.5
750
560
0
V/ 3.3 V
VOH
Output high voltage
460
DC coupled, 50 Ω to ground, VDD = 1.8 V
DC coupled, 50 Ω to ground, VDD = 2.5
V/ 3.3 V
–150
–150
VOL
Output low voltage
0
DC coupled, 50 Ω to ground, VDD = 1.8 V
2 × |VOH
VOD,DIFF Differential output peak-peak swing
–VOL
|
VDD = 3.3 V / 2.5 V, fout = 100 MHz
VDD = 1.8 V, fout = 100 MHz
0.2
0.35
0.50
0.40
Vpp
Vpp
Vcross
Absolute crossing point voltage
0.15
0.275
Vcross-
VDD = 3.3 V / 2.5 V / 1.8 V, fout = 100
MHz
Absolute crossing point voltage variation
0.14
V
delta
50 Ω to ground; DC coupled load;
measured slew rate in ±150 mV from
center.
dV/dt
Output slew rate
2
12
V/ns
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
Output slew rate variation
Output duty cycle
TEST CONDITIONS
MIN
45
1
TYP
MAX
UNIT
%
20
ΔdV/dt
ODC
50
55
%
LVCMOS Output Characteristics
Fout
Output frequency
200
0.36
0.5
MHz
V
IOL = 3.6 mA, VDD = 1.8 V
IOL = 5.0 mA, VDD = 2.5 V
IOL = 6.6 mA, VDD = 3.3 V
IOH = 3.6 mA, VDD = 1.8 V
IOH = 5.0 mA, VDD = 2.5 V
IOH = 6.6 mA, VDD = 3.3 V
20% to 80% of VOH –VOL, CL = 2 pF
VOL
Output low voltage
V
0.66
V
1.44
2
V
VOH
Output high voltage
V
2.64
V
tR/tF
ODC
Rout
Output rise/fall time
Output duty cycle
Output impedance
0.5
50
50
1
55
60
15
30
ns
%
45
40
OE = HIGH
Ω
pF
pF
Fout > 50 MHz(3)
Fout < 50 MHz(3)
CL
Maximum capacitive load
Function Pin Input Characteristics (OE/ST Pin)
VIL
VIH
IIL
Input low voltage
Input high voltage
Input low current
Input high current
Input capacitance
0.6
40
V
1.3
V
OE = GND
OE = VDD
µA
µA
pF
–40
IIH
CIN
2
LVDS, HCSL and LVPECL Frequency Tolerance
Inclusive of: solder shift, initial tolerance,
variation over –40℃to 85℃, variation
over rated supply voltage range, and 10
year aging at 25℃.
25
20
ppm
ppm
–25
–20
FT
Total frequency stability
Inclusive of: solder shift, initial tolerance,
variation over –40℃to 85℃, variation
over supply voltage range.
LVCMOS Frequency Tolerance
Inclusive of: solder shift, initial tolerance,
variation over –40℃to 105℃, variation
over rated supply voltage range, and 10
year aging at 25℃.
25
20
ppm
ppm
–25
–20
FT
Total frequency stability
Inclusive of: solder shift, initial tolerance,
variation over –40℃to 105℃, variation
over rated supply voltage range.
Differential Output PSRR Characteristics
Sine wave at 50 kHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fs/mV
–71
–71
–72
–70
–64
–64
–67
–68
4
Spur induced by 50 mV power supply
ripple at 156.25 MHz output, VDD = 2.5
V/3.3 V, No power supply decoupling
capacitor
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
PSRR
Sine wave at 50 kHz
Spur induced by 50 mV power supply
ripple at 156.25 MHz output, VDD = 1.8
V, no power supply decoupling capacitor
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
PSRR
PSRR
Jitter sensitivity to power supply ripple
100 kHz sine wave ripple, 3.3 V supply(2)
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS PSRR Characteristics
Sine wave at 50 kHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fs/mV
–72
–71
–70
–69
–50
–50
–52
–55
10
Spur induced by 50 mV power supply
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
PSRR
ripple at 50 MHz output, VDD = 2.5 V/3.3
V, no power supply decoupling capacitor
Sine wave at 50 kHz
Spur induced by 50 mV power supply
ripple at 50 MHz output, VDD = 1.8 V, no
power supply decoupling capacitor
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
PSRR
PSRR
Jitter sensitivity to power supply ripple;
100 kHz sine wave ripple, 3.3 V supply(2)
Power-On Characteristics
Time elapsed from 0.95 x VDD until
output is enabled and output is within
specification
tSTART_UP Start-up Time
5
ms
Time elapsed from OE = VIH until output
is enabled and output is within
specification, Fout > 10 MHz
tOE-EN
Output enable time
Output disable time
25
1
µs
µs
Time elapsed from OE = VIL until output is
disabled, Fout > 10 MHz
tOE-DIS
LVPECL - Clock Output Jitter
RJ
RMS jitter (integration BW: 12 kHz to 20
MHz)
Fout = 156.25 MHz
Fout = 156.25 MHz.
Fout = 312.5 MHz
Fout = 312.5 MHz.
100
125
fs
PN1k
PN10k
PN100k
PN1M
PN10M
RJ
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase Noise at 1 MHz offset
Phase Noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–95
–127
–146
–156
–158
RMS jitter (integration BW: 12 kHz to 20
MHz)
100
125
fs
PN1k
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
–89
–121
–140
–150
–154
125
PN10k
PN100k
PN1M
PN10M
Fout = 100 MHz
170
125
125
150
150
135
Fout = 125 MHz
100
fs
Fout = 155.52 MHz
Fout = 161.1328125 MHz
Fout = 200 MHz
100
fs
RMS jitter (integration BW: 12 kHz to 20
MHz)
RJ
110
fs
120
fs
Fout = 400 MHz
100
fs
RPeriodJITT
,RMS
RMS period jitter
1.7
13
ps
ps
Fout ≥25 MHz
Fout ≥25 MHz
RJITT,PK-
PK
Peak-peak period jitter
LVDS - Clock Output Jitter
RJ RMS jitter (integration BW: 12 kHz to 20
MHz)
Fout = 156.25 MHz
100
125
fs
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PN1k
PN10k
PN100k
PN1M
PN10M
RJ
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–95
–128
–146
–156
–156.5
Fout = 156.25 MHz
RMS jitter (integration BW: 12 kHz to 20
MHz)
Fout = 312.5 MHz
Fout = 312.5 MHz.
100
125
fs
PN1k
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
–89
–122
–139
–150
–153.5
140
PN10k
PN100k
PN1M
PN10M
Fout = 100 MHz
170
125
140
160
150
135
Fout = 125 MHz
110
fs
Fout = 155.52 MHz
Fout = 161.1328125 MHz
Fout = 200 MHz
105
fs
RMS jitter (integration BW: 12 kHz to 20
MHz)
RJ
125
fs
125
fs
Fout = 400 MHz
100
fs
RPeriodJIT
RMS period jitter
1.6
13
ps
ps
Fout ≥25 MHz
Fout ≥25 MHz
T,RMS
RJITT,PK-
Peak-peak period jitter
PK
HCSL - Clock Output Jitter
PCIe Gen 1 common clock jitter (jitter limit
= 86 ps)
JPCIe1-cc
0.146
0.447
0.103
0.135
0.029
0.033
0.029
0.033
0.007
0.007
0.007
0.009
6.4
6.99
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
fs
JPCIe1-
PCIe Gen 1 SRNS jitter
SRNS
PCIe Gen 2 common clock jitter (jitter limit
= 3 ps)
JPCIe2-cc
0.554
0.56
JPCIe2-
PCIe Gen 2 SRNS jitter
SRNS
PCIe Gen 3 common clock jitter (jitter limit
= 1 ps)
JPCIe3-cc
0.164
0.180
0.164
0.180
0.070
0.074
0.042
0.052
125
JPCIe3-
PCIe Gen 3 SRNS jitter
SRNS
Fout = 100 MHz
PCIe Gen 4 common clock jitter (jitter limit
= 500 fs)
JPCIe4-cc
JPCIe4-
PCIe Gen 4 SRNS jitter
SRNS
PCIe Gen 5 common clock jitter (jitter limit
= 150 fs)
JPCIe5-cc
JPCIe5-
PCIe Gen 5 SRNS jitter
SRNS
PCIe Gen 6 common clock jitter (jitter limit
= 100 fs)
JPCIe6-cc
JPCIe6-
PCIe Gen 6 SRNS jitter
SRNS
RJ
RMS jitter (integration BW: 12 kHz to 20
MHz)
Fout = 156.25 MHz
100
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PN1k
PN10k
PN100k
PN1M
PN10M
RJ
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–95
–127
–146
–156
–158
Fout = 156.25 MHz.
RMS jitter (integration BW: 12 kHz to 20
MHz)
Fout = 312.5 MHz
Fout = 312.5 MHz.
100
125
fs
PN1k
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
–89
–121
–140
–150
–154
125
PN10k
PN100k
PN1M
PN10M
Fout = 100 MHz
170
125
125
150
150
135
Fout = 125 MHz
100
fs
Fout = 155.52 MHz
Fout = 161.1328125 MHz
Fout = 200 MHz
100
fs
RMS jitter (integration BW: 12 kHz to 20
MHz)
RJ
110
fs
120
fs
Fout = 400 MHz
100
fs
RPeriodJIT
RMS period jitter
1.7
13
ps
ps
Fout ≥25 MHz
Fout ≥25 MHz
T,RMS
RJITT,PK-
Peak-peak period jitter
PK
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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V,
LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS - Clock Output Jitter
RMS jitter (integration BW: 12 kHz to 20
MHz)
RJ
Fout = 156.25 MHz
0.25
0.5
ps
PN1k
Phase noise at 1 kHz offset
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
–100
–128
–143
–150
–152
0.25
0.25
0.25
0.5
PN10k
PN100k
PN1M
PN10M
Fout = 156.25 MHz
Fout = 24 MHz
Fout = 25 MHz
Fout = 33.33 MHz
Fout = 40 MHz
Fout = 50 MHz
Fout = 66.66 MHz
Fout = 74.25 MHz
Fout = 78 MHz
Fout = 100 MHz
Fout = 125 MHz
.5
.5
RMS jitter (integration BW: 12 kHz to 5
MHz)
ps
1
ps
1
ps
0.4
1
ps
RJ
0.5
1
ps
RMS jitter (integration BW: 12 kHz to 20
MHz)
0.3
0.5
0.5
0.5
0.5
ps
0.35
0.35
0.35
ps
ps
ps
RPeriodJIT
RMS period jitter
1.5
13
ps
ps
Fout ≥25 MHz
Fout ≥25 MHz
T,RMS
RJITT,PK-
Peak-peak period jitter
PK
(1) DC Load condition
(2) Measured using TI LMK6x Evaluation Module;
(3) Refer to the Application Curves section for Rise time and fall time details for different capacitor load values.
(4) The Jitter specifications are based on design and characterization
7.8 Timing Diagrams
OUTx_N
VOH
VOD = VOH - VOL
VOL
OUTx_P
80%
0 V
20%
VOUT-DIFF = 2 × VOD
tR
tF
图7-1. Differential Output Voltage and Rise/Fall Time
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80%
OUT_REFx/2
20%
VOUT,SE
tR
tF
图7-2. Single-Ended Output Voltage and Rise/Fall Time
7.9 Typical Characteristics
50
54
51
48
45
42
39
36
33
30
VDD = 1.8V
Output Format = LVCMOS
VDD = 2.5 V
OUTPUT FORMAT = LVCMOS
47.5
45
42.5
40
37.5
35
-40 o
25 o
105 o
C
C
C
-40 o
25 o
105 o
C
C
C
32.5
30
20
40
60
80
100
120
140
160
20
40
60
80
100
120
140
160
Frequency (MHz)
Frequency (MHz)
图7-3. Current Consumption vs Frequency
图7-4. Current Consumption vs Frequency
(LVCMOS, 1.8 V)
(LVCMOS, 2.5 V)
57
54
51
48
45
42
39
36
33
100
90
80
70
60
50
-40 o
25 o
85 o
C
C
C
VDD = 3.3V
OUTPUT FORMAT = LVCMOS
VDD = 1.8 V
OUTPUT FORMAT = HCSL
-40 o
C
C
C
25 o
105 o
100 125 150 175 200 225 250 275 300 325 350 375 400
20
40
60
80
100
120
140
160
Frequency (MHz)
Frequency (MHz)
图7-6. Current Consumption vs Frequency
图7-5. Current Consumption vs Frequency
(HCSL, 1.8 V)
(LVCMOS, 3.3 V)
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7.9 Typical Characteristics (continued)
100
90
80
70
60
50
VDD = 3.3 V
OUTPUT FORMAT = HCSL
-40 o
C
25 o
85 o
C
C
100 125 150 175 200 225 250 275 300 325 350 375 400
Frequency (MHz)
图7-7. Current Consumption vs Frequency
图7-8. Current Consumption vs Frequency
(HCSL, 2.5 V)
(HCSL, 3.3 V)
100
100
VDD = 2.5 V
OUTPUT FORMAT = LVPECL
VDD = 1.8 V
OUTPUT FORMAT = LVPECL
90
90
80
70
60
50
80
70
60
50
-40 o
C
-40 o
C
25 o
85 o
C
C
25 o
85 o
C
C
50
100
150
200
250
300
350
400
100 125 150 175 200 225 250 275 300 325 350 375 400
Frequency (MHz)
Frequency (MHz)
图7-9. Current Consumption vs Frequency
图7-10. Current Consumption vs Frequency
(LVPECL, 1.8 V)
(LVPECL, 2.5 V)
100
100
-40 o
C
VDD = 1.8 V
OUTPUT FORMAT = LVDS
VDD = 3.3 V
OUTPUT FORMAT = LVPECL
25 o
85 o
C
C
90
80
70
60
50
90
80
70
60
50
-40 o
C
25 o
85 o
C
C
100 125 150 175 200 225 250 275 300 325 350 375 400
100 125 150 175 200 225 250 275 300 325 350 375 400
Frequency (MHz)
Frequency (MHz)
图7-11. Current Consumption vs Frequency
图7-12. Current Consumption vs Frequency
(LVPECL, 3.3 V)
(LVDS, 1.8 V)
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7.9 Typical Characteristics (continued)
100
100
90
80
70
60
50
VDD = 3.3 V
OUTPUT FORMAT = LVDS
VDD = 2.5 V
OUTPUT FORMAT = LVDS
90
80
70
60
50
-40 o
C
-40 o
C
25 o
85 o
C
C
25 o
85 o
C
C
100 125 150 175 200 225 250 275 300 325 350 375 400
100 125 150 175 200 225 250 275 300 325 350 375 400
Frequency (MHz)
Frequency (MHz)
图7-13. Current Consumption vs Frequency
图7-14. Current Consumption vs Frequency
(LVDS, 2.5 V)
(LVDS, 3.3 V)
160
155
150
145
140
135
130
125
120
115
110
105
100
95
160
155
150
145
140
135
130
125
120
115
110
105
100
95
90
90
100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200
100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200
Frequency (MHz)
Frequency (MHz)
图7-15. RMS Jitter vs Frequency (100 MHz to 200 MHz) for
图7-16. RMS Jitter vs Frequency (100 MHz to 200 MHz) for
LVPECL, HCSL; TYPICAL 3.3 V, 25°C
LVDS; TYPICAL 3.3 V, 25°C
170
165
160
155
150
145
140
135
130
125
120
115
110
105
100
95
90
85
80
200 205 210 215 220 225 230 235 240 245 250 255 260 265 270 275 280 285 290 295 300
Frequency (MHz)
图7-17. RMS Jitter vs Frequency (200 MHz to 300 MHz) for
图7-18. RMS Jitter vs Frequency (200 MHz to 300 MHz) for
LVPECL, HCSL; TYPICAL 3.3 V, 25°C
LVDS; TYPICAL 3.3 V, 25°C
160
155
150
145
140
135
130
125
120
115
110
105
100
95
160
155
150
145
140
135
130
125
120
115
110
105
100
95
90
90
85
85
80
80
300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400
300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400
Frequency (MHz)
Frequency (MHz)
图7-19. RMS Jitter vs Frequency (300 MHz to 400 MHz) for
图7-20. RMS Jitter vs Frequency (300 MHz to 400 MHz) for
LVPECL, HCSL; TYPICAL 3.3 V, 25°C
LVDS; TYPICAL 3.3 V, 25°C
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7.9 Typical Characteristics (continued)
400
380
360
340
320
300
280
260
240
220
200
180
160
140
120
100
400
380
360
340
320
300
280
260
240
220
200
180
160
140
120
100
40
45
50
55
60
65
70
75
80
85
90
95
100
40
45
50
55
60
65
70
75
80
85
90
95
100
Frequency (MHz)
Frequency (MHz)
图7-21. RMS Jitter vs Frequency (Below 100 MHz) for LVPECL,
图7-22. RMS Jitter vs Frequency (Below 100 MHz) for LVDS;
HCSL; TYPICAL 3.3 V, 25°C
TYPICAL 3.3 V, 25°C
400
380
360
340
320
300
280
260
240
220
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
200
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200
Frequency (MHz)
Frequency (MHz)
图7-24. RMS Jitter vs Frequency ( 10 MHz - 100 MHz) for
图7-23. RMS Jitter vs Frequency ( 100 MHz - 200 MHz) for
LVCMOS; TYPICAL 3.3 V, 25°C
LVCMOS; TYPICAL 3.3 V, 25°C
55
55
1.8 V
2.5 V
1.8 V
54
54
2.5 V
3.3 V
3.3 V
53
52
51
50
49
48
47
46
45
53
52
51
50
49
48
47
46
45
25
50
75
100
125
150
175
200
-40
-20
0
20
40
60
80
100
Frequency (MHz)
Temperature (oC)
图7-25. Duty Cycle (%) vs Frequency vs Power Supply; 25°C
图7-26. Duty Cycle (%) vs Temperature vs Power Supply; 50-
MHz Frequency
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7.9 Typical Characteristics (continued)
57.5
-40 o
25 o
105 o
C
C
C
55
52.5
50
47.5
45
25
50
75
100
125
150
175
200
Frequency (MHz)
图7-27. Duty Cycle (%) vs Frequency Over Temperature Range for LVCMOS; 3.3 V
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8 Parameter Measurement Information
8.1 Device Output Configurations
High-impedance probe
LMK6C Device
Oscilloscope
2 pF
图8-1. LMK6C Output Test Configuration
Phase Noise
Analyzer
LMK6C Device
图8-2. LMK6C Output Phase Noise Test Configuration
Oscilloscope
(50- inputs)
LMK6D Device
图8-3. LMK6D Output Test Configuration
Phase Noise
Analyzer
LMK6D Device
Balun
图8-4. LMK6D Output Phase Noise Configuration
Oscilloscope
(50- inputs)
LMK6P Device
Rp
Rp
图8-5. LMK6P Output Test Configuration
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Phase Noise
Analyzer
LMK6P Device
Balun
Rp
Rp
图8-6. LMK6P Output Phase Noise Configuration
表8-1. LMK6P Output Test configuration and Phase Noise Configuration Rp Values
SUPPLY (V)
Rp (Ω)
207.5
112.5
83.3
3.3 V
2.5 V
1.8 V
Oscilloscope
(50- inputs)
LMK6H Device
图8-7. LMK6H Output Test Configuration
Phase Noise
Analyzer
Clock
Buffer
LMK6H Device
50
50
图8-8. LMK6H Output Phase Noise Configuration
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9 Detailed Description
9.1 Overview
The LMK6x is a fixed-frequency BAW based oscillator that can provide ultra-low jitter for both differential and
single-ended output types.
9.2 Functional Block Diagram
Power
Conditioning
BAW
VDD
CLK_P
CLK_N
Fractional
Output
Divider
Output
driver
GND
Temp
Sensor
Frequency Control
Logic
Output/Chip
Control Logic
OE / ST / NC
9.3 Feature Description
9.3.1 Bulk Acoustic Wave (BAW)
TI’s BAW resonator technology uses piezoelectric transduction to generate high-Q resonance at 2.5 GHz. The
resonator is defined by the quadrilateral area overlaid by top and bottom electrodes. Alternating high- and low-
acoustic impedance layers form acoustic mirrors beneath the resonant body to prevent acoustic energy leakage
into the substrate. Furthermore, these acoustic mirrors are also placed on top of the resonator stack to protect
the device from contamination and minimize energy leakage into the package materials. This unique dual-Bragg
acoustic resonator (DBAR) allows efficient excitation without the need of costly vacuum cavities around the
resonator. As a result, TI’s BAW resonator is immune to frequency drift caused by adsorption of surface
contaminants and can be directly placed in a non-hermetic plastic package with the oscillator IC in small
standard oscillator footprints. Refer to BAW for more details on BAW technology.
9.3.2 Device Block-Level Description
The device contains a BAW oscillator, a Fractional Output Divider (FOD), and output driver, which together
generates a pre-programmed output frequency. Temperature variations of oscillation frequency are continuously
monitored by internal precision temperature sensor and provided as input to the frequency control logic block.
Using this frequency control logic block, frequency corrections are performed internally for maintaining the output
frequency within ±25 ppm across temperature range and aging. The output driver is capable of providing both
single-ended LVCMOS and differential LVPECL, LVDS, and HCSL output formats. The device contains an
internal LDO which reduces the power supply noise, resulting in low noise clock output.
9.3.3 Function Pin(s)
Pin 1 on the LMK6C and pin 1 or pin 2 on the LMK6P, LMK6D, and LMK6H are the function pins which have
multiple functions based on the orderable part number. The function can be used as Output Enable (OE), Stand
By (ST) or No Connect (NC). Options for both Active High and Active Low are available for OE and ST. Contact
TI for Active Low options. 表9-1 lists the functions of pin 1 and pin 2 for differential output 6-pin packages and 表
9-2 lists the functions of pin 1 for single-ended outputs.
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表9-1. Function Pin Descriptions for 6-Pin Packages (LMK6D, LMK6H, LMK6P)
ORDERABLE OPTION
PIN DESCRIPTION
OUTPUT FUNCTION
OTHER FUNCTIONAL PIN
CONFIGURATION
HIGH or No Connect : Output
active at Specified Frequency
Pin 2 can be left floating or
grounded
E (Pin 1)
Output Enable (Active High / NC) LOW : Output disabled, high
impedance; current consumption
is given by IDD-PD
HIGH or No Connect : Output
active at Specified Frequency
Pin 1 can be left floating or
grounded
F (Pin 2)
A (Pin 1)
B (Pin 2)
Output Enable (Active High / NC) LOW : Output disabled, high
impedance; current consumption
is given by IDD-PD
LOW : High Impedance; standby Pin 2 can be left open or
mode; current consumption is
given by standby current IDD-STBY
HIGH or No Connect : Output
active at Specified Frequency
grounded
Standby (Active Low)
Standby (Active Low)
LOW : High Impedance; standby Pin 1 can be left open or
mode; current consumption is
given by standby current IDD-STBY
HIGH or No Connect : Output
active at Specified Frequency
grounded
表9-2. Function Pin Descriptions for 4-Pin Packages (LMK6C)
ORDERABLE OPTION
PIN DESCRIPTION
OUTPUT FUNCTION
HIGH or No Connect : Output active at
Specified Frequency
LOW : Output disabled, high impedance;
current consumption is given by IDD-PD
E (Pin 1)
Output Enable (Active High / NC)
LOW : High Impedance; standby mode;
current consumption is given by standby
current IDD-STBY
A (Pin 1)
Standby (Active Low)
HIGH or No Connect : Output active at
Specified Frequency
In standby mode, all blocks are powered down to provide a maximum current consumption savings equivalent to
the standby current provided in the Current Consumption Characteristics portion of the Electrical Characteristics
table. The return to the output clock active time corresponds to same as the initial start-up time.
The Function Pin is driven internally with resistance >100 kΩ.
9.3.4 Clock Output Interfacing and Termination
These figures show the recommended output interfacing and termination circuits.
LVCMOS
Receiver
LMK6C Device
图9-1. LMK6C Output to LVCMOS Receiver
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LVDS
Receiver
LMK6D Device
100 Ω
图9-2. LMK6D Output DC-Coupled to LVDS Receiver With Internal Termination/Biasing
LVDS
Receiver
LMK6D Device
100 Ω
图9-3. LMK6D Output AC Coupled to LVDS Receiver With Internal Termination/Biasing
Vdd
R1
R1
LVPECL
Receiver
LMK6P Device
R2
R2
图9-4. LMK6P Output DC-Coupled to LVPECL Receiver With External Termination/Biasing
(T-Network)
表9-3. LMK6P T-Network DC-Coupled Resistor Values
SUPPLY (V)
R1 (Ω)
R2 (Ω)
82
3.3
2.5
1.8
133
250
62.5
56.5
450
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Vdd
R1
R1
LVPECL
Receiver
LMK6P Device
R2
R2
Rp
Rp
图9-5. LMK6P Output AC-Coupled to LVPECL Receiver With External Termination/Biasing
(T-Network)
表9-4. LMK6P T-Network AC-Coupled Resistor Values
SUPPLY (V)
Rp (Ω)
207.5
112.5
83.3
R1 (Ω)
R2 (Ω)
82
3.3
2.5
1.8
133
250
62.5
56.6
450
LVPECL
Receiver
LMK6P Device
R1
R1
R2
图9-6. LMK6P Output DC-Coupled to LVPECL Receiver With External Termination/Biasing
(Y-Network)
表9-5. LMK6P Y-Network DC-Coupled Resistor Values
SUPPLY (V)
R1 (Ω)
R2 (Ω)
78.8
3.3
2.5
1.8
50
50
31.3
50
16.7
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LVPECL
Receiver
LMK6P Device
R1
R1
Rp
Rp
R2
图9-7. LMK6P Output AC-Coupled to LVPECL Receiver With External Termination/Biasing
(Y-Network)
表9-6. LMK6P Y-Network AC-Coupled Resistor Values
SUPPLY (V)
Rp (Ω)
207.5
112.5
83.3
R1 (Ω)
R2 (Ω)
78.8
3.3
2.5
1.8
50
50
31.3
50
16.7
HCSL
Receiver
LMK6H Device
50Ω
50Ω
图9-8. LMK6H Output to HCSL Receiver With External Termination
HCSL
Receiver
LMK6H Device
50Ω
50Ω
图9-9. LMK6H Output AC-Coupled to HCSL Receiver With External Termination
9.3.5 Temperature Stability
图 9-10 shows the frequency variation of the LMK6x differential output oscillator over the temperature range of
–40°C to 85°C for total of 60 units. 图 9-11 shows the frequency variation of the LMK6C single-ended output
oscillator over the operating temperature range of –40°C to 105°C. These plots represent the typical
temperature stability of the device, remaining below ±10 ppm. The devices are soldered onto the evaluation
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board as per the standard soldering profile and frequency variation measurements are carried out. The output
frequency is 156.25 MHz for these tests.
25
20
15
10
5
0
-5
-10
-15
-20
-25
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (oC)
图9-10. Frequency Change Over Temperature (LMK6x Differential Output Device)
25
20
15
10
5
0
-5
-10
-15
-20
-25
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
Temperature (OC)
图9-11. Frequency Change Over Temperature (LMK6C Single-Ended Output Device)
9.3.6 Mechanical Robustness
For reference oscillators, vibration and shock are common causes for increased phase noise and jitter,
frequency shift and spikes, or even physical damages to the resonator and the package. Compared to quartz
crystals, the BAW resonator is more immune to vibration and shock due to its orders of magnitude, smaller
mass, and higher frequency, which means force applied to the device from acceleration is much smaller due to
smaller mass.
图9-12 shows the LMK6x BAW oscillator vibration performance. In this test, the LMK6x oscillator mounted on an
EVM is subject to 10g acceleration force, ranging from 50 Hz to 2 kHz in x, y, and z-axis. Phase noise trace with
spur due to vibration is captured using Keysight E5052B and frequency deviation is calculated from the spur
power. Then the frequency deviation is converted to ppb by noting the carrier frequency and normalized to
ppb/g. Finally, the RMS sum of ppb/g along all three axes is reported as the Vibration sensitivity in ppb/g. LMK6x
performance under vibration is approximately 2 ppb/g while most quartz oscillators best case is 3 ppb/g and
worse can be above 10 ppb/g.
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10
9
8
7
6
5
4
3
2
1
0
50
60 70 80 90 100
200
300
400
500 600 700 800
1000
2000
Vibration Frequency (Hz)
图9-12. LMK6X BAW Oscillator Vibration Performance
9.4 Device Functional Modes
The LMK6x BAW Oscillator is a fixed output frequency device and does not require any programming. The
device pin 1 (and pin 2 for a 6-pin device) has different functions. See the Function Pin(s) section for more
information on the function pins.
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LMK6x is high-performance, fixed-frequency oscillator that can be used as a reference clock. The product
family supports any output frequency between 1 MHz to 400 MHz for differential LMK6D, LMK6H, LMK6P or 1
MHz to 200 MHz for singled-ended LVCMOS clock output types, and 1.8-V or 2.5-V through 3.3-V supply rails.
10.2 Typical Application
For reference schematic implementation for LMK6x family of oscillators, refer to the LMK6EVM User's Guide for
bypass capacitor and AC-coupling capacitor value recommendations. Refer to the Clock Output Interfacing and
Termination section for output clock required termination and biasing.
图 10-1 shows a typical application example. The LMK6D differential oscillator is used as an input to the LVDS
buffer input in this example.
Output
driver
CLK_ P
CLK_ N
Power
Conditioning
VDD
OE
100
1 μF
GND
Output/Chip
Control Logic
ASIC / FPGA / PHY
LMK6D Differential Oscillator - 156.25 MHz
图10-1. Application Example
10.2.1 Design Requirements
The LMK6x is a fixed-frequency oscillator with no programming needed. Make sure to follow the recommended
termination options as described in the Clock Output Interfacing and Termination section closely. Refer to the
Function Pin(s) section to understand the pin 1 and pin 2 functions, and order the part number as per your
requirements for Output Enable (OE), Standby (ST) options.
10.2.2 Detailed Design Procedure
The LMK6x has three different options for differential output which are LVDS, LVPECL, HCSL type and one
LVCMOS single-ended output type. For designing with the any of the oscillator output type in actual system, use
the proper AC or DC termination based on the application requirement. Refer to the Clock Output Interfacing and
Termination section for the details of all the AC and DC termination schemes and use the appropriate option.
The figures in this section have all the AC and DC coupling options with the termination resistor values. The
LMK6x has an integrated LDO and has excellent PSRR performance as shown in the Electrical Characteristics
table. Refer to the LMK6EVM for the reference layout recommendation while designing the LMK6x BAW
oscillator.
For the Function Pin 1 of LMK6C, connect typical 10-kΩ or less resistor to VDD for driving the OE pin High.
Note this pin can be left open if you do not want to use pullup resistor as the device has > 100-kΩinternal pullup
resistor. For driving the OE pin to Low, use the typical 10 kΩ or less resistor as a pulldown resistor. For the
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Function Pin 1 or Functional Pin 2 for LMK6D, LMK6H, LMK6P, you can use the similar approach described for
LMK6C.
10.2.3 Application Curves
The LMK6C LVCMOS output connects to different load capacitances based on the actual application use case in
a system. With the different load capacitance, the rise time / fall time varies for the specific output frequency. The
following graphs shows the Rise / Fall time for load capacitance of 2.2 pF, 4.7 pF, 10 pF, 15 pF and 22 pF for
temperature range from –40°C to 105°C.
3000
2700
2400
2100
0 pF
2.2 pF
1800
4.7 pF
10 pF
1500
15 pF
22 pF
1200
900
600
300
0
-40
-20
0
20
40
60
80
100
Temperature (oC)
图10-2. Rise / Fall time (ps) vs Temperature for 25-MHz Output Frequency, 3.3-V Supply
3000
2700
2400
0 pF
2.2 pF
2100
4.7 pF
10 pF
15 pF
22 pF
1800
1500
1200
900
600
300
0
-40
-20
0
20
40
60
80
100
Temperature (oC)
图10-3. Rise / Fall time (ps) vs Temperature for 50-MHz Output Frequency, 3.3-V Supply
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3000
2700
2400
2100
1800
1500
1200
900
0 pF
2.2 pF
4.7 pF
600
300
0
-40
-20
0
20
40
60
80
100
Temperature (oC)
图10-4. Rise / Fall time (ps) vs Temperature for 100-MHz Output Frequency, 3.3-V Supply
3000
2700
2400
2100
1800
1500
1200
900
600
300
0
0 pF
2.2 pF
4.7 pF
-40
-20
0
20
40
60
80
100
Temperature (oC)
图10-5. Rise / Fall time (ps) vs Temperature for 200-MHz Output Frequency, 3.3-V Supply
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3000
2700
2400
2100
1800
0 pF
2.2 pF
4.7 pF
10 pF
15 pF
22 pF
Temp = 25oC
Frequency = 50 MHz
1500
1200
900
600
300
0
1.8
2.1
2.4
2.7
3
3.3
Supply Voltage (V)
图10-6. Rise / Fall time (ps) vs Supply Voltage vs Load Capacitance
10.3 Power Supply Recommendations
For the best electrical performance of the LMK6x, TI recommends use 1 µF capacitor on the device power
supply bypass network. TI also recommends using component side mounting of the power-supply bypass
capacitors, and best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low impedance connection to the ground plane.
10.4 Layout
10.4.1 Layout Guidelines
The following sections provide recommendations for board layout, solder reflow profile and power-supply
bypassing when using the LMK6x to ensure good thermal and electrical performance and signal integrity of the
entire system.
10.4.1.1 Ensuring Thermal Reliability
The LMK6x is a high-performance device. Therefore, pay careful attention to device configuration and printed
circuit board (PCB) layout with respect to power consumption. The ground pin must be connected to the ground
plane of the PCB through three vias or more to maximize thermal dissipation out of the package.
The equation below describes the relationship between the PCB temperature around the LMK6x and its junction
temperature.
TB = TJ –ΨJB × P
(1)
where
• TB: PCB temperature around the LMK6x
• TJ: Junction temperature of LMK6x
• ΨJB: Junction-to-board thermal resistance parameter of LMK6x (refer to the Thermal Information tables in the
Specifications section for this information)
• P: On-chip power dissipation of LMK6x
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10.4.1.2 Recommended Solder Reflow Profile
TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the LMK6x to be
processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
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10.4.2 Layout
Refer to the LMK6EVM User's Guide for printed circuit board layout examples for LMK6D, LMK6H, LMK6P and
LMK6C devices. The figured below show the PCB layout example as done on the evaluation module for the
LMK6x EVM.
图10-7. PCB Layout Example From LMK6 EVM - Top Layer
图10-8. PCB Layout Example From LMK6 EVM - GND Layer 1
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图10-9. PCB Layout Example From LMK6 EVM - GND Layer 2
图10-10. PCB Layout Example From LMK6 EVM - Bottom Layer
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, LMK6EVM User's Guide
• Texas Instruments, Standalone BAW Oscillators Advantages Over Quartz Oscillators application note
• Texas Instruments, BAW oscillator solutions for Building Automation application note
• Texas Instruments, BAW oscillator solutions for Factory Automation application note
• Texas Instruments, BAW oscillator solutions for Grid Infrastructure application note
• Texas Instruments, BAW oscillator solutions for Optical Modules application note
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
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PACKAGE OUTLINE
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.6
2.4
B
3.3
3.1
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08
C
1.7
SYMM
(0.1) TYP
3
4
4X 0.95
SYMM
1.9
0.55
2X
0.45
0.1
0.05
C
A
B
B
6
C
1
0.75
0.65
4X
PIN 1 ID
(OPTIONAL)
0.1
C
A
0.7
0.5
6X
0.05
C
4224885/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.7)
SYMM
6
1
4X
(0.95)
2X (0.5)
SYMM
(1.9)
4X (0.7)
6X (0.6)
4
3
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
METAL
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224885/B 10/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
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LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.7)
SYMM
6
1
4X
(0.95)
2X (0.5)
SYMM
(1.9)
(R0.05)
TYP
4X (0.65)
4
3
6X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1,3,4 & 6: 93%
SCALE: 20X
4224885/B 10/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
PACKAGE OUTLINE
VSON - 1 mm max height
DLE0004A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.6
2.4
B
3.3
3.1
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
1.6
0.08
C
SYMM
(0.1) TYP
2
3
1.05
SYMM
2.1
4
1
0.75
0.65
4X
PIN 1 ID
(OPTIONAL)
0.1
C
A B
0.05
C
0.7
4X
0.5
4225945/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DLE0004A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.6)
SYMM
1
4
(1.05) TYP
SYMM
(2.1)
4X (0.7)
3
2
(R0.05) TYP
4X (0.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225945/B 10/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DLE0004A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.6)
SYMM
1
4
(1.05) TYP
SYMM
(2.1)
4X (0.65)
4X (0.6)
3
2
(R0.05)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
ALL PADS: 93%
SCALE: 20X
4225945/B 10/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
PACKAGE OUTLINE
VSON - 1 mm max height
DLF0006A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.1
1.9
B
2.6
2.4
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08
C
1.3
SYMM
(0.1) TYP
3
4
4X 0.825
SYMM
1.65
0.3
2X
0.2
0.1
C
A
B
B
6
1
0.05
C
PIN 1 ID
(OPTIONAL)
0.7
0.6
4X
0.8
0.6
6X
0.1
C A
0.05
C
4224884/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DLF0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.5)
SYMM
6
1
4X
(0.825)
2X (0.25)
SYMM
(1.65)
4X (0.65)
4
3
(R0.05) TYP
6X (0.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224884/B 10/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DLF0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.5)
SYMM
6
1
4X
(0.825)
2X (0.25)
SYMM
(1.65)
(R0.05)
TYP
4X (0.6)
4
3
6X (0.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1,3,4 & 6: 92%
SCALE: 20X
4224884/B 10/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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45
Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
PACKAGE OUTLINE
VSON - 1 mm max height
DLF0004A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.1
1.9
B
2.6
2.4
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08
C
1.3
SYMM
(0.1) TYP
2
3
0.825
SYMM
1.65
4
1
PIN 1 ID
(OPTIONAL)
0.7
0.6
4X
0.8
0.6
6X
0.1
0.05
C A B
C
4225946/C 12/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DLF0004A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.5)
SYMM
4
1
4X
(0.825)
SYMM
(1.65)
4X (0.65)
3
2
(R0.05) TYP
6X (0.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225946/C 12/2022
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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47
Product Folder Links: LMK6C LMK6D LMK6H LMK6P
LMK6C, LMK6D, LMK6H, LMK6P
ZHCSNQ0D –APRIL 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DLF0004A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.5)
SYMM
4
1
4X
(0.825)
SYMM
(1.65)
(R0.05)
TYP
4X (0.6)
3
2
6X (0.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1,3,4 & 6: 92%
SCALE: 20X
4225946/C 12/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
48
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Product Folder Links: LMK6C LMK6D LMK6H LMK6P
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK6CE02500CDLFR
LMK6CE02500CDLFT
LMK6CE03333CDLER
LMK6CE03333CDLET
LMK6CE04000CDLFR
LMK6CE04000CDLFT
LMK6CE04800DDLFR
LMK6CE04800DDLFT
LMK6CE05000CDLFR
LMK6CE05000CDLFT
LMK6CE07425DDLFR
LMK6CE07425DDLFT
LMK6CE15625DDLFR
LMK6CE15625DDLFT
LMK6DA12288ADLER
LMK6DA12288ADLET
LMK6DA12500ADLFR
LMK6DA12500ADLFT
LMK6DA15552ADLER
LMK6DA15552ADLET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DLF
DLF
DLE
DLE
DLF
DLF
DLF
DLF
DLF
DLF
DLF
DLF
DLF
DLF
DLE
DLE
DLF
DLF
DLE
DLE
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LCBG
LCBG
HCB8
HCB8
HCB6
HCB6
LC1C
LC1C
LCCB
LCCB
LC19
LC19
LC12
LC12
HDA4
HDA4
LDA6
LDA6
HDA3
HDA3
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK6DA20000ADLER
LMK6DA20000ADLET
LMK6HA10000ADLER
LMK6HA10000ADLET
LMK6HA10000ADLFR
LMK6HA10000ADLFT
LMK6HA10000BDLFR
LMK6HA10000BDLFT
LMK6PA15625ADLER
LMK6PA15625ADLET
LMK6PA15625ADLFR
LMK6PA15625ADLFT
PLMK6CE01920CDLFT
PLMK6CE02400CDLET
PLMK6CE02400CDLFT
PLMK6CE02500CDLET
PLMK6CE02500CDLFT
PLMK6CE04000CDLFT
PLMK6CE15625CDLFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DLE
DLE
DLE
DLE
DLF
DLF
DLF
DLF
DLE
DLE
DLF
DLF
DLF
DLE
DLF
DLE
DLF
DLF
DLF
6
6
6
6
6
6
6
6
6
6
6
6
4
4
4
4
4
4
4
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
HDA1
HDA1
LHA8
LHA8
LHA8
LHA8
LH18
LH18
LPA2
LPA2
LPA2
LPA2
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
250
250
250
250
250
250
250
250
RoHS & Green
TBD
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
PCEC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2023
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK6CE07425DDLFT
VSON
DLF
4
250
180.0
8.4
2.25
2.8
1.1
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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9-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON DLF
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
LMK6CE07425DDLFT
4
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DLE 6
2.5 x 3.2, multiple pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229714/A
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PACKAGE OUTLINE
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.6
2.4
B
3.3
3.1
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.7
SYMM
(0.1) TYP
3
4
4X 0.95
SYMM
1.9
0.55
2X
0.45
0.1
0.05
C A B
C
6
1
0.75
0.65
4X
PIN 1 ID
(OPTIONAL)
0.1
C A B
0.7
0.5
6X
0.05
C
4224885/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.7)
SYMM
6
1
4X
(0.95)
2X (0.5)
SYMM
(1.9)
4X (0.7)
4
3
6X (0.6)
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224885/B 10/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
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EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DLE0006A
PLASTIC QUAD FLAT PACK-NO LEAD
(1.7)
SYMM
6
1
4X
(0.95)
2X (0.5)
SYMM
(1.9)
(R0.05)
TYP
4X (0.65)
4
3
6X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1,3,4 & 6: 93%
SCALE: 20X
4224885/B 10/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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