LMK05318B [TI]
采用 BAW 技术的超低抖动、单通道网络同步器时钟;型号: | LMK05318B |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 BAW 技术的超低抖动、单通道网络同步器时钟 时钟 |
文件: | 总90页 (文件大小:4288K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMK05318B
ZHCSN15B –JUNE 2020 –REVISED JUNE 2021
LMK05318B 超低抖动时钟发生器
1 特性
2 应用
• 一个数字锁相环(DPLL),具有:
• SyncE (G.8262)、SONET/SDH(Stratum 3/3E、
G.813、GR-1244、GR-253)、IEEE 1588 PTP 从
时钟,或光传输网络(G.709)
• 用于以太网交换机和路由器的400G 线卡、网络卡
• 无线基站(BTS)、无线回程
• 测试与测量、医疗成像
– 无中断切换:±50ps 相位瞬态
– 具有快速锁定功能的可编程环路带宽
– 使用低成本TCXO/OCXO 实现符合标准的同步
和保持模式
• 两个具备业界领先性能的模拟锁相环(APLL):
• 56G/112G PAM-4 PHY、ASIC、FPGA、SoC 和处
理器的抖动消除、漂移衰减和基准时钟生成
– 312.5MHz 频率下50fs RMS 抖动(APLL1)
– 155.52MHz 频率下125fs RMS 抖动(APLL2)
• 两个基准时钟输入
3 说明
– 基于优先级的输入选择
– 在缺失参考时实现数字保持
• 具有可编程驱动器的八个时钟输出
– 多达六个不同的输出频率
LMK05318B 是一款高性能网络同步器时钟器件,提供
抖动消除、时钟生成、先进的时钟监控和卓越的无中断
切换性能,可满足通信基础设施和工业应用的严格时序
要求。该器件具有超低抖动和高电源噪声抑制 (PSNR)
性能,可降低高速串行链路中的误码率(BER)。
– AC-LVDS、AC-CML、AC-LVPECL、HCSL 和
1.8V LVCMOS 输出格式
• 加电后自定义时钟的EEPROM/ROM
• 灵活的配置选项
该器件可使用 TI 专有的体声波 (BAW) VCO 技术生成
具有50fs RMS 抖动的输出时钟,而不受XO 和基准输
入的抖动和频率的影响。
– 输入和输出为1Hz (1PPS) 至800MHz
– XO/TCXO/OCXO 输入:10MHz 至100MHz
– DCO 模式:< 0.001ppb/阶跃,可进行精确的时
钟控制(IEEE 1588 PTP 从运行)
– 先进的时钟监控和状态
器件信息
封装(1)
封装尺寸(标称值)
器件型号
LMK05318B
VQFN (48)
7.00mm × 7.00mm
– I2C 或SPI 接口
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• PSNR:–83dBc(3.3V 电源下噪声为50mVpp)
• 3.3V 电源,提供1.8V、2.5V 或3.3V 输出
• 工业温度范围:-40 °C 至+85 °C
VDD
VDDO
3.3 V
1.8 / 2.5 / 3.3 V
Output
Muxes
LMK05318B
Ultra-Low Jitter
Network Synchronizer Clock
Power Conditioning
OUT0
OUT1
÷OD
÷OD
Differential
or HCSL
DPLL
APLL1
VCO1
PRIREF
SECREF
Differential
or LVCMOS
OUT2
OUT3
÷R
DCO
Hitless
Switching
XO/
TCXO/
OCXO
÷OD
÷OD
÷OD
÷OD
OUT4
OUT5
×1, ×2
÷
÷
Differential,
HCSL, or
1.8-V LVCMOS
APLL2
VCO2
EEPROM,
ROM
I2C/SPI
OUT6
OUT7
Registers
÷
÷
LOGIC I/Os
STATUS
Device Control
and Status
简化版方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS801
LMK05318B
ZHCSN15B –JUNE 2020 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
9.4 Device Functional Modes..........................................54
9.5 Programming............................................................ 59
10 Application and Implementation................................67
10.1 Application Information........................................... 67
10.2 Typical Application.................................................. 70
10.3 Do's and Don'ts.......................................................75
11 Power Supply Recommendations..............................76
11.1 Power Supply Bypassing........................................ 76
11.2 Device Current and Power Consumption................76
12 Layout...........................................................................78
12.1 Layout Guidelines................................................... 78
12.2 Layout Example...................................................... 78
12.3 Thermal Reliability.................................................. 79
13 Device and Documentation Support..........................80
13.1 Device Support....................................................... 80
13.2 接收文档更新通知................................................... 80
13.3 支持资源..................................................................80
13.4 Trademarks.............................................................80
13.5 Electrostatic Discharge Caution..............................80
13.6 术语表..................................................................... 80
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................3
6 Pin Configuration and Functions...................................4
6.1 Device Start-Up Modes...............................................7
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings ....................................... 8
7.2 ESD Ratings .............................................................. 8
7.3 Recommended Operating Conditions ........................8
7.4 Thermal Information: 4-Layer JEDEC Standard
PCB ..............................................................................9
7.5 Thermal Information: 10-Layer Custom PCB .............9
7.6 Electrical Characteristics ............................................9
7.7 Timing Diagrams.......................................................16
7.8 Typical Characteristics..............................................18
8 Parameter Measurement Information..........................21
8.1 Output Clock Test Configurations............................. 21
9 Detailed Description......................................................23
9.1 Overview...................................................................23
9.2 Functional Block Diagram.........................................24
9.3 Feature Description...................................................28
Information.................................................................... 80
4 Revision History
Changes from Revision A (January 2021) to Revision B (June 2021)
Page
• 将数据表标题从:具有两个频域的LMK05318B 超低抖动网络同步器时钟更改为:LMK05318B 超低抖动时钟
发生器................................................................................................................................................................1
• Added Vod for specific fOUT test conditions for AC-LVDS, AC-CML, and AC-LVPECL.......................................9
• Changed VIL max from 0.5 to 0.6 on SCL/SDA pin............................................................................................ 9
• Specified ZDM.................................................................................................................................................. 53
• Clarified the 5 MSBs of I2C (11001b) can be programmed in EEPROM ......................................................... 60
• Changed SLAVEADR byte number from: 5 to: 10............................................................................................64
• Clarified reading NVM Spare Bytes..................................................................................................................64
Changes from Revision * (June 2020) to Revision A (January 2021)
Page
• 将155.52MHz 时的典型RMS 抖动从130fs 更改为125fs................................................................................. 1
• Changed the maximum APLL1 PFD frequency from 50 MHz to 80 MHz...........................................................9
• Changed the maximum AC-LVDS output frequency from 800 MHz to 1250 MHz............................................. 9
• Changed the maximum AC-CML output frequency from 800 MHz to 1250 MHz...............................................9
• Changed the maximum AC-LVPECL output frequency from 800 MHz to 1250 MHz......................................... 9
• Changed the output format in RMS jitter test conditions from AC-DIFF to AC-LVPECL.................................... 9
• Changed the max RMS jitter for 312.5 MHz from 100 fs to 80 fs....................................................................... 9
• Changed the max RMS jitter for 156.25 MHz from 100 fs to 90 fs..................................................................... 9
• Changed the max RMS jitter for 153.6 MHz from 250 fs to 200 fs..................................................................... 9
• Changed the max RMS jitter for 155.52 MHz from 250 fs to 200 fs................................................................... 9
• Added typical performance plot for output voltage swing vs. output frequency................................................18
• Added descriptions for reference frequency monitoring................................................................................... 36
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5 说明(续)
DPLL 支持抖动和漂移衰减的可编程环路带宽,而两个 APLL 支持分频率转换,从而可以实现灵活的时钟生成。
DPLL 上支持的同步选项包括采用相位消除的无中断切换、数字保持和频率阶跃小于 0.001ppb(十亿分之一)的
DCO 模式,从而实现精确的时钟控制(IEEE 1588 PTP 从运行)。DPLL 可以锁相到 1 PPS(每秒脉冲数)基准
输入,并且在一个输出上支持可选零延迟模式,以实现具有可编程失调电压的确定性输入到输出相位校准。先进
的基准输入监控块可确保稳健的时钟故障检测并在发生基准缺失(LOR) 时帮助将输出时钟干扰降至最低。
该器件可以使用通用的低频TCXO 或OCXO 来根据同步标准设置自由运行型或保持型输出频率稳定性。否则,在
自由运行型或保持型频率稳定性和漂移不重要时,该器件可以使用标准 XO。该器件可通过 I2C 或 SPI 接口实现
完全编程,在通电后支持通过内部 EEPROM 或 ROM 进行自定义频率配置。EEPROM 在出厂时进行了预编程,
且可根据需要进行系统内编程。
请参阅节7.8,以了解测试条件。
图5-1. 312.5MHz 输出相位噪声(APLL1),< 50fs RMS 抖动
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6 Pin Configuration and Functions
STATUS0
STATUS1/ FDEC
CAP_DIG
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD_PLL2
CAP_PLL2
LF2
2
3
VDD_DIG
4
VDD_XO
XO_N
VDD_IN
5
PRIREF_P
6
XO_P
GND
PRIREF_N
7
GPIO2/SDO/ FINC
LF1
REFSEL
8
HW_SW_CTRL
SECREF_P
SECREF_N
GPIO0/SYNCN
9
CAP_PLL1
VDD_PLL1
SCL/SCK
10
11
12
SDA/SDI
Not to scale
图6-1. RGZ Package 48-Pin VQFN Top View
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
POWER
Ground / Thermal Pad.
GND
PAD
G
The exposed pad must be connected to PCB ground for proper electrical and thermal performance.
A 5×5 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
Core Supply (3.3 V) for Primary and Secondary Reference Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_IN
5
P
P
Core Supply (3.3 V) for XO Input.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_XO
33
VDD_PLL1
VDD_PLL2
VDD_DIG
27
36
4
P
P
P
Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
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表6-1. Pin Functions (continued)
PIN
NAME
VDDO_01
TYPE(1)
DESCRIPTION
NO.
18
19
37
40
43
46
P
P
P
P
P
P
VDDO_23
VDDO_4
VDDO_5
VDDO_6
VDDO_7
CORE BLOCKS
LF1
Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin.
29
34
A
A
External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby capacitor on each pin. For LF1, a 0.47-µF capacitor is suggested for typical APLL1
loop bandwidths around 1.0 kHz. For LF2, a 0.1-µF capacitor is suggested for typical APLL2 loop
bandwidth around 500 kHz.
LF2
CAP_PLL1
CAP_PLL2
CAP_DIG
28
35
3
A
A
A
External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
INPUT BLOCKS
PRIREF_P
PRIREF_N
SECREF_P
6
7
I
I
I
DPLL Primary and Secondary Reference Clock Inputs.
Each input pair can accept a differential or single-ended clock as a reference to the DPLL. Each pair
has a programmable input type with internal termination to support AC- or DC-coupled clocks. A
single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground.
An unused input pair can be left floating.
10
For low-frequency input, an internal AC-coupling capacitor can be disabled to improve noise
immunity. Differential Input and LVCMOS input can be DC-coupled to the receiver.
SECREF_N
XO_P
11
31
I
I
XO/TCXO/OCXO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator
as a reference to the APLLs. This input has a programmable input type with internal termination to
support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to
the P input with the N input pulled down to ground. A low-frequency TCXO or OCXO can be used to
set the clock output frequency accuracy and stability during free-run and holdover modes.
In DPLL mode, the XO frequency must have a non-integer relationship to the VCO1 frequency so
APLL1 can operate in fractional mode (required for proper DPLL operation). In APLL-only mode, the
XO frequency can have either an integer or non-integer relationship to the VCO1 frequency.
XO_N
32
I
OUTPUT BLOCKS
OUT0_P
OUT0_N
OUT1_P
OUT1_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
OUT5_P
OUT5_N
OUT6_P
OUT6_N
OUT7_P
OUT7_N
14
15
17
16
20
21
23
22
39
38
42
41
45
44
48
47
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, and HCSL.
Unused differential outputs should be terminated if active or left floating if disabled through
registers.
The OUT[0:3] bank is preferred for PLL1 clocks to minimize output crosstalk.
Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8-
V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if active
or left floating if disabled through registers.
The OUT[4:7] bank is preferred for PLL2 clocks to minimize output crosstalk. When PLL2 is not
used, the OUT[4:7] bank can be used for PLL1 clocks without risk of cross-coupling from PLL2.
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表6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
LOGIC CONTROL / STATUS (2) (3)
Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the
registers, serial interface, and logic pin functions. The input level is sampled only at device power-
on reset (POR).
HW_SW_CTRL
PDN
9
I
I
See 表6-2 for start-up mode descriptions and logic pin functions.
Device Power-Down (active low).
When PDN is pulled low, the device is in hard-reset and all blocks including the serial interface are
powered down. When PDN is pulled high, the device is started according to device mode selected
by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
13
I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See 表6-2.
When HW_SW_CTRL is 0 or 1, the serial interface is I2C. SDA and SCL pins (open-drain) require
external I2C pullup resistors. The default 7-bit I2C address is 11001xxb, where the MSB bits
(11001b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic
input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO1 input state (3-level)
during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b.
SDA/SDI
25
I/O
When HW_SW_CTRL is Float, the serial interface is SPI (4-wire, Mode 0) using the SDI, SCK,
SCS, and SDO pins.
I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See 表6-2.
SCL/SCK
26
12
24
I
I
I
GPIO0/SYNCN
GPIO1/SCS
Multifunction Inputs or Outputs.
See 表6-2.
GPIO2/SDO/
FINC
30
1
I/O
I/O
STATUS0
Status Outputs 0 and 1.
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain),
and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
In I2C mode, the STATUS1/FDEC pin can function as a DCO mode control input pin. See 表6-2.
STATUS1/
FDEC
2
8
I/O
I
Manual DPLL Reference Clock Input Selection. (3-level, 1.8-V compatible).
REFSEL = 0 (PRIREF), 1 (SECREF), or Float or VIM (Auto Select). This control pin must be enabled
by register default or programming. Leave pin floating if unused.
REFSEL
(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
(2) Internal resistors: PDN pin has 200-kΩpullup to VDD_IN. HW_SW_CTRL, GPIO, REFSEL, and STATUS pins each have a 150-kΩ
bias to VIM (approximately 0.8 V) when PDN = 0 or 400-kΩpulldown when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
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6.1 Device Start-Up Modes
The HW_SW_CTRL input pin selects the device start-up mode that determines the memory page (EEPROM or
ROM) used to initialize the registers, the serial interface, and the logic pin functions at power-on reset. The initial
register settings determine the frequency configuration of the device on start-up. After start-up, the device
registers can be accessed through the serial interface for device monitoring and programming, and the logic pins
will function as defined by the selected mode.
表6-2. Device Start-Up Modes
HW_SW_CTRL
INPUT LEVEL(1)
START-UP
MODE
MODE DESCRIPTION
Registers are initialized from EEPROM, and I2C interface is enabled.
Logic pins:
•
•
•
•
•
SDA/SDI, SCL/SCK: I2C Data, I2C Clock (open-drain)
EEPROM + I2C
(Soft pin mode)
GPIO0/SYNCN: Output SYNC Input (active low). Pull up externally if not used.
GPIO1/SCS (1): I2C Address LSB Select (Low = 00b, Float = 01b, High = 10b)
GPIO2/SDO/FINC (2): DPLL DCO Frequency Increment (active high)
STATUS1/FDEC (2): DPLL DCO Frequency Decrement (active high), or Status output
0
Registers are initialized from EEPROM, and SPI interface is enabled.
Logic pins:
•
•
•
•
SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)
GPIO0/SYNCN: Output SYNC Input (active low). Pull up externally if not used.
GPIO1/SCS: SPI Chip Select (SCS)
Float
EEPROM + SPI
(Soft pin mode)
(VIM
)
GPIO2/SDO/FINC: SPI Data Out (SDO)
Registers are initialized from the ROM page selected by GPIO pins, and I2C interface is enabled.
Logic pins:
•
•
•
SDA/SDI, SCL/SCK: I2C Data, I2C Clock (open-drain)
GPIO[2:0] (1): ROM Page Select Inputs (000b to 111b) during POR.
After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins can function the same as for
HW_SW_CTRL = 0.
ROM + I2C
(Hard pin mode)
1
(1) The input levels on these pins are sampled only during POR.
(2) FINC and FDEC pins are only available when DCO mode and GPIO pin control are enabled by registers.
Note
To ensure proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and STATUS1
pins must all be floating or biased to VIM (0.8-V typical) before the PDN pin is pulled high. These three
pins momentarily operate as 3-level inputs and get sampled at the low-to-high transition of PDN to
determine the device start-up mode during POR. If any of these pins are connected to a system host
(MCU or FPGA), TI recommends using external biasing resistors on each pin (10-kΩ pullup to 3.3 V
with 3.3-kΩ pulldown to GND) to set the inputs to VIM during POR. After power up, the STATUS pins
can operate as LVCMOS outputs to overdrive the external resistor bias for normal status operation.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
VDD(2)
VDDO(3)
VIN
Core supply voltages
3.6
3.6
Output supply voltages
V
Input voltage range for clock and logic inputs
Output voltage range for logic outputs
Output voltage range for clock outputs
Junction temperature
VDD+0.3
VDD+0.3
VDDO+0.3
150
V
VOUT_LOGIC
VOUT
V
V
TJ
°C
°C
Tstg
Storage temperature
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before the PDN is pulled high to trigger the
internal power-on reset (POR).
(3) VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3.135
1.71
2.375
3.135
1.71
0
NOM
3.3
MAX
3.465
1.89
UNIT
V
VDD(1)
Core supply voltages
1.8
V
VDDO_x(2)
Output supply voltage for AC-LVDS/CML/LVPECL or HCSL driver
2.5
2.625
3.465
1.89
V
3.3
V
VDDO_x(2)
VIN
Output supply voltage for 1.8-V LVCMOS driver(3)
Input voltage range for clock and logic inputs
Junction temperature
1.8
V
3.465
135
V
TJ
°C
ms
tVDD
Power supply ramp time(4)
0.01
100
nEEcyc
EEPROM program cycles(5)
100 cycles
(1) VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before internal power-on reset (POR).
(2) VDDO refers to all-output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
(3) The LVCMOS driver supports full rail-to-rail swing when VDDO_x is 1.8 V ±5%. When VDDO_x is 2.5 V or 3.3 V, the LVCMOS driver
will not fully swing to the positive rail due to the dropout voltage of the internal LDO regulator of output channel.
(4) Time for VDD to ramp monotonically above 2.7 V for proper internal power-on reset. For slower or non-monotonic VDD ramp, hold
PDN low until after VDD voltages are valid.
(5) nEEcyc specifies the maximum EEPROM program cycles allowed for customer programming. The initial count of factory-programmed
cycles is non-zero due to production tests, but factory-programmed cycles are excluded from the nEEcyc limit. The total number of
EEPROM program cycles can be read from the 8-bit NVM count status register (NVMCNT), which automatically increments by 1 on
each successful programming cycle. TI does not ensure EEPROM endurance if the nEEcyc limit is exceeded by the customer.
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7.4 Thermal Information: 4-Layer JEDEC Standard PCB
LMK05318B
THERMAL METRIC(1) (2) (3)
RGZ (VQFN)
48 PINS
23.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
RθJC(bot)
ψJT
13.2
7.4
Junction-to-case (bottom) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.4
0.2
7.3
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The thermal information is based on a 4-layer JEDEC standard board with 25 thermal vias (5 x 5 pattern, 0.3-mm holes).
(3) ΨJB can allow the system designer to measure the board temperature (TPCB) with a fine-gauge thermocouple and back-calculate the
device junction temperature, TJ = TPCB + (ΨJB x Power). Measurement of ΨJB is defined by JESD51-6.
7.5 Thermal Information: 10-Layer Custom PCB
LMK05318B
THERMAL METRIC(1) (2) (3)
RGZ (VQFN)
UNIT
48 PINS
9.1
RθJA
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
4.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
4.4
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The thermal information is based on a 10-layer 200-mm x 250-mm x 1.6-mm board with 25 thermal vias (5 x 5 pattern, 0.3-mm holes).
(3) ΨJB can allow the system designer to measure the board temperature (TPCB) with a fine-gauge thermocouple and back-calculate the
device junction temperature, TJ = TPCB + (ΨJB x Power). Measurement of ΨJB is defined by JESD51-6.
7.6 Electrical Characteristics
Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
Core Current Consumption
(VDD_DIG)
IDD_DIG
21
43
mA
mA
mA
mA
Core Current Consumption
(VDD_IN)
IDD_IN
Core Current Consumption
(VDD_PLL1)
IDD_PLL1
DPLL and APLL1 enabled
110
20
Core Current Consumption
(VDD_XO)
IDD_XO
APLL2 disabled
APLL2 enabled
20
mA
mA
Core Current Consumption
(VDD_PLL2)
IDD_PLL2
120
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output mux and divider enabled,
excludes driver(s)
65
mA
Divider value = 2 to 6
Output mux and divider enabled,
excludes driver(s)
70
mA
Output Current Consumption, per
channel(3)
(VDDO_x)
Divider value > 6
IDDO_x
AC-LVDS
11
16
18
25
6
mA
mA
mA
mA
mA
AC-CML
AC-LVPECL
HCSL, 50-Ω load to GND
1.8-V LVCMOS (x2), 100 MHz
Total Current Consumption (all
VDD and VDDO pins, 3.3 V)
Device powered-down (PDN pin held
low)
IDDPDN
56
mA
XO INPUT CHARACTERISTICS (XO)
fIN
Input frequency range
10
1
100
2.6
2
MHz
Vpp
Vpp
|V|
VIN-SE
VIN-DIFF
VID
Single-ended input voltage swing LVCMOS input, DC-coupled to XO_P
Differential input voltage swing(11) Differential input
Differential input voltage swing(11) Differential input
Input slew rate(13)
0.4
0.2
0.2
40
1
dV/dt
IDC
0.5
V/ns
%
Input duty cycle
60
50-Ω and 100-Ω internal terminations
IIN
Input leakage
disabled
350
µA
–350
REFERENCE INPUT CHARACTERISTICS (PRIREF, SECREF)
Input frequency range
Input frequency range
Differential input(4)
5
800
250
MHz
MHz
fIN
LVCMOS input
1E–6
LVCMOS input, DC-coupled to REF_P.
Internally DC-coupled
VIH
Input high voltage
1.8
V
V
LVCMOS input, DC-coupled to REF_P.
Internally DC-coupled
VIL
Input low voltage
0.6
2.6
LVCMOS input, DC-coupled to REF_P.
Internally AC-coupled
VIN-SE
Single-ended input voltage swing
1
Vpp
Differential input voltage swing(11) Differential input, , VHYST = 50 mV
Differential input voltage swing(11) Differential input, , VHYST = 200 mV
Differential input voltage swing(11) Differential input, VHYST = 50 mV
Differential input voltage swing(11) Differential input, VHYST = 200 mV
Input slew rate(13)
0.4
0.7
2
2
1
1
Vpp
Vpp
V
VIN-DIFF
0.2
VID
0.35
0.2
V
dV/dt
IIN
0.5
V/ns
50-Ω and 100-Ω internal terminations
Input leakage
disabled
350
µA
–350
VCO CHARACTERISTICS
fVCO1 VCO1 Frequency Range
fVCO2 VCO2 Frequency Range
2499.750
5500
2500 2500.250
6250
MHz
MHz
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
APLL CHARACTERISTICS
APLL1 Phase Detector
Frequency
fPD1
fPD2
1
80
MHz
MHz
APLL2 Phase Detector
Frequency
10
150
AC-LVDS OUTPUT CHARACTERISTICS (OUTx)
fOUT
Output frequency(5)
1250
450
MHz
mV
25 MHz ≤fOUT ≤800 MHz; TYP at
156.25 MHz
250
390
fOUT = 50 MHz
285
275
270
400
390
385
280
450
450
450
VOD
Output voltage swing (VOH - VOL)
100 MHz ≤fOUT ≤200 MHz
fOUT = 312.5
fOUT = 1250 MHz
Differential output voltage swing,
peak-to-peak
VOUT-DIFF
VOS
2×VOD
Vpp
mV
ps
Output common mode
Output-to-output skew
100
430
100
350
250
Same post divider, output divide values,
and output type
tSK
20% to 80%, < 300 MHz
225
85
ps
tR/tF
Output rise/fall time(12)
± 100 mV around center point,
300 MHz ≤fOUT ≤800 MHz
ps
PNFLOOR
ODC
Output phase noise floor
Output duty cycle(9)
fOUT = 156.25 MHz; fOFFSET > 10 MHz
-160
dBc/Hz
%
45
55
AC-CML OUTPUT CHARACTERISTICS (OUTx)
fOUT
Output frequency(5)
1250
800
MHz
25 MHz ≤fOUT ≤800 MHz; TYP at
fOUT = 156.25 MHz
400
600
fOUT = 50 MHz
500
490
480
620
600
580
400
700
690
680
VOD
Output voltage swing (VOH - VOL)
mV
100 MHz ≤fOUT ≤200 MHz
fOUT = 312.5
fOUT = 1250 MHz
Differential output voltage swing,
peak-to-peak
VOUT-DIFF
VOS
2×VOD
Vpp
mV
ps
Output common mode
Output-to-output skew
150
550
100
300
150
Same post divider, output divide values,
and output type
tSK
20% to 80%, < 300 MHz
225
50
ps
tR/tF
Output rise/fall time(12)
± 100 mV around center point,
300 MHz ≤fOUT ≤800 MHz
ps
PNFLOOR
ODC
Output phase noise floor
Output duty cycle(9)
fOUT = 156.25 MHz; fOFFSET > 10 MHz
-160
dBc/Hz
%
45
55
AC-LVPECL OUTPUT CHARACTERISTICS (OUTx)
fOUT
Output frequency(5)
1250
MHz
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
25 MHz ≤fOUT ≤800 MHz; TYP at
fOUT = 156.25 MHz
500
780
1000
fOUT = 50 MHz
660
640
620
810
780
740
510
920
900
880
VOD
Output voltage swing (VOH - VOL
)
mV
100 MHz ≤fOUT ≤200 MHz
fOUT = 312.5 MHz
fOUT = 1250 MHz
Differential output voltage swing,
peak-to-peak
VOUT-DIFF
VOS
2×VOD
Vpp
mV
ps
Output common mode
Output-to-output skew
300
700
100
300
100
Same post divider, output divide values,
and output type
tSK
20% to 80%, < 300 MHz
200
35
ps
tR/tF
Output rise/fall time(12)
± 100 mV around center point,
300 MHz ≤fOUT ≤800 MHz
ps
PNFLOOR
ODC
Output phase noise floor
Output duty cycle(9)
fOUT = 156.25 MHz; fOFFSET > 10 MHz
dBc/Hz
%
–162
45
55
HCSL OUTPUT CHARACTERISTICS (OUTx)
fOUT
VOH
VOL
Output frequency(5)
Output high voltage
Output low voltage
400
880
150
MHz
mV
600
mV
–150
Same post divider, output divide values,
and output type
tSK
Output-to-output skew
Output slew rate(12)
100
4
ps
V/ns
dBc/Hz
%
dV/dt
PNFLOOR
ODC
± 150 mV around center point
100 MHz
1.6
45
Output phase noise floor (fOFFSET
> 10 MHz)
–160
Output duty cycle(9)
55
200
0.4
1.8-V LVCMOS OUTPUT CHARACTERISTICS (OUT[4:7])
fOUT
VOH
VOL
IOH
Output frequency
Output high voltage
Output low voltage
Output high current
Output low current
Output rise/fall time
MHz
V
1E–6
IOH = 1 mA
IOL = 1 mA
1.2
V
mA
mA
ps
–23
20
IOL
tR/tF
20% to 80%
250
Same post divider, output divide values,
and output type
Output-to-output skew
Output-to-output skew
100
1.5
ps
ns
tSK
Same post divider, output divide values,
LVCMOS-to-DIFF
PNFLOOR
ODC
Output phase noise floor
Output duty cycle(9)
Output impedance
fOUT = 66.66 MHz; fOFFSET > 10 MHz
-160
50
dBc/Hz
%
45
55
ROUT
Ω
3-LEVEL LOGIC INPUT CHARACTERISTICS (HW_SW_CTRL, GPIO1, REFSEL, STATUS[1:0])
VIH
VIM
Input high voltage
Input mid voltage
1.4
0.7
V
V
Input floating with internal bias and
PDN pulled low
0.9
VIL
IIH
IIL
Input low voltage
Input high current
Input low current
0.4
40
40
V
VIH = VDD
VIL = GND
µA
µA
–40
–40
2-LEVEL LOGIC INPUT CHARACTERISTICS (PDN, GPIO[2:0], SDI, SCK, SCS)
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIH
Input high voltage
Input low voltage
Input high current
Input low current
1.2
0.6
40
40
V
VIH = VDD
VIL = GND
-40
-40
µA
µA
IIL
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC OUTPUT CHARACTERISTICS (STATUS[1:0], SDO)
VOH
VOL
Output high voltage
Output low voltage
IOH = 1 mA
IOL = 1 mA
1.2
V
V
0.6
20% to 80%, LVCMOS mode, 1 kΩto
GND
tR/tF
Output rise/fall time
500
ps
SPI TIMING REQUIREMENTS (SDI, SCK, SCS, SDO)
SPI clock rate
fSCK
20
5
MHz
MHz
ns
SPI clock rate; NVM write
t1
t2
t3
t4
t5
t6
t7
t8
SCS to SCK setup time
SDI to SCK setup time
SDI to SCK hold time
SCK high time
10
10
10
25
25
ns
ns
ns
SCK low time
ns
SCK to SDO valid read-back data
SCS pulse width
20
ns
20
10
ns
SDI to SCK hold time
ns
I2C-COMPATIBLE INTERFACE CHARACTERISTICS (SDA, SCL)
VIH
VIL
IIH
Input high voltage
Input low voltage
Input leakage
1.2
V
V
0.6
15
µA
V
–15
VOL
Output low voltage
IOL = 3 mA
0.3
100
400
Standard
fSCL
I2C clock rate
kHz
Fast mode
tSU(START)
tH(START)
tW(SCLH)
tW(SCLL)
tSU(SDA)
tH(SDA)
START condition setup time
START condition hold time
SCL pulse width high
SCL pulse width low
SDA setup time
SCL high before SDA low
SCL low after SDA low
0.6
0.6
0.6
1.3
100
0
µs
µs
µs
µs
ns
µs
ns
ns
ns
µs
SDA hold time
SDA valid after SCL low
0.9
300
300
300
tR(IN)
SDA/SCL input rise time
SDA/SCL input fall time
SDA output fall time
tF(IN)
tF(OUT)
CBUS ≤400 pF
tSU(STOP)
STOP condition setup time
0.6
1.3
Bus free time between STOP and
START
tBUS
µs
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Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY NOISE REJECTION (PSNR) / CROSSTALK SPURS
VDD = 3.3 V, VDDO_x = 3.3 V, 156.25
MHz, AC-DIFF output
dBc
dBc
dBc
dBc
dBc
dBc
–83
–78
–63
–58
–45
–75
Spur induced by power supply
noise (VN = 50 mVpp) (6) (7)
PSNR50mV
VDD = 3.3 V, VDDO_x = 3.3 V, 156.25
MHz, HCSL output
VDD = 3.3 V, VDDO_x = 1.8 V, 156.25
MHz, AC-DIFF output
Spur induced by power supply
noise (VN = 25 mVpp)(6) (7)
VDD = 3.3 V, VDDO_x = 1.8 V, 156.25
MHz, HCSL output
PSNR25mV
VDD = 3.3 V, VDDO_x = 1.8 V, 156.25
MHz, LVCMOS output
Spur level due to output-to-output fOUTx = 156.25 MHz, fOUTy = 155.52
SPURXTALK
SPUR
crosstalk (adjacent channels)(7)
MHz, AC-LVPECL
Highest spur level within 12 kHz
to 40 MHz band (excludes output
crosstalk and integer-boundary
spurs)(7)
fVCO1 = 2500 MHz, fVCO2 = 6065.28
MHz, fOUTx = 156.25 MHz, fOUTy
155.52 MHz, AC-LVPECL
=
dBc
–80
PLL CLOCK OUTPUT PERFORMANCE CHARACTERISTICS
312.5 MHz AC-LVPECL output from
RMS Phase Jitter (12 kHz to 20
MHz)(14)
APLL1, fXO = 48.0048 MHz, fPD1
fXO/2, fVCO1 = 2.5 GHz
=
50
60
80 fs RMS
90 fs RMS
156.25 MHz AC-LVPECL output from
RMS Phase Jitter (12 kHz to 20
MHz)(14)
APLL1, fXO = 48.0048 MHz, fPD1
fXO/2, fVCO1 = 2.5 GHz
=
153.6 MHz AC-LVPECL output from
APLL2, fXO = 48.0048 MHz, fPD1
fXO/2, fVCO1 = 2.5 GHz, fPD2 = fVCO1/18,
fVCO2 = 5.5296 GHz
RJ
RMS Phase Jitter (12 kHz to 20
MHz)(14)
=
125
125
200 fs RMS
200 fs RMS
155.52 MHz AC-LVPECL output from
APLL2, fXO = 48.0048 MHz, fPD1 =
fXO/2, fVCO1 = 2.5 GHz, fPD2 = fVCO1/18,
fVCO2 = 5.59872 GHz
RMS Phase Jitter (12 kHz to 20
MHz)(14)
BW
JPK
DPLL bandwidth range(8)
Programmed bandwidth setting
0.01
4000
Hz
dB
DPLL closed-loop jitter
peaking(10)
fREF = 25 MHz, fOUT = 10 MHz, DPLL
BW = 0.1 Hz or 10 Hz
0.1
Jitter modulation = 10 Hz, 25.78125
Gbps
JTOL
Jitter tolerance
6455
UI p-p
ps
Valid for a single switchover event
between two clock inputs at the same
frequency
Phase hit between two reference
inputs with 0 ppm error
tHITLESS
± 50
± 10
Valid for a single switchover event
between two clock inputs at the same
frequency
Frequency transient during hitless
switch
fHITLESS
ppb
(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a
given configuration.
(2) Configuration A (All PLL blocks on except APLL2 is disabled): fREF = 25 MHz, fXO = 48.0048 MHz, fVCO1 = 2.5 GHz.
(3) IDDO_x current for an operating output is the sum of mux, divider, and an output format.
(4) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one
other monitor (frequency, window detectors) to validate the input clock. Otherwise, consider using an LVCMOS clock for an input
below 5 MHz.
(5) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min specification.
(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with ampitude VN and frequency fN (between 100
kHz and 1 MHz) is injected onto VDD and VDDO_x pins.
(7) DJSPUR (ps pk-pk) = [2 × 10(dBc/20) / (π× fOUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and fOUT is the output frequency
(in MHz).
(8) Actual loop bandwidth may be lower. The valid loop bandwidth range may be constrained by the DPLL TDC frequency used in a given
configuration.
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(9) Parameter is specified for PLL outputs divided from either VCO domain.
(10) DPLL closed-loop jitter peaking of 0.1 dB or less is based on the DPLL bandwidth setting configured by the TICS Pro software tool.
(11) Minimum limit applies for the minimum setting of the differential input amplitude monitor (xREF_LVL_SEL = 0).
(12) Measured on the differential output waveform (OUTx_P - OUTx_N). Output with 2-pF load.
(13) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input
clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due
to their common mode noise rejection. TI also recommended to use the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
(14) Excluding output coupling spurs
7.7 Timing Diagrams
t1
t4
t5
SCK
SDI Write/Read
SDO Read
t2
–
W/R
A14
D0/A0
DON‘T CARE
A13...D1/A1
t6
D7
DON‘T CARE
D1
D0
t7
SCS
t8
图7-1. SPI Timing Parameters
ACK
STOP
STOP
START
tW(SCLL)
tf(SM)
tW(SCLH)
tr(SM)
VIH(SM)
VIL(SM)
SCL
th(START)
tSU(SDATA)
tr(SM)
th(SDATA)
tSU(START)
tBUS
tSU(STOP)
tf(SM)
VIH(SM)
VIL(SM)
SDA
图7-2. I2C Timing Diagram
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OUTx_N
OUTx_P
VOH
VOD = VOH - VOL
VOL
80%
0 V
20%
VOUT-DIFF = 2 × VOD
tR
tF
图7-3. Differential Output Voltage and Rise/Fall Time
80%
OUT_REFx/2
20%
VOUT,SE
tR
tF
图7-4. Single-Ended Output Voltage and Rise/Fall Time
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7.8 Typical Characteristics
Unless otherwise noted: VDD = 3.3 V, VDDO = 1.8 V, TA = 25 °C, AC-LVPECL output measured. DPLL: fREF
=
25 MHz, fTDC = 25 MHz, BWDPLL = 10 Hz, DPLL locked to reference. APLL1: fXO = 48.0048 MHz, fPD1 = 24.0024
MHz (fXO÷2), fVCO1 = 2500 MHz, BWAPLL1 = 2.5 kHz, DPLL mode. APLL2: fPD2 = 138. 8 MHz (fVCO1÷18),
BWAPLL2 = 500 kHz, Cascaded APLL2 mode for 图 7-9 and 图 7-10. The PLL output clock phase noise at
different frequency offsets are determined by different noise contributors, such as external clock input sources
(REF IN, OCXO, XO) and internal noise sources (PLL, VCO), as well as the configured PLL loop bandwidths
(BWREF-DPLL, BWTCXO-DPLL, BWAPLL). The phase noise profile shown for each external clock source (fSOURCE
)
was normalized to the PLL output frequency (fOUT) by adding 20×LOG10(fOUT / fSOURCE) to the measured phase
noise of the source.
Jitter = 40 fs RMS (12 kHz to 20 MHz)
DPLL Mode (APLL2 Disabled)
Jitter = 56 fs RMS (12 kHz to 20 MHz)
DPLL Mode (APLL2 Disabled)
图7-5. 625-MHz Output Phase Noise (APLL1)
图7-6. 156.25-MHz Output Phase Noise (APLL1)
Jitter = 63 fs RMS (12 kHz to 20 MHz)
DPLL Mode (APLL2 Disabled)
Jitter = 74 fs RMS (12 kHz to 20 MHz)
DPLL Mode (APLL2 Disabled)
图7-7. 125-MHz Output Phase Noise (APLL1)
图7-8. 100-MHz Output Phase Noise (APLL1)
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Jitter = 117 fs RMS (12 kHz to 20 MHz)
Jitter = 120 fs RMS (12 kHz to 20 MHz)
DPLL Mode With Cascaded APLL2
fVCO2 = 5598.72 MHz
DPLL Mode With Cascaded APLL2
fVCO2 = 5737.5 MHz
图7-9. 155.52-MHz Output Phase Noise (APLL2)
图7-10. 212.5-MHz Output Phase Noise (APLL2)
0
0
CML
HCSL
LVDS
LVPECL
CML
HCSL
LVCMOS
LVDS
LVPECL
-10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Noise Frequency (Hz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Noise Frequency (kHz)
D002
D001
50-mVpp noise injected onto supplies (VDD = 3.3 V, VDDO =
3.3 V)
25-mVpp noise injected onto supplies (VDD = 3.3 V, VDDO =
1.8 V)
图7-11. PSNR vs. Noise Frequency (50 mVpp) For
图7-12. PSNR vs. Noise Frequency (25 mVpp) For
156.25-MHz Output 1
156.25-MHz Output
1
DJSPUR (ps pk-pk) = 2 × 10(dBc/20) / (π× fOUT) × 1E6, where dBc is the PSNR spur level (in dBc) and fOUT is the output frequency (in
MHz).
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1.8
1.6
1.4
1.2
1
AC-LVDS
AC-CML
AC-LVPECL
0.8
0.6
0.4
0
200
400
600
800
Output frequency (MHz)
1000
1200
1400
D001
图7-13. Output Swing vs Frequency
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8 Parameter Measurement Information
8.1 Output Clock Test Configurations
High-impedance
probe
LVCMOS
DUT
Oscilloscope
2 pF
图8-1. LVCMOS Output Test Configuration
Phase Noise/
Spectrum
Analyzer
LVCMOS
DUT
图8-2. LVCMOS Output Phase Noise Test Configuration
Oscilloscope
(50-ꢀ inputs)
AC-LVPECL, AC-LVDS, AC-CML
DUT
图8-3. AC-LVPECL, AC-LVDS, AC-CML Output AC Test Configuration
Phase Noise/
Spectrum Analyzer
DUT
Balun
AC-LVPECL, AC-LVDS, AC-CML
图8-4. AC-LVPECL, AC-LVDS, AC-CML Output Phase Noise Test Configuration
0 ꢀ
Oscilloscope
(50-ꢀ inputs)
DUT
HCSL
0 ꢀ
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图8-5. HCSL Output Test Configuration
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Opt œ 33 ꢀ
HCSL
Phase Noise/
Spectrum
Analyzer
DUT
Balun
Opt œ 33 ꢀ
HCSL
50 ꢀ
50 ꢀ
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图8-6. HCSL Output Phase Noise Test Configuration
Sine wave
Modulator
Power Supply
Phase Noise/
Spectrum
Analyzer
Signal Generator
DUT
Device Output
Balun
Reference
Input
Single-sideband spur level measured in dBc with a known noise amplitude and frequency injected onto the device power supply.
图8-7. Power Supply Noise Rejection (PSNR) Test Configuration
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9 Detailed Description
9.1 Overview
The LMK05318B has two reference inputs, one digital PLL (DPLL), two analog PLLs (APLLs) with integrated
VCOs, and eight output clocks with a RMS phase jitter of 50-fs typical from APLL1 and 130-fs typical from
APLL2. APLL1 uses an ultra-high performance BAW VCO (VCO1) with a very high quality factor, and thus has
no dependency on the phase noise or frequency of the external oscillator (XO) input clock. This minimizes the
overall solution cost and allows the use of an off-the-shelf XO, TCXO, or OCXO selected to meet the free-run
and holdover frequency stability requirements of the application. APLL1 is cascaded with the DPLL, allowing the
APLL1 domain to be locked to the DPLL reference input for synchronous clock generation. APLL2 can be used
to generate unrelated clock frequencies either locked to the APLL1 domain or the free-running XO input.
The DPLL reference input mux supports automatic input selection or manual input selection through software or
pin control. The device provides hitless switching with proprietary phase cancellation for superior phase transient
performance (±50 ps typical). The reference clock input monitoring block monitors the clock inputs and will
perform a hitless switchover or holdover when a loss of reference (LOR) is detected. A LOR condition can be
detected upon any violation of the threshold limits set for the input monitors, which include amplitude, missing
pulse, runt pulse, and 1-PPS (pulse-per-second) detectors. The threshold limits for each input detector can be
set and enabled per clock input. The tuning word history monitor feature allows the initial output frequency
accuracy upon entry into holdover to be determined by the historical average frequency when locked, minimizing
the frequency and phase disturbance during a LOR condition.
The device has eight outputs with programmable drivers, allowing up to eight differential clocks, or a combination
of differential clocks and up to four 1.8-V LVCMOS pairs (two outputs per pair). The output clocks can be
selected from either APLL/VCO domain through the output muxes. The output dividers have a SYNC feature to
allow multiple outputs to be phase-aligned. A 1-PPS output can be supported on Output 7 (OUT7). If needed,
the user can enable the zero-delay mode (ZDM) synchronization to achieve deterministic phase alignment
between an APLL1 clock on OUT7 and the selected reference input.
To support IEEE 1588 PTP slave clock or other clock steering applications, the DPLL also supports DCO mode
with less than 0.001-ppb (part per billion) frequency resolution for precise frequency and phase adjustment
through external software or pin control.
The device is fully programmable through I2C or SPI and supports custom start-up frequency configuration with
the internal EEPROM, which is factory pre-programmed and in-system programmable if needed. Internal LDO
regulators provide excellent PSNR to reduce the cost and complexity of the power delivery network. The clock
input and PLL monitoring status can be observed through the status pins and interrupt registers for full
diagnostic capability.
9.1.1 ITU-T G.8262 (SyncE) Standards Compliance
The LMK05318B meets the applicable requirements of the ITU-T G.8262 (SyncE) standard. See the ITU-T
G.8262 Compliance Test Result for the LMK05318 (SNAA316) application report for more information.
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9.2 Functional Block Diagram
VDDO (x6)
1.8 / 2.5 / 3.3 V
VDD (x5)
3.3 V
Power Conditioning
(all blocks)
Outputs
SYNC
Reference Inputs
APLL1
OUT0
VCO1
÷R
5-b
0
1
2
3
×1, ×2
XO
0
1
÷OD
8-b
PFD
OUT1
OUT2
÷N
40-b Frac-N
PRIREF
0
1
2
3
DPLL
÷OD
8-b
÷R
16-b
TDC
OUT3
OUT4
SECREF
REFSEL
÷FB
40-b Frac-N
Input
Monitors
0
1
2
3
÷OD
8-b
FINC/FDEC
DCO
0
1
2
3
÷RP
/3 to /6
÷RS
/1 to /32
÷OD
8-b
OUT5
OUT6
OUT7
Post
Dividers
APLL2
VCO2
2
3
PFD
/2 to /7
Digital
0
1
2
3
÷OD
8-b
SDA/SDI
SCL/SCK
EEPROM
ROM
I2C/
SPI
÷N
Registers
/2 to /7
24-b Frac-N
GPIO2/SDO/FINC
GPIO1/SCS
0
1
2
3
GPIO0/SYNCN
PLL
Monitors
÷OD
8-b × 24-b
Device Control and Status
HW_SW_CTRL
PDN
STATUS1/FDEC
STATUS0
LF1
LF2
CAP
(x3)
图9-1. Top-Level Device Block Diagram
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9.2.1 PLL Architecture Overview
图 9-2 shows the PLL architecture implemented in the LMK05318B. The primary "PLL1" channel consists of a
digital PLL (DPLL) and analog PLL (APLL1) with integrated BAW VCO (VCO1) capable of generating clocks with
RMS phase jitter of 50-fs typical. A secondary APLL (APLL2) with integrated LC VCO (VCO2) can be used as an
additional clock generation domain with RMS phase jitter of 130-fs typical.
The DPLL is comprised of a time-to-digital converter (TDC), digital loop filter (DLF), and 40-bit fractional
feedback (FB) divider with sigma-delta-modulator (SDM). The APLLs are comprised of a reference (R) divider,
phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO. APLL2 has
a reference selection mux that allows APLL2 to be either locked to the VCO domain of the APLL1 (Cascaded
APLL2) or locked to the XO input (Non-Cascaded APLL2). Otherwise, APLL2 can be disabled (powered-down) if
this clock domain is not needed. The VCO of the APLL1 feeds the output clock distribution blocks directly,
whereas the VCO of the APLL2 drives the clock distribution blocks through the VCO post-dividers.
Post
Dividers
APLL2
fPD2
VCO2
0
1
fVCO2/P1
fVCO2
PFD
LF
÷P1
R Dividers
÷RP
/2 to /7
÷N
24-bit Frac-N SDM
fVCO2/P2
/3 to /6
÷P2
To
Output
Muxes
÷RS
/1 to /32
×1, ×2
XO
DPLL
APLL1
PRIREF
0
1
fPD1
fTDC
VCO1
÷R
5-bit
÷R
fVCO1
SECREF
TDC
DLF
LF
PFD
16-bit
(x2)
÷FB
40-bit Frac-N SDM
÷N
40-bit Frac-N SDM
fVCO1
÷PR
÷2
To
Output
Muxes
38-bit
DCO option
FINC/FDEC
DCO
FDEV
DPLL feedback clock
A. DCO frequency adjustments can be software or pin controlled.
图9-2. PLL Architecture
The following sections describe the basic principle of operation for DPLL mode and APLL-only mode. See 节
9.4.2 for more details on the PLL modes of operation including holdover.
9.2.2 DPLL Mode
In DPLL mode, the external XO input source determines the free-run and holdover frequency stability and
accuracy of the output clocks. The BAW VCO1 determines the APLL1 output clock phase noise and jitter
performance over the 12-kHz to 20-MHz integration band, regardless of the frequency and jitter of the XO input.
This allows the use a cost-effective, low-frequency TCXO or OCXO as the external XO input to support
standards-compliant frequency stability and low loop bandwidth (≤10 Hz) required in synchronization
applications like SyncE and IEEE 1588.
The principle of operation for DPLL mode after power-on reset and initialization is as follows. If APLL2 is in
Cascaded mode as shown in 图 9-3, VCO1 is held at the nominal center frequency of 2.5 GHz while APLL2
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locks. Then APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. Once a
valid DPLL reference input is detected, the DPLL begins lock acquisition. The DPLL TDC compares the phase of
the selected reference input clock and the FB divider clock (from VCO1) and generates a digital correction word
corresponding to the phase error. The correction word is filtered by the DLF, and the DLF output controls the
APLL1 N divider SDM to pull the VCO1 frequency into lock with the reference input. VCO2 will track the VCO1
domain during DPLL lock acquisition and locked modes, allowing the user to synchronize the clock domain of
the APLL2 to the DPLL reference input. Cascading APLL2 provides a high-frequency, ultra-low-jitter reference
clock from VCO1 to minimize the APLL2 in-band phase noise/jitter impact that would otherwise occur if the
reference of the APLL2 is from a XO/TCXO/OCXO with low frequency and/or high phase noise floor.
If APLL2 is not cascaded as shown in 图 9-4, VCO2 will lock to the XO input after initialization and operate
independently of the DPLL/APLL1 domain.
When all reference inputs to the DPLL are lost, the PLLs will enter holdover mode and track the stability and
accuracy of the external XO source.
If DCO mode is enabled on the DPLL, a frequency deviation step value (FDEV) can be programmed and used to
adjust (increment or decrement) the FB divider SDM of the DPLL, where the frequency adjustment effectively
propagates through the APLL1 domain (and APLL2 domain if cascaded) to the output clocks.
The programmed DPLL loop bandwidth (BWDPLL) should be lower than all of the following:
1. 1/100th of the DPLL TDC rate
2. the APLL1 loop bandwidth (1 to 10 kHz typical)
3. the maximum DPLL bandwidth setting of 4 kHz.
Post
Dividers
APLL2
fPD2
VCO2
0
1
fVCO2/P1
fVCO2
PFD
LF
÷P1
R Dividers
÷RP
/2 to /7
÷N
24-bit Frac-N SDM
fVCO2/P2
/3 to /6
÷P2
To
Output
Muxes
÷RS
/1 to /32
×1, ×2
XO
DPLL
APLL1
PRIREF
0
1
fPD1
fTDC
VCO1
÷R
5-bit
÷R
fVCO1
SECREF
TDC
DLF
LF
PFD
16-bit
(x2)
÷FB
40-bit Frac-N SDM
÷N
40-bit Frac-N SDM
fVCO1
÷PR
÷2
To
Output
Muxes
38-bit
DCO option
FINC/FDEC
DCO
FDEV
DPLL feedback clock
图9-3. DPLL Mode With Cascaded APLL2
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Post
Dividers
APLL2
fPD2
VCO2
0
1
fVCO2/P1
fVCO2
PFD
LF
÷P1
R Dividers
÷RP
/2 to /7
÷P2
÷N
24-bit Frac-N SDM
fVCO2/P2
/3 to /6
To
Output
Muxes
÷RS
/1 to /32
×1, ×2
XO
DPLL
APLL1
PRIREF
0
1
fPD1
fTDC
VCO1
÷R
5-bit
÷R
fVCO1
SECREF
TDC
DLF
LF
PFD
16-bit
(x2)
÷FB
40-bit Frac-N SDM
÷N
40-bit Frac-N SDM
fVCO1
÷PR
÷2
To
Output
Muxes
38-bit
DCO option
FINC/FDEC
DCO
FDEV
DPLL feedback clock
图9-4. DPLL Mode With Non-Cascaded APLL2
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9.2.3 APLL-Only Mode
In APLL-only mode, the external XO input source determines the free-run frequency stability and accuracy of the
output clocks. The BAW VCO1 determines the APLL1 output clock phase noise and jitter performance over the
12-kHz to 20-MHz integration band, regardless of the frequency and jitter of the XO input.
The principle of operation for APLL-only mode after power-on reset and initialization is as follows. If APLL2 is in
Cascaded mode as shown in 图 9-5, VCO1 is held at the nominal center frequency of 2.5 GHz while APLL2
locks. Then APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. The DPLL
blocks are not used and do not affect the APLLs. VCO2 will track the VCO1 domain. Cascading APLL2 provides
a high-frequency, ultra-low-jitter reference clock from VCO1 to minimize the APLL2 in-band phase noise/jitter
impact that would occur otherwise if the reference of the APLL2 is from a XO/TCXO/OCXO with low frequency,
high phase noise floor, or both.
If APLL2 is not cascaded as shown in 图 9-4, VCO2 will lock to the XO input after initialization and operate
independent of the DPLL/APLL1 domain.
Post
Dividers
APLL2
fPD2
VCO2
0
1
fVCO2/P1
fVCO2
PFD
LF
÷P1
R Dividers
÷RP
/3 to /7
÷N
24-bit Frac-N SDM
fVCO2/P2
/3 to /6
÷P2
To
Output
Muxes
÷RS
/1 to /32
×1, ×2
XO
DPLL
APLL1
PRIREF
0
1
fPD1
fTDC
VCO1
÷R
5-bit
÷R
fVCO1
SECREF
TDC
DLF
LF
PFD
16-bit
(x2)
÷FB
40-bit Frac-N SDM
÷N
40-bit Frac-N SDM
fVCO1
÷PR
÷2
To
Output
Muxes
38-bit
DCO option
FINC/FDEC
DCO
FDEV
DPLL feedback clock
图9-5. APLL-Only Mode With Cascaded APLL2
9.3 Feature Description
The following sections describe the features and functional blocks of the LMK05318B.
9.3.1 Oscillator Input (XO_P/N)
The XO input is the reference clock for the fractional-N APLLs. The XO input determines the output frequency
accuracy and stability in free-run or holdover modes.
For DPLL mode, the XO frequency must have a non-integer relationship with the VCO1 frequency so APLL1
can operate in fractional mode. For APLL-only mode, the XO frequency can have an integer or fractional
relationship with the VCO1 and/or VCO2 frequencies.
In DPLL mode applications, such as SyncE and IEEE 1588, the XO input can be driven by a low-frequency
TCXO, OCXO, or external traceable clock that conforms to the frequency accuracy and holdover stability
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required by the applicable synchronization standard. TCXO and OCXO frequencies of 12.8, 19.2, 19.44, 24,
24.576, and 30.72 MHz are commonly available and cost-effective options that allow the APLL1 to operate in
fractional mode for a VCO1 frequency of 2.5 GHz.
An XO/TCXO/OCXO source with low-frequency or a high-phase jitter/noise floor will have no impact on the
output jitter performance because the BAW VCO determines the jitter and phase noise over the 12-kHz to 20-
MHz integration bandwidth.
The XO input buffer has programmable input on-chip termination and AC-coupled input biasing configurations as
shown in 图9-6. The buffered XO path also drives the input monitoring blocks.
28 pF
XO_P
100 kꢀ
S1
S2
VAC-DIFF
(weak bias)
Differential or
Single-Ended*
S3
50 ꢀ
100 ꢀ
XO path
S2
100 kꢀ
28 pF
XO_ N
*Supports 2.5-V
single-ended swing
S1
50 ꢀ
图9-6. XO Input Buffer
表9-1 lists the typical XO input buffer configurations for common clock interface types.
表9-1. XO Input Buffer Modes
INTERNAL SWITCH SETTINGS
XO_TYPE
INPUT TYPES
INTERNAL TERM. (S1, S2)(1)
INTERNAL BIAS (S3)(2)
Differential
(DC-coupled or AC-coupled)
1h
OFF
ON (1.3 V)
Differential
(AC-coupled or DC-coupled, Internal 100-
3h
ON (1.3 V)
100 Ω
Ω)
HCSL
4h
8h
Ch
OFF
OFF
OFF
50 Ω
OFF
(DC-coupled, internal 50-Ω)
LVCMOS
(DC-coupled)
Single-ended
(DC-coupled, internal 50-Ω)
50 Ω
(1) S1, S2: OFF = External termination is assumed.
(2) S3: OFF = External input bias or DC coupling is assumed.
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9.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)
The reference inputs (PRIREF and SECREF) can accept differential or single-ended clocks. Each input has
programmable input type, termination, and AC-coupled input biasing configurations as shown in .Each input
buffer drives the reference input mux of the DPLL block. The DPLL input mux can select from any of the
reference inputs. The DPLL can switch between inputs with different frequencies provided they can be divided-
down to a common frequency by DPLL R dividers. The reference input paths also drive the various detector
blocks for reference input monitoring and validation.
To LVCMOS
Slew Rate Detector
S5
PRIREF_P/
SECREF_P
7 pF
VAC-DIFF
(Weak bias)
Differential or
Single-Ended
REF path
GND
7 pF
PRIREF_N/
SECREF_N
GND
图9-7. Reference Input Buffer
表9-2 lists the reference input buffer configurations for common clock interface types.
表9-2. Reference Input Buffer Modes
INTERNAL SWITCH SETTINGS
LVCMOS INTERNAL
AC CAPACITOR
REFx_TYPE,
REF_DC_MODE
INPUT TYPES
INTERNAL TERM.
(S1, S2)
LVCMOS SLEW RATE
DETECT (S4)(1)
BYPASS MODE (S5)
(2)
Differential
(DC-coupled or AC-coupled)
0h, 0h
3h, 0h
4h, 0h
OFF
100 Ω
50 Ω
OFF
OFF
OFF
OFF
OFF
OFF
Differential
(AC-coupled, internal 100-Ω)
HCSL
(DC-coupled, internal 50-Ω)
LVCMOS
(DC-coupled, internal AC-coupling
enabled)
8h, 0h
OFF
ON
OFF
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表9-2. Reference Input Buffer Modes (continued)
INTERNAL SWITCH SETTINGS
LVCMOS INTERNAL
AC CAPACITOR
REFx_TYPE,
REF_DC_MODE
INPUT TYPES
INTERNAL TERM.
(S1, S2)
LVCMOS SLEW RATE
DETECT (S4)(1)
BYPASS MODE (S5)
(2)
LVCMOS
(DC-coupled, Internal AC-coupling
disabled)
8h, 1h
Ch, 0h
OFF
OFF
ON
ON
Single-ended
(DC-coupled, internal 50-Ω, Internal AC-
coupling enabled)
OFF
50 Ω
(1) S4: OFF = Differential input amplitude detector is used for all input types except LVCMOS or Single-ended.
(2) S5: OFF = Internal AC Coupling capacitor (7pF) is used. Switch S5 is set by REF_DC_MODE register. R40[3] can be used to set S5
for Primary Reference. R40[2] can be used to set S5 for Secondary Reference.
9.3.2.1 Programmable Input Hysteresis
For differential/single-ended/LVCMOS input buffers, Input hysteresis can be set to 50 mV or 200 mV in AC-
coupling mode. In DC-coupling code, non-programmable Input hysteresis can be enabled/disabled.
表9-3. Programmable Hysteresis Mode
R40[2] - FOR PRIREF INPUT, R40[3] - FOR R45[0] - FOR PRIREF INPUT, R45[1] - FOR
DESCRIPTION
SECREF INPUT
SECREF INPUT
Sets AC-coupled buffer hysteresis voltage to
50 mV
0h
0h
Sets AC-coupled buffer hysteresis voltage to
200 mV
0h
1h
1h
1h
0h
1h
Enables DC hysteresis
Disables DC hysteresis
9.3.3 Clock Input Interfacing and Termination
These figures show the recommended input interfacing and termination circuits. Unused clock inputs can be left
floating or pulled down.
VDD
Rs
R1
R2
LVCMOS
Driver
XO_P
XO_N
50 W
Rs = 50 œ ROUT
LMK05318B
(ROUT
)
VDD
3.3 V
2.5 V
1.8 V
R1 (ꢀ) R2 (ꢀ)
125
0
375
open
open
0
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图9-8. Single-Ended LVCMOS to XO Input (XO_P)
Rs
LVCMOS
3.3V LVCMOS
Driver
LMK05318B
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图9-9. Single-Ended LVCMOS (1.8, 2.5, 3.3 V) to Reference (PRIREF_P/SECREF_P)
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Vcco
LVPECL Driver
LVPECL
LMK05318B
50 ꢀ
50 ꢀ
Vcco œ 2 V
图9-10. DC-Coupled LVPECL to Reference (PRIREF_P/SECREF_P) or XO Inputs
LMK05318B
LVDS Driver
100 ꢀ
LVDS
Copyright © 2020, Texas Instruments Incorporated
图9-11. DC-Coupled LVDS to Reference (PRIREF/SECREF) or XO Inputs
CML
Driver
LMK05318B
CML
Copyright © 2020, Texas Instruments Incorporated
图9-12. DC-Coupled CML (Source Terminated) to Reference (PRIREF/SECREF) or XO Inputs
50 ꢀ
HCSL
Driver
LMK05318B
HCSL
50 ꢀ
Copyright © 2020, Texas Instruments Incorporated
图9-13. HCSL (Load Terminated) to Reference (PRIREF/SECREF) or XO Inputs
Driver
LVDS
RB (ꢀ)
open
open
150
LMK05318B
Differential
Driver
100 ꢀ
CML*
3.3-V LVPECL
2.5-V LVPECL
HCSL
82
Internal input biasing
RB
RB
50
*CML driver has 50-ꢀ pull-up
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图9-14. AC-Coupled Differential to Reference (PRIREF/SECREF) or XO Inputs
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9.3.4 Reference Input Mux Selection
For the DPLL block, the reference input mux selection can be done automatically using an internal state
machine with a configurable input priority scheme, or manually through software register control or hardware pin
control. The input mux can select from PRIREF or SECREF. The priority for all inputs can be assigned through
registers. The priority ranges from 0 to 2, where 0 = ignore (never select), 1 = first priority, and 2 = second
priority. When both inputs are configured with the same priority setting, PRIREF will be given first priority. The
selected input can be monitored through the status pins or register.
9.3.4.1 Automatic Input Selection
There are two automatic input selection modes that can be set by register: Auto Revertive and Auto Non-
Revertive.
• Auto Revertive: In this mode, the DPLL automatically selects the valid input with the highest configured
priority. If a clock with higher priority becomes valid, the DPLL will automatically switch over to that clock
immediately.
• Auto Non-Revertive: In this mode, the DPLL automatically selects the highest priority input that is valid. If a
higher priority input because valid, the DPLL will not switch-over until the currently selected input becomes
invalid.
9.3.4.2 Manual Input Selection
There are two manual input selection modes that can be set by a register: Manual with Auto-Fallback and
Manual with Auto-Holdover. In either manual mode, the input selection can be done through register control (see
表9-4) or hardware pin control (see 表9-5).
• Manual with Auto-Fallback: In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically fallback to the highest priority
input that is valid or qualified. If no prioritized inputs are valid, the DPLL will enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
• Manual with Auto-Holdover: In this mode, the manually selected reference is the active reference until it
becomes invalid. If the reference becomes invalid, the DPLL will automatically enter holdover mode (if tuning
word history is valid) or free-run mode. The DPLL will exit holdover mode when the selected input becomes
valid.
表9-4. Manual Input Selection by Register Bits
DPLL_REF_MAN_REG_SEL BIT
DPLLx_REF_MAN_SEL BIT
SELECTED INPUT
PRIREF
0
1
0
0
SECREF
表9-5. Manual Input Selection by Hardware Pins
REFSEL PIN
DPLL_REF_MAN_SEL BIT
SELECTED INPUT
PRIREF
0
1
1
1
Float (VIM
)
Auto Select
SECREF
1
The reference input selection flowchart is shown in 图9-15.
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See Device POR and
PLL Initialization and
DPLL Modes Flowcharts
DPLL
Locked
Yes: With
Auto-Holdover
Yes: Auto
Revertive
No
Input Select Mode
= Manual?
Input Select Mode
= Auto?
Yes: With
Auto-Fallback
LOR on
Selected Input, or
Higher Priority Input
Valid?
Yes: Auto
Non-Revertive
No
No
Loss of Ref (LOR)
on Selected Input?
Yes
No
Loss of Ref (LOR) on
Selected Input?
Yes
Yes
Holdover Mode
Holdover Mode
No
No
Higher Priority
Input Valid?
Manually Selected
Input Valid?
Yes: Auto-Switch
according to Priority
settings
Yes: Switch to
Selected Input
Lock Acquisition
(Fastlock, Hitless Switch)
图9-15. Reference Input Selection Flowchart
9.3.5 Hitless Switching
The DPLL supports hitless switching through TI's proprietary phase cancellation scheme. When hitless switching
is enabled, it will prevent a phase transient (phase hit) from propagating to the outputs when the two switched
inputs have a fixed phase offset and are frequency-locked. The inputs are frequency-locked when they have
same exact frequency (0-ppm offset), or have frequencies that are integer-related and can each be divided to a
common frequency by integers. When hitless switching is disabled, a phase hit equal to the phase offset
between the two inputs will be propagated to the output at a rate determined by the DPLL fastlock bandwidth.
The hitless switching specifications (tHITLESS and fHITLESS) are valid for reference inputs with no wander. In the
case where two inputs are switched but are not frequency-locked, the output smoothly transitions to the new
frequency with reduced transient.
9.3.5.1 Hitless Switching With 1-PPS Inputs
Hitless switching between 1-PPS inputs is supported when zero-delay mode (ZDM) synchronization is disabled,
but the switchover event should only occur after the DPLL has acquired lock. If a switchover occurs before the
DPLL has locked initially, the switchover will not be hitless and the DPLL will take an indeterminate amount of
time to lock. In this case, a soft-reset should be issued for the DPLL to lock to the selected input. In an
application, the system host can monitor the DPLL lock status through a STATUS pin or bit to determine when
the DPLL has locked before allowing a switchover between 1-PPS inputs. The DPLL lock time is governed by
the DPLL bandwidth (typically 10 mHz for a 1-PPS input).
Hitless switching between 1-PPS inputs is not supported when ZDM synchronization is enabled.
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9.3.6 Gapped Clock Support on Reference Inputs
The DPLL supports locking to an input clock that has missing periods and is referred to as a gapped clock.
Gapping severely increases the jitter of a clock, so the DPLL provides the high input jitter tolerance and low loop
bandwidth necessary to generate a low-jitter periodic output clock. The resulting output will be a periodic non-
gapped clock with an average frequency of the input with its missing cycles. The gapped clock width cannot be
longer than the reference clock period after the R divider (RPRI/SECREF / fPRI/SECREF). The reference input
monitors should be configured to avoid any flags due to the worst-case clock gapping scenario to achieve and
maintain lock. Reference switchover between two gapped clock inputs may violate the hitless switching
specification if the switch occurs during a gap in either input clock.
9.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
The following section describes the input clock and PLL monitoring, status, and interrupt features.
XO
Status Bits
EN
LOS_XO_FDET
LOS_XO_FDET
Frequency
XO Input Monitor
Ref Inputs
PRIREF
SECREF
REF
Mux
÷R
PLLs
Clock Status
Ref Input Monitors (x2)
EN
DIFF: Min. Swing
LVCMOS: Slew rate
Amplitude
EN
EN
EN
EN
LOR
Validation Timer
PRI/SECREF
Valid
Late detect window
Early detect window
Jitter threshold
Missing pulse
Runt pulse
LOR_AMP
Starts when LOR‰0
DPLL
Selected
Input
LOR_FREQ
LOR_MISSCLK
REFSWITCH
Valid time
Phase valid*
5
Detector Status (1 = fault)
PRI/SECREF
Status
*Enable for 1-PPS input
图9-16. Clock Monitors for Reference and XO Inputs
9.3.7.1 XO Input Monitoring
The XO input has a coarse frequency monitor to help qualify the input before it is used to lock the APLLs.
The XO frequency detector clears its LOS_XO_FDET flag when the input frequency is detected within the
supported range of 10 MHz to 100 MHz. The XO frequency monitor uses a RC-based detector and cannot
precisely detect if the XO input clock has sufficient frequency stability to ensure successful VCO calibration
during the PLL start-up when the external XO clock has a slow or delayed start-up behavior. See 节 10.1.4 for
more information.
The XO frequency detector can be bypassed by setting the XO_FDET_BYP bit (shown as EN in 图9-16) so that
the XO input is always considered valid by the PLL control state machine. The user can observe the
LOS_XO_FDET status flag through the status pins and status bit.
9.3.7.2 Reference Input Monitoring
Each DPLL reference clock input is independently monitored for input validation before it is qualified and
available for selection by the DPLL. The reference monitoring blocks include amplitude, missing pulse, and runt
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pulse monitors. For a 1-PPS input, the phase valid monitor and LVCMOS input amplitude monitor are supported,
while the differential input amplitude, missing pulse, and runt pulse monitors are not supported and must be
disabled. A validation timer sets the minimum time for all enabled reference monitors to be clear of flags before
an input is qualified.
The enablement and valid threshold for all reference monitors and validation timers are programmable per input.
The reference monitors and validation timers are optional to enable, but are critical to achieve reliable DPLL lock
and optimal transient performance during holdover or switchover events, and are also used to avoid selection of
an unreliable or intermittent clock input. If a given detector is not enabled, it will not set a flag and will be ignored.
The status flag of any enabled detector can be observed through the status pins for any reference input
(selected or not selected). The status flags of the enabled detectors can also be read through the status bits for
the selected input of the DPLL.
9.3.7.2.1 Reference Validation Timer
The validation timer sets the amount of time for each reference to be clear of flags from all enabled input
monitors before the timer is qualified and valid for selection. The validation timer and enable settings are
programmable.
9.3.7.2.2 Amplitude Monitor
The reference amplitude detector determines if the input meets the amplitude-related threshold depending on
the input buffer configuration. For differential input mode, the amplitude detector clears its LOR_AMP flag when
the differential input voltage swing (peak-to-peak) is greater than the minimum threshold selected by the
registers (400, 500, or 600 mVpp nominal). For LVCMOS input mode, the input slew rate detector clears its
LOR_AMP flag when its slew rate is faster than 0.2 V/ns on the clock edge selected by the registers (rising edge,
falling edge, or both edges). If either the differential or LVCMOS input clock does not meet the specified
thresholds, the amplitude detector will set the LOR_AMP flag and disqualify the input.
If the input frequency is below 5 MHz, the differential input detector may signal a false flag. In this case, the
amplitude detector should be disabled and at least one other input monitor (frequency, window, or 1-PPS phase
valid detector) should be enabled to validate the input clock. The LVCMOS input detector can be used for low-
frequency clocks down to 1 Hz or 1 PPS.
9.3.7.2.3 Frequency Monitoring
The precision frequency detector measures the frequency offset or error (in ppm) of all input clocks relative to
the frequency accuracy of the XO input, which is considered as the "0-ppm reference clock" for frequency
comparison. The valid and invalid ppm frequency thresholds are configurable through the registers. The monitor
will clear the LOR_FREQ flag when the relative input frequency error is less than the valid ppm threshold.
Otherwise, the monitor will set the LOR_FREQ flag when the relative input frequency error is greater than the
invalid ppm threshold. The ppm delta between the valid and invalid thresholds provides hysteresis to prevent the
LOR_FREQ flag from toggling when the input frequency offset is crossing these thresholds.
A measurement accuracy (ppm) and averaging factor are used in computing the frequency detector register
settings. A higher measurement accuracy (smaller ppm) or higher averaging factor will increase the
measurement delay to set or clear the flag, which allow more time for the input frequency to settle, and can also
provide better measurement resolution for an input with high drift or wander. Note that higher averaging reduces
the maximum frequency ppm thresholds that can be configured.
9.3.7.2.4 Missing Pulse Monitor (Late Detect)
The missing pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal
clock period plus a programmable late window threshold (TLATE). When an input pulse arrives before TLATE, the
pulse is considered valid and the missing pulse flag will be cleared. When an input pulse does not arrive before
TLATE (due to a missing or late pulse), the flag will be set immediately to disqualify the input.
Typically, TLATE should be set higher than the longest clock period (including cycle-to-cycle jitter) of the input, or
higher than the gap width for a gapped clock. The missing pulse monitor can act as a coarse frequency detector
with faster detection than the ppm frequency detector. The missing pulse monitor is supported for input
frequencies between 2 kHz and fVCO1/12 and should be disabled when outside this range.
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The missing pulse and runt pulse monitors operate from the same window detector block for each reference
input. The status flags for both these monitors are combined by logic-OR gate and can be observed through
status pin. The window detector flag for the selected DPLL input can also be observed through the
corresponding MISSCLK status bit.
9.3.7.2.5 Runt Pulse Monitor (Early Detect)
The runt pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal clock
period minus a programmable early window threshold (TEARLY). When an input pulse arrives after TEARLY, the
pulse is considered valid and the runt pulse flag will be cleared. When an early or runt input pulse arrives before
TEARLY, the monitor will set the flag immediately to disqualify the input.
Typically, TEARLY should be set lower than the shortest clock period (including cycle-to-cycle jitter) of the input.
The early pulse monitor can act as a coarse frequency detector with faster detection than the ppm frequency
detector. The early pulse monitor is supported for input frequencies between 2 kHz and fVCO1/12 and should be
disabled when outside of this range.
Ideal Reference Period
Ideal Edge
Ideal Reference Input
(rising-edge triggered)
Early Pulse (Input disqualified at this input rising edge)
Example A: Input with
Early (Runt) Pulse
Late Pulse (Input disqualified after TLATE
)
Example B: Input with
Missing (Late) Pulse
Gapped Clock (To avoid disqualifying input at the
missing clock cycle, set TLATE window > Gap width)
Example C: Input with
Missing (Gapped) Clock
Gap width
Valid
Invalid
Valid Windows
Valid Window size can be relaxed by increasing the Window size.
Window Step Size = 2 / fVCO1
Early Window
)
(TEARLY
Late Window
)
(TLATE
Minimum Valid Window
is 3 × (2 / fVCO1
)
图9-17. Early and Late Window Detector Examples
9.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
The phase valid monitor is designed specifically for 1-PPS input validation because the frequency and window
detectors do not support this mode. The phase valid monitor uses a window detector to validate 1-PPS input
pulses that arrive within the nominal clock period (TIN) plus a programmable jitter threshold (TJIT). When the
input pulse arrives within the counter window (TV), the pulse is considered valid and the phase valid flag will be
cleared. When the input pulse does not arrive before TV (due to a missing or late pulse), the flag will be set
immediately to disqualify the input. TJIT should be set higher than the worst-case input cycle-to-cycle jitter.
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Ideal Edge
(TIN < TV
Counter resets at
valid edge (TIN‘ < TV)
Counter time-out (TIN‘‘ > TV).
Input is disqualified here
)
Late Pulse
(Large peak jitter)
Ideal Input Period
TIN
TIN‘
TIN‘‘
TIN‘ > TIN
TIN‘‘ >> TIN
Example:
1-PPS Input
TJIT
Valid Counter (TV)
TV = TIN + TJIT
TV
TV
图9-18. 1-PPS Input Window Detector Example
9.3.7.3 PLL Lock Detectors
The loss-of-lock (LOL) status is available for each APLL and the DPLL. The APLLs are monitored for loss-of-
frequency lock only. The DPLL is monitored for both loss-of-frequency lock (LOFL) and loss-of-phase lock
(LOPL). The DPLL lock threshold and loss-of-lock threshold are programmable for both LOPF and LOFL
detectors.
The DPLL frequency lock detector will clear its LOFL flag when the frequency error of the DPLL relative to the
selected reference input is less than the lock ppm threshold. Otherwise, it will set the LOFL flag when the
frequency error of the DPLL is greater than the unlock ppm threshold. The ppm delta between the lock and
unlock thresholds provides hysteresis to prevent the LOFL flag from toggling when the DPLL frequency error is
crossing these thresholds.
A measurement accuracy (ppm) and averaging factor are used in computing the frequency lock detector register
settings. A higher measurement accuracy (smaller ppm) or higher averaging factor will increase the
measurement delay to set or clear the LOFL flag. Higher averaging may be useful when locking to an input with
high wander or when the DPLL is configured with a narrow loop bandwidth. Note that higher averaging reduces
the maximum frequency ppm thresholds that can be configured.
The DPLL phase lock detector will clear its LOPL flag when the phase error of the DPLL is less than the phase
lock threshold. Otherwise, the lock detector will set the LOPL flag when the phase error is greater than the phase
unlock threshold.
Users can observe the APLL and DPLL lock detector flags through the status pins and the status bits.
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PLLs
Status Bits
2
DPLL Frequency Lock
Detector
APLL Lock
Detectors
LOL_PLL[1:2]
Lock
Unlock
LOFL
LOL_PLL1
APLL
LOL_PLL2
Thresh
(ppm)
Thresh
(ppm)
XO
APLL1
APLL2
fVCO1
fTDC
DPLL
PLLs Status
Free-run
Tuning Word
LOFL_DPLL
DPLL Phase Lock
Detector
LOPL_DPLL
LOPL
DPLL
HIST
Lock
Unlock
Tuning Word History
History
Update
HLDOVR
Count
Delay
Holdover
Active
Thresh
(ns)
Thresh
(ns)
EN Average Ignore
time time
图9-19. PLL Lock Detectors and History Monitor
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9.3.7.4 Tuning Word History
The DPLL domain has a tuning word history monitor block that determines the initial output frequency accuracy
upon entry into holdover. The tuning word can be updated from one of three sources depending on the DPLL
operating mode:
1. Locked Mode: From the output of the digital loop filter when locked
2. Holdover Mode: From the final output of the history monitor
3. Free Run Mode: From the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, it effectively averages the reference input
frequency by accumulating history from the digital loop filter output during a programmable averaging time
(TAVG). Once the input becomes invalid, the final tuning word value is stored to determine the initial holdover
frequency accuracy. Generally, a longer TAVG time will produce a more accurate initial holdover frequency. The
stability of the 0-ppm reference clock (XO input) determines the long-term stability and accuracy of the holdover
output frequency.
There is also a separate programmable delay timer (TIGN) that can be set to ignore the history data that is
corrupted just prior to entry into holdover. The history data could be corrupted if a tuning word update occurs
while the input clock is failing and before it is detected by the input monitors. Both TAVG and TIGN times are
programmable through the HISTCNT and HISTDLY register bits, respectively, and are related to the TDC rate.
The tuning word history is initially cleared after a device hard-reset or soft-reset. After the DPLL locks to a new
reference, the history monitor waits for the first TAVG timer to expire before storing the first tuning word value and
begins to accumulate history. The history monitor will not clear the previous history value during reference
switchover or holdover exit. The history can be manually cleared or reset by toggling the history enable bit
(HIST_EN = 1 →0 →1), if needed.
Initial start of history
when LOFL‰ 0 only
Ref Lost
LOR‰ 1
Ref Valid
LOR‰ 0
Ref Valid
LOR‰ 0
History
Reset
No History
History Data Accumulating
History Valid
History Data Accumulating
TAVG(0)
TAVG(1)
TIGN
TAVG(2..n)
History Delay(1)
Delay to ignore
history updates
prior to LOR.
History Count(1)
Timer to average history data to
compute initial holdover frequency accuracy.
Initial holdover
frequency determined
by averaged history.
Previous history is persistent
(not cleared or reset after
exiting holdover).
Time
Free Run Lock Acq.
LOFL = 1, LOPL = 1
Locked
LOFL‰ 0, then LOPL‰ 0
Holdover
LOFL = 0, LOPL‰ 1
Lock Acq.
Locked
LOFL = 0, LOPL = 1 LOFL = 0, LOPL‰ 0
(1) History count and delay windows are programmable.
图9-20. Tuning Word History Windows
If the TAVG period is set very long (minutes or hours) to obtain a more precise historical average frequency, it is
possible for a switchover or holdover event to occur before the first tuning word is stored and available for use.
To overcome this, there is an intermediate history update option (HIST_INTMD). If the history is reset, then the
intermediate average can be updated at intervals of TAVG/2K , where K = HIST_INTMD to 0, during the first TAVG
period only. If HIST_INTMD = 0, there is no intermediate update and the first average is stored after the first
TAVG period. However, if HIST_INTMD = 4, then four intermediate averages are taken at TAVG/16, TAVG/8,
TAVG/4, and TAVG/2, as well as at TAVG. After the first TAVG period, all subsequent history updates occur at the
TAVG period.
When no tuning word history exists, the free-run tuning word value (TUNING_FREE_RUN) determines the initial
holdover output frequency accuracy.
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9.3.7.5 Status Outputs
The STATUS0 and STATUS1 pins can be configured to output various status signals and interrupt flags for
device diagnostics and debug purposes. The status signal, output driver type, and output polarity settings are
programmable. The status signals available at these pins are listed in 表9-6. When the status signal is asserted,
the status output will be driven high (active high), assuming the output polarity is not inverted (or active low).
表9-6. Status Pin Signals Available per Device Block
DEVICE BLOCK MONITORED
STATUS SIGNAL (ACTIVE HIGH)
XO
XO Loss of Signal (LOS)
APLLx Lock Detected ( LOL)
APLLx VCO Calibration Active
APLLx N Divider, divide-by-2
APLL1 and APLL2
APLLx Digital Lock Detect (DLD)
APLL2 R Divider, divide-by-2
EEPROM
EEPROM Active
All Inputs and PLLs
Interrupt (INTR)
PRIREF/SECREF Monitor Divider Output, divide-by-2
PRIREF/SECREF Amplitude Monitor Fault
PRIREF/SECREF Missing or Early Pulse Monitor Fault
PRIREF/SECREF Validation Timer Active
PRIREF/SECREF Phase Validation Monitor Fault
DPLL R Divider, divide-by-2
PRIREF and SECREF
DPLL FB Divider, divide-by-2
DPLL Phase Lock Detected ( LOPL)
DPLL PRIREF/SECREF Selected
DPLL Holdover Active
DPLL
DPLL Reference Switchover Event
DPLL Tuning History Update
DPLL FastLock Active
DPLL Loss of Lock (LOFL)
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9.3.7.6 Interrupt
Any of the two status pins can be configured as a device interrupt output pin. The interrupt logic configuration is
set through registers. When the interrupt logic is enabled, the interrupt output can be triggered from any
combination of interrupt status indicators, including LOS for the XO, LOR for the selected DPLL input, LOL for
each APLL and the DPLL, and holdover and switchover events for the DPLL. When the interrupt polarity is set
high, a rising edge on the live status bit will assert its interrupt flag (sticky bit). Otherwise, when the polarity is set
low, a falling edge on the live status bit will assert its interrupt flag. Any individual interrupt flag can be masked so
it does not trigger the interrupt output. The unmasked interrupt flags are combined by the AND/ OR gate to
generate the interrupt output, which can be selected on either status pin.
When a system host detects an interrupt from the LMK05318B, the host can read the interrupt flag or "sticky"
registers to identify which bits were asserted to resolve the fault conditions in the system. After the system faults
have been resolved, the host can clear the interrupt output by writing zeros to the sticky bits that were asserted.
INTR
Flag*
INTR
Enable
INTR
Mask
INTR
Polarity
INT_AND_OR
Status Bits
F
F
LOS_FDET_XO
LOS_XO
2
Status Pins (x2)
F
F
F
F
F
LOL_PLL[1:2]
LOFL_DPLL
STATx_SEL
LOPL_DPLL
HIST
INTR
AND/OR
Gate
Polarity
Type
0xA
HLDOVR
Status
Select
STATUS0
STATUS1
F
F
F
F
Other
status
signals
REFSWITCH
LOR_MISSCLK
LOR_FREQ
LOR_AMP
Sticky Status Registers
0x013 to 0x014
Live Status Registers
0x00D to 0x00E
*Write 0 to clear INTR flag bits
图9-21. Status and Interrupt
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9.3.8 PLL Relationships
图9-22 shows the PLL architecture implemented in the LMK05318B. The PLLs can be configured in the different
PLL modes described in 节9.2.1.
Post
Dividers
APLL2
fPD2
VCO2
0
1
fVCO2/P1
fVCO2
PFD
LF
÷P1
R Dividers
÷RP
/2 to /7
÷N
24-bit Frac-N SDM
fVCO2/P2
/3 to /6
÷P2
To
Output
Muxes
÷RS
/1 to /32
×1, ×2
XO
DPLL
APLL1
PRIREF
0
1
fPD1
fTDC
VCO1
÷R
5-bit
÷R
fVCO1
SECREF
TDC
DLF
LF
PFD
16-bit
(x2)
÷FB
40-bit Frac-N SDM
÷N
40-bit Frac-N SDM
fVCO1
÷PR
÷2
To
Output
Muxes
38-bit
DCO option
FINC/FDEC
DCO
FDEV
DPLL feedback clock
图9-22. PLL Architecture
9.3.8.1 PLL Frequency Relationships
The following equations provide the PLL frequency relationships required to achieve closed-loop operation
according to the selected PLL mode. The TICS Pro programming software can be used to generate valid divider
settings based on the desired frequency plan configuration and PLL mode.
• To operate APLL1 in Free-run mode (locked to the XO input), the conditions in 方程式1 and 方程式2 must
be met.
• To operate APLL1 in DPLL mode, the conditions in 方程式1, 方程式2, 方程式3, and 方程式4 must be met.
• To operate APLL2 in Cascaded mode, the conditions in 方程式1, 方程式2, 方程式5, and 方程式7 must be
met.
• To operate APLL2 in Non-cascaded mode, the conditions in 方程式6 and 方程式7 must be met.
Note that any divider in the following equations refer to the actual divide value (or range) and not its
programmable register value.
方程式1 and 方程式2 relate to APLL1:
fPD1 = fXO × DXO / RXO
(1)
where
• fPD1 = APLL1 phase detector frequency
• fXO: XO input frequency
• DXO: XO input doubler (1 = disabled, 2 = enabled)
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• RXO: APLL1 XO Input R divider value (1 to 32)
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fVCO1 = fPD1 × (INTAPLL1 + NUMAPLL1 / DENAPLL1
)
(2)
where
• fVCO1: VCO1 frequency
• INTAPLL1: APLL1 N divider integer value (12 bits, 1 to 212 –1)
• NUMAPLL1: APLL1 N divider numerator value (40 bits, 0 to 240 –1)
• DENAPLL1: APLL1 N divider denominator value (fixed 240 or programmable 1 to 224-1)
– 0.0625 < NUMAPLL1 / DENAPLL1 < 0.9375 (In DPLL Mode)
方程式3 and 方程式4 relate to the DPLL:
fTDC = fPRIREF / RPRIREF = fSECREF / RSECREF
where
(3)
(4)
• fTDC: DPLL TDC input frequency (see 方程式3)
• fPRIREF or fSECREF: PRIREF or SECREF input frequency
• RPRIREF or RSECREF: PRIREF or SECREF R divider value (16 bits, 1 to 216 –1)
fVCO1 = fTDC × 2 × PRDPLL × (INTDPLL + NUMDPLL/ DENDPLL
)
where
• PRDPLL: DPLL prescaler divider value (2 to 17)
• INTDPLL: DPLL FB divider integer value (30 bits, 1 to 230 –1)
• NUMDPLL: DPLL FB divider numerator value (40 bits, 0 to 240 –1)
• DENDPLL: DPLL FB divider denominator value (40 bits, 1 to 240)
方程式5, 方程式6, and 方程式7 relate to APLL2:
Cascaded APLL2: fPD2 = fVCO1 / (RAPLL2_PRE × RAPLL2_SEC
)
(5)
where
• fPD2: APLL2 phase detector frequency
• RAPLL2_PRE: Cascaded APLL2 Pre R divider value (3 to 6)
• RAPLL2_SEC: Cascaded APLL2 Secondary R divider value (1 to 32)
Non-Cascaded APLL2: fPD2 = fXO × DXO
(6)
(7)
fVCO2 = fPD2 × (INTAPLL2 + NUMAPLL2 / DENAPLL2
)
where
• fVCO2: VCO2 frequency
• INTAPLL2: APLL2 N divider integer value (9 bits, 1 to 29 –1)
• NUMAPLL2: APLL2 N divider numerator value (24 bits, 0 to 224 –1)
• DENAPLL2: APLL2 N divider denominator value (fixed 224 or programmable 1 to 224-1.)
方程式 8, 方程式 9, 方程式 10, and 方程式 12 relate to the output frequency, which depends on the selected
APLL clock source and output divider value:
APLL1 selected: fCHxMUX = fVCO1
(8)
(9)
APLL2 selected: fCHxMUX = fVCO2 / PnAPLL2
OUT[0:6]: fOUTx = fCHxMUX / ODOUTx
(10)
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OUT7: fOUT7 = fCH7MUX / (ODOUT7 × OD2)
(11)
(12)
where
• fCHxMUX: Output mux source frequency (APLL1 or APLL2 post-divider clock)
• PnAPLL2: APLL2 primary "P1" or secondary "P2" post-divide value (2 to 7)
• fOUTx: Output clock frequency (x = 0 to 7)
• ODOUTx: OUTx output divider value (8 bits, 1 to 28)
• OD2: OUT7 secondary output divider value (24 bits, 1 to 224)
– If OD2 > 1, then ODOUT7 ≥6
9.3.8.2 Analog PLLs (APLL1, APLL2)
APLL1 has a 24-bit (programmable) or40-bit (fixed) fractional-N divider and APLL2 has a 24-bit (programmable)
fractional-N divider to support high-resolution frequency synthesis and very low phase noise and jitter. APLL1
has the ability to tune its VCO1 frequency through sigma-delta modulator (SDM) control in DPLL mode. APLL2
has the ability to lock its VCO2 frequency to the VCO1 frequency.
In free-run mode, APLL1 uses the XO input as an initial reference clock to VCO1. The PFD of the APLL1
compares the fractional-N divided clock with its reference clock and generates a control signal. The control
signal is filtered by the APLL1 loop filter to generate the control voltage of the VCO1 to set its output frequency.
The SDM modulates the N divider ratio to get the desired fractional ratio between the PFD input and the VCO
output. APLL2 operates similar to APLL1, but the user can select the reference of the APLL2 from either the
VCO1 clock or XO clock.
In DPLL mode, the APLL1 fractional SDM is controlled by the DPLL loop to pull the VCO1 frequency into lock
with the DPLL reference input. If APLL2 derives its reference from VCO1, then VCO2 will be effectively locked to
the DPLL reference input, assuming there is no synthesis error introduced by the fractional N divide ratio of
APLL2.
9.3.8.3 APLL Reference Paths
9.3.8.3.1 APLL XO Doubler
The APLL XO doubler can be enabled to double the PFD frequency up to 50 MHz for APLL1 and up to 150 MHz
for APLL2 in Non-cascaded mode. Enabling the XO doubler adds minimal noise and can be useful to increase
the PFD frequency to optimize phase noise, jitter, and fractional spurs. The flat portion of the APLL phase noise
can improve when the PFD frequency is increased.
9.3.8.3.2 APLL1 XO Reference (R) Divider
APLL1 has a 5-b XO R divider that can be used to meet the maximum APLL1 PFD frequency specification. It
can also be used to ensure the APLL1 fractional-N divide ratio (NUM/DEN) is between 0.0625 to 0.9375, which
is recommended to support the DPLL frequency tuning range. Otherwise, the XO R divider can be bypassed
(divide by 1).
9.3.8.3.3 APLL2 Reference (R) Dividers
APLL2 has a cascaded primary R divider (÷3 to ÷6) and secondary R divider (÷1 to ÷32) to divide-down the
VCO1 clock to meet the maximum APLL2 PFD frequency specification in Cascaded APLL2 mode. The dividers
can also be used to operate APLL2 in integer mode or avoid near-integer spurs in fractional mode.
9.3.8.4 APLL Phase Frequency Detector (PFD) and Charge Pump
The APLL1 PFD frequency can operate up to 50 MHz and can be computed by 方程式 1. APLL1 has
programmable charge pump settings from 0 to 1500 µA in 100-µA steps. Best performance from APLL1 is
achieved with a charge pump currents of 800 µA or higher.
The APLL2 PFD frequency can operate up to 150 MHz and can be computed by 方程式 5 in Cascaded mode or
方程式6 in Non-cascaded mode. APLL2 has programmable charge pump settings of 1.6, 3.2, 4.8, or 6.4 mA.
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9.3.8.5 APLL Feedback Divider Paths
The VCO output of each APLL is fed back to its PFD block through the fractional feedback (N) divider. The
VCO1 output is also fed back to the DPLL feedback path in DPLL mode.
9.3.8.5.1 APLL1 N Divider With SDM
The APLL1 fractional N divider includes a 12-b integer portion (INT), a 40-b numerator portion (NUM), a fixed 40-
b or programmable 24-b denominator portion (DEN), and a sigma-delta modulator. The INT and NUM are
programmable, while the denominator is fixed to 240 or programmable from 1 to 224 – 1 for the very high-
frequency resolution on the VCO1 clock. The total APLL1 N divider value is: N = INT + NUM / DEN .
Programmable denominator should be used in APLL mode only (DPLL powered down).
In APLL free-run mode, the PFD frequency and total N divider for APLL1 determine the VCO1 frequency, which
can be computed by 方程式2.
9.3.8.5.2 APLL2 N Divider With SDM
The APLL2 fractional N divider includes a 9-b integer portion (INT), a 24-b numerator portion (NUM), a fixed
programmable 24-b denominator portion (DEN), and a sigma-delta modulator. The INT , NUM and DEN are
programmable for high frequency resolution on the VCO2 clock. The total APLL2 N divider value is: N = INT +
NUM / DEN .
The PFD frequency and total N divider for APLL2 determine the VCO2 frequency, which can be computed by 方
程式7.
9.3.8.6 APLL Loop Filters (LF1, LF2)
APLL1 supports a programmable loop bandwidth from 100 Hz to 10 kHz (typical range), and APLL2 supports a
programmable loop bandwidth from 100 kHz to 1 MHz (typical range). The loop filter components can be
programmed to optimize the APLL bandwidth depending on the reference input frequency and phase noise. The
LF1 and LF2 pins each require an external "C2" capacitor to ground. See the suggested values for the LF1 and
LF2 capacitors in 节6.
图 9-23 shows the APLL loop filter structure between the PFD/charge pump output and VCO control input.
PLLATINUMSIM-SW can be used for APLL Loop Filter simulation.
VCO
Programmable
Loop Filter
R3
R4
PFD /
Charge Pump
C1
R2
C3
C4
LF1, LF2
C2
图9-23. Loop Filter Structure of Each APLL
9.3.8.7 APLL Voltage Controlled Oscillators (VCO1, VCO2)
Each APLL contains a fully-integrated VCO, which takes the voltage from its loop filter and converts this into a
frequency. VCO1 uses proprietary BAW resonator technology with a very high quality factor to deliver the lowest
phase jitter and has a tuning range of 2.5 GHz ± 50 ppm. VCO2 uses a high-performance LC VCO with a wider
tuning range of 5.5 to 6.25 GHz to cover a additional unrelated clock frequencies, if needed.
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9.3.8.7.1 VCO Calibration
Each APLL VCO must be calibrated to ensure that the PLL can achieve lock and deliver optimal phase noise
performance. VCO calibration establishes an optimal operating point within the VCO tuning range. VCO
calibration is executed automatically during initial PLL start-up after device power-on, hard-reset, or soft-reset
once the XO input is detected by its input monitor. To ensure successful calibration and APLL lock, it is critical for
the XO clock to be stable in amplitude and frequency before the start of calibration; otherwise, the calibration
can fail and prevent PLL lock and output clock start-up. Before VCO calibration and APLL lock, the output drivers
are typically held in the mute state (configurable per output) to prevent spurious output clocks.
A VCO calibration can be triggered manually for a single APLL by toggling a PLL power-down cycle (PLLx_PDN
bit = 1 → 0) through host programming. This may be needed after the APLL N divider value (VCO frequency) is
changed dynamically through programming.
9.3.8.8 APLL VCO Clock Distribution Paths (P1, P2)
APLL1 has no VCO post-dividers. The primary VCO1 clock (P1) and a secondary VCO1 inverted clock (P2) are
distributed to all output channel muxes. The inverted clock is optional, but it can help reduce spurious outputs in
some cases.
APLL2 has two VCO2 post-dividers to provide more flexible clock frequency planning. The primary VCO2 post-
divider clock (P1) and secondary post-divider clock (P2) are distributed to all output channel muxes. Both VCO2
post-dividers support independently programmable dividers (÷2 to ÷7). Note that output SYNC is not supported
between output channels selecting a VCO2 post-divider of 2.
TI recommends a PLL2 or device soft-reset after changing the APLL2 post-divider value to initialize it for
deterministic divider operation.
9.3.8.9 DPLL Reference (R) Divider Paths
Each reference input clock (PRIREF and SECREF) has its own 16-b reference divider to the DPLL TDC block.
The R divider output of the selected reference sets the TDC input frequency. To support hitless switching
between inputs with different frequencies, the R dividers can be used to divide the clocks to a single common
frequency to the DPLL TDC input.
9.3.8.10 DPLL Time-to-Digital Converter (TDC)
The TDC input compares the phase of the R divider clock of the selected reference input and the DPLL
feedback divider clock from VCO1. The TDC output generates a digital correction word corresponding to the
phase error which is processed by the DPLL loop filter.
The DPLL TDC input frequency (fTDC) can operate up to 26 MHz and can be computed by 方程式3.
9.3.8.11 DPLL Loop Filter (DLF)
The DPLL supports a programmable loop bandwidth from 10 mHz to 4 kHz and can achieve jitter peaking below
0.1 dB (typical). The low-pass jitter transfer characteristic of the DPLL attenuates its reference input noise with
up to 60-dB/decade roll-off above the loop bandwidth.
The DPLL loop filter output controls the fractional SDM of APLL1 to steer the VCO1 frequency into lock with the
selected DPLL reference input.
9.3.8.12 DPLL Feedback (FB) Divider Path
The DPLL feedback path has a fixed prescaler (÷2), programmable prescaler (÷2 to ÷17), and a fractional
feedback (FB) divider. The programmable DPLL FB divider includes a 30-b integer portion (INT), 40-b numerator
portion (NUM), and 40-b denominator portion (DEN). The total DPLL FB divider value is: FBDPLL = INT + NUM /
DEN.
In DPLL mode, the TDC frequency and total DPLL feedback divider and prescalers determine the VCO1
frequency, which can be computed by 方程式4.
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9.3.9 Output Clock Distribution
The output clock distribution blocks shown in 图 9-24 include six output muxes, six output dividers, and eight
programmable output drivers. The output dividers support output synchronization (SYNC) to allow phase
synchronization between two or more output channels. Also, the OUT7 channel has an optional zero-delay
mode (ZDM) synchronization feature to support deterministic input-to-output phase alignment (typically for 1-
PPS clocks) with programmable offset.
Clock Bus
OUT0
OUT1
0
1
2
3
÷OD
8-b
OUT[0:3] bank
preferred for
PLL1 clocks
PLL1
fVCO1
0
1
OUT2
OUT3
0
1
2
3
÷OD
8-b
VCO1
Output Channel Configuration
Power-
down
Output Type
Mux
0
1
2
3
÷OD
÷OD
8-b
OUT4
2
PLL2
SYNC EN
(1)
Auto Mute,
Mute Level
fVCO2
2
3
0
1
2
3
÷P1
/2 to /7
÷P2
÷OD
8-b
OUT5
OUT6
OUT7
SYNC
VCO2
OUT[4:7] bank
preferred for
PLL2 clocks
0
1
2
3
÷OD
8-b
0
1
2
3
÷OD
8-b
÷OD_2
24-b
SYNC_SW
SYNC
GPIO0/SYNCN
(active-low pin)
图9-24. Output Clock Distribution
9.3.10 Output Channel Muxes
Each of the six output channels has an output mux. Each output mux for the OUT0 to OUT7 channels can
individually select between the PLL1 VCO clocks (normal or inverted) and PLL2 VCO post-divider clocks.
9.3.11 Output Dividers (OD)
Each of the six output channels has an output divider after the output mux. The OUT[0:1] channel has a single
output divider that is similar to the OUT[2:3] channel output divider. Each OUT[4:7] channel has an individual
output divider. The output divider is used to generate the final clock output frequency from the source selected
by the output mux.
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Each OUT[0:6] channel has an 8-bit divider (OD) that can support output frequencies from 10 to 800 MHz (or up
to the maximum frequency supported by the configured output driver type). It is possible to configure the PLL
post-divider and output divider to achieve higher clock frequencies, but the output swing of the driver may fall out
of specification.
The OUT7 channel has cascaded 8-bit (OD) and 24-bit (OD2) output dividers to support output frequencies from
1 Hz (1 PPS) to 800 MHz. The total OUT7 divide value is the product of the cascaded divider values (OD ×
OD2).
Each output divider is powered from the same VDDO_x supply used for the clock output drivers. The output
divider can be powered down if not used to save power. For either OUT[0:1] or OUT[2:3] channel, the output
divider is automatically powered down when both output drivers are disabled. For any OUT[4:7] channel, the
output divider is automatically powered down when its output driver is disabled. For proper functioning of the
output divider, clock frequency to the output divider should be under 3 GHz.
9.3.12 Clock Outputs (OUTx_P/N)
Each clock output can be individually configured as a differential driver (AC-LVDS/CML/LVPECL), HCSL driver,
or 1.8-V LVCMOS drivers (two per pair). Otherwise, it can be disabled if not used to save power.
Each output channel has its own internal LDO regulator to provide excellent PSNR and minimize jitter and spurs
induced by supply noise. The OUT[0:1] channel (mux, divider, and drivers) are powered through a single output
supply pin (VDDO_01), and similarly for the OUT[2:3] channel (VDDO_23). Each OUT[4:7] channel have their
own output supply pin (VDDO[4:7]). Each output supply can be separately powered by 1.8 V, 2.5 V, or 3.3 V for a
differential or HCSL output, or 1.8 V for an LVCMOS output.
For differential and HCSL driver modes, the output clock specifications (such as output swing, phase noise, and
jitter) are not sensitive to the VDDO_x voltage because of the internal LDO regulator of the channel. When an
output channel is left unpowered, the output(s) of the channel will not generate any clocks.
表9-7. Output Driver Modes
OUTx_FMT
00h
OUTPUT FORMAT(1)
Disabled (powered-down)
AC-LVDS
10h
14h
AC-CML
18h
AC-LVPECL
2Ch
2Dh
30h
HCSL (External 50-Ωto GND)
HCSL (Internal 50-Ωto GND)
LVCMOS (HiZ / HiZ)
LVCMOS (HiZ / –)
LVCMOS (HiZ / +)
LVCMOS (Low / Low)
LVCMOS (–/ HiZ)
LVCMOS (–/ –)
LVCMOS (–/ +)
32h
33h
35h
38h
3Ah
3Bh
3Ch
3Eh
3Fh
LVCMOS (+ / HiZ)
LVCMOS (+ / –)
LVCMOS (+ / +)
(1) LVCMOS modes are only available on OUT[4:7].
9.3.12.1 AC-Differential Output (AC-DIFF)
The programmable differential output driver uses a switched-current mode type shown in 图 9-25. A tail current
of 4, 6, or 8 mA (nominal) can be programmed to achieve VOD swing compatible with AC-coupled LVDS, CML, or
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LVPECL receivers, respectively, across a 100-Ω differential termination. The differential output driver is ground-
referenced (similar to an HCSL driver), meaning the differential output has a low common-mode voltage (VOS).
The differential driver has internal biasing, so external pullup or pulldown resistors should not be applied. The
differential output should be interfaced through external AC-coupling to a differential receiver with proper input
termination and biasing.
VDDO_x
LDO
I1 = 4 mA
From
output
channel
Output tail current (I1 + I2) can be programmed
to 4, 6, or 8 mA for LVDS-, CML-, and LVPECL-
compatible swing across AC-coupled
P
N
P
N
clk_p
50-W single-ended or 100-W differential load.
clk_n
OUTx_P
I2 = 0, 2, or 4 mA
P
N
P
N
OUTx_N
图9-25. AC-LVDS/CML/LVPECL Output Driver Structure
9.3.12.2 HCSL Output
The HCSL output is an open-drain differential driver that can be DC-coupled to an HCSL receiver. The HCSL
output has programmable internal 50-Ω termination to ground which can be enabled if the receiver side does
not provide termination. If the internal termination is disabled, external 50-Ω to ground (on P and N) is required
at either the driver side (source terminated) or the receiver side (load terminated).
9.3.12.3 1.8-V LVCMOS Output
The LVCMOS driver has two outputs per pair. Each output on P and N can be configured for normal polarity,
inverted polarity, or disabled as HiZ or static low level. The LVCMOS output high level (VOH) is determined by the
VDDO_x voltage of 1.8 V for rail-to-rail LVCMOS output voltage swing. If a VDDO_x voltage of 2.5 V or 3.3 V is
applied to the LVCMOS driver, the output VOH level not will not swing to the VDDO_x rail due to the internal LDO
regulator of the channel.
A LVCMOS output clock is an unbalanced signal with large voltage swing, therefore it can be a strong aggressor
and couple noise onto other jitter-sensitive differential output clocks. If an LVCMOS clock is required from an
output pair, configure the pair with both outputs enabled but with opposite polarity (+/– or –/+) and leave the
unused output floating with no trace connected.
9.3.12.4 Output Auto-Mute During LOL
Each output driver can automatically mute or squelch its clock when the selected output mux clock source is
invalid, as configured by its CHx_MUTE bit. The source can be invalid based on the LOL status of each PLL by
configuring the APLL and DPLL mute control bits (MUTE_APLLx_LOCK, MUTE_DPLL_LOCK,
MUTE_DPLL_PHLOCK). The mute level can be configured per output channel by its CHx_MUTE_LVL bits,
where the mute level depends on the configured output driver type (Differential/HCSL or LVCMOS). The mute
level for a differential or HCSL driver can be set to output common mode, differential high, or differential low
levels. The mute level for an LVCMOS driver pair can be set to output low level for each of its outputs (P and N)
independently. When auto-mute is disabled or bypassed (CHx_MUTE = 0 and CHx_MUTE_LVL = 0), the output
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clock can have incorrect frequency or be unstable before and during the VCO calibration. For this reason, the
mute bypass mode should only be used for diagnostic or debug purposes.
9.3.13 Glitchless Output Clock Start-Up
When APLL auto-mute is enabled, the outputs will start up in synchronous fashion without clock glitches once
APLL lock is achieved after any the following events: device power-on, exiting hard-reset, exiting soft-reset, or
deasserting output SYNC (when SYNC_MUTE = 1).
9.3.14 Clock Output Interfacing and Termination
These figures show the recommended output interfacing and termination circuits. Unused clock outputs can be
left floating and powered down by programming.
LVCMOS
1.8 V LVCMOS
LMK05318B
Receiver
图9-26. 1.8-V LVCMOS Output to 1.8-V LVCMOS Receiver
LVDS
Receiver
LMK05318B
AC-LVDS
100 ꢀ
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图9-27. AC-LVDS Output to LVDS Receiver With Internal Termination/Biasing
50 ꢀ
CML
Receiver
LMK05318B
AC-CML
50 ꢀ
Copyright © 2020, Texas Instruments Incorporated
图9-28. AC-CML Output to CML Receiver With Internal Termination/Biasing
AC-LVPECL
LVPECL Receiver
LMK05318B
50 ꢀ
50 ꢀ
VDD_IN œ 1.3 V
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图9-29. AC-LVPECL Output to LVPECL Receiver With External Termination/Biasing
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33 ꢀ (optional)
HCSL
LMK05318B
HCSL Receiver
33 ꢀ (optional)
50 ꢀ
50 ꢀ
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If HCSL Internal Termination (50-Ωto GND) is enabled, short 33-Ωand remove 50-Ωexternal resistors.
图9-30. HCSL Output to HCSL Receiver With External Source Termination
9.3.15 Output Synchronization (SYNC)
Output SYNC can be used to phase-align two or more output clocks with a common rising edge by allowing the
output dividers to exit reset on the same PLL output clock cycle. Any output dividers selecting the same PLL
output can be synchronized together as a SYNC group by triggering a SYNC event through the hardware pin or
software bit.
The following requirements must be met to establish a SYNC group for two or more output channels:
• Output dividers have their respective SYNC enable bit set (CHx_SYNC_EN = 1).
• Output dividers have their output mux selecting the same PLL output.
• The PLL (post-divider) output has its SYNC enable bit set (for example, PLL1_P1_SYNC_EN = 1).
A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit
(active high). When SYNC is asserted, the SYNC-enabled dividers held are reset and clock outputs are muted.
When SYNC is deasserted, the outputs will start with their initial clock phases synchronized or aligned. SYNC
can also be used to mute any SYNC-enabled outputs to prevent output clocks from being distributed to
downstream devices until they are configured and ready to accept the incoming clock.
Output channels with their SYNC disabled (CHx_SYNC_EN bit = 0) will not be affected by a SYNC event and
will continue normal output operation as configured. Also, VCO and PLL post-divider clocks do not stop running
during the SYNC so they can continue to source output channels that do not require synchronization. Output
dividers with divide-by-1 (divider bypass mode) are not gated during the SYNC event.
表9-8. Output Synchronization
GPIO0/SYNCN PIN
SYNC_SW BIT
OUTPUT DIVIDER AND DRIVER STATE
0
0→1
1
1
1→0
0
Output driver(s) muted and output divider(s) reset
Outputs in a SYNC group are unmuted with their initial clock phases aligned
Normal output driver/divider operation as configured
Note
Output SYNC is not supported (output-to-output skew specifications is not ensured) between output
channels selecting a PLL2 output (P1 or P2) with VCO2 post-divider of 2.
9.3.16 Zero-Delay Mode (ZDM) Synchronization for 1-PPS Input and Output
Zero-delay mode synchronization can be enabled to achieve deterministic (+/-1 VCO cycle) input-output phase
delay between the selected DPLL reference input clock and the OUT7 clock as shown in 图 9-31. This is
primarily used to achieve deterministic phase relationship between a 1-PPS input and 1-PPS output. This feature
can be configured through registers by enabling ZDM (DPLL_ZDM_SYNC_EN bit = 1) and enabling OUT7
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divider synchronization (CH7_SYNC_EN bit = 1). The OUT7 clock must be derived from the DPLL and APLL1
VCO domain (fVCO1).
When the DPLL is not locked and the DPLL reference input is invalid, the OUT7 clock is held in mute state (no
clock). Once the reference input is validated and selected, the OUT7 channel divider is reset or SYNCed using
the DPLL reference input clock edge to achieve a deterministic phase relationship between the reference input
and OUT7 clock. OUT7 is not affected by normal output SYNC events, and OUT[0:6] are not be affected by a
ZDM SYNC event. The input-to-output phase offset can be adjusted through the DPLL phase offset register
control (DPLL_REF_SYNC_PH_OFFSET bits). If the DPLL phase offset is programmed on-the-fly with 1-PPS
input, it can take a long time to adjust due to the narrow DPLL bandwidth (10 mHz typical).
Hitless switching between 1-PPS inputs is not supported when ZDM is enabled. If a switchover event between 1-
PPS inputs occurs when ZDM is enabled, a soft-reset should be issued for the DPLL to relock and realign the 1-
PPS output to the selected input.
DPLL + APLL1
OUT7 Channel
÷R
fTDC
fVCO1
÷OD
SYNC
REF
OUT7
Phase Offset
DPLL_REF_SYNC
_PH_OFFSET
DPLL_ZDM_SYNC_EN
图9-31. DPLL ZDM Synchronization Between Reference Input and OUT7
9.4 Device Functional Modes
9.4.1 Device Start-Up Modes
The LMK05318B can start up in one of three device modes depending on the 3-level input level sampled on the
HW_SW_CTRL pin during power-on reset (POR):
• HW_SW_CTRL = 0: EEPROM + I2C Mode (Soft pin mode)
• HW_SW_CTRL = Float (VIM): EEPROM + SPI Mode (Soft pin mode)
• HW_SW_CTRL = 1: ROM + I2C Mode (Hard pin mode)
The device start-up mode determines:
• The memory bank (EEPROM or ROM) used to initialize the register settings that sets the frequency
configuration.
• The serial interface (I2C or SPI) used for register access.
• The logic pin functionality for device control and status.
After start-up, the I2C or SPI interface is enabled for register access to monitor the device status and control (or
reconfigure) the device if needed. The register map configurations are the same for I2C and SPI.
表6-2 summarizes the device start-up mode and corresponding logic pin functionality.
图9-32 shows the device power-on reset configuration sequence.
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Power-On Reset
(POR)
Device POR
Configuration Sequence
PDN = 0
Hard Reset?
Outputs muted
PDN = 1
HW_SW_CTRL = 1
GPIO[2:0] = 000b to 111b
(ROM Page Select)
HW_SW_CTRL = 0
GPIO1 = 0, Float, 1 (I2C Addr. Select)
Start-up Mode?
(sample pin states)
HW_SW_CTRL = Float
STATUS[1:0] = Float
EEPROM + I2C
(Soft Pin) Mode
EEPROM + SPI
(Soft Pin) Mode
ROM + I2C
(Hard Pin) Mode
Registers initialize from EEPROM/ROM and I2C/SPI,
Control & Status pins activate (after hard reset only).
All blocks reset to initial states.
RESET_SW = 0
Device Block
Configuration
Soft Reset?
RESET_SW = 1
Register and EEPROM programming available.
Normal Operation
See PLL Initialization
Flowchart
图9-32. Device POR Configuration Sequence
9.4.1.1 EEPROM Mode
In EEPROM mode, the frequency configuration of the device is loaded to the registers from the non-volatile
EEPROM. The factory default start-up configuration for EEPROM mode is summarized in 节 9.5.9. If a different
custom start-up configuration is needed, a different EEPROM image can be programmed in-system through the
serial interface. The EEPROM supports up to 100 programming cycles to facilitate clock reconfiguration for
system-level prototyping, debug, and optimization.
The EEPROM image can store a single frequency configuration (one register page). Upon request, a factory pre-
programmed device with a custom EEPROM image could be assigned by TI with a unique orderable part
number (OPN).
TI suggests to use the EEPROM mode when either of the following is true:
• A single custom start-up frequency configuration is required from a single OPN.
• A host device is available to program the registers (and EEPROM if needed) with a new configuration after
power up through I2C or SPI. SPI is not supported in ROM mode.
9.4.1.2 ROM Mode
In ROM mode, the frequency configuration of the device is loaded to the registers from one of eight register
pages in ROM selected by the GPIO[2:0] control pins. All register pages in the ROM image can be factory-set in
hardware (mask ROM) and are not software programmable. Only the I2C interface is available for register
access after start-up in ROM mode.
The factory ROM image have default register pages intended for TI internal use, but ROM pages may be
allocated for future custom frequency configurations upon request.
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A benefit of ROM mode over EEPROM mode is that a custom ROM image can support up to eight different pin-
selectable frequency configurations from a single OPN. Upon request, a factory-preset device with a custom
ROM image could be assigned by TI with a unique OPN.
9.4.2 PLL Operating Modes
The following sections describe the PLL modes of operation shown in 图9-33.
See Device POR
and PLL Initialization
Flowchart
No valid input
available
Free-run Mode(1)
Initial frequency accuracy
determined by free-run
tuning word register.
(1) Free-run/Holdover Mode frequency
stability determined by TCXO/OCXO/
XO.
Valid Input
Available for
Selection? (2)
No
(2) See Input Selection Flowchart.
Yes
Lock Acquisition
(Fastlock, Hitless Switch)
Phase-locked to
selected input
Yes
Valid Input
Available for
Selection? (2)
No
DPLL Locked
DCO Mode available.
No
Loss of Ref (LOR) on
Selected Input? (2)
Holdover Mode(1)
Initial holdover frequency
accuracy determined by
averaged history data.
Yes
No
Yes
Is Tuning Word
History Valid?
A. Assumes DPLL_HLDOVR_MODE bit is 0 to enter free-run mode if history is not valid.
图9-33. PLL Operating Mode
9.4.2.1 Free-Run Mode
After device POR configuration and initialization, APLL1 will automatically lock to the XO clock when it is
detected by its input monitor. Then, APLL2 will acquire lock to either VCO1 or XO frequency as selected. The
output clock frequency accuracy and stability in free-run mode are equal to that of the XO input. The reference
inputs remain invalid (unqualified) during free-run mode.
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9.4.2.2 Lock Acquisition
The DPLL constantly monitors its reference inputs for a valid input clock. When at least one valid input clock is
detected, the PLL1 channel will exit free-run mode or holdover mode and initiate lock acquisition through the
DPLL. The device supports the Fastlock feature where the DPLL temporarily engages a wider loop bandwidth to
reduce the lock time. Once the lock acquisition is done, the loop bandwidth is set to its normal configured loop
bandwidth setting (BWDPLL).
9.4.2.3 Locked Mode
Once locked, the APLL1 output clocks are frequency- and phase-locked to the selected DPLL input clock. While
the DPLL is locked, the APLL1 output clocks will not be affected by frequency drift on the XO input. The DPLL
has a programmable frequency lock detector and phase lock detectors to indicate loss-of-frequency lock (LOFL)
and loss-of-phase lock (LOPL) status flags, which can be observed through the status pins or status bits. Once
frequency lock is detected (LOFL → 0), the tuning word history monitor (if enabled) will begin to accumulate
historical averaging data used to determine the initial output frequency accuracy upon entry into holdover mode.
9.4.2.4 Holdover Mode
When a loss-of-reference (LOR) condition is detected and no valid input is available, the PLL1 channel enters
holdover mode. If the tuning word history is valid, the initial output frequency accuracy upon entry into holdover
will be pulled to the computed average frequency accuracy just prior to the loss of reference. If history is not
valid (no history exists) and the DPLL_HLDOVR_MODE bit is 0, the holdover frequency accuracy will be
determined by the free-run tuning word register (user programmable). Otherwise, if history is not valid and
DPLL_HLDOVR_MODE is 1, the DPLL will hold its last digital loop filter output control value (which is not tuning
word history).
If history is valid, the initial holdover frequency accuracy depends on the DPLL loop bandwidth and the elapsed
time used for historical averaging. See 节 9.3.7.4 for more information. In general, the longer the historical
average time, the more accurate the initial holdover frequency assuming the 0-ppm reference clock (XO input) is
drift-free. The stability of the XO reference clock determines the long-term stability and accuracy of the holdover
output frequency. Upon entry into holdover, the LOPL flag will be asserted (LOPL → 1). The LOFL flag will not
be asserted, however, as long as the holdover frequency accuracy does not drift beyond of the programmed
loss-of-frequency-lock threshold. When a valid input becomes available for selection, the PLL1 channel will exit
holdover mode and automatically phase lock with the new input clock without any output glitches.
9.4.3 PLL Start-Up Sequence
图 9-34 shows the general sequence for PLL start-up after device configuration. This sequence is also
applicable after a device soft-reset or individual PLL soft-reset. To ensure proper VCO calibration, it is critical for
the external XO clock to be stable in amplitude and frequency prior to the start of VCO calibration. Otherwise,
the VCO calibration can fail and prevent the start-up of the PLL and its output clocks.
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Device Configured
See Device POR
Configuration Flowchart
XO Detected
VCO Calibration
PLL Initialization Sequence
APLL2 locks before APLL1 in Cascaded mode.
Outputs lock to XO frequency.
Outputs un-mute if DPLL auto-mute disabled.
Outputs auto-SYNC if enabled.
APLL(s) Locked
(Free-run from XO)
Input Monitoring (fastest to slowest detector):
1. Missing and/or Early clock detector
2. Amplitude or Slew rate detector
Ref. Input
Validation
3. Frequency (ppm) detector
4. 1-PPS phase valid detector (skip #1 and 3 for 1-PPS)
5. After enabled detectors are valid, validation timer starts
and must finish before input is qualified.
Valid Input Selected
DPLL
Lock Acquisition
Fastlock DPLL bandwidth is temporarily asserted
during lock acquisition.
Outputs lock to selected input clock frequency.
Outputs are un-muted if DPLL auto-mute enabled.
Configured DPLL bandwidth is asserted.
DCO Mode control
available (ZDM
must be disabled)
DPLL
Locked
DPLL frequency- and phase-lock detectors are monitored.
Output will have deterministic input-to-output phase
relationship if Zero-Delay Mode (ZDM) SYNC is enabled.
See DPLL Modes
and
Input Selection
Flowcharts
图9-34. PLL Start-Up Sequence
9.4.4 Digitally-Controlled Oscillator (DCO) Mode
To support the IEEE 1588 slave clock and other clock steering applications, the DPLL supports DCO mode to
allow precise output clock frequency adjustment of less than 0.001 ppb/step. DCO mode can be enabled
(DPLL_FDEV_EN = 1) when the DPLL is locked.
The DCO frequency step size can be programmed through a 38-bit frequency deviation word register
(DPLL_FDEV bits). The DPLL_FDEV value is an offset added to or subtracted from the current numerator value
of the DPLL fractional feedback divider and determines the DCO frequency offset at the VCO output.
The DCO frequency increment (FINC) or frequency decrement (FDEC) updates can be controlled through
software control or pin control in I2C mode. DCO updates through software control are always available through
I2C or SPI by writing to the DPLL_FDEV_REG_UPDATE register bit. Writing a 0 will increment the DCO
frequency by the programmed step size, and writing a 1 will decrement it by the step size. SPI can achieve faster
DCO update rates than to I2C because the SPI has faster register transfer.
When pin control mode is enabled (GPIO_FDEV_EN = 1) in I2C mode, the GPIO2/SDO/FINC pin will function as
the FINC input and the STATUS1/FDEC pin will function as the FDEC input (STATUS1 output will be disabled). A
positive pulse on the FINC pin or FDEC pin will apply a corresponding DCO update to the DPLL. The minimum
positive pulse width applied to the FINC or FDEC pins should be greater than 100 ns to be captured by the
internal sampling clock. The DCO update rate should be limited to less than 1 MHz when using pin control.
When DCO mode is disabled (DPLL_FDEV_EN = 0), the DCO frequency offset will be cleared and the VCO
output frequency will be determined by the original numerator value of the DPLL fractional feedback divider.
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APLL1
APLL2
DPLL
fVCO2
fTDC
FINC/FDEC Pin Control
fVCO1
GPIO_FDEV_EN
DPLL_FDEV_EN
GPIO2/FINC
FINC
FDEC
DCO
Step
STATUS1/FDEC
38-bit
DPLL_FDEV
FINC/FDEC Register Control
DPLL_FDEV_REG_UPDATE
I2C/SPI
The DPLL Numerator is incremented or decremented by the
DCO FDEV step word on the rising-edge of FINC or FDEC.
0x160[0]
Write:
0 = FINC
1 = FDEC
图9-35. DCO Mode Control Options
9.4.4.1 DCO Frequency Step Size
方程式 13 shows the formula to compute the DPLL_FDEV register value required to meet the specified DCO
frequency step size in ppb (part-per-billion) when DCO mode is enabled for the DPLL.
DPLL_FDEV = (Reqd_ppb / 109) × DENDPLL × fVCO1 / (2 × PRDPLL) / (fREF / RREF
)
(13)
where
• DPLL_FDEV: Frequency deviation value (0 to 238 –1)
• Reqd_ppb: Required DCO frequency step size (in ppb)
• DENDPLL: DPLL FB divider denominator value (1 to 240)
• fVCO1: VCO1 frequency
• PR: DPLL feedback prescaler divide value (2 to 17)
• fREF: PRIREF or SECREF input frequency
• Rx: PRIREF or SECREF input divide value (1 to 216 –1)
9.4.4.2 DCO Direct-Write Mode
An alternate method to update the DCO frequency is to take the current numerator value (DPLL_REF_NUM) of
the DPLL fractional feedback divider, compute the adjusted numerator value by adding or subtracting the
DPLL_FDEV step value computed above, and write the adjusted numerator value through I2C or SPI.
9.4.5 Zero-Delay Mode Synchronization
The DPLL supports a zero-delay mode (ZDM) synchronization option to achieve a known and deterministic
phase relationship between the selected DPLL reference input and the OUT7 clock. This is primarily intended to
achieve phase alignment between a 1-PPS input and 1-PPS output. See 节9.3.16.
9.5 Programming
9.5.1 Interface and Control
A system host device (MCU or FPGA) can use either I2C or SPI to access the register, SRAM, and EEPROM
maps. The register and EEPROM map configurations are the same for I2C and SPI. The device can be
initialized, controlled, and monitored through register access during normal operation (when PDN is deasserted).
Some device features can also be controlled and monitored through the external logic control and status pins.
In the absence of a host, the LMK05318B can self-start from its on-chip EEPROM or ROM page depending on
the state of HW_SW_CTRL pin. The EEPROM or ROM page is used to initialize the registers upon device POR.
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A custom EEPROM configuration can be programmed in-system through the register interface by either I2C or
SPI. The ROM configurations are fixed in hardware and cannot be modified.
图 9-36 shows the device control pin, register, and memory interfaces. The arrows refer to the control interface
directions between the different blocks.
The register map has 435 data bytes. Some registers, such as status registers and internal test/diagnostic
registers (above R352), do not need to be written during device initialization.
The SRAM/EEPROM map has one register page with 256 data bytes. The SRAM/EEPROM map has fewer
bytes because not all bit fields are mapped from the register space. To program the EEPROM, it is necessary to
write the register contents to SRAM (internal register commit or direct write), then Program EEPROM with the
register contents from SRAM.
The ROM map has eight register pages with 249 data bytes per page. The ROM contents are fixed in hardware
and cannot be modified.
Mask ROM
Select ROM Mode
(8 Pages)
(Page 0 to 7)
Addr: 0x000 to 0x7C7
Data: 1992 bytes
- Initialize Registers from ROM Page
(249 bytes / Page)
Memory
Interface
STATUS0
STATUS1/FDEC
HW_SW_CTRL
Control/
Status Pins
Serial
Interface
PDN
GPIO0/SYNCN
GPIO2/SDO/FINC
GPIO1/SCS
Device
Control
and
Device Blocks
(Inputs, PLLs,
Outputs,
Registers
Block Interface
Addr: 0x000 to 0x1B2
Data: 435 bytes
Status
Monitors, etc.)
I2C/SPI
Pins
SCL/SCK
SDA/SDI
Memory
Interface
Memory
Interface
- Write SRAM (Commit Registers)
- Read SRAM
- Initialize Registers from EEPROM
- Read EEPROM
Program
EEPROM
SRAM
NVM EEPROM
Addr: 0x000 to 0x100
Data: 256 bytes
Addr: 0x000 to 0x100
Data: 256 bytes
Select EEPROM Mode
图9-36. Device Control, Register, and Memory Interfaces
9.5.2 I2C Serial Interface
When started in I2C mode (HW_SW_CTRL = 0 or 1), the LMK05318B operates as an I2C slave and supports
bus rates of 100 kHz (standard mode) and 400 kHz (fast mode). Slower bus rates can work as long as the other
I2C specifications are met.
In EEPROM mode, the LMK05318B can support up to four different I2C addresses depending on the GPIO1
pins. The 7-bit I2C address is 11001xxb, where the two LSBs are determined by the GPIO1 input levels sampled
at device POR and the five MSBs (11001b) are initialized from the EEPROM. In ROM mode, the two LSBs are
fixed to 00b, while the five MSB (11001b) are initialized from the EEPROM. The five MSBs (11001b) can be
changed with new EEPROM programming.
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Write Transfer
1
7
1
1
A
1
S
Secondary Address
Wr
8
8
1
Register Address High
A
Register Address Low
A
8
1
1
Data Byte
A
P
Read Transfer
1
7
1
1
S
Secondary Address
Wr
A
8
8
1
1
Register Address High
A
Register Address Low
A
7
1
1
1
Sr
Secondary Address
Rd
A
8
1
1
Data Byte
A
P
Legend
S
Sr
Start condition sent by main device
Write bit = 0 sent by main device
Acknowledge sent by main device
Stop condition sent by main device
Not-acknowledge sent by main device
|
|
|
Repeated start condition sent by main device
Read bit = 1 sent by main device
Wr Rd
A
P
N
A
Acknowledge sent by secondary device
|
|
Not-acknowledge sent by secondary device
Data sent by secondary device
N
Data
Data sent by main device
Data
图9-37. I2C Byte Write and Read Transfers
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9.5.2.1 I2C Block Register Transfers
The device supports I2C block write and block read register transfers as shown in 图9-38.
Block Write Transfer
1
7
1
1
A
1
S
Secondary Address
8
Wr
8
1
Register Address High
A
Register Address Low
A
8
1
8
1
1
Data Byte
A
Data Byte
A
P
Block Read Transfer
1
7
1
1
S
Secondary Address
Wr
A
8
8
1
1
Register Address High
A
Register Address Low
A
7
1
1
1
Sr
Secondary Address
Rd
A
8
1
8
1
1
Data Byte
A
Data Byte
A
P
图9-38. I2C Block Register Transfers
9.5.3 SPI Serial Interface
When started in SPI mode (HW_SW_CTRL = Float or VIM), the device uses a 4-wire SPI interface with SDI,
SCK, SDO, and SCS signals. The host device must present data to the device MSB first. A message includes a
transfer direction bit ( W/R), a 15-bit address field (A14 to A0), and a 8-bit data field (D7 to D0) as shown in 图
9-39. The W/R bit is 0 for a SPI write and 1 for a SPI read.
MSB
LSB
0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
MSB Transmitted First
Bit Definition
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
A
A
14 13 12 11
A
First Out
Message Field Definition
Register Address (15 bits)
Data Payload (8 bits)
图9-39. SPI Message Format
A message frame is initiated by asserting SCS low. The frame ends when SCS is deasserted high. The first bit
transferred is the W/R bit. The next 15 bits are the register address, and the remaining eight bits are data. On
write transfers, data is committed in bytes as the final data bit (D0) is clocked in on the rising edge of SCK. If the
write access is not an even multiple of eight clocks, the trailing data bits are not committed. On read transfers,
data bits are clocked out from the SDO pin on the falling edges of SCK.
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9.5.3.1 SPI Block Register Transfer
The device supports a SPI block write and block read transfers. A SPI block transfer is exactly (2 + N) bytes
long, where N is the number of data bytes to write or read. The host device (SPI master) is only required to
specify the lowest address of the sequence of addresses to be accessed. The device will automatically
increment the internal register address pointer if the SCS pin remains low after the host finishes the initial 24-bit
transmission sequence. Each transfer of eight bits (a data payload width) results in the device automatically
incrementing the address pointer (provided the SCS pin remains active low for all sequences).
9.5.4 Register Map and EEPROM Map Generation
The TICS Pro software tool for EVM programming has a step-by-step design flow to enter the user-selected
clock design parameters, calculate the frequency plan, and generate the device register settings for the desired
configuration. The register map data (hex format) or SRAM/EEPROM map data can be exported to enable host
programming of the LMK05318B on start-up.
If desired, customers may send their TICS Pro setup file (.tcs) to TI to review and optimize the configuration
settings, or to support factory pre-programmed samples.
9.5.5 General Register Programming Sequence
For applications that use a system host to program the initial LMK05318B configuration after start-up, this
general procedure can be followed from the register map data generated and exported from TICS Pro:
1. Apply power to the device to start in I2C or SPI mode. The PDN pin must be pulled high or driven high.
2. Write the register settings from lower to higher addresses (R0 to R352) while applying the following register
mask (do not modify mask bits = 1):
• Mask R12 = A7h (Device reset/control register)
• Mask R157 = FFh (NVM control bits register)
• Mask R164 = FFh (NVM unlock bits register)
• Mask R353 to R435 = FFh (Internal test/diagnostic registers should not be written)
3. Write 1b to R12[7] to assert device soft-reset. This does not reset the register values.
4. Write 0b to R12[7] to exit soft-reset and begin the PLL start-up sequence.
5. See 节9.5.6.1 to store the active configuration to the EEPROM to enable auto-startup on the next power
cycle.
9.5.6 EEPROM Programming Flow
Before the EEPROM can be programmed, it is necessary to program the desired configuration to the SRAM
through the memory control registers. The register data can be written to the SRAM by transferring the active
register configuration internally using Method #1, or by direct writes to the SRAM using Method #2.
• Method #1 (Register Commit) requires the active registers be first programmed to the desired configuration,
but does not require knowledge of the SRAM/EEPROM map.
• Method #2 (Direct Writes) bypasses any writes to the active registers, allowing the device to continue normal
operation without disruption while the SRAM/EEPROM are programmed.
The programming flow for the two methods are different and described as follows.
9.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
This sequence can be followed to program the SRAM and EEPROM using the active register configuration.
1. Program the desired configuration to the active registers (see 节9.5.5). This requires the register settings in
the register map format.
2. Write SRAM Using Register Commit.
3. Program EEPROM.
9.5.6.1.1 Write SRAM Using Register Commit
The SRAM array is volatile shadow memory mapped to a subset of the active configuration registers and is used
to program the EEPROM.
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Once the active registers have been programmed, the data can be internally committed to the SRAM with a
single register transaction:
1. Write 40h to R157 (REGCOMMIT bit, self-clearing). This commits the current register data to the SRAM
internally.
2. (Optional) : Program any of the user-programmable fields to SRAM. See 节9.5.6.2.2 for more information.
This step should not precede the prior step.
9.5.6.1.2 Program EEPROM
The EEPROM array is non-volatile memory mapped directly from the SRAM array.
After the register settings have been written to the SRAM (by either Method #1 or #2), the EEPROM can be
programmed through the following sequence:
1. Write EAh to R164 (NVMUNLK). This unlocks the EEPROM to allow programming.
2. Write 03h to R157 (NVM_ERASE_PROG bits). This programs the EEPROM from the entire contents of the
SRAM. The total erase/program cycle takes about 230 ms.
• NOTE: Steps 1 and 2 must be atomic writes without any other register transactions in-between.
3. (Optional) : Read or poll R157[2] (NVMBUSY bit). When this bit cleared, the EEPROM programming is done.
4. (Optional) : Write 00h to R164. This locks the EEPROM to protect against inadvertent programming.
On the next power up or hard-reset, the device can self-start in EEPROM mode from the newly programmed
configuration. Also, the NVMCNT register value will be incremented by 1 after power up or hard-reset to reflect
total number of EEPROM programming cycles completed successfully.
9.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
This sequence can be followed to program the EEPROM by writing the SRAM directly to avoid disruption to the
current device operation. This requires the register settings in the SRAM/EEPROM map format.
1. Write SRAM Using Direct Writes.
2. Program EEPROM.
9.5.6.2.1 Write SRAM Using Direct Writes
This SRAM direct write method can be used if it is required to store a different device configuration to EEPROM
without disrupting the current operational state of the device. This method requires that the SRAM/EEPROM
map data is already generated, which can be exported by TICS Pro.
The SRAM can be directly written without modifying the active configuration registers through the following
sequence:
1. Write the most significant five bits of the SRAM address to R159 (MEMADR byte 1) and write the least
significant eight bits of the SRAM address to R160 (MEMADR byte 0).
2. Write the SRAM data byte to R162 (RAMDAT byte) for the address specified in the previous step in the
same register transaction.
• Any additional write (or read) transfers in same transaction will cause the SRAM address pointer to be
auto-incremented and a subsequent write (or read) will take place at the next SRAM address.
• Byte or Block write transfers to R162 can be used to write the entire SRAM map sequentially from Byte 0
to 252.
– Bytes 253 to 255 must not be modified or overwritten and shall be reserved for TI internal use only.
• Alternatively, it is valid to write R159 and R160 to set the memory address pointer explicitly before each
write to R162.
• Access to the SRAM will terminate at the end of current write transaction.
• Note that reading the RAMDAT register will also cause the memory address pointer to be auto-
incremented.
9.5.6.2.2 User-Programmable Fields In EEPROM
表 9-9 summarizes the address of several user-programmable bytes in EEPROM. These bytes can be written
using the SRAM direct write method prior to programming the EEPROM. It is optional to modify these bytes from
their factory default settings.
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表9-9. User-Programmable Fields
ADDRESS BYTE #
FIELD NAME
DESCRIPTION
(DECIMAL)
I2C Slave Address MSB Bits [7:3].
Bits [7:3] can be written to set the five MSBs of the 7-bit slave address. Bits [2:0]
should be written with zeros. The two LSBs of the 7-bit address are determined by the
control pins on device start-up. Default SLAVEADR[7:0] value = C8h (corresponds to
7-bit address of 64h).
10
SLAVEADR[7:0]
After the EEPROM is programmed and a subsequent POR cycle, the SLAVEADR
value stored in EEPROM can be read from R10.
EEPROM Image Revision.
This byte can be written to set the EEPROM image revision number or any customer-
specific data for part traceability.
11
EEREV[7:0]
After the EEPROM is programmed and a subsequent POR cycle, the EEREV value
stored in EEPROM can be read from R11.
249
250
251
252
NVM_SPARE_BY0[7:0]
NVM_SPARE_BY1[7:0]
NVM_SPARE_BY2[7:0]
NVM_SPARE_BY3[7:0]
NVM Spare Bytes.
These four bytes can be written with any customer-specific data for part traceability.
After the EEPROM is programmed, these bytes can only be read directly from
EEPROM, as there is no register allocation (see 节9.5.8).
9.5.7 Read SRAM
The contents of the SRAM can be read back, one word at a time, starting with that of the requested address
through the following sequence. This sequence can be used to verify the contents of the SRAM before it is
transferred to the EEPROM during an EEPROM program cycle.
1. Write the most significant five bits of the SRAM address to R159 (MEMADR byte 1) and write the least
significant eight bits of the SRAM address to R160 (MEMADR byte 0).
2. Read R162 (RAMDAT byte) to fetch the SRAM data byte from the address specified in the previous step in
the same register transaction.
• Any additional read transfers that are part of the same transaction will cause the SRAM address to auto-
increment and a subsequent read will take place at the next SRAM address.
• Byte or Block read transfers from R162 can be used to read the entire SRAM map sequentially from Byte
0 to 252.
• Access to SRAM will terminate at the end of current register transaction.
9.5.8 Read EEPROM
The contents of the EEPROM can be read back, one word at a time, starting with that of the requested address
through the following sequence. This sequence can be used to verify the EEPROM contents after the last
successful program cycle.
1. Write the most significant five bit of the EEPROM address in R159 (MEMADR byte 1) and write the least
significant eight bits of the EEPROM address in R160 (MEMADR byte 0).
2. Read R161 (NVMDAT byte) to fetch the EEPROM data byte from the address specified in the previous step
in the same register transaction.
• Any additional read transfer that is part of the same transaction will cause the EEPROM address pointer
to be auto-incremented and a subsequent read will take place of the next address.
• Byte or Block read transfers from R161 can be used to read the entire EEPROM map sequentially from
Byte 0 to 252.
• Access to EEPROM will terminate at the end of current register transaction.
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9.5.9 EEPROM Start-Up Mode Default Configuration
The generic LMK05318B device is factory pre-programmed with the EEPROM default configuration in 表9-10. A
different start-up configuration can be stored to the EEPROM through in-system programming.
表9-10. LMK05318B EEPROM Start-Up Default Configuration
SYSTEM CLOCK
XO
FREQUENCY (MHz)
INPUT TYPE
XO DOUBLER
48.0048
AC-DIFF(ext. term)
Disabled
CLOCK INPUTS
PRIREF
FREQUENCY (MHz)
INPUT TYPE
AUTO PRIORITY
25
25
AC-DIFF(ext. term)
AC-DIFF(ext. term)
1st
SECREF
2nd
MANUAL REGISTER
SELECTION
INPUT SELECTION
DPLL
INPUT SELECT MODE
MANUAL SELECTION MODE
Manual with Auto-Fallback
Pin Select
PRIREF
CLOCK OUTPUTS
OUT0
FREQUENCY (MHz)
OUTPUT MUX
PLL 1
OUTPUT TYPE
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
156.25
156.25
156.25
156.25
156.25
156.25
25
OUT1
PLL 1
OUT2
PLL 1
OUT3
PLL 1
OUT4
PLL 1
OUT5
PLL 1
OUT6
PLL 1
OUT7
100
PLL 1
PLL CONFIGURATION
PLL MODE
DPLL Mode
DPLL Mode
Disabled
LOOP BW (Hz)
TDC or PFD RATE (MHz)
DPLL
APLL1
APLL2
100
1000
–
25
24.0024
–
REF INPUT MONITORS (1)
PRIREF
VALIDATION TIMER (s)
FREQ DET VALID (ppm)
FREQ DET INVALID (ppm)
0.1
0.1
-
-
-
-
SECREF
1-PPS JITTER THRESHOLD
REF INPUT MONITORS (2)
EARLY DETECT WINDOW (ns)
LATE DETECT WINDOW (ns)
(μs)
PRIREF
33.6
33.6
46.4
46.4
–
–
SECREF
DCO MODE
DPLL
DCO CONTROL
STEP SIZE (ppb)
FINC/FDEC MODE
DCO Disabled
Register bit
–
ZERO-DELAY MODE
REF-to-OUT7
DPLL ZDM SYNC
PHASE OFFSET (ns)
ZDM Disabled
–
STATUS PINS
STATUS0
SIGNAL
TYPE
POLARITY
Active High
Active High
DPLL Loss of Frequency Lock
DPLL Holdover Active
3.3-V LVCMOS
3.3-V LVCMOS
STATUS1
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10 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
10.1.1 Device Start-Up Sequence
The device start-up sequence is shown in 图10-1.
Power-On Reset
(POR)
Device POR
Configuration Sequence
PDN = 0
Hard Reset?
Outputs muted
PDN = 1
HW_SW_CTRL = 1
GPIO[2:0] = 000b to 111b
(ROM Page Select)
HW_SW_CTRL = 0
GPIO1 = 0, Float, 1 (I2C Addr. Select)
Start-up Mode?
(sample pin states)
HW_SW_CTRL = Float
STATUS[1:0] = Float
EEPROM + I2C
(Soft Pin) Mode
EEPROM + SPI
(Soft Pin) Mode
ROM + I2C
(Hard Pin) Mode
Registers initialize from EEPROM/ROM and I2C/SPI,
Control & Status pins activate (after hard reset only).
All blocks reset to initial states.
RESET_SW = 0
Soft Reset?
RESET_SW = 1
Device Block
Configuration
Register and EEPROM programming available.
XO Detected
VCO Calibration
PLL Initialization Sequence
APLL2 locks before APLL1 in Cascaded mode.
Outputs lock to XO frequency.
Outputs un-mute if DPLL auto-mute disabled.
Outputs auto-SYNC if enabled.
APLL(s) Locked
(Free-run from XO)
Input Monitoring (fastest to slowest detector):
1. Missing and/or Early clock detector
2. Amplitude or Slew rate detector
Ref. Input
Validation
3. Frequency (ppm) detector
4. 1-PPS phase valid detector (skip #1 and 3 for 1-PPS)
5. After enabled detectors are valid, validation timer starts
and must finish before input is qualified.
Valid Input Selected
DPLL
Lock Acquisition
Fastlock DPLL bandwidth is temporarily asserted
during lock acquisition.
Outputs lock to selected input clock frequency.
Outputs are un-muted if DPLL auto-mute enabled.
Normal DPLL bandwidth is asserted.
DPLL frequency- and phase-lock detectors are monitored.
Output will have deterministic input-to-output phase
relationship if Zero-Delay Mode (ZDM) SYNC is enabled.
DCO Mode control
available (ZDM
must be disabled)
DPLL
Locked
See DPLL Modes
and
Input Selection
Flowcharts
图10-1. Device Start-Up Sequence
10.1.2 Power Down (PDN) Pin
The PDN pin (active low) can be used for device power down and used to initialize the POR sequence. When
PDN is pulled low, the entire device is powered down and the serial interface is disabled. When PDN is pulled
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high, the device POR sequence is triggered to begin the device start-up sequence and normal operation as
depicted in 图 10-1. If the PDN pin is toggled to issue a momentary hard-reset, the negative pulse applied to the
PDN pin should be greater than 200 ns to be captured by the internal digital system clock.
表10-1. PDN Control
PDN PIN STATE
DEVICE OPERATION
Device is disabled
Normal operation
0
1
10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
10.1.3.1 Mixing Supplies
The LMK05318B incorporates flexible power supply architecture. While all VDD core supplies should be
powered by the same 3.3-V rail, the individual output supplies can be powered from separate 1.8-V, 2.5-V, or
3.3-V rails. This can allow all VDDO output supplies to operate at 1.8 V to minimize power consumption.
10.1.3.2 Power-On Reset (POR) Circuit
The LMK05318B integrates a built-in power-on reset (POR) circuit that holds the device in reset until all of the
following conditions have been met:
• All VDD core supplies have ramped above 2.72 V
• PDN pin has ramped above 1.2 V (minimum VIH)
10.1.3.3 Powering Up From a Single-Supply Rail
As long as all VDD core supplies are driven by the same 3.3-V supply rail that ramp in a monotonic manner from
0 V to 3.135 V, irrespective of the ramp time, then there is no requirement to add a capacitor on the PDN pin to
externally delay the device power-up sequence. As shown in 图 10-2, the PDN pin can be left floating or
otherwise driven by a system host to meet the clock sequencing requirements in the system.
VDD_PLLx, VDD_IN,
3.135 V
VDD_DIG,
VDD_XO,VDDOx,
PDN
Decision Point 2:
VDD_PLLx/VDD_IN/
VDD_DIG / VDD_XO /
VDDOx ≥ 2.72 V
VDD_IN
200 kꢀ
Decision Point 1:
PDN ≥ 1.2 V
PDN
0 V
图10-2. Recommendation for Power Up From a Single-Supply Rail
10.1.3.4 Power Up From Split-Supply Rails
If some VDD core supplies are driven from different supply rails, TI recommends to start the PLL calibration after
all of the core supplies have ramped above 3.135 V. This can be realized by delaying the PDN low-to-high
transition. The PDN input incorporates a 200-kΩ resistor to VDD_IN and as shown in 图 10-3, a capacitor from
the PDN pin to GND can be used to form an R-C time constant with the internal pullup resistor. This R-C time
constant can be designed to delay the low-to-high transition of PDN until all the core supplies have ramped
above 3.135 V.
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Alternatively, the PDN pin can be driven high by a system host or power management device to delay the device
power-up sequence until all VDD supplies have ramped.
VDD_PLLx,
VDD_IN,
3.135 V
Decision Point 3
VDD_PLLx/
VDD_DIG,
VDDXO
VDD_IN/ VDD_DIG/
VDDXO
VDD_IN
≥ 2.72 V
Decision Point 2:
VDDOx ≥ 1.7 V
VDDO_x,
PDN
200 kΩ
PDN
Decision Point 1:
PDN ≥ 1.2 V
CPDN
Delay
0 V
图10-3. Recommendation for Power Up From Split-Supply Rails
10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
In case the VDD core supplies ramp with a non-monotonic manner or a slow ramp time from 0 V to 3.135 V over
100 ms, TI recommends to delay the VCO calibration until after all of the core supplies have ramped above
3.135 V. This could be achieved by delaying the PDN low-to-high transition with one of the methods described in
节10.1.3.4.
If any core supply cannot ramp above 3.135 V before the PDN low-to-high transition, it is acceptable to issue a
device soft-reset after all core supplies have ramped to manually trigger the VCO calibration and PLL start-up
sequence.
10.1.4 Slow or Delayed XO Start-Up
The external XO clock input is used as the reference input for the VCO calibration, therefore the XO input
amplitude and frequency must be stable before the start of VCO calibration to ensure successful PLL lock and
output start-up. If the XO clock is not stable prior to VCO calibration, the VCO calibration can fail and prevent
PLL lock and output clock start-up.
If the XO clock has a slow start-up time or has glitches on power up (due to a slow or non-monotonic power
supply ramp, for example), TI recommends to delay the start of VCO calibration until after the XO is stable. This
could be achieved by delaying the PDN low-to-high transition until after the XO clock has stabilized using one of
the methods described in 节 10.1.3.4. It is also possible to issue a device soft-reset after the XO clock has
stabilized to manually trigger the VCO calibration and PLL start-up sequence.
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10.2 Typical Application
图 10-4 shows a reference schematic to help implement the LMK05318B and its peripheral circuitry. Power filtering examples are given for the core
supply pins and independent output supply pins. Single-ended LVCMOS, AC-coupled differential, and HCSL clock interfacing examples are shown for the
clock input and output pins. An external LVCMOS oscillator drives an AC-coupled voltage divider network as an example to interface the 3.3-V LVCMOS
output to meet the input voltage swing specified for the XO input. The required external capacitors are placed close to the LMK05318B and are shown
with the suggested values. External pullup and pulldown resistor options at the logic I/O pins set the default input states. The I2C or SPI pins and other
logic I/O pins can be connected to a host device (not shown) to program and control the LMK05318B and monitor its status. This example assumes the
device will start up from EEPROM mode with an I2C interface (HW_SW_CTRL = 0).
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POWER FILTERING
LMK05318
VDDOx = 1.8, 2.5, or 3.3 V (DIFF or HCSL)
VDDOx = 1.8 V (1.8-V LVCMOS)
3.3V
3.3V
U1
VDD_DIG
VDD_IN
VDD_PLL1
VDD_PLL2
FB1
FB2
VDDIN
VDDPLL1
VDDDIG
VDDIN
VDDPLL1
VDDPLL2
VDDO01
VDDO23
VDDO4
VDDO5
VDDO6
VDDO7
4
5
27
36
18
19
37
40
43
46
0.1µF C2
0.1µF C8
0.1µF C10
0.1µF C12
0.1µF C13
0.1µF C14
0.1µF C1
0.1µF C7
0.1µF C9
0.1µF C11
220 ohm
220 ohm
VDDO_01
VDDO_23
VDDO_4
VDDO_5
VDDO_6
VDDO_7
C3
C4
10µF
C5
0.1µF
C6
10µF
0.1µF
10µF
10µF
10µF
C15
C16
C17
3
28
35
CAP_DIG
CAP_PLL1
CAP_PLL2
3.3V
3.3V
OUT0_P
OUT0_N
14
15
OUT0_P
OUT0_N
FB3
FB4
VDDXO
VDDPLL2
0.47uF
0.1uF
C22
C23
29
34
220 ohm
220 ohm
LF1
LF2
C18
C19
10µF
C20
0.1µF
C21
10µF
OUT1_P
OUT1_N
17
16
OUT1_P
OUT1_N
0.1µF
PRIREF_P
PRIREF_N
6
7
PRIREF_P
PRIREF_N
OUT2_P
OUT2_N
20
21
OUT2_P
OUT2_N
Place C near pins
SECREF_P
SECREF_N
10
11
SECREF_P
SECREF_N
OUT3_P
OUT3_N
3.3V
1.8/2.5/3.3V
23
22
OUT3_P
OUT3_N
FB5
VDDDIG
VDDOx
REFSEL
HWCTRL
OUT4_P
OUT4_N
8
9
39
38
220 ohm
REFSEL
OUT4_P
OUT4_N
C24
1µF
C25
0.1µF
C26
10µF
HW_SW_CTRL
OUT5_P
OUT5_N
42
41
OUT5_P
OUT5_N
GPIO0
GPIO1
GPIO2
XO_P
XO_N
VDDXO
12
24
30
31
32
33
GPIO0
GPIO1
GPIO2
XO_P
XO_N
VDD_XO
OUT6_P
OUT6_N
45
44
OUT6_P
OUT6_N
CLOCK INPUT EXAMPLES
OUT7_P
OUT7_N
48
47
OUT7_P
OUT7_N
DIFF DRIVER
OUT+
0.1µF
0.1µF
C27 PRIREF_P
C28 PRIREF_N
TP1
TP2
AC-DIFF
INT. TERM
PDN
13
PDN
STAT0
STAT1
1
2
STATUS0
STATUS1
OUT-
SDA
SCL
25
26
SDA
SCL
49
PAD
LVCMOS DRIVER
OUT
LMK05318
Rterm
22
SECREF_P
SECREF_N
LVCMOS
1.8 V to 3.3 V
CONNECT E-PAD TO PCB GROUND
LAYERS WITH 6x6 VIA PATTERN.
CLOCK OUTPUT EXAMPLES
3.3-V LVCMOS OSC EXAMPLE (XO, TCXO)
AC-DIFF RECEIVER
50R
C29
R1
R2
XO_P
XO_N
IN+
0.1µF
0.1µF
OUT0_P
OUT0_N
C30
C31
100
0.1µF
0.1µF
3.3V_LDO
Vbias
50R
AC-DIFF
Y1
VDD
FB6
R3
49.9
4
3
1
2
E/C
IN-
OUT
GND
Place C+R near
XO_P pin
C32
0.1µF
C33
10µF
C34
0.1µF
2.5x2.0mm
8W48070002
48.0048 MHz
HCSL RECEIVER
IN+
50R
50R
OUT1_P
OUT1_N
0
0
R4
HCSL
EXT. TERM
R5
LOGIC I/O PINS
IN-
CONNECT LOGIC I/O PINS TO HOST MCU/FPGA AS NEEDED.
3.3V
LVCMOS RECEIVER
10k R6 DNP
REFSEL
HWCTRL
10k R7
10k R9
LOGIC I/O DEFINITIONS FOR EEPROM START-UP MODE:
1.8-V
LVCMOS
OUT7_P
0
R10
3.6k R8 DNP
IN (Hi-Z)
I2C MODE -- HW_SW_CTRL = 0
- SDA, SCL = I2C DATA, I2C CLK
- GPIO0 = OUTPUT SYNC (ACTIVE LOW)
- GPIO1 = I2C ADDR LSB SELECT (L=00b, Float=01b, H=10b)
10k R11
10k R13 DNP
10k R15 DNP
GPIO0
GPIO1
GPIO2
10k R12
10k R14
10k R16
DNP
SPI MODE -- HW_SW_CTRL = STATUS[1:0] = Float (or 0.8-V
EXTERNAL BIAS WITH Rpu=10k AND Rpd=3.3k)
- SDA, SCL = SPI DATA IN, SPI CLK
- GPIO1 = SPI SCS
PDN
0.01µF
C35 DNP
4.7k R17
4.7k R18
SDA
SCL
- GPIO2 = SPI DATA OUT
图10-4. LMK05318B Reference Schematic Example
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10.2.1 Design Requirements
In a typical application, consider the following design requirements or parameters to implement the overall clock
solution:
1. Device initial configuration: The device should be configured as either host programmed (MCU or FPGA) or
factory pre-programmed.
2. Device start-up mode and serial interface: Typically, this will be EEPROM + I2C or SPI mode.
3. XO frequency, signal type, and frequency accuracy and stability: Consider a high-stability TCXO or OCXO
for the XO input if any of the following is required:
• Standard-compliant frequency stability (such as SyncE, SONET/SDH, IEEE 1588)
• Lowest possible close-in phase noise at offsets ≤100 Hz
• Narrow DPLL bandwidth ≤10 Hz
4. For the DPLL/APLL1 domain, determine the following:
• Input clocks: frequency, buffer mode, priority, and input selection mode
• Output clocks: frequency, buffer mode
• DPLL loop bandwidth and maximum TDC frequency
• If the DCO Mode is required
5. For the APLL2 domain, determine the following:
• APLL2 reference: VCO1 for synchronous clocking with Cascaded APLL2, or XO for asynchronous
clocking with Non-cascaded APLL2
• Output clocks: frequency, buffer mode
6. Input clock and PLL monitoring options
7. Status outputs and interrupt flag
8. Power supply rails
10.2.2 Detailed Design Procedure
In a typical application, TI recommends the following steps:
1. Use the LMK05318B GUI in the TICS Pro programming software for a step-by-step design flow to enter the
design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for
the desired configuration. The register settings can be exported (in hex format) to enable host programming
or factory pre-programming.
• If using a generic (non-custom) device, a host device can program the register settings through the serial
interface after power up and issue a soft-reset (by RESET_SW bit) to start the device. The host can also
store the settings to the EEPROM to allow automatic start-up with these register settings on subsequent
power-on reset cycles.
• Alternatively, a LMK05318B setup file for TICS Pro (.tcs) can be sent to TI to support factory pre-
programmed samples.
2. Tie the HW_SW_CTRL pin to ground to select EEPROM+I2C mode, or bias the pin to VIM through the weak
internal resistors or external resistors to select EEPROM+SPI mode. Determine the logic I/O pin
assignments for control and status functions. See 节6.1 for more information.
• Connect I2C/SPI and logic I/O pins (1.8-V compatible levels) to the host device pins with the proper I/O
direction and voltage levels.
3. Select an XO frequency by following 节9.3.1 for more information.
• Choose an XO with target phase jitter performance that meets the frequency stability and accuracy
requirements required for the output clocks during free-run or holdover.
• For a 3.3-V LVCMOS driver, follow the OSC clock interface example in 图10-4. Power the OSC from a
low-noise LDO regulator or optimize its power filtering to avoid supply noise-induced jitter on the XO
clock.
• TICS Pro: Configure the XO input buffer mode to match the XO driver interface requirements. See 表9-1
for more information.
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4. Wire the clock I/O for each PLL domain in the schematic and use TICS Pro to configure the device settings
as follows:
• Reference inputs: Follow the LVCMOS or differential clock input interface examples in 图10-4 or in 节
9.3.3.
– TICS Pro: For DPLL mode, configure the reference input buffer modes to match the reference clock
driver interface requirements. See 表9-2 for more information.
– LVCMOS clock input should be used for input frequencies below 5 MHz when amplitude monitoring is
enabled.
• TICS Pro: For DPLL mode, configure the DPLL input selection modes and input priorities. See 节9.3.4
for more information.
• TICS Pro: If APLL2 is used, configure the APLL2 reference for VCO1 domain (Cascaded APLL2) or XO
clock (Non-cascaded APLL2).
–
• TICS Pro: Configure each output with the required clock frequency and PLL domain. TICS Pro can
calculate the VCO frequencies and divider settings for the PLL and outputs. Consider the following output
clock assignment guidelines to minimize crosstalk and spurs:
– OUT[0:3] bank is preferred for PLL1 clocks.
– OUT[4:7] bank is preferred for PLL2 clocks.
– Group identical output frequencies (or harmonic frequencies) on adjacent channels, and use the
output pairs with a single divider (OUT0/1 or OUT2/3) when possible to minimize power.
– Separate clock outputs when the difference of the two frequencies, |fOUTx –fOUTy|, falls within the
jitter integration bandwidth (12 kHz to 20 MHz, for example). Any outputs that are potential aggressors
should be separated by at least four static pins (power pin, logic pin, or disabled output pins) to
minimize potential coupling. If possible, separate these clocks by the placing them on opposite output
banks, which are on opposite sides of the chip for best isolation.
– Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output
clocks. If an LVCMOS output is required, use dual complementary LVCMOS mode (+/–or –/+) with
the unused LVCMOS output left floating with no trace.
– If not all outputs pairs are used in the application, consider connecting an unused output to a pair of
RF coaxial test structures for testing purposes (such as SMA, SMP ports).
• TICS Pro: Configure the output drivers.
– Configure the output driver modes to match the receiver clock input interface requirements. See 表
9-7 for more information.
– Configure any output SYNC groups that need their output phases synchronized. See 节9.3.15 for
more information.
– Configure the output auto-mute modes, output mute levels, and APLL and DPLL mute options. See 节
9.3.12.4 for more information.
• Clock output Interfacing: Follow the single-ended or differential clock output interface examples in 图10-4
or in 节9.3.14.
– Differential outputs should be AC-coupled and terminated and biased at the receiver inputs.
– HCSL outputs should have 50-Ωtermination to GND (at source or load side) unless the internal
source termination is enabled by programming.
– LVCMOS outputs have internal source termination to drive 50-Ωtraces directly. LVCMOS VOH level is
determined by VDDO voltage (1.8 V).
• TICS Pro: Configure the DPLL loop bandwidth.
– Below the loop bandwidth, the reference noise is added to the TDC noise floor and the XO/TCXO/
OCXO noise. Above the loop bandwidth, the reference noise will be attenuated with roll-off up to 60
dB/decade. The optimal bandwidth depends on the relative phase noise between the reference input
and the XO. The loop bandwidth of the APLL1 can be configured to provide additional attenuation of
the reference input, TDC, and XO phase noise above the bandwidth of the APLL1 (typically around 1
kHz).
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• TICS Pro: Configure the maximum TDC frequency to optimize the DPLL TDC noise contribution for the
desired use case.
– Wired: The maximum TDC rate is preset to 400 kHz. This supports SyncE and other use cases using
a narrow loop bandwidth (≤10 Hz) with a TCXO/OCXO/XO to set the frequency stability and wander
performance.
– Wireless: The maximum TDC rate is preset to 26 MHz for lowest in-band TDC noise contribution. This
supports wireless and other use cases where close-in phase noise is critical.
– Custom: The maximum TDC rate can be specified for any value up to 26 MHz.
• TICS Pro: If clock steering is needed (such as for IEEE 1588 PTP), enable DCO mode for the DPLL loop
and enter the frequency step size (in ppb). The FDEV step register will be computed according to 节
9.4.4.1. Enable the FINC/FDEC pin control on the GPIO pins, if needed.
• TICS Pro: If deterministic input-to-output clock phase is needed for 1-PPS input and 1-PPS output (on
OUT7), enable the ZDM and OUT7 divider synchronization features. See 节9.3.16 for more information.
5. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor
when not required or when the input operates beyond the supported frequency range of the monitor. See 节
9.3.7.2 for more information.
• Amplitude monitor: Set the LVCMOS detected slew rate edge or the differential input amplitude threshold
to monitor input signal quality. Disable the monitor for a differential input below 5 MHz or else use an
LVCMOS input clock.
• Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock
period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set TLATE based on the
number of allowable missing clock pulses.
• Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock
period, including worst-case cycle-to-cycle jitter.
• 1-PPS Phase validation monitor: Set the phase validation jitter threshold, including worst-case input
cycle-to-cycle jitter.
• Validation timer: Set the amount of time the reference input must be qualified by all enabled input
monitors before the input is valid for selection.
6. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See
节9.3.7.3 and 节9.3.7.4 for more information.
• DPLL tuning word history: Set the history count/averaging time (TAVG), history delay/ignore time (TIGN),
and intermediate averaging option.
• DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
7. TICS Pro: Configure each status output pin and interrupt flag as needed. See 节9.3.7.5 and 节9.3.7.6 for
more information.
• Select the desired status signal selection, status polarity, and driver mode (3.3-V LVCMOS or open-
drain). Open-drain requires an external pullup resistor.
• If the Interrupt is enabled and selected as a status output, configure the flag polarity and the mask bits for
any interrupt source, and the combinational AND/ OR gate as needed.
8. Consider the following guidelines for designing the power supply:
• Outputs with identical frequency or integer-related (harmonic) frequencies can share a common filtered
power supply.
– Example: 156.25-MHz and 312.5-MHz outputs on OUT[0:1] and OUT[2:3] can share a filtered VDDO
supply (Group 1), while 100-MHz, 50-MHz, and 25-MHz outputs on OUT[4:7] can share a separate
VDDO supply (Group 2).
• For lowest power, AC-DIFF or HCSL outputs can be powered from a 1.8-V supply with no degradation in
output swing or phase noise (compared to 2.5 V or 3.3 V).
• 1.8-V LVCMOS outputs should be powered from a 1.8-V supply.
• See 节10.1.3.
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10.2.3 Application Curves
Jitter = 65 fs RMS (12 kHz to 20 MHz)
fVCO1 = 2500 MHz (VCO1 inverted)
Jitter = 136 fs RMS (12 kHz to 20 MHz)
fVCO2 = 6065.28 MHz (VCO2 post-divider = 3)
图10-5. 156.25-MHz Output Phase Noise (OUT3)
图10-6. 155.52-MHz Output Phase Noise (OUT4)
With 155.52-MHz Output Enabled (OUT4)
With 156.25-MHz Output Enabled (OUT3)
10.3 Do's and Don'ts
• Power all the VDD pins with proper supply decoupling and bypassing connect as shown in 图10-4.
• Power down unused blocks through registers to minimize power consumption.
• Use proper source or load terminations to match the impedance of input and output clock traces for any
active signals to/from the device.
• Leave unused clock outputs floating and powered down through register control.
• Leave unused clock inputs floating.
• For EEPROM+SPI Mode: Leave HW_SW_CTRL and STATUS[1:0] pins floating during POR to ensure proper
start-up. These pins has internal biasing to VIM internally.
– If HW_SW_CTRL or either STATUS pin is connected to a system host (MCU or FPGA), the host device
must be configured with high-impedance input (no pullup or pulldown resistors) to avoid conflict with the
internal bias to VIM. If needed, external biasing resistors (10-kΩpullup to 3.3 V and 3.3-kΩpulldown) can
be connected on each STATUS pin to bias the inputs to VIM during POR.
• Consider routing each STATUS pin to a test point or high-impedance input of a host device to monitor device
status outputs.
• Consider using a LDO regulator to power the external XO/TCXO/OCXO source.
– High jitter and spurious outputs on the oscillator clock are often caused by high spectral noise and ripple
on the power supply.
• Include dedicated header to access the I2C or SPI interface of the device, as well as a header pin for ground.
– This can enabled off-board programming for device bring-up, prototyping, and diagnostics using the TI
USB2ANY interface and TICS Pro software tools.
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11 Power Supply Recommendations
11.1 Power Supply Bypassing
图 11-1 shows two general placements of power supply bypass capacitors on either the back side or the
component side of the PCB. If the capacitors are mounted on the back side, 0402 components can be
employed. For component side mounting, use 0201 body size capacitors to facilitate signal routing. A
combination of component side and back side placement can be used. Keep the connections between the
bypass capacitors and the power supply on the device as short as possible. Ground the other side of the
capacitor using a low-impedance connection to the ground plane.
(Does not indicate actual location of the LMK05318B supply pins)
图11-1. Generalized Placement of Power Supply Bypass Capacitors
11.2 Device Current and Power Consumption
The device power consumption is dependent on the actual configuration programmed to the device. The
individual supply pin current consumption values in 节 7.6 can be used to estimate device power consumption
and power supply dimensioning.
11.2.1 Current Consumption Calculations
Core supply currents:
IDD_CORE = IDD_DIG + IDD_IN + IDD_XO + IDD_PLL1 + IDD_PLL2
OUT[0:1] or OUT[2:3] channel supply current:
IDDO_XY = IDDO_XYDIVIDER + IDDO_XDRIVER + IDDO_YDRIVER
OUT[4:7] channel supply current:
(14)
(15)
(16)
IDDO_X = IDDO_XDIVIDER + IDDO_XDRIVER
When the divider and drivers of an output channel are disabled, the IDDO_x of the channel equals
approximately 0 mA.
11.2.2 Power Consumption Calculations
Core power consumption:
PCORE = IDD_CORE × VDD
(17)
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Output power consumption:
POUT = (IDDO_01 × VDDO_01) + (IDDO_23 × VDDO_23) + ... + (IDDO_7 × VDDO_7)
Total device power consumption:
(18)
(19)
PTOTAL = PCORE + POUT
11.2.3 Example
Estimate the current and power consumption for the following device configuration:
• VDD = 3.3 V and VDDO_x = 1.8 V
• DPLL/APLL1 mode with Cascaded APLL2
• XO: 48 MHz, PRIREF and SECREF: 25 MHz
• OUT[0:1]: 156.25 MHz AC-LVPECL (x2), PLL1
• OUT[2:3]: 156.25 MHz AC-CML (x2), PLL1
• OUT4: 133.33 MHz AC-LVDS, PLL2
• OUT5: Disabled
• OUT6: 100 MHz HCSL, PLL1
• OUT7: 25 MHz LVCMOS (x2), PLL1
From 方程式14: IDD_CORE = 18 + 38 + 20 + 110 + 120 = 306 mA
From 方程式15 and 方程式16:
• IDDO_01 = 70 + 16 + 16 = 102 mA
• IDDO_23 = 70 + 14 + 14 = 98 mA
• IDDO_4 = 70 + 10 = 80 mA
• IDDO_5 = 0 mA
• IDDO_6 = 70 + 25 = 95 mA
• IDDO_7 = 70 + 6 = 76 mA
From 方程式17: PCORE = 306 mA × 3.3 V = 1.01 W
From 方程式18: POUT = (102 + 98 + 80 + 95 + 76) mA × 1.8 V = 0.812 W
From 方程式19: PTOTAL = 1.01 W + 0.812 W = 1.822 W
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12 Layout
12.1 Layout Guidelines
• Isolate input, XO/OCXO/TCXO and output clocks from adjacent clocks with different frequencies and other
nearby dynamic signals.
• Consider the XO/OCXO/TCXO placement and layout in terms of the supply/ground noise and thermal
gradients from nearby circuitry (for example, power supplies, FPGA, ASIC) as well as system-level vibration
and shock. These factors can affect the frequency stability/accuracy and transient performance of the
oscillator.
• Avoid impedance discontinuities on controlled-impedance 50-Ωsingle-ended (or 100-Ωdifferential) traces
for clock and dynamic logic signals.
• Place bypass capacitors close to the VDD and VDDO pins on the same side as the IC, or directly below the
IC pins on the opposite side of the PCB. Larger decoupling capacitor values can be placed further away.
• Place external capacitors close to the CAP_x and LFx pins.
• Use multiple vias to connect wide supply traces to the respective power islands or planes, if possible.
• Use at least a 5×5 through-hole via pattern to connect the IC ground/thermal pad to the PCB ground planes.
• See the Land Pattern Example, Solder Mask Details, and Solder Paste Example in 节14.
12.2 Layout Example
图12-1. General PCB Ground Layout for Thermal Reliability (8+ Layers Recommended)
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12.3 Thermal Reliability
The LMK05318B is a high-performance device. To ensure good electrical and thermal performance, TI
recommends to design a thermally-enhanced interface between the IC ground/thermal pad and the PCB ground
using at least a 5×5 through-hole via pattern connected to multiple PCB ground layers as shown in 图12-1.
12.3.1 Support for PCB Temperature up to 105 °C
The device can maintain a safe junction temperature below the recommended maximum value of 125 °C even
when operated on a PCB with a maximum board temperature (TPCB) of 105 °C. This can shown by the following
example calculation, which assumes the total device power (PTOTAL) computed with all blocks enabled using the
typical current consumption from the 节 7.6 (VDD = 3.3 V, VDDO = 1.8 V) and the thermal data in 节 7.5 with no
airflow.
TJ = TPCB + (ΨJB × PTOTAL) = 113.8 °C
(20)
where
• TPCB = 105 °C
• ΨJB = 4.4 °C/W
• PTOTAL = PCORE + POUTPUT = 2.0 W
– PCORE = (18 + 38 + 20 + 110 + 120) mA × 3.3 V = 1.01 W
• DPLL, APLL1, APLL2, and all Inputs enabled
– POUTPUT = (102 + 102 + 86 + 86 + 86 + 86) mA × 1.8 V = 0.986 W
• All output channels enabled with output divider values > 6 and AC-LVPECL output types
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13 Device and Documentation Support
13.1 Device Support
13.1.1 TICS Pro
TICS Pro is an offline software tool for EVM programming and also for register map generation to program a
device configuration for a specific application. For TICS Pro, go to www.ti.com/tool/TICSPRO-SW.
13.1.2 Related Documentation
See the following:
• ITU-T G.8262 Compliance Test Result for the LMK05318 (SNAA316)
• Supported Synchronization Modes With LMK05318 (SNAA324)
• Clocking High-Speed 56G PAM-4 Serial Links With LMK05318 (SNAA325)
• LMK05318EVM User's Guide (SNAU236)
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
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邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK05318BRGZR
LMK05318BRGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LK05318B
LK05318B
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK05318BRGZR
LMK05318BRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
180.0
16.4
16.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK05318BRGZR
LMK05318BRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
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PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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