LMH6732MA/NOPB [TI]
具有可调节带宽的高速运算放大器 | D | 8 | -40 to 85;
| 型号： | LMH6732MA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节带宽的高速运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总34页 (文件大小：1937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6732
www.ti.com
SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
LMH6732 High Speed Op Amp with Adjustable Bandwidth
Check for Samples: LMH6732
1
FEATURES
APPLICATIONS
2
•
Exceptional Performance at Any Supply
Current:
VS = ±5V, TA = 25°C, AV = +2V/V, VOUT = 2VPP
Typical unless Noted:
•
•
•
•
Battery Powered Systems
Video Switching and Distribution
Remote Site Instrumentation
Mobile Communications Gear
,
-3dB
BW
(MHz)
DG/DP
(%/deg.)
PAL
Slew
Rate 1MHz
(V/μs) (dBc)
THD
Output
Current
(mA)
ICC
(mA)
DESCRIPTION
The LMH6732 is a high speed op amp with a unique
combination of high performance, low power
consumption, and flexibility of application. The supply
current is adjustable, over a continuous range of
more than 10 to 1, with a single resistor, RP. This
feature allows the device to be used in a wide variety
of high performance applications including device turn
on/ turn off (Enable/ Disable) for power saving or
multiplexing. Typical performance at any supply
current is exceptional. The LMH6732's design has
been optimized so that the output is well behaved,
eliminating spurious outputs on "Enable".
1.0
3.4
9.0
55
0.20 / 0.036
0.022 / 0.017
0.025 / 0.010
400
2100
2700
-70.0
-78.5
-79.6
9
180
540
45
115
•
Ultra High Speed (−3dB BW) 1.5GHz
(ICC = 10mA, 0.25VPP
)
•
•
Single Resistor Adjustability of Supply Current
Fast Enable/ Disable Capability 20ns
(ICC = 9mA)
•
"Popless" Output on "Enable" 15mV
(ICC = 1mA)
The LMH6732's combination of high performance,
low power consumption, and large signal
performance makes it ideal for a wide variety of
remote site equipment applications such as battery
powered test instrumentation and communications
gear. Other applications include video switching
matrices, ATE and phased array radar systems.
•
•
•
Ultra Low Disable Current <1μA
Unity Gain Stable
Improved Replacement for CLC505 & CLC449
The LMH6732 is available in the SOIC and SOT-23
packages. To reduce design times and assist in
board layout, the LMH6732 is supported by an
evaluation board.
1600
0.6
R
= 100W
= +2
L
0.4
0.2
0
9
6
1400
A
V
OUTPUT
0.25V
PP
R
= 700W
F
1200
1000
-0.2
-0.4
-0.6
-0.8
-1
800
600
400
I
= 9mA
= +2
CC
CONTROL
VOLTAGE
A
V
3
0
R
R
= 700W
= 100W
2.0V
F
L
PP
LMH6732 ON
200
0
1V OUTPUT
PP
500MHz
-1.2
-1.4
0
1
2
3
4
5
6
7
8
9 10 11 12
0
10 20 30 40 50 60 70 80 90 100
I
(mA)
CC
ns
Figure 1. −3dB BW vs. ICC
Figure 2. Turn-On/Off Characteristics
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6732
SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VS
±6.75V
See(3)
IOUT
ICC
14mA
Common Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Soldering Information
V− to V+
+150°C
−65°C to +150°C
235°C
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
Human Body Model
260°C
ESD Tolerance(4)
2000V
Machine Model
200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications..
(3) The maximum output current (IO) is determined by device power dissipation limitations.
(4) Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.
Operating Ratings(1)
Thermal Resistance
Package
8-Pin SOIC
θJC (°C/W)
65°C/W
θJA (°C/W)
166°C/W
198°C/W
6-Pin SOT-23
120°C/W
Operating Temperature
Nominal Supply Voltage
Operating Supply Current
−40°C to +85°C
±4.5V to ±6V
0.5mA < ICC < 12mA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
2
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Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMH6732
LMH6732
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
Electrical Characteristics ICC = 9mA(1)
AV = +2, RF = 700Ω, VS = ±5V, RL = 100Ω, RP = 39kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min(2)
Typ(2)
Max(2)
Units
Frequency Domain Response
SSBW
LSBW
GF0.1dB
GFP
-3dB Bandwidth
VOUT = 2VPP
540
315
MHz
MHz
MHz
dB
-3dB Bandwidth
VOUT = 4.0VPP
0.1dB Gain Flatness
Frequency Response Peaking
Frequency Response Rolloff
Linear Phase Deviation
VOUT = 2VPP
180
DC to 200MHz, VOUT = 2VPP
DC to 200MHz, VOUT = 2VPP
DC to 200MHz, VOUT = 2VPP
DC to 140MHz, VOUT = 2VPP
RL = 150Ω, 4.43MHz
RL = 150Ω, 4.43MHz
0.01
0.15
0.6
GFR
dB
LPD
deg
0.1
DG
DP
Differential Gain
0.025
0.010
%
Differential Phase
deg
Time Domain Response
TRS
TRL
TS
Rise Time
2V Step
0.8
0.9
18
ns
Fall Time
2V Step
Settling Time to 0.04%
Overshoot
AV = −1, 2V Step
2V Step
5V Step, 40% to 60%(3)
ns
%
OS
SR
1
Slew Rate
2700
V/µs
Distortion And Noise Response
HD2
HD3
THD
V N
IN
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input Referred Voltage Noise
2VPP, 20MHz
2VPP, 20MHz
2VPP, 1MHz
>1MHz
−60
−64
−79.6
2.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
Input Referred Inverting Noise Current >1MHz
9.7
INN
Input Referred Non-Inverting Noise
Current
>1MHz
1.8
SNF
INV
Noise Floor
>1MHz
−154
dBm1Hz
Total Integrated Input Noise
1MHz to 200MHz
60
μV
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise
specified.
(2) Typical numbers are the most likely parametric norm. Bold numbers refer to over temperature limits.
(3) Slew Rate is the average of the rising and falling edges.
Copyright © 2003–2013, Texas Instruments Incorporated
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Electrical Characteristics ICC = 9mA(1) (continued)
AV = +2, RF = 700Ω, VS = ±5V, RL = 100Ω, RP = 39kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min(2)
Typ(2)
Max(2)
Units
Static, DC Performance
VIO
Input Offset Voltage
±3.0
±8.0
mV
9.9
DVIO
IBN
Input Offset Voltage Average Drift
Input Bias Current
See(4)
Non Inverting(5)
16
μV/°C
μA
−2
±11
±12
DIBN
IBI
Input Bias Current Average Drift
Input Bias Current
Non-Inverting(4)
Inverting(5)
5
nA/°C
−9
±20
μA
± 30
DIBI
Input Bias Current Average Drift
Inverting(4)
−14
nA/°C
dB
+PSRR
Positive Power Supply Rejection Ratio DC
52
62
50
−PSRR
CMRR
ICC
Negative Power Supply Rejection
Ratio
DC
51
48
56
52
9.0
<1
dB
dB
mA
μA
Common Mode Rejection Ratio
DC
49
46
Supply Current
RL = ∞, RP = 39kΩ
7.5
6.6
10.5
11.7
ICC
I
Supply Current During Shutdown
Miscellaneous Performance
RIN
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop
RL = ∞
4.7
1.8
MΩ
pF
CIN
Input Capacitance
Output Resistance
Output Voltage Range
ROUT
VO
32
mΩ
±3.60
±3.75
±3.55
V
VOL
RL = 100Ω
±2.90
±3.10
±2.85
CMIR
IO
Common Mode Input Range
Output Current
Common Mode
±2.2
V
Closed Loop
±75
±115
mA
−40mV ≤ VO ≤ 40mV
TON
Turn-on Time
Turn-off Time
0.5VPP Sine Wave, 90% of Full
Value
20
9
ns
TOFF
0.5VPP Sine Wave, <5% of Full
Value
VO glitch
FDTH
Turn-on Glitch
Feed-Through
50
mV
dB
f = 10MHz, AV = +2, Off State
−61
(4) Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change
(5) Negative input current implies current flowing out of the device.
4
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
Electrical Characteristics ICC = 3.4mA(1)
AV = +2, RF = 1kΩ, VS = ±5V, RL = 100Ω, RP = 137kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(2)
(2)
Frequency Domain Response
SSBW
LSBW
GF0.1dB
GFP
-3dB Bandwidth
VOUT = 2VPP
180
100
MHz
MHz
MHz
dB
-3dB Bandwidth
VOUT = 4.0VPP
0.1dB Gain Flatness
Frequency Response Peaking
Frequency Response Rolloff
Linear Phase Deviation
VOUT = 2VPP
50
DC to 75MHz, VOUT = 2VPP
DC to 75MHz, VOUT = 2VPP
DC to 55MHz, VOUT = 2VPP
DC to 25MHz, VOUT = 2VPP
RL = 150Ω, 4.43MHz
RL = 150Ω, 4.43MHz
0.15
0.05
0.5
GFR
dB
LPD
deg
0.1
DG
DP
Differential Gain
0.022
0.017
%
Differential Phase
deg
Time Domain Response
TRS
TRL
TS
Rise Time
2V Step
1.7
2.1
18
ns
Fall Time
2V Step
Settling Time to 0.04%
Overshoot
AV = −1, 2V Step
2V Step
5V Step, 40% to 60%(3)
ns
%
OS
SR
2
Slew Rate
2100
V/µs
Distortion And Noise Response
HD2
HD3
THD
V N
IN
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input Referred Voltage Noise
2VPP, 10MHz
2VPP, 10MHz
2VPP, 1MHz
>1MHz
−51
−65
−78.5
4.1
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
Input Referred Inverting Noise Current >1MHz
8.8
INN
Input Referred Non-Inverting Noise
Current
>1MHz
1.1
SNF
INV
Noise Floor
>1MHz
−151
dBm1Hz
Total Integrated Input Noise
1MHz to 100MHz
60
μV
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise
specified.
(2) Typical numbers are the most likely parametric norm. Bold numbers refer to over temperature limits.
(3) Slew Rate is the average of the rising and falling edges.
Copyright © 2003–2013, Texas Instruments Incorporated
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Electrical Characteristics ICC = 3.4mA(1) (continued)
AV = +2, RF = 1kΩ, VS = ±5V, RL = 100Ω, RP = 137kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(2)
(2)
Static, DC Performance
VIO
Input Offset Voltage
±2.5
±7.0
mV
±8.5
DVIO
IBN
Input Offset Voltage Average Drift
Input Bias Current
See(4)
Non Inverting(5)
10
μV/°C
μA
−0.4
±4
±6
DIBN
IBI
Input Bias Current Average Drift
Input Bias Current
Non-Inverting(4)
Inverting(5)
8
nA/°C
−1
±12
μA
±16
DIBI
Input Bias Current Average Drift
Inverting(4)
−3
nA/°C
dB
+PSRR
Positive Power Supply Rejection Ratio DC
52
64
50
−PSRR
CMRR
ICC
Negative Power Supply Rejection
Ratio
DC
51
50
57
55
3.4
<1
dB
dB
mA
μA
Common Mode Rejection Ratio
DC
49
48
Supply Current
RL = ∞, RP = 137kΩ
2.8
2.6
3.9
4.1
ICC
I
Supply Current During Shutdown
Miscellaneous Performance
RIN
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop
RL = ∞
15
1.7
MΩ
pF
CIN
Input Capacitance
Output Resistance
Output Voltage Range
ROUT
VO
50
mΩ
±3.60
±3.78
±3.55
V
VOL
RL = 100Ω
±2.90
±3.10
±2.85
CMIR
IO
Common Mode Input Range
Output Current
Common Mode
±2.2
±45
V
Closed Loop
±30
mA
−20mV ≤ VO ≤ 20mV
TON
Turn-on Time
Turn-off Time
0.5VPP Sine Wave, 90% of Full
Value
42
10
ns
TOFF
0.5VPP Sine Wave, <5% of Full
Value
VO glitch
FDTH
Turn-on Glitch
Feed-Through
25
mV
dB
f = 10MHz, AV = +2, Off State
−61
(4) Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change
(5) Negative input current implies current flowing out of the device.
6
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
Electrical Characteristics ICC = 1.0mA(1)
AV = +2, RF = 1kΩ, VS = ±5V, RL = 500Ω, RP = 412kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(2)
(2)
Frequency Domain Response
SSBW
LSBW
GF0.1dB
GFP
-3dB Bandwidth
VOUT = 2VPP
55
30
MHz
MHz
MHz
dB
-3dB Bandwidth
VOUT = 4.0VPP
0.1dB Gain Flatness
Frequency Response Peaking
Frequency Response Rolloff
Linear Phase Deviation
VOUT = 2VPP
20
DC to 25MHz, VOUT = 2VPP
DC to 25MHz, VOUT = 2VPP
DC to 20MHz, VOUT = 2VPP
DC to 14MHz, VOUT = 2VPP
RL = 500Ω, 4.43MHz
RL = 500Ω, 4.43MHz
0.11
0.05
1
GFR
dB
LPD
deg
0.3
DG
DP
Differential Gain
0.020
0.036
%
Differential Phase
deg
Time Domain Response
TRS
TRL
TS
Rise Time
2V Step
3.7
5.1
18
ns
Fall Time
2V Step
Settling Time to 0.04%
Overshoot
AV = −1, 2V Step
2V Step
5V Step, 40% to 60%(3)
ns
%
OS
SR
2
Slew Rate
400
V/µs
Distortion And Noise Response
HD2
HD3
THD
V N
IN
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input Referred Voltage Noise
2VPP, 5MHz
2VPP, 5MHz
2VPP, 1MHz
>1MHz
−43
−65
−70.0
8.4
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
Input Referred Inverting Noise Current >1MHz
9.0
INN
Input Referred Non-Inverting Noise
Current
>1MHz
0.8
SNF
INV
Noise Floor
>1MHz
−147
dBm1Hz
Total Integrated Input Noise
1MHz to 100MHz
29
μV
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise
specified.
(2) Typical numbers are the most likely parametric norm. Bold numbers refer to over temperature limits.
(3) Slew Rate is the average of the rising and falling edges.
Copyright © 2003–2013, Texas Instruments Incorporated
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Electrical Characteristics ICC = 1.0mA(1) (continued)
AV = +2, RF = 1kΩ, VS = ±5V, RL = 500Ω, RP = 412kΩ; Unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(2)
(2)
Static, DC Performance
VIO
Input Offset Voltage
±1.6
±6.0
mV
±7.3
DVIO
IBN
Input Offset Voltage Average Drift
Input Bias Current
See(4)
Non Inverting(5)
4
μV/°C
μA
0.04
±2.0
±2.5
DIBN
IBI
Input Bias Current Average Drift
Input Bias Current
Non-Inverting(4)
Inverting(5)
−1
nA/°C
−0.1
±6
μA
±8
DIBI
Input Bias Current Average Drift
Inverting(4)
−3
nA/°C
dB
+PSRR
Positive Power Supply Rejection Ratio DC
52
64
51
−PSRR
CMRR
ICC
Negative Power Supply Rejection
Ratio
DC
51
49
59
55
1.0
<1
dB
dB
mA
μA
Common Mode Rejection Ratio
DC
49
47
Supply Current
RL = ∞, RP = 412kΩ
0.70
0.66
1.3
1.4
ICC
I
Supply Current During Shutdown
Miscellaneous Performance
RIN
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop
RL = ∞
46
1.7
MΩ
pF
CIN
Input Capacitance
Output Resistance
Output Voltage Range
ROUT
VO
100
m Ω
±3.60
±3.78
±3.55
V
VOL
RL = 500Ω
±2.90
±3.10
±2.85
CMIR
IO
Common Mode Input Range
Output Current
Common Mode
±2.2
±9
V
Closed Loop
±6
mA
−15mV ≤ VO ≤ 15mV
TON
Turn-on Time
Turn-off Time
0.5VPP Sine Wave, 90% of Full
Value
95
40
ns
TOFF
0.5VPP Sine Wave, <5% of Full
Value
VO glitch
FDTH
Turn-on Glitch
Feed-Through
15
mV
dB
f = 10MHz, AV = +2, Off State
−61
(4) Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change
(5) Negative input current implies current flowing out of the device.
8
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
CONNECTION DIAGRAMS
1
8
N/C
R
P
1
6
+
V
OUT
2
3
4
7
6
5
+
-IN
-
V
R
-
P
2
V
+IN
OUT
+
-
+
4
3
-
-IN
+IN
N/C
V
Figure 3. 8-Pin SOIC (Top View)
See Package Number D (R-PDSO-G8)
Figure 4. 6-Pin SOT-23 (Top View)
See Package Number DBV (R-PDSO-G6)
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TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response
ICC = 9mA
Frequency Response
ICC = 3.4mA
Frequency Response
ICC = 1mA
150
100
50
1
0
1
0
150
100
50
1
150
100
50
A
= +2, R = 700W
A
= +2, R = 1kW
V
F
A
V
= +2
V
F
GAIN
GAIN
GAIN
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
PHASE
PHASE
0
0
0
A
V
= +6
PHASE
-50
A
= +6, R = 500W
F
-50
-50
V
A
= +6, R = 500W
V
F
A
= +21
V
-100
-150
-200
-250
-100
-150
-200
-250
-100
-150
-200
-250
A
= +21, R = 1kW
A
V
= +21, R = 1kW
V
F
F
I
= 1mA
CC
-5
-6
I
= 9mA
= 2V
I
= 3.4mA
= 2V
CC
CC
V
= 2V
= 500W
= 1kW
OUT
PP
V
OUT
V
OUT
PP
PP
R
R
L
F
R
L
= 100W
R
= 100W
L
-7
100k
1M
10M
100M
1G
100k
100k
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5.
Figure 6.
Figure 7.
Frequency Response
ICC = 9mA
Frequency Response
ICC = 3.4mA
Frequency Response
ICC = 1mA
-30
-30
1
0
1
-30
1
A
= -2, R = 400W
F
A
= -2, R = 450W
V
V
F
GAIN
= -1, R = 500W
GAIN
= -1, R = 750W
A = -1
V
GAIN
-80
-80
0
-80
0
A
V
F
A
V
F
-130
-180
-230
-280
-330
-380
-430
-130
-180
-230
-280
-330
-380
-430
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
-130
-180
-230
-280
-330
-380
-430
-1
-2
-3
-4
-5
-6
-7
A
= -2
V
PHASE
PHASE
PHASE
A
= -6
V
A
A
= -6, R = 200W
F
A
V
= -6, R = 200W
F
V
A
= -20
V
= -20, R = 500W
V
F
A
= -20, R = 500W
V
F
I
= 1mA
= 2V
CC
I
= 9mA
= 2V
I
= 3.4mA
CC
V
R
R
CC
OUT
PP
V
V
= 2V
OUT
PP
= 500W
= 1kW
OUT
PP
L
F
R
L
= 100W
R
= 100W
L
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8.
Figure 9.
Figure 10.
Frequency Response
ICC = 9mA
Frequency Response
ICC = 3.4mA
Frequency Response
ICC = 1mA
150
100
1
1
150
100
50
1
150
100
50
A
= +2, R = 1kW
F
A
V
= +2, R = 700W
A = +2
V
V
GAIN
F
GAIN
GAIN
0
-1
-2
-3
-4
-5
-6
-7
0
-1
-2
-3
-4
-5
-6
-7
0
-1
-2
-3
-4
-5
-6
-7
A
= +6
V
50
PHASE
= +6
PHASE
PHASE
0
0
0
A
V
-50
A
= +6, R = 500W
-50
-50
V
F
A
= +6, R = 500W
V
F
A
= +21
V
-100
-150
-200
-250
-100
-150
-200
-250
-100
-150
-200
-250
A
= +21, R = 1kW
F
A
= +21, R = 1kW
V
V
F
I
= 1mA
CC
I
= 9mA
CC
V
= 4V
= 500W
= 1kW
I
= 3.4mA
= 4V
OUT
PP
CC
V
= 4V
OUT
PP
R
L
F
V
OUT
PP
R
= 100W
L
R
R
= 100W
L
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11.
Figure 12.
Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Frequency Response
ICC = 9mA
Frequency Response
ICC = 3.4mA
Frequency Response
ICC = 1mA
-30
1
1
-30
A
= -2, R = 400W
V
F
A = -1
V
GAIN
0
GAIN
-80
-80
0
A
= -1, R = 500W
F
V
-130
-180
-230
-280
-330
-380
-430
-1
-2
-1
-2
-3
-4
-5
-6
-7
-130
-180
-230
-280
-330
-380
-430
A
V
= -2
PHASE
PHASE
A
V
= -6
-3
-4
A
= -6, R = 200W
F
V
A
= -20
V
A
= -20, R = 500W
V
F
I
= 1mA
= 4V
CC
-5
-6
-7
V
R
R
I
= 9mA
= 4V
OUT
PP
CC
= 500W
= 1kW
V
L
F
OUT
PP
R
L
= 100W
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14.
Figure 15.
Figure 16.
Noise
ICC = 9mA
Noise
ICC = 3.4mA
Noise
ICC = 1mA
100
10
100
100
I
= 3.4mA
CC
I
= 1mA
I
= 9mA
CC
CC
IN-
IN-
IN-
en
10
10
IN+
e
n
1
e
n
IN+
IN+
0.1
1
1
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17.
Figure 18.
Figure 19.
CMRR and PSRR
ICC = 9mA
CMRR and PSRR
ICC = 3.4mA
CMRR and PSRR
ICC = 1mA
70
60
50
70
70
60
50
-PSRR
60
50
-PSRR
-PSRR
+PSRR
CMRR
+PSRR
+PSRR
CMRR
40
30
40
30
40
30
CMRR
20
10
20
10
20
10
I
= 1mA
I
= 9mA
I
= 3.4mA
CC
CC
CC
INPUT REFERRED
100k
INPUT REFERRED
INPUT REFERRED
100k
0
0
0
100k
10M
10M
10M
10k
1M
100M
10k
1M
100M
100 1k
10k
1M
100M
100 1k
100 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20.
Figure 21.
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
2nd Distortion vs. Output Amplitude
ICC = 9mA
2nd Distortion vs. Output Amplitude
ICC = 3.4mA
2nd Distortion vs. Output Amplitude
ICC = 1mA
-20
-30
-40
-10
-10
-20
-30
-40
-50
-60
-70
I
= 9mA
20MHz
CC
50MHz
20MHz
-20
-30
-40
-50
-60
-70
R
R
= 700W
F
50MHz
= 100W
L
V
10MHz
20MHz
A
= +2
-50
-60
-70
50MHz
5MHz
10MHz
5MHz
10MHz
I = 1mA
CC
I
= 3.4mA
CC
-80
R
R
= 1kW
R
R
= 1kW
F
F
5MHz
-80
-80
1MHz
= 500W
= 100W
L
V
L
V
-90
1MHz
-90
-90
1MHz
A
= +2
A
= +2
-100
-100
-100
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
V
(V
)
V
(V )
OUT PP
OUT PP
V
(V )
OUT PP
Figure 23.
Figure 24.
Figure 25.
3rd Distortion vs. Output Amplitude
ICC = 9mA
3rd Distortion vs. Output Amplitude
ICC = 3.4mA
3rd Distortion vs. Output Amplitude
ICC = 1mA
0
-20
-30
-40
-50
-10
-20
-30
-40
-50
-60
-70
50MHz
20MHz
50MHz
20MHz
20MHz
50MHz
-40
5MHz
10MHz
5MHz
-60
-70
-80
10MHz
10MHz
5MHz
-60
I
= 1mA
CC
-80
I
= 9mA
CC
I
= 3.4mA
= 1kW
CC
R
R
= 1kW
F
R
R
A
= 700W
F
L
R
R
A
F
L
-80
= 500W
-100
-120
L
V
= 100W
= 100W
= +2
-90
-90
A
= +2
= +2
1MHz
V
1MHz
1MHz
V
6
-100
-100
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
7
8
V
(V
OUT PP
)
V
(V )
OUT PP
V
(V )
OUT PP
Figure 26.
Figure 27.
Figure 28.
Frequency Response for Various CL
ICC = 9mA
Frequency Response for Various CL
ICC = 3.4mA
Frequency Response for Various CL
ICC = 1mA
I
= 9mA, A = +2, R = 1kW
I = 3.4mA, A = +2, R = 1kW
CC V L
CC
V
L
C
R
= 10pF
L
= 4W
S
C
R
= 100pF,
L
= 27W
S
C
R
= 33pF,
L
= 51W
S
I
= 1mA,
= +2,
CC
C
= 56pF,
L
A
V
R
S
= 36W
R
L
= 1kW
20 MHz/DIV
20 MHz/DIV
5 MHz/DIV
Figure 29.
Figure 30.
Figure 31.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Small Signal Step Response
ICC = 9mA
Small Signal Step Response
ICC = 3.4mA
Small Signal Step Response
ICC = 1mA
1.5
1
1.5
1
1.5
1
A
V
= -1
0.5
0.5
0.5
A
= +2
= -1
A
= -1
A
= +2
= -1
V
V
V
I
= 1mA
CC
R
= 500W
I
= 9mA
L
CC
0
-0.5
-1
0
0
R
= 100W
L
I
= 3.4mA
CC
A
-0.5
V
A
-0.5
V
R
= 100W
L
A
= +2
V
-1
-1
-1.5
0
-1.5
-1.5
5
10
TIME (ns)
15
20
0
10
20
40
50
60
30
0
10
20
30
40
50
TIME (ns)
TIME (ns)
Figure 32.
Figure 33.
Figure 34.
Large Signal Step Response
ICC = 9mA
Large Signal Step Response
ICC = 3.4mA
Large Signal Step Response
ICC = 1mA
3
2
3
2
3
2
A
V
= -1
A
= +2
A
= -1
V
A
V
= -1
V
A
= +2
V
A
= +2
1
1
1
V
0
0
0
I
= 9mA
CC
R
L
= 100W
I
= 3.4mA
I
= 1mA
CC
CC
-1
-1
-1
R
L
= 100W
R
= 500W
A
V
= +2
L
A = -1
V
A
= -1
V
-2
-3
-2
-3
-2
-3
0
10
20
40
50
0
10
20
40
50
30
30
0
20
40
TIME (ns)
80
100
60
TIME (ns)
TIME (ns)
Figure 35.
Figure 36.
Figure 37.
Output Glitch
ICC = 9mA
Output Glitch
ICC = 3.4mA
Output Glitch
ICC = 1mA
I
= 1mA
10
10
10
I
= 9mA
I
= 3.4mA
CC
CC
CC
0.04
0.04
0.04
0.02
0
R
= 100W
L
R
= 100W
R
= 100W
9
8
L
L
OUTPUT
0.02
0
0.02
0
OUTPUT
OUTPUT
7
6
-0.02
-0.02
-0.02
5
5
0
5
0
-0.04
-0.06
4
3
2
1
-0.04
-0.06
-0.04
-0.06
LMH6732 ON
LMH6732 ON
LMH6732 ON
-0.08
-0.1
-0.08
-0.1
-0.08
-0.1
0
0
10 20 30 40 50 60 70 80 90 100
0
20 40 60 80 100 120 140160 180 200
ns
0
50 100 150 200 250 300 350 400 450 500
ns
ns
Figure 38.
Figure 39.
Figure 40.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Turn-On/Off Characteristics
ICC = 9mA
Turn-On/Off Characteristics
ICC = 3.4mA
Turn-On/Off Characteristics
ICC = 1mA
0.6
0.4
0.2
0
0.6
0.4
0.2
0
0.6
0.4
0.2
0
200MHz, 0.8VPP OUTPUT
50MHz, 0.9VPP OUTPUT
9
6
9
6
9
6
OUTPUT
OUTPUT
OUTPUT
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
I
= 9mA
= +2
CC
CONTROL
VOLTAGE
CONTROL
VOLTAGE
CONTROL
VOLTAGE
A
I
= 3.4mA
A = +2
V
I
= 1mA
V
CC
CC
3
0
3
0
3
0
R
R
= 700W
= 100W
A
V
= +2
F
L
LMH6732 ON
R
= 1kW
R
= 1kW
= 100W
LMH6732 ON
F
L
F
LMH6732 ON
1V OUTPUT
PP
500MHz
R
= 100W
-1.2
-1.4
-1.2
-1.4
-1.2
-1.4
R
L
0
10 20 30 40 50 60 70 80 90 100
0
20 40 60 80 100 120 140 160 180 200
0
50 100 150 200 250 300 350 400 450 500
ns
ns
ns
Figure 41.
ICC vs. RP
Figure 42.
IP vs. ICC
Figure 43.
Max Output Current vs. ICC
10
9
140
120
25°C
V
= 0V
OUT
-40°C
8
7
100
80
6
5
4
3
2
1
0
85°C
60
40
20
0
0
2
4
I
6
8
10
10
100
1k
(mA)
CC
R
(kW)
P
Figure 44.
Figure 45.
BW vs. ICC
Figure 46.
BW vs. ICC for Various Temperature
Slew Rate vs. ICC
1000
1000
3000
2500
A
V
= +2
25°C
V
A
= +2
V
-40°C
= 2V
PP
OUT
A
= +2
V
2000
A
V
= +6
85°C
100
100
1500
1000
500
0
V
= 2V
PP
OUT
10
10
0
2
4
I
6
8
10
0
2
4
I
6
8
10
0
2
4
6
8
10
(mA)
CC
(mA)
CC
I
(mA)
CC
Figure 47.
Figure 48.
Figure 49.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
−3dB BW vs. ICC
VOS, IBI & IBN VS. ICC
Output Impedance vs. Frequency
1600
5
4.5
4
0
100
I
BN
R
= 100W
L
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
3.4mA
1400
A
V
= +2
0.25V
PP
R
= 700W
F
1200
1000
10
3.5
3
I
BI
1mA
2.5
2
9mA
800
600
400
1
V
OS
1.5
1
2.0V
PP
0.1
0.5
0
A TYPICAL DEVICE
200
0
0
2
4
I
6
8
10
(mA)
0.01
CC
0
1
2
3
4
5
6
7
8
9
10 11 12
100k
1M
10M
100M
1G
I
(mA)
CC
FREQUENCY (Hz)
Figure 50.
Transimpedance
Figure 51.
Figure 52.
Recommended RS vs. CL
Settling Time
120
110
100
90
220
60
50
40
30
20
1
0.1
GAIN
R
= 100W
L
A
V
= -1
V
200
180
160
140
120
100
80
= 2V
OUT
PP
9mA
1mA
80
3.4mA
1mA
70
I
= 1mA
CC
60
PHASE
3.4mA
50
9mA
3.4mA
1mA
0.01
0.001
40
60
30
40
I
= 9mA
CC
10
0
20
20
9mA
I
= 3.4mA
1k
100k
1M
10M
100M
1G
CC
FREQUENCY (Hz)
0
50 100 150 200 250 300 350
(pF)
1
10
100
ts (ns)
10k
C
L
Figure 53.
Figure 54.
Figure 55.
DG/DP
ICC = 9mA
DG/DP for Various RL
ICC = 9mA
DG/DP for Various RL
ICC = 3.4mA
0.03
0.015
0
0.01
0.005
0
0.1
0.1
0.08
0.06
0.04
0.02
0
4.43MHz
I
= 9mA
CC
4.43MHz
DP
A
= +2
DP
V
0.05
0
DP
R
= 700W
F
DG
-0.05
-0.1
DG
-0.02
-0.04
-0.06
-0.08
-0.1
-0.015
-0.005
I
= 9mA
= 150W
= 700W
CC
R
L
F
I
= 3.4mA
= +2
CC
DG
R
A
-0.15
-0.2
V
-0.03
-0.01
1.5
R = 1kW
F
-1.5
-0.75
0
0.75
4.43MHz
V
(V)
OUT
0
1
2
3
4
5
4
0
2
3
1
NUMBER OF 150W LOADS
NUMBER OF 150W LOADS
Figure 56.
Figure 57.
Figure 58.
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APPLICATION INFORMATION
+5V
6.8µF
PIN NUMBERS SHOWN
FOR SOIC PACKAGE
R
R
F
A
V
= 1 +
0.1µF
8
G
R
P
V
7
-5V
IN
3
2
C
100pF
+
P
LMH6732
V
OUT
6
-
4
R
F
NOTE: C MAY ALSO
P
BE CONNECTED FROM
PIN 8 TO GROUND
0.1µF
6.8µF
R
G
-5V
Figure 59. Recommended Non-Inverting Gain Circuit
+5V
6.8µF
PIN NUMBERS SHOWN
FOR SOIC PACKAGE
R
R
F
A
V
=
0.1µF
8
G
R
P
7
-5V
3
2
C
100pF
+
P
LMH6732
V
OUT
6
-
4
V
R
IN
F
NOTE: C MAY ALSO
P
BE CONNECTED FROM
PIN 8 TO GROUND
R
G
0.1µF
6.8µF
-5V
Figure 60. Recommended Inverting Gain Circuit
DESCRIPTION
The LMH6732 is an adjustable supply current, current-feedback operational amplifier. Supply current and
consequently dynamic performance can be easily adjusted by selecting the value of a single external resistor
(RP).
NOTE
The following discussion uses the SOIC package pin numbers. For the corresponding
SOT-23 package pin numbers, please refer to the Connection Diagrams section.
SELECTING AN OPERATING POINT
The operating point is determined by the supply current which in turn is determined by current (IP) flowing out of
pin 8. As the supply current is increased, the following effects will be observed:
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
Table 1. Device Parameters Related to Supply Current
Specification
Bandwidth
Effect as ICC Increases
Increases
Rise Time
Decreases
Enable/ Disable Speed
Output Drive
Increases
Increases
Input Bias Current
Input Impedance
Increases
Decreases (see Source impedance Discussion)
Both the Electrical Characteristics pages and the TYPICAL PERFORMANCE CHARACTERISTICS section
illustrate these effects to help make the supply current vs. performance trade-off. The supply current is adjustable
over a continuous range of more than 10 to 1 with a single resistor, RP, allowing for easy trade-off between
power consumption and speed. Performance is specified and tested at ICC = 1mA, 3.4mA, and 9mA. (Note:
Some test conditions and especially the load resistances are different for the three supply current settlings.) The
performance plots show typical performance for all three supply currents levels.
When making the supply current vs. performance trade-off, it is first a good idea to see if one of the standard
operating points (ICC = 1mA, 3.4mA, or 9mA) fits the application. If it does, performance ensured on the
specification pages will apply directly to your application. In addition, the value of RP may be obtained directly
from the Electrical Characteristics pages.
BEYOND 1GHz BANDWIDTH
As stated above, the LMH6732 speed can be increased by increasing the supply current. The −3dB Bandwidth
can even reach the unprecedented value of 1.5GHz (AV = +2, VOUT = 0.25VPP). Of course, this comes at the
expense of power consumption (i.e. supply current). The relationship between −3dB BW and supply current is
shown in Figure 48 to Figure 50. The supply current would nominally have to be set to around 10mA to achieve
this speed. The absolute maximum supply current setting for the LMH6732 is 14mA. Beyond this value, the
operation may become unpredictable.
The following discussion will assist in selecting ICC for applications that cannot operate at one of the
specified supply current settlings.
Use the typical performance plots for critical specifications to select the best ICC. For parameters containing
Min/Max ratings in the data sheet tables, interpolate between the values of ICC in the plots & specification tables
to estimate the max/min values in the application.
The simplified schematic for the supply current setting path (IP) is shown below in Figure 61.
+
+
V
5kW
-
V
-
I
P
R
P
Figure 61. Supply Current Control's Simplified Schematic
The terminal marked "RP" is tied to a potential through a resistor RP. The current flowing through RP (IP) sets the
LMH6732's supply current. Throughout the data sheet, the voltages applied to RP and V− are both considered to
be −5V. However, the two potentials do not necessarily have to be the same. This is beneficial in applications
where non-standard supply voltages are used or when there is a need to power down the op amp via digital logic
control.
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The relationship between ICC and IP is given by:
lP = ICC/57 (approximate ratio at ICC = 3.4mA; consult Figure 45 for relationship at any ICC).
Knowing IP leads to a direct calculation of RP.
RP + 5kΩ = [(V+ -1.6)-V−]/ IP
RP+ 5kΩ= =8.4 /IP (for V+ = 5V and V− = −5V).
First, an operating point needs to be determined from the plots & specifications as discussed above. From this, IP
is obtained. Knowing IP and the potential RP is tied to, RP can be calculated.
EXAMPLE
An application requires that VS = ±3V and performance in the 1mA operating point range. The required IP can
therefore be determined as follows:
IP=21μA
RP is connected from pin 8 to V−. Calculate RP under these conditions:
RP+ 5kΩ = [(V+ -1.6)-V−] / IP
RP+ 5kΩ = [(3V-1.6V) - (-3V)] / 21μA
RP = 205kΩ
The LMH6732 will have performance similar to RP = 412kΩ shown on the datasheet, but with 40% less power
dissipation due to the reduced supply voltages. The op amp will also have a more restricted common-mode
range and output swing.
DYNAMIC SHUTDOWN CAPABILITY
The LMH6732 may be powered on and off very quickly by controlling the voltage applied to RP. If RP is
connected between pin 8 and the output of a CMOS gate powered from ±5V supplies, the gate can be used to
turn the amplifier on and off. This is shown in Figure 62 below:
PIN NUMBERS SHOWN
* EXPERIMENTALLY
FOR SOIC PACKAGE
ADJUSTED VALUE
ö 5pF*
R
P
TO PIN 8 OF
LMH6732
CMOS LOGIC GATE
(WITH ±5V OUTPUT SWING)
Figure 62. Dynamic Control of Power Consumption Using CMOS Logic
When the gate output is switched from high to low, the LMH6732 will turn on. In the off state, the supply current
typically reduces to 1μA or less. The LMH6732's "off state" supply current is reduced significantly compared to
the CLC505. This extremely low supply current in the "off state" is quite advantageous since it allows for
significant power saving and minimizes feed-through. To improve switching time, a speed up capacitor from the
gate output to pin 8 is recommended. The value of this capacitor will depend on the RP value used and is best
established experimentally. Turn-on and turn-off times of <20ns (ICC = 9mA) are achievable with ordinary CMOS
gates.
EXAMPLE
An open collector logic device is used to dynamically control the power dissipation of the circuit. Here, the
desired connection for RP is from pin 8 to the open collector logic device.
18
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
PIN NUMBERS SHOWN
FOR SOIC PACKAGE
R
P
TO PIN 8 OF
LMH6732
OPEN COLLECTOR
TTL GATE
Figure 63. Controlling Power On State with TTL Logic (Open Collector Output)
When the logic gate goes low, the LMH6732 is turned on. The LMH6732 V+ connection would be to +5V supply.
Performance desired is that given for ICC = 3.4mA under standard conditions. From the ICC vs. IP plot, IP = 61μA.
Then calculating RP:
RP + 5kΩ = [(5V-1.6V)- 0] / 61μA
RP = 51kΩ
"POPLESS OUTPUT" & OFF CONDITION OUTPUT STATE
The LMH6732 has been especially designed to have minimum glitches during turn-on and turn-off. This is
advantageous in situations where the LMH6732 output is fed to another stage which could experience false auto-
ranging, or even worse reset operation, due to these transient glitches. Example of this application would be an
AGC circuit or an ADC with multiple ranges set to accommodate the largest input amplitude. For the LMH6732,
these sorts of transients are typically less than 50mV in amplitude (see Electrical Characteristics Tables for
Typical values). Applications designed to utilize the CLC505's low output glitch would benefit from using the
LMH6732 instead since the LMH6732's output glitch is improved to be even lower than the CLC505's. In the "Off
State", the output stage is turned off and is in effect put into a high-Z state. In this sate, output can be forced by
other active devices. No significant current will flow through the device output pin in this mode of operation.
MUX APPLICATION
Since The LMH6732's output is essentially open in the “off” state, it is a good candidate for a fast 2:1 MUX.
Figure 64 shows one such application along with the output waveform in Figure 65 displaying the switching
between a continuous triangle wave and a single cycle sine wave (signals trigger locked to each other for stable
scope photo). Switching speed of the MUX will be less than 50 ns and is governed by the “Ton" and “Toff” times
for U1 and U2 at the supply current set by RP1 and RP2. Note that the “Control” input is a 5V CMOS logic level.
1.3 kW
1.3 kW
R
R
F1
G1
2
3
-
LMH6732
U1
6
V
IN1
CONTROL
3
+
8
50W
+5V
R
P1
1
V
OUT
2
47 kW
IN2
8
3
2
V
= ±5V
S
-
LMH6732
V
FOR LMH6732
1/4 CD4049
1/4 CD4049
U2
6
5
50W
+
8
4
R
R
F2
G2
1.3 kW
1.3 kW
R
P2
47 kW
Figure 64. 50 ns 2:1 MUX Schematic
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OUTPUT
R
F
= R = 1.3 kW
G
V
S
= ±5V
0V
CONTROL
2 µs/DIV
Figure 65. MUX “VOUT” and “Control” Waveform
DIFFERENTIAL GAIN AND PHASE
Differential gain and phase are measurements useful primarily in composite video channels. They are measured
by monitoring the gain and phase changes of a high frequency carrier (3.58MHz for NTSC and 4.43MHz for PAL
systems) as the output of the amplifier is swept over a range of DC voltages. Specifications for the LMH6732
include differential gain and phase. Test signals used are based on a 1VPP video level. Test conditions used are
the following:
DC sweep range: 0 to 100 IRE units (black to white)
Carrier: 4.43MHz at 40 IRE units peak to peak
AV = +2, RL = 75Ω + 75Ω
SOURCE IMPEDANCE
For best results, source impedance in the non-inverting circuit configuration (see Figure 59) should be kept below
5kΩ.
Above 5kΩ it is possible for oscillation to occur, depending on other circuit board parasitics. For high signal
source impedances, a resistor with a value of less than 5kΩ may be used to terminate the non-inverting input to
ground.
FEEDBACK RESISTOR
In current-feedback op amps, the value of the feedback resistor plays a major role in determining amplifier
dynamics. It is important to select the correct value. The LMH6732 provides optimum performance with feedback
resistors as shown in Table 2 below. Selection of an incorrect value can lead to severe roll-off in frequency
response, (if the resistor value is too large) or , peaking or oscillation (if the value is too low).
Table 2. Feedback Resistor Selection for Various Gain Settings and ICC’s
Gain (V/V)
ICC (mA)
3.4
Unit
9
1
AV = +1
700
700
500
400
500
200
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
AV = +2
AV = −1
AV = −2
AV = +6
AV = −6
AV = +21
AV = −20
1k
750
450
500
200
1k
500
500
20
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LMH6732
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SNOSA47B –FEBRUARY 2003–REVISED MARCH 2013
For ICC > 9mA at any closed loop gain setting, a good starting point for RF would be the 9mA value stated in
Table 2 above. This value could then be readjusted, if necessary, to achieve the desired response.
PRINTED CIRCUIT LAYOUT & EVALUATION BOARDS
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information).
Use the following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Evaluation Board
Device
Package
Part Number
LMH730216
LMH730227
LMH6732MF
LMH6732MA
SOT-23
SOIC
The supply current adjustment resistor, RP, in both evaluation boards should be tied to the appropriate potential
to get the desired supply current. To do so, leave R2 (LMH730216) [ R5 (LMH730227) ] uninstalled. Jumper
"Dis" connector to V−. Install R1 (LMH730216) [ R4 (LMH730227) ] to set the supply current.
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6732MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH67
32MA
LMH6732MF/NOPB
LMH6732MFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
1000 RoHS & Green
3000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A97A
A97A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6732MF/NOPB
LMH6732MFX/NOPB
SOT-23
SOT-23
DBV
DBV
6
6
1000
3000
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6732MF/NOPB
LMH6732MFX/NOPB
SOT-23
SOT-23
DBV
DBV
6
6
1000
3000
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6732MA/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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