LMH6553MRX/NOPB [TI]
具有输出限制钳位的 900MHz 全差动放大器 | DDA | 8 | -40 to 125;
| 型号： | LMH6553MRX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输出限制钳位的 900MHz 全差动放大器 | DDA | 8 | -40 to 125 放大器 光电二极管 |
| 文件： | 总45页 (文件大小：1936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
LMH6553 900 MHz Fully Differential Amplifier With Output Limiting Clamp
Check for Samples: LMH6553
1
FEATURES
DESCRIPTION
The LMH6553 is a 900 MHz differential amplifier with
an integrated adjustable output limiting clamp. The
clamp increases system performance and provides
transient over-voltage protection to following stages.
The internal clamp feature of the LMH6553 reduces
or eliminates the need for external discrete overload
protection networks. When used to drive ADCs, the
amplifier's output clamp allows low voltage ADC
inputs to be protected from being overdriven and
damaged by large input signals appearing at the
system input. Fast overdrive recovery of 600 ps
ensures the amplifier output rapidly recovers from a
clamping event and quickly resumes to follow the
input signal. The LMH6553 delivers exceptional
bandwidth, distortion, and noise performance ideal for
driving ADCs up to 14-bits. The LMH6553 could also
be used for automotive, communication, medical, test
and measurement, video, and LIDAR applications.
23
•
900 MHz −3 dB Small Signal
Bandwidth @ AV = 1
•
670 MHz −3 dB Large Signal
Bandwidth @ AV = 1
•
•
•
•
•
•
•
−79 dB THD @ 20 MHz
−92 dB IMD3 @ fc = 20 MHz
10 ns Settling Time to 0.1%
600 ps Clamp Overdrive Recovery Time
40 mV Clamp Accuracy with 100% Overdrive
−0.1 mV/°C Clamp Temperature Drift
4.5 to 12 Supply Voltage Operation
APPLICATIONS
•
•
•
•
•
•
•
•
•
Differential ADC Driver
Video Over Twisted Pair
With external gain set resistors and integrated
common mode feedback, the LMH6553 can be
configured as either a differential input to differential
output or single ended input to differential output gain
block. The LMH6553 can be AC or DC coupled at the
input which makes it suitable for a wide range of
applications including communication systems and
high speed oscilloscope front ends. The LMH6553 is
available in 8-pin SO PowerPAD and 8-pin WSON
packages, and is part of our LMH™ high speed
amplifier family.
Differential Line Driver
Single End to Differential Converter
High Speed Differential Signaling
IF/RF Amplifier
SAW Filter Buffer/Driver
CCD Output Limiting Amplifier
Automotive Safety Applications
Typical Application
275W
ADC
+
50W
V
R
R
O
255W
Single-Ended
AC-Coupled
Source
-
V
IN+
+
V
CM
59W
255W
LMH6553
8 to14 Bit
-
V
IN-
+
V
CM
O
V
-
49.9W
0.1mF
V
59W
+
CLAMP
C
-
275W
Figure 1. Single-Ended Input Differential Output ADC Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
4000V
350V
13.2V
±VS
Machine Model
Supply Voltage
Common Mode Input Voltage
Maximum Input Current (pins 1, 2, 7, 8)
Maximum Output Current (pins 4, 5)
Maximum Junction Temperature
30 mA
(4)
150°C
For soldering specifications
see product folder at http://www.ti.com and
http://www.ti.com/lit/SNOA549
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum output current (IOUT) is determined by device power dissipation limitations. See POWER DISSIPATION of Application
Information for more details.
(1)
Operating Ratings
(2)
Operating Temperature Range
Storage Temperature Range
Total Supply Voltage
−40°C to +125°C
−65°C to +150°C
4.5V to 12V
Package Thermal Resistance (θJA
)
8-Pin SO PowerPAD
59°C/W
58°C/W
8-Pin WSON
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)– TA) / θJA. All numbers apply for packages soldered directly onto a PC Board.
2
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
(1)
VS = ±5V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±5V, AV = 1, VCM = 0V, VCLAMP = 3V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC Performance (Differential)
(2)
SSBW
LSBW
Small Signal −3 dB Bandwidth
VOUT = 0.2 VPP, AV = 1, RL = 1 kΩ
VOUT = 0.2 VPP, AV = 1
900
720
680
630
350
VOUT = 0.2 VPP, AV = 2
MHz
VOUT = 0.2 VPP, AV = 4
VOUT = 0.2 VPP, AV = 8, (RF = 400Ω, RG
50Ω)
=
Large Signal −3 dB Bandwidth
VOUT = 2 VPP, AV = 1, RL = 1 kΩ
VOUT = 2 VPP, AV = 1
670
540
530
490
350
50
VOUT = 2 VPP, AV = 2
MHz
VOUT = 2 VPP, AV = 4
VOUT = 2 VPP, AV = 8, (RF = 400Ω, RG = 50Ω)
0.1 dB Bandwidth
0.5 dB Bandwidth
Slew Rate
VOUT = 0.2 VPP, AV = 1
VOUT = 0.2 VPP, AV = 1
4V Step, AV = 1
2V Step
MHz
MHz
V/μs
ps
525
2300
690
10
Rise/Fall Time, 10%-90%
0.1% Settling Time
1.0% Settling Time
2V Step
ns
2V Step
6
ns
Distortion and Noise Response
HD2
HD3
IMD3
2nd Harmonic Distortion
VOUT = 2 VPP, f = 20 MHz, RL = 800Ω
VOUT = 2 VPP, f = 70 MHz, RL = 800Ω
VOUT = 2 VPP, f = 20 MHz, RL = 800Ω
VOUT = 2 VPP, f = 70 MHz, RL = 800Ω
−79
−78
−90
−71
−92
dBc
dBc
3rd Harmonic Distortion
3rd-Order Two-Tone
Intermodulation
fc = 20 MHz, , VOUT = 2 VPP Composite,
RL = 200Ω
dBc
fc = 150 MHz, , VOUT = 2 VPP Composite,
−76
RL = 200Ω
Input Noise Voltage
f = 100 kHz
1.2
nV/√Hz
pA/√Hz
dB
Input Noise Current
f = 100 kHz
13.6
10.3
Noise Figure (See Figure 58)
50Ω System, AV = 9, 10 MHz
Input Characteristics
(4)
IBI
Input Bias Current
−95
50
2.5
82
95
18
µA
µA
dBc
Ω
(3)
−
+
IBoffset
CMRR
RIN
Input Bias Current Differential
VCM = 0V, VID = 0V, IBoffset = (IB - IB )/2
DC, VCM = 0V, VID = 0V
Differential
−18
(3)
Common Mode Rejection Ratio
Input Resistance
15
CIN
Input Capacitance
Differential
0.5
±3.6
pF
V
CMVR
Input Common Mode Voltage
Range
CMRR > 38 dB
±3.3
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. See Application Information for information on temperature de-rating of this device."
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Exceeding limits could result in excessive device current.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
VS = ±5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±5V, AV = 1, VCM = 0V, VCLAMP = 3V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Output Performance
(5)
Output Voltage Level
Linear Output Current
Short Circuit Current
Single-Ended Output
−3.7
±3.78
±120
±150
+3.7
V
(5)
IOUT
ISC
VOUT = 0V
±100
mA
mA
One Output Shorted to Ground VIN = 2V
(6)
Single-Ended
Clamp Performance
VCLAMP VCLAMP Voltage Range
(7)
Continuous Operation
VCM
VCM
2.0
+
+
V
(8)
VCLAMP Peak Voltage
VCM
3.0
Default VCLAMP Voltage
VCLAMP Floating
0.92
1.0
1.08
+53
V
Upper Clamp Level Accuracy
VCLAMP = 2V, VCM = 1.5V, VO = 2V, 100%
Overdrive
−53
−40
mV
Lower Clamp Level Accuracy
VCLAMP = 2V, VCM = 1.5V, VO = 1V, 100%
Overdrive
−30
−8
+30
175
Clamp Accuracy Temperature Drift
Clamp Pin Bias Current
−0.1
−175
150
0.3
mV/°C
µA
VIN = 0V, VCLAMP(MIN) = −3.1 V
−200
VIN = 0V, VCLAMP(MAX) = +4.5V
Clamp Pin Bias Drift
µA/°C
µA
Diff Amp Input Bias Shift
Clamp Pin Input Impedance
Linear to Clamped Operation
60
30
1
KΩ/pF
Clamp Pin Feedthrough
Clamp Bandwidth
Clamp Slew Rate
Clamp Overshoot
f = 10 MHz
−60
140
64
dB
0.5VDC + 40 mVPP, SE VIN = 2V
100% Overdrive
MHz
V/µs
mV
VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V,
VCM = 0V, 100% Overdrive
125
Clamp Overshoot
VIN = 2V Step, AV = 2 V/V, VCLAMP = 2V,
250
mV
VCM = 1.5V, 100% Overdrive
(9)
Clamp Overshoot Width
650
600
ps
ps
Clamp Overdrive Recovery Time
VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V,
VCM = 0V, 50% Output Crossing
(10)
Linearity Guardband
f = 75 MHz, VOD = 2 VPP, RL = 800, SFDR
Down 3 dB
22
mV
Output Common Mode Control Circuit
+
−
Common Mode Small Signal
Bandwidth
VIN = VIN = 0
220
MHz
+
−
Slew Rate
VIN = VIN = 0
340
1
V/μs
VOSCM
Output Common Mode Error
Common Mode, VIN = Float, VCM = 0
−25
25
mV
(5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(6) Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION in Application Information for
more details.
(7) Exceeding limits could result in excessive device current.
(8) This parameter is ensured by design and/or characterization and is not tested in production. The condition of VCLAMP = 3V is not
intended for continuous operation; continuous operation with VCLAMP = 3V may incur permanent damage to the device.
(9) Clamp Overshoot Width is the duration of overshoot in a 100% overdrive condition.
(10) Linearity Guardband is defined for an output sinusoid (f = 75 MHz, VOD = 2 VPP). It is the difference between the VCLAMP level and the
peak output voltage where the SFDR is decreased by 3 dB.
4
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
VS = ±5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±5V, AV = 1, VCM = 0V, VCLAMP = 3V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Input Bias Current
Conditions
(11)
Min
−8
−9
Typ
−3.5
Max
Units
VCM(TYPICAL) = 0,
1
(11)
VCM(MIN) = −3.2 V,
−4.5
−2.5
±3.18
80
µA
(11)
VCM(MAX) = +3.2V,
2
Voltage Range
CMRR
±3.14
0.995
V
Measure VOD, VID = 0V
dB
kΩ
V/V
Input Resistance
Gain
200
ΔVO,CM/ΔVCM
1.00
1.008
Miscellaneous Performance
ZT
Open Loop Transimpedance
Differential
DC, ΔVS = ±1V
RL = ∞
112
87
dBΩ
PSRR
IS
Power Supply Rejection Ratio
Supply Current
dB
25
29.1
33
37
mA
(11) Negative current implies current flowing out of the device.
(1)
VS = ±2.5V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±2.5V, AV = 1, VCM = 0V, VCLAMP = 2V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC Performance (Differential)
(2)
SSBW
LSBW
Small Signal −3 dB Bandwidth
VOUT = 0.2 VPP, AV = 1, RL = 1 kΩ
VOUT = 0.2 VPP, AV = 1
875
630
580
540
315
VOUT = 0.2 VPP, AV = 2
MHz
VOUT = 0.2 VPP, AV = 4
VOUT = 0.2 VPP, AV = 8 , (RF = 400Ω, RG
50Ω)
=
Large Signal −3 dB Bandwidth
VOUT = 2 VPP, AV = 1, RL = 1 kΩ
VOUT = 2 VPP, AV = 1
640
485
435
420
405
60
VOUT = 2 VPP, AV = 2
MHz
VOUT = 2 VPP, AV = 4
VOUT = 2 VPP, AV = 8, (RF = 400Ω, RG = 50Ω)
0.1 dB Bandwidth
0.5 dB Bandwidth
Slew Rate
VOUT = 0.2 VPP, AV = 1
VOUT = 0.2 VPP, AV = 1
2V Step, AV = 1
2V Step
MHz
MHz
V/μs
ps
236
1350
860
10
Rise/Fall Time, 10%-90%
0.1% Settling Time
1.0% Settling Time
2V Step
ns
2V Step
6
ns
Distortion and Noise Response
HD2
2nd Harmonic Distortion
VOUT = 2 VPP, f = 20 MHz, RL = 800Ω
VOUT = 2 VPP, f = 70 MHz, RL = 800Ω
−80
−72
dBc
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. See Application Information for information on temperature de-rating of this device."
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
VS = ±2.5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±2.5V, AV = 1, VCM = 0V, VCLAMP = 2V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
3rd Harmonic Distortion
Conditions
Min
Typ
−78
Max
Units
HD3
VOUT = 2 VPP, f = 20 MHz, RL = 800Ω
VOUT = 2 VPP, f = 70 MHz, RL = 800Ω
dBc
−66
−87
IMD3
3rd-Order Two-Tone
Intermodulation
fc = 20 MHz, VOUT = 2 VPP Composite,
RL = 200Ω
dBc
fc = 150 MHz, VOUT = 2 VPP Composite,
−68
RL = 200Ω
Input Noise Voltage
f = 100 kHz
1.1
nV/√Hz
pA/√Hz
dB
Input Noise Current
f = 100 kHz
13.6
10.3
Noise Figure (See Figure 58)
50Ω System, AV = 9, 10 MHz
Input Characteristics
(4)(5)
(5)
IBI
Input Bias Current
−90
45
2
90
24
µA
µA
dBc
Ω
(3)
−
+
IBoffset
CMRR
RIN
Input Bias Current Differential
VCM = 0V, VID = 0V, IBoffset = (IB - IB )/2
DC, VCM = 0V, VID = 0V
Differential
−24
(3)
Common Mode Rejection Ratio
Input Resistance
80
15
CIN
Input Capacitance
Differential
0.5
±1.2
pF
V
CMVR
Input Common Mode Voltage
Range
CMRR > 38 dB
±1.0
Output Performance
Output Voltage Swing
(3)
(3)
Differential Output
5.32
±75
5.47
±95
VPP
mA
mA
IOUT
ISC
Linear Output Current
Short Circuit Current
VOUT = 0V
One Output Shorted to Ground VIN = 2V
±140
(6)
Single-Ended
Clamp Performance
VCLAMP VCLAMP Voltage Range
(7)
Continuous Operation
VCM
VCM
2.0
+
+
V
(8)
VCLAMP Peak Voltage
VCM
3.0
Default VCLAMP Voltage
VCLAMP Floating
0.42
0.48
0.54
+39
V
Upper Clamp Level Accuracy
VIN = 0V, VCLAMP = +0.5V, VCM = 0, VO
=
−39
−30
+0.5V,
100% Overdrive
mV
Lower Clamp Level Accuracy
VIN = 0V, VCLAMP = +0.5V, VCM = 0, VO
=
−18
6
+18
−0.5V,
100% Overdrive
Clamp Accuracy Temperature Drift
Clamp Pin Bias Current
−0.1
23.5
0.3
mV/°C
µA
VIN = 0V, VCLAMP = 1V, VCM = 0
Linear to Clamped Operation
Clamp Pin Bias Drift
µA/°C
µA
Diff Amp Input Bias Shift
Clamp Pin Input Impedance
50
30
1
kΩ/pF
Clamp Pin Feedthrough
Clamp Bandwidth
f = 10 MHz
−60
125
52
dB
0.5VDC + 40 mVPP, SE VIN = 2V
100% Overdrive
MHz
V/µs
Clamp Slew Rate
(4) Exceeding limits could result in excessive device current.
(5) IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF
(6) Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION in Application Information for
more details.
(7) Exceeding limits could result in excessive device current.
(8) This parameter is ensured by design and/or characterization and is not tested in production. The condition of VCLAMP = 3V is not
intended for continuous operation; continuous operation with VCLAMP = 3V may incur permanent damage to the device.
6
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
VS = ±2.5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, VS = ±2.5V, AV = 1, VCM = 0V, VCLAMP = 2V, RF = RG = 275Ω,
RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Clamp Overshoot
Conditions
Min
Typ
105
Max
Units
VIN = 1V Step, AV = 2 V/V, VCLAMP = 0.5V,
VCM= 0V, 100% Overdrive
mV
Clamp Overshoot
VIN = 1V Step, AV= 2 V/V, VCLAMP = 1V,
105
mV
VCM = 0.5V, 100% Overdrive
(9)
Clamp Overshoot Width
650
600
ps
ps
Clamp Overdrive Recovery Time
VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V,
VCM = 0V, 50% Output Crossing
(10)
Linearity Guardband
f = 75 MHz, VOD = 2 VPP, RL = 800, SFDR
Down 3 dB
40
mV
Output Common Mode Control Circuit
+
−
Common Mode Small Signal
Bandwidth
VIN = VIN = 0
130
MHz
+
−
Slew Rate
VIN = VIN = 0
186
2
V/μs
mV
µA
V
VOSCM
Output Common Mode Error
Input Bias Current
Voltage Range
CMRR
Common Mode, VIN = float, VCM = 0
−20
20
(11)
VCM = 0,
−3.5
±0.81
84
±0.75
0.995
Measure VOD, VID = 0V
dB
Input Resistance
Gain
200
1.00
kΩ
V/V
ΔVO,CM/ΔVCM
1.008
Miscellaneous Performance
ZT
Open Loop Transimpedance
Differential
DC, ΔVS = ±1V
RL = ∞
105
85
dBΩ
PSRR
IS
Power Supply Rejection Ratio
Supply Current
dB
23
26.5
30
34
mA
(9) Clamp Overshoot Width is the duration of overshoot in a 100% overdrive condition.
(10) Linearity Guardband is defined for an output sinusoid (f = 75 MHz, VOD = 2 VPP). It is the difference between the VCLAMP level and the
peak output voltage where the SFDR is decreased by 3 dB.
(11) Negative current implies current flowing out of the device.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
CONNECTION DIAGRAM
1
2
3
4
8
-IN
+IN
7
6
-
+
V
CM
V+
V
CLAMP
V-
5
+OUT
-OUT
DAP
Figure 2. 8-Pin SO PowerPAD
Top View
1
2
3
4
8
7
6
5
+IN
V
-IN
V
CM
V+
CLAMP
V-
-OUT
+OUT
DAP
Figure 3. 8-Pin WSON
Top View
8
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin No.
Pin Name
Description
1
2
-IN
Negative Input
VCM
V+
Output Common Mode Control
Positive Supply
3
4
+OUT
-OUT
V-
Positive Output
5
Negative Output
6
Negative Supply
7
VCLAMP
+IN
Output Voltage Clamp Control
Positive Input
8
DAP
DAP
Die Attach Pad (See THERMAL
PERFORMANCE for more information)
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics VS = ±5V
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Frequency Response vs. Gain
Frequency Response vs. Gain
= 1
1
0
1
0
A
V
A
V
= 1
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= 0.2 V
PP
V
= 0.2 V
PP
SINGLE-ENDED INPUT
OUT
OUT
DIFFERENTIAL INPUT
1
10 100
1000
10000
1
10 100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4.
Figure 5.
Frequency Response vs. VOUT
Frequency Response vs. VOUT
1
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
A
= +5V
V
A
= +5V
S
V
S
V
= 2V/V
DIFFERENTIAL INPUT
= 2V/V
SINGLE-ENDED INPUT
1
1
10 100
1000
10000
1
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6.
Figure 7.
Frequency Response vs. Supply Voltage (RL = 200Ω)
Frequency Response vs. Supply Voltage (RL = 1 kΩ)
3
2
V
S
= +5V
2
1
1
0
R
R
= 200Ö
= 275Ö
L
F
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
V
= +2.5V
= 1 kÖ
S
-2
-3
-4
-5
-6
-7
-8
-9
R
L
F
R
= 225Ö
V
= +5V
S
R
= 1 kÖ
= 225Ö
L
F
R
V
A
= 0.2 V
PP
V
A
= 0.2 V
PP
OD
OD
= 1 V/V
= 1 V/V
DIFFERENTIAL INPUT
V
V
DIFFERENTIAL INPUT
1
10 100
1000
10000
1
10 100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8.
Figure 9.
10
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Frequency Response vs. Capacitive Load
Suggested RO vs. Capacitive Load
-9
60
50
40
30
20
10
0
-8
-7
-6
-5
-4
-3
-2
-1
0
V
A
= 200 mV
PP
OD
= 1 V/V
V
V
= +5V
S
LOAD = (C || 1 kÖ) IN
L
LOAD = 1 kÖ || CAP LOAD
SERIES WITH 2 R
OUTS
1
1
10
100
1
10
100
1000
CAPACITIVE LOAD (pF)
Figure 11.
FREQUENCY (MHz)
Figure 10.
Frequency Response vs. Resistive Load
3
Frequency Response vs. Resistive Load
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
-9
R
L
= 200Ö
V
A
= +5V
= 1V/V
= 275Ö
= 2 V
V
A
= +5V
S
V
S
V
= 1V/V
= 275Ö
R
R
F
F
V
V
= 0.2 V
PP
OUT
PP
OUT
SINGLE-ENDED INPUT
SINGLE-ENDED INPUT
1
10 100
1000
10000
1
10 100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12.
Figure 13.
Frequency Response vs. RF
1 VPP Pulse Response Single-Ended Input
-0.8
3
2
1
-0.6
-0.4
-0.2
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= +2.5V
= 200Ö
= 275Ö
S
0.2
0.4
0.6
0.8
R
R
V
L
F
A
= 1 V/V
= 2 V
V
V
OUT
PP
= 3V
CLAMP
= 0V
R
L
= 1 kÖ
V
CM
DIFFERENTIAL INPUT
0
5
10 15 20 25 30 35 40
TIME (ns)
1
10 100
1000
10000
FREQUENCY (MHz)
Figure 14.
Figure 15.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
2 VPP Pulse Response Single-Ended Input
4 VPP Pulse Response Single-Ended Input
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
1.5
1.0
0.5
0.0
V
= +5V
S
0.5
V
= +5V
S
-0.5
-1.0
-1.5
R
R
= 200Ö
= 275Ö
L
F
R
= 200Ö
= 275Ö
L
F
1.0
R
1.5
V
V
= 3V
CLAMP
= 0V
V
V
= 3V
CLAMP
= 0V
2.0
CM
CM
2.5
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
TIME (ns)
TIME (ns)
Figure 16.
Figure 17.
Pulse Response with 0% and 100% Overdrive
Pulse Response with 0% and 100% Overdrive
3.0
1.5
100% Overdrive
0% Overdrive
0% Overdrive
= 1V
100% Overdrive
= 0.5V
V
= 2V
V
V
V
= 2.5V
CLAMP
CLAMP
CLAMP
CLAMP
2.5
2.0
1.5
1.0
0.5
0
1.0
0.5
0
V
S
= +5V
-0.5
-1.0
-1.5
V
= +5V
S
V
A
= 2V/V
= 200Ö
V
A
= 2V/V
= 200Ö
R
L
R
L
V
= 1.5V
CM
V
= 0V
CM
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
TIME (ns)
Figure 18.
Figure 19.
Overdrive Recovery with VS = ±5V
2.4
Overdrive Recovery with VS = ±2.5V
1.2
12
10
8
6.0
4.8
3.6
2.4
1.2
0
2.0
1.6
1.2
0.8
0.4
0
0.8
0.4
0
6
VCLAMP = 0.5V
VCLAMP = 0.5V
4
2
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-2
-4
-6
-8
-10
-12
-1.2
-2.4
-3.6
-4.8
-6.0
-0.4
-0.8
-1.2
VS = +5V
VS = +2.5V
AV = 5 V/V
RF = 275Ö
RL = 200Ö
AV = 5 V/V
RF = 275Ö
RL = 200Ö
VCLAMP = 3V
VCLAMP = 3V
0
200
400
600
800
1000
0
200
400
600
800
1000
TIME (ns)
TIME (ns)
Figure 20.
Figure 21.
12
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Output Common Mode Pulse Response
Distortion vs. Frequency Single-Ended Input (RL=800Ω)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-60
-50
-40
-30
-20
-10
0
V
= +5V
= 800Ö
= 2V
S
10
20
30
40
50
60
R
V
L
V
= +5V
= 200Ö
= 275Ö
= 2V
OD
PP
S
R
= 275Ö
R
R
V
F
L
F
V
V
= 3V
CLAMP
= 0V
CM
OD
PP
10 30 50 70 90 110 130 150 170 190
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (MHz)
TIME (ns)
Figure 22.
Figure 23.
Distortion vs. Supply Voltage (fc=20Mhz, RL=800Ω)
Distortion vs. Supply Voltage (fc=75Mhz, RL=800Ω)
-50
-40
RL = 800Ö
VOD = 2 VPP
RL = 800Ö
VOD = 2 VPP
-45
-55
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
VCLAMP = 3V
VCM = 0
fc = 75 MHz
VCLAMP = 3V
VCM = 0
fc = 20 MHz
-60
-65
-70
-75
-80
-85
-90
-95
4
5
6
7
8
9
10 11 12
4
5
6
7
8
9
10 11 12
TOTAL SUPPLY VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
Figure 24.
Figure 25.
Distortion vs.
VCM (fc=20Mhz, RL=800Ω)
Distortion vs.
VCM (fc=75Mhz, RL=800Ω)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
V
= +5V
S
V
= +5V
= 800Ö
= 2V
S
-20
-30
-40
-50
-60
-70
-80
-90
R
= 800Ö
L
R
L
V
V
= 2V
PP
OD
V
OD
PP
= 3V
CLAMP
V
= 3V
CLAMP
f
= 75 MHz
c
f
c
= 20 MHz
2.5
0
0.5
1
1.5
CM
2
2.5
3
0
0.5
1
1.5
(V)
2
3
V
V
(V)
CM
Figure 26.
Figure 27.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Distortion vs.
Frequency Single-Ended Input (RL=200Ω)
Distortion vs.
Supply Voltage (fc=20Mhz, RL=200Ω)
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
RL = 200Ö
VOD = 2VPP
VCLAMP = 3V
VCM = 0V
fc = 20 MHz
VS = ±5V
RL = 200Ö
VOD = 2VPP
RF = 275Ö
VCLAMP = 3V
VCM = 0V
10 30 50 70 90 110 130 150 170 190 200
4
5
6
7
8
9
10 11 12
FREQUENCY (MHz)
TOTAL SUPPLY VOLTAGE (V)
Figure 28.
Figure 29.
Distortion vs.
Supply Voltage (fc=75Mhz, RL=200Ω)
Distortion vs.
VCM (fc=20Mhz, RL=200Ω)
-40
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VS = ±5V
RL = 200Ö
VOD = 2VPP
VCLAMP = 3V
VCM = 0V
RL = 200Ö
VOD = 2 VPP
VCLAMP = 3V
fc = 20MHz
-45
-50
-55
-60
-65
-70
-75
-80
-85
HD3
fc = 75 MHz
1.5
4
5
6
7
8
9
10 11 12
0
0.5
1
2
2.5
3
TOTAL SUPPLY VOLTAGE (V)
VCM (V)
Figure 31.
Figure 30.
14
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Distortion vs.
VCM (fc=75Mhz, RL=200Ω)
Maximum VOUT vs.
IOUT
4.5
4
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
VS = ±5V
RL = 200Ö
VOD = 2 VPP
VCLAMP = 3V
fc = 75MHz
HD2
3.5
3
V
= +5V
S
R
V
= 275Ö
F
= 3V
CM
2.5
2
V
= 5V
CLAMP
V
IN
= 3.5V SINGLE-ENDED INPUT
0
20
40
60
80
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (mA)
VCM (V)
Figure 32.
Figure 33.
Minimum VOUT vs.
IOUT
Closed Loop Output Impedance
-2
1000
100
10
VS = +5V
VIN = 0V
AV = 1 V/V
V
= +5V
S
R
= 275Ö
F
V
V
= -3V
CM
-2.5
-3
= -1V
CLAMP
V
= -3.5V SINGLE-ENDED INPUT
IN
1
0.1
0.01
-3.5
-4
0.001
0.0001
10
0.01
1
100
1000
0.1
0
20
40
60
80
OUTPUT CURRENT (mA)
FREQUENCY (MHz)
Figure 34.
Figure 35.
Closed Loop Output Impedance
Open Loop Transimpedance
1000
100
10
120
110
100
90
VS = +2.5V
VIN = 0V
AV = 1 V/V
MAGNITUDE
1
0
80
0.1
PHASE
-45
-90
-135
-180
70
0.01
60
0.001
50
VS = +5V
0.0001
40
0.01
10
0.01
1
100
1000
0.1
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36.
Figure 37.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Open Loop Transimpedance
PSRR
120
110
100
90
100
90
80
70
60
50
40
30
20
10
0
MAGNITUDE
0
80
PHASE
-45
-90
-135
-180
70
AV = 2 V/V
RL = 200Ö
VIN = 0V
60
50
VCM = 0V
VS = +2.5V
VCLAMP = 3V
40
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 38.
Figure 39.
PSRR
CMRR
80
70
60
50
40
30
20
10
0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
AV = 2 V/V
RL = 200Ö
VOUT = 1.0 VPP
VCM = 0V
AV = 2 V/V
RL = 200Ö
VIN = 0V
VCLAMP = 3V
VCM = 0V
0.1
1
10
100
1000
1.0e-1
1.0
1.0e1
1.0e2
1.0e3
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40.
Figure 41.
Balance Error
Noise Figure
-15
14
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
VS = +2.5V
13
12
11
10
9
AV = 9 V/V
RF = 275Ö
VCM = 0V
VCLAMP = 3V
50Ö SYSTEM
RL = 200Ö
RF = 274Ö
AV = 1 V/V
1
10
100
1000
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 42.
Figure 43.
16
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
Noise Figure
Differential S-Parameter Magnitude vs. Frequency
14
13
12
11
10
9
10
S21
AV = 9 V/V
RF = 275Ö
VCM = 0V
VCLAMP = 3V
50Ö SYSTEM
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
S11
(SINGLE-ENDED
INPUT)
S22
S11
VS = +5V
AV = 1 V/V
50W SYSTEM
S12
0
20 40 60 80 100 120 140 160 180 200
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 44.
Figure 45.
Differential S-Parameter Phase vs. Frequency
150
3rd Order Intermodulation Products vs. VOUT
-50
VS = ±5V
S22
100
50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
RF = 324Ö
AV = 2 V/V
VCM = 0V
S21
S12
VCLAMP = 3V
0
-50
S11
-100
-150
-200
-250
-300
-350
S11
(SINGLE-ENDED
INPUT)
VS = +5V
AV = 1 V/V
50W SYSTEM
fc = 75 MHz (2MHz SPACING)
SINGLE-ENDED INPUT
10
100
1000
1
2
3
4
5
6
FREQUENCY (MHz)
DIFFERENTIAL VOUT (VPP)
Figure 46.
Figure 47.
3rd Order Intermodulation Products vs. VOUT
-30
3rd Order Intermodulation Products vs. Center Frequency
-50
VS = ±5V
VS = ±2.5V
RF = 324Ö
AV = 2 V/V
VCM = 0V
RL = 200Ö
RF = 324Ö
AV = 2 V/V
VOD = 2 VPP
VCLAMP = 3V
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-40
-50
VCLAMP = 3V
-60
-70
-80
-90
SINGLE-ENDED INPUT
2MHz SPACING
fc = 75 MHz (2MHz SPACING)
SINGLE-ENDED INPUT
-100
1
2
3
4
5
25
50
75
100
125
150
DIFFERENTIAL VOUT (VPP
)
CENTER FREQUENCY (MHz)
Figure 48.
Figure 49.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics VS = ±5V (continued)
(TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, for single ended in, differential out, unless specified).
3rd Order Intermodulation Products vs. Center Frequency
3rd Order Intermodulation Products vs. Center Frequency
-50
-30
VS = ±5V
VS = ±2.5V
RL = 200Ö
RF = 324Ö
RL = 800Ö
AV = 2 V/V
VOD = 2 VPP
VCLAMP = 3V
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-40
RF = 324Ö
AV = 2 V/V
VOD = 2 VPP
VCLAMP = 2V
-50
-60
-70
-80
-90
SINGLE-ENDED INPUT
2MHz SPACING
SINGLE-ENDED INPUT
2 MHz SPACING
-100
25
50
75
100
125
150
25
50
75
100
125
150
CENTER FREQUENCY (MHz)
CENTER FREQUENCY (MHz)
Figure 50.
Figure 51.
3rd Order Intermodulation Products vs. Center Frequency
3rd Order Intermodulation Products vs. VCLAMP
-30
-30
VS = ±2.5V
V
= ±5V
S
RL = 800Ö
R
R
= 324Ö
= 200Ö
= 2 V/V
-40
-50
F
-40
RF = 324Ö
L
AV = 2V/V
VOD = 2VPP
VCLAMP = 2V
-50
-60
A
V
V
V
f
= 150 Mhz
= 50 Mhz
c
= 2 V
= 0V
OD
CM
PP
-60
-70
-70
f
c
-80
-80
-90
-90
SINGLE-ENDED INPUT
2 MHz SPACING
-100
-100
0.5
1.0
1.5
2.0
(V)
2.5
3.0
25
50
75
100
125
150
V
CLAMP
CENTER FREQUENCY (MHz)
Figure 52.
Figure 53.
18
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
APPLICATION INFORMATION
The LMH6553, a fully differential current feedback amplifier with integrated output common mode control and
output limiting clamp, is designed to provide protection of following input stages. The common mode feedback
circuit sets the output common mode voltage independent of the input common mode, as well as forcing the
outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single
ended to differential conversion.
The proprietary current feedback architecture of the LMH6553 offers gain and bandwidth independence even at
high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1
equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC
offset error, and output balance. Resistors with 0.1% tolerances are recommended for optimal performance, and
the amplifier is internally compensated to operate with optimum gain flatness with values of RF between 250Ω
and 350Ω depending on package selection, PCB layout, and load resistance.
The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a
low impedance source and should be bypassed to ground with a 0.1 µF ceramic capacitor. Any unwanted signal
coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier. This pin
must not be left floating.
The LMH6553 can be operated with either a single 5V supply or split +5V and −5V supplies. Operation on a
single 5V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be
required. For example, in a DC coupled input application on a single 5V supply, with a VCM of 1.5V, the input
common voltage at a gain of 1 will be 0.75V which is outside the minimum 1.5V to 3.5V input common mode
range of the amplifier. The minimum VCM for this application should be greater than 1.5V depending on output
signal swing. Alternatively, AC coupling of the inputs in this example results in equal input and output common
mode voltages, so a 1.5V input common mode would result. Split supplies allow much less restricted AC and DC
coupled operation with optimum distortion performance.
The LMH6553 has a VCLAMP input which allows control of the maximum amplifier output swing to prevent
overdriving of following stages such as sensitive ADC inputs and also provides fast recovery from transients that
would otherwise saturate the signal path.
RECOMMENDED FEEDBACK RESISTOR
The LMH6553 is available in both an 8-pin WSON and SO PowerPAD package. The recommended feedback
resistor, RF, for the WSON package is 275Ω and 325Ω for the SO PowerPAD to give a flat frequency response
with minimal peaking.
FULLY DIFFERENTIAL OPERATION
The LMH6553 is ideal for a fully differential configuration. The circuit shown in Figure 54 is a typical fully
differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the
closed loop gain AV = VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are
optional and help keep the amplifier stable when presented with a capacitive load. Refer to DRIVING
CAPACITIVE LOADS for details.
R
R
F
O
R
G
+
V
IN
C
L
R
V
L
O
V
CM
~
-
R
G
V
CLAMP
R
F
R
O
Figure 54. Typical Application
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
When driven from a differential source, the LMH6553 provides low distortion, excellent balance, and common
mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is
observed in board layout.
275W
50W
61W
R
= 50W
275W
S
+
V
IN
V
CM
R
L
~
-
275W
R
= 50W
S
61W
V
CLAMP
50W
275W
Figure 55. Differential S-Parameter Test Circuit
The circuit configuration shown in Figure 55 was used to measure differential S parameters in a 50Ω
environment at a gain of 1 V/V. Refer to Figure 45 and Figure 46 in Typical Performance Characteristics for
measurement results.
SINGLE-ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION
In many applications, it is required to drive a differential input ADC from a single-ended source. Traditionally,
transformers have been used to provide single to differential conversion, but these are inherently bandpass by
nature and cannot be used for DC coupled applications. The LMH6553 provides excellent performance as a
single-to-differential converter down to DC. Figure 56 shows a typical application circuit where an LMH6553 is
used to produce a differential signal from a single ended source.
R
F
A , R
V
IN
+
V
R
S
R
R
O
G
+
IN-
V
-
IN
V
CM
V
R
OUT
+
LMH6553
ADC
IN+
T
~
-
R
O
V
R
G
-
R
M
+
V
CLAMP
-
+
-
R
F
«
∆
∆
≈
«
∆
∆
≈
≈
∆
∆
«
2(1 - b )
R
1
≈
∆
∆
«
G
A
V
=
b =
1
b
1
+ b
2
R
+ R
F
G
=
=
R
«
∆
∆
≈
R
|| R
«
∆
∆
≈
S
T
IN
≈
∆
∆
«
R + R
G M
≈
∆
∆
2R + R (1-b )
G
M
2
=
b =
2
R
IN
R
R
|| R
M
T
S
R
+ R + R
F M
1 + b
G
2
«
Figure 56. Single-Ended Input with Differential Output
When using the LMH6553 in single-to-differential mode, the complementary output is forced to a phase inverted
replica of the driven output by the common mode feedback circuit as opposed to being driven by its own
complementary input. Consequently, as the driven input changes, the common mode feedback action results in a
varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal
common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which
is superimposed on the differential output signal. The ratio of the change in output common mode voltage to
output differential voltage is commonly referred to as output balance error. The output balance error response of
the LMH6553 over frequency is shown in the Typical Performance Characteristics.
20
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
To match the input impedance of the circuit in Figure 56 to a specified source resistance, RS, requires that RT ||
RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 56.
These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain
with the proper input termination. Component values for several common gain configurations in a 50Ω
environment are given in Table 1.
Table 1. Gain Component Values for 50Ω System
WSON Package
Gain
0 dB
RF
RG
RT
RM
275Ω
275Ω
275Ω
255Ω
127Ω
54.9Ω
59Ω
26.7Ω
28.7Ω
34Ω
6 dB
68.1Ω
107Ω
12 dB
Table 2. Gain Component Values for 50Ω System
SO PowerPAD Package
Gain
0 dB
RF
RG
RT
RM
325Ω
325Ω
325Ω
316Ω
150Ω
68.1Ω
56.2Ω
64.9Ω
88.7Ω
26.7Ω
28Ω
6 dB
12 dB
31.6Ω
275W
50W
255W
255W
R
= 50W
S
+
V
IN
V
CM
~
59W
R
L
-
V
CLAMP
26.7W
50W
275W
Figure 57. Single Ended Input S-Parameter Test Circuit (50Ω System)
The circuit shown in Figure 57 was used to measure S-parameters for a single-to-differential configuration.
Figure 45 and Figure 46 in Typical Performance Characteristics are taken using the recommended component
values for 0 dB gain.
SINGLE SUPPLY OPERATION
Single supply operation is possible on supplies from 5V to 10V; however, as discussed earlier, AC input coupling
is recommended for low supplies due to input common mode limitations. An example of an AC coupled, single
supply, single-to-differential circuit is shown in Figure 58. Note that when AC coupling, both inputs need to be AC
coupled irrespective of single-to-differential or differential-to-differential configuration. For higher supply voltages,
DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough
so that the amplifier's inputs and outputs are within their specified operating ranges.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
R
F
R
O
V
O
1
V 1
I
R
R
S
G
-
V
+
V
IN
C
R
L
L
OUT
V
CM
R
T
~
+
-
R
G
V 2
I
V
O
2
R
M
R
F
R
O
V
CLAMP
VICM = VOCM
VO1 + VO2
*VCM
=
VI1 + VI2
2
2
VICM
=
*BY DESIGN
Figure 58. AC Coupled for Single Supply Operation
SPLIT SUPPLY OPERATION
For optimum performance, split supply operation is recommended using +5V and −5V supplies; however,
operation is possible on split supplies as low as +2.25V and −2.25V and as high as +6V and −6V. Provided the
total supply voltage does not exceed the 4.5V to 12V operating specification, asymmetric supply operation is also
possible and in some cases advantageous. For example, if 5V DC coupled operation is required for low power
dissipation but the amplifier input common mode range prevents this operation, it is still possible with split
supplies of (V+) and (V−). Where (V+) - (V−) = 5V and V+ and V− are selected to set the amplifier input common
mode voltage to suit the application.
CLAMP OPERATION
The output clamp allows control of the maximum amplifier output swing to prevent overdriving of following stages
such as sensitive ADC inputs and provide fast recovery from signal transients that would otherwise saturate the
signal path. Figure 59 shows the relationship between VCLAMP and the +OUT and −OUT outputs. The example
circuit shown has a single ended input and is set for a gain of 2 V/V. For proper operation VCM < VCLAMP < VCM
+
2.0V and the upper single ended output voltage is limited to the voltage level set at the VCLAMP input. The output
common mode control loop forces the lower single ended voltage to be limited to 2*VCM - VCLAMP. The maximum
clamped single ended output swing is therefore equal to 2*(VCLAMP - VCM) and the maximum differential output
swing is therefore equal to 4*(VCLAMP - VCM). In the example of Figure 59 with VCLAMP set to 2V and VCM set to
1.5V, the maximum single ended output is therefore 1 VPP centered at 1.5V and the maximum differential output
is 2 VPP. This is shown for the case of a 2 VPP input sine wave which for a gain of 2 V/V in unclamped operation
would provide single ended outputs at +OUT and -OUT of 2 VPP but is shown being clamp limited to 1 VPP
.
22
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
V
VON_SE
2.5
VCLAMP
2.0
1.5
VCM
=
1 VPP
1.0
0.5
2*VCM œ VCLAMP
SE Unclampled output
t
0
RF
RG
0V
VIN = 2VPP
+
VCM
Differential Output
VON-VOP = 2VPP
VCM = 1.5V
VCLAMP
-
RG
RF
V
VOP_SE
Vclamp = 2.0V
2.5
2.0
1.5
VCLAMP
1 VPP
VCM
=
1.0
0.5
2*VCM œ VCLAMP
SE Unclampled output
0
t
Figure 59. Clamp Operation
CLAMP PERFORMANCE
Key clamp performance specifications are listed in the electrical characteristics section. Figure 60 illustrates the
clamp overdrive recovery time which is defined as the difference in input to output propagation delay due to a
step change at the input for a clamped output versus a normal linear unclamped, non-saturated output.
Clamp Overdrive
Recovery Time
V
Response to step
from clamped state
50%
Normal Linear
response to step
Time
Figure 60. Clamp Overdrive Recovery Time
MAXIMUM OUTPUT LEVEL
The maximum unclamped output swing in normal operation is 4VPP single ended or 8 VPP differential due to the
requirement that VCLAMP < VCM + 2.0V. For split supply operation of +5V and −5V, the maximum output voltage is
limited by the output stage's ability to swing close to either supply (VOUT < ±3.7V). As shown in Figure 61, if
VCLAMP is set > 3.7V, the amplifier output will saturate at the positive supply before the clamp can operate and
similarly if 2*VCM - VCLAMP < −3.7V, the amplifier output will saturate at the negative supply.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
VOUT(MAX)
+V
V
CLAMP
5
SE Unclamped output
= + 3.7V
4
= 3
2
V
OUT(MAX)
V
CM
1
2*V
t
œ V
CLAMP
CM
0
VOUT(MIN)
t
0
-1
-2
V
CLAMP
V
= -3
-4
CM
V
= -3.7V
OUT(MIN)
SE Unclamped output
œ V
CLAMP
-5
2*V
CM
-V
Figure 61. Split Supply VOUT(MAX) and VOUT(MIN) Output Levels
OUTPUT NOISE PERFORMANCE AND MEASUREMENT
Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6553
refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher
input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback
resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This
allows operation of the LMH6553 at much higher gain without incurring a substantial noise performance penalty,
simply by choosing a suitable feedback resistor.
Figure 62 shows a circuit configuration used to measure noise figure for the LMH6553 in a 50Ω system. An RF
value of 275Ω is chosen for the SO PowerPAD package to minimize output noise while simultaneously allowing
both high gain (9 V/V) and proper 50Ω input termination. Refer to SINGLE-ENDED INPUT TO DIFFERENTIAL
OUTPUT OPERATION for calculation of resistor and gain values. Noise figure values at various frequencies are
shown in Figure 43 in Typical Performance Characteristics.
275W
+
V
1 mF
2:1 (TURNS)
R
= 50W
50W
S
10W
+
-
V
IN
V
CM
50W
V
O
LMH6553
~
+
-
10W
1 mF
-
V
275W
= 9 V/V
A
V
Figure 62. Noise Figure Circuit Configuration
24
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well, there are usually current spikes associated with
switched capacitor or sample and hold circuits. Figure 63 shows the LMH6553 driving the ADC14C105. The
amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6553 common mode
voltage is set by the ADC14C105. The 0.1 µF capacitor, in series with the 49.9Ω resistor, is inserted to ground
across the 68.1Ω resistor to balance the amplifier inputs. The circuit in Figure 63 has a 2nd order lowpass LC
filter formed by the 620 nH inductors along with the 22 pF capacitor across the differential inputs of the
ADC14C105. The filter has a pole frequency of about 50 MHz. The two 100Ω resistors serve to isolate the
capacitive loading of the ADC from the amplifier and ensure stability. For switched capacitor input ADCs, the
input capacitance will vary based on the clock cycle, as the ADC switches between the sample and hold mode.
See your particular ADC's datasheet for details.
274W
50W
ADC14C105
+
V
Single-Ended
AC-Coupled
Source
620 nH
127W
100W
100W
-
V
+
14-Bit
105 MSPS
CM
68.1W
22 pF
LMH6553
-
+
V
REF
127W
68.1W
620 nH
-
49.9W
0.1mF
V
+
V
-
CLAMP
274W
Figure 63. Driving a 14-bit ADC
Figure 64 shows the SFDR and SNR performance vs. frequency for the LMH6553 and ADC14C105 combination
circuit with the ADC input signal level at −1 dBFS. The ADC14C105 is a single channel 14-bit ADC with
maximum sampling rate of 105 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to
differential mode. An external bandpass filter is inserted in series between the input signal source and the
amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input
impedance seen at the LMH6553 amplifier inputs, RM is chosen to match ZS || RT for proper input balance.
100
95
90
85
80
75
70
65
60
55
50
0
5
10 15 20 25 30 35 40
INPUT FREQUENCY (MHz)
Figure 64. LMH6553/ADC14C105 SFDR and SNR Performance vs. Frequency
The amplifier and ADC should be located as close together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on it's outputs
and the ADC is sensitive to high frequency noise that may couple in on its inputs. Some high performance ADCs
have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all
input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2).
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
The LMH6553 is capable of driving a variety of Texas Instruments Analog-to-Digital Converters. This is shown in
Table 3, which offers a list of possible signal path ADC and amplifier combinations. The use of the LMH6553 to
drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-
sampling or over-sampling). See application note AN-236 (SNAA079) for more details on the sampling processes
and application note AN-1393, Using High Speed Differential Amplifiers to Drive ADCs (SNOA461). For more
information regarding a particular ADC, refer to the particular ADC datasheet for details.
Table 3. DIFFERENTIAL INPUT ADCs COMPATIBLE WITH LMH6553 DRIVER
Product Number
ADC1173
Max Sampling Rate (MSPS)
Resolution
8
Channels
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
15
20
ADC1175
8
ADC08351
42
8
ADC1175-50
ADC08060
50
8
60
8
ADC08L060
ADC08100
60
8
100
200
500
1000
1000
20
8
ADC08200
8
ADC08500
8
ADC081000
ADC08D1000
ADC10321
8
8
10
10
10
10
10
10
10
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
14
14
14
14
14
SINGLE
DUAL
ADC10D020
ADC10030
20
27
SINGLE
DUAL
ADC10040
40
ADC10065
65
SINGLE
DUAL
ADC10DL065
ADC10080
65
80
SINGLE
DUAL
ADC11DL066
ADC11L066
ADC11C125
ADC11C170
ADC12010
66
66
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
125
170
10
ADC12020
20
ADC12040
40
ADC12D040
ADC12DL040
ADC12DL065
ADC12DL066
ADC12L063
ADC12C080
ADC12DS080
ADC12L080
ADC12C105
ADC12DS105
ADC12C170
ADC14L020
ADC14L040
ADC14C080
ADC14DS080
ADC14C105
40
40
DUAL
65
DUAL
66
DUAL
63
SINGLE
SINGLE
DUAL
80
80
80
SINGLE
SINGLE
DUAL
105
105
170
20
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
40
80
80
105
SINGLE
26
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
Table 3. DIFFERENTIAL INPUT ADCs COMPATIBLE WITH LMH6553 DRIVER (continued)
Product Number
ADC14DS105
ADC14155
Max Sampling Rate (MSPS)
Resolution
Channels
DUAL
105
155
14
14
SINGLE
DRIVING CAPACITIVE LOADS
As noted previously, capacitive loads should be isolated from the amplifier outputs with small valued resistors.
This is particularly the case when the load has a resistive component that is 500Ω or higher. A typical ADC has
capacitive components of around 10 pF and the resistive component could be 1000Ω or higher. If driving a
transmission line, such as 50Ω coaxial or 100Ω twisted pair, using matching resistors will be sufficient to isolate
any subsequent capacitance.
BALANCED CABLE DRIVER
With up to 8 VPP differential output voltage swing and 100 mA of linear drive current the LMH6553 makes an
excellent cable driver as shown in Figure 65. The LMH6553 is also suitable for driving differential cables from a
single ended source.
275W
100W
TWISTED PAIR
50W
127W
R
= 50W
61.8W
S
+
-
V
IN
V
CM
~
2 V
PP
127W
28.7W
V
CLAMP
50W
275W
A
= 2 V/V
V
Figure 65. Fully Differential Cable Driver
POWER SUPPLY BYPASSING
The LMH6553 requires supply bypassing capacitors as shown in Figure 66 and Figure 67. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic
distortion performance. A small capacitor, ~0.01 µF, placed across the supply rails, and as close to the chip's
supply pins as possible, can further improve HD2 performance. Narrow traces or small vias will reduce the
effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and VCLAMP pins to
ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise
sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
+
V
10 mF
0.1 mF
+
-
V
CM
0.01 mF
V
CLAMP
0.1 mF
0.1 mF
-
V
0.1 mF
10 mF
Figure 66. Split Supply Bypassing Capacitors
V+
0.01 mF
0.1 mF
10 mF
+
-
V
CM
V
CLAMP
0.1 mF
0.01 mF
Figure 67. Single Supply Bypassing Capacitors
POWER DISSIPATION
The LMH6553 is optimized for maximum speed and performance in the small form factor of the standard WSON
package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.
Therefore, it is of utmost importance to make sure that the TJMAX of 150°C is never exceeded.
Follow these steps to determine the maximum power dissipation for the LMH6553:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* VS
where
•
VS = V+ - V−. (Be sure to include any current through the feedback network if VCM is not mid-rail.)
(1)
2. Calculate the RMS power dissipated in each of the output stages:
PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS − V−OUT) * I−
)
OUT
where
•
VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were
single ended amplifiers and VS is the total supply voltage
(2)
3. Calculate the total RMS power:
PT = PAMP + PD
(3)
28
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
LMH6553
www.ti.com
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
The maximum power that the LMH6553 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
•
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SO PowerPAD package θJA is 59°C/W
For WSON package θJA is 58°C/W
(4)
Note: If VCM is not mid-rail, then there will be quiescent current flowing in the feedback network. This current
should be included in the thermal calculations and added into the quiescent power dissipation of the amplifier.
THERMAL PERFORMANCE
The LMH6553 is available in both the SO PowerPAD and WSON packages. Both packages are designed for
enhanced thermal performance and features an exposed die attach pad (DAP) at the bottom center of the
package that creates a direct path to the PCB for maximum power dissipation. The DAP is floating and is not
electrically connected to internal circuitry.
The thermal advantage of the two packages is fully realized only when the exposed die attach pad is soldered
down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. The thermal
land can be connected to any power or ground plane within the allowable supply voltage range of the device.
The junction-to-ambient thermal resistance (θJA) of the LMH6553 can be significantly lowered, as opposed to an
alternative with no direct soldering to a thermal land. Based on thermal analysis of the WSON package, the
junction-to-ambient thermal resistance (θJA) can be improved by a factor of two when the die attach pad of the
WSON package is soldered directly onto the PCB with thermal land and thermal vias are 1.27 mm and 0.33 mm
respectively. Typical copper via barrel plating is 1 oz, although thicker copper may be used to further improve
thermal performance.
For more information on board layout techniques for the WSON package, refer to Application Note 1187
(literature number SNOA401). This application note also discusses package handling, solder stencil and the
assembly process.
ESD PROTECTION
The LMH6553 is protected against electrostatic discharge (ESD) on all pins. The LMH6553 will survive 4000V
Human Body model and 350V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. The current that flows through the ESD diodes will either exit the chip through the supply
pins or through the device, hence it is possible to power up a chip with a large signal applied to the input pins.
BOARD LAYOUT
The LMH6553 is a very high performance amplifier. In order to get maximum benefit from the differential circuit
architecture, board layout and component selection are very critical. The circuit board should have a low
inductance ground plane and well bypassed wide supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as
should the supply bypass capacitors. Refer to POWER SUPPLY BYPASSING for recommendations on bypass
circuit layout. Evaluation boards are available free of charge through the product folder on TI’s web site.
By design, the LMH6553 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and
power plane metal should be removed from beneath the amplifier and from beneath RF and RG for best
performance at high frequency.
With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to
distortion and balance errors.
EVALUATION BOARD
See the LMH6553 Product Folder for evaluation board availability and ordering information.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: LMH6553
LMH6553
SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision G (March 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 29
30
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6553
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6553MR/NOPB
LMH6553MRE/NOPB
LMH6553MRX/NOPB
ACTIVE SO PowerPAD
DDA
8
8
8
95
RoHS & Green
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
LMH65
53MR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
250
SN
SN
LMH65
53MR
DDA
2500 RoHS & Green
1000 RoHS & Green
LMH65
53MR
LMH6553SD/NOPB
LMH6553SDE/NOPB
ACTIVE
ACTIVE
WSON
WSON
NGS
NGS
8
8
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
6553
250
RoHS & Green
6553
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6553MRE/NOPB
LMH6553MRX/NOPB
SO
PowerPAD
DDA
DDA
8
8
250
178.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
SO
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
PowerPAD
LMH6553SD/NOPB
LMH6553SDE/NOPB
WSON
WSON
NGS
NGS
8
8
1000
250
178.0
178.0
12.4
12.4
3.3
3.3
2.8
2.8
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6553MRE/NOPB
LMH6553MRX/NOPB
LMH6553SD/NOPB
LMH6553SDE/NOPB
SO PowerPAD
SO PowerPAD
WSON
DDA
DDA
NGS
NGS
8
8
8
8
250
2500
1000
250
208.0
356.0
208.0
208.0
191.0
356.0
191.0
191.0
35.0
35.0
35.0
35.0
WSON
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DDA HSOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6553MR/NOPB
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
NGS0008C
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.8
0.7
SEATING PLANE
0.08 C
1.6 0.1
SYMM
(0.1) TYP
0.05
0.00
EXPOSED
THERMAL PAD
5
4
SYMM
9
2X
1.5 0.1
1.5
1
8
0.3
0.2
6X 0.5
8X
0.1
C A B
C
0.5
0.3
PIN 1 ID
8X
0.05
4214924/A 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NGS0008C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
8
1
8X (0.25)
(0.5)
9
SYMM
(1.5)
6X (0.5)
4
5
(
0.2) VIA
TYP
(R0.05) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214924/A 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NGS0008C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
METAL
TYP
8X (0.6)
SYMM
8
1
8X (0.25)
SYMM
(1.38)
9
6X (0.5)
4
5
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214924/A 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.287
1.673
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.287
1.673
4218820/A 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.287)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(4.9)
NOTE 9
SYMM
(2.287)
(1.3)
SOLDER MASK
TYP
OPENING
6X (1.27)
5
4
(
0.2) TYP
VIA
SYMM
(5.4)
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218820/A 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008D
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.287)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(2.287)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.557 X 2.557
2.287 X 2.287 (SHOWN)
2.088 X 2.088
0.125
0.150
0.175
1.933 X 1.933
4218820/A 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
LMH6553SDX/NOPB
900 MHz Fully Differential Amplifier with Output Limiting Clamp 8-WSON -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明