LMH0346MH/NOPB [TI]
具有双路差动输出的 3G HD/SD SDI 时钟恢复器 | PWP | 20 | -40 to 85;
| 型号： | LMH0346MH/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双路差动输出的 3G HD/SD SDI 时钟恢复器 | PWP | 20 | -40 to 85 时钟 光电二极管 商用集成电路 |
| 文件： | 总24页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH0346
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SNLS248J –APRIL 2007–REVISED APRIL 2013
3 Gbps HD/SD SDI Reclocker with Dual Differential Outputs
Check for Samples: LMH0346
1
FEATURES
DESCRIPTION
The LMH0346 3 Gbps HD/SD SDI Reclocker retimes
serial digital video data conforming to the SMPTE
424M, SMPTE 292M, and SMPTE 259M (C)
standards. The LMH0346 operates at serial data
rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967
Gbps, and 2.97 Gbps. The LMH0346 supports DVB-
ASI operation at 270 Mbps.
2
•
Supports SMPTE 424M, SMPTE 292M, and
SMPTE 259M (C) Serial Digital Video
Standards
•
Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps,
2.967 Gbps, and 2.97 Gbps Serial Data Rate
Operation
•
•
•
•
•
Supports DVB-ASI at 270 Mbps
Single 3.3V Supply Operation
The LMH0346 automatically detects the incoming
data rate and adjusts itself to retime the incoming
data to suppress accumulated jitter. The LMH0346
recovers the serial data-rate clock and optionally
provides it as an output. The LMH0346 has two
differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output.
Controls and indicators are: serial clock or second
serial data output select, manual rate select input,
SD/HD rate indicator output, lock detect output,
auto/manual data bypass and output mute. The serial
data inputs, outputs, and serial clock outputs are
differential LVPECL compatible. The CML serial data
and serial clock outputs are suitable for driving 100Ω
differentially terminated networks. The control logic
inputs and outputs are LVCMOS compatible.
370 mW Typical Power Consumption
Two Differential, Reclocked Outputs
Choice of Second Reclocked Output or Low-
Jitter, Differential, Data-Rate Clock Output
•
Single 27 MHz External Crystal or Reference
Clock Input
•
•
•
•
•
•
Manual or Automatic Rate Select Input
SD/HD Operating Rate Indicator Output
Lock Detect Indicator Output
Output Mute Function for Data and Clock
Auto/Manual Reclocker Bypass
Differential LVPECL Compatible Serial Data
Inputs and Outputs
The LMH0346 is powered from a single 3.3V supply.
Power dissipation is typically 370 mW.
•
•
•
•
LVCMOS Control Inputs and Indicator Outputs
20-Pin HTSSOP or 24-Pin WQFN Package
Industrial Temperature Range: -40°C to +85°C
The device is available in two space-saving
packages: a 6.5 X 4.4 mm 20-pin HTSSOP and an
even more space–efficient 5 X 4 mm 24-pin WQFN
package.
Footprint Compatible With the LMH0046 and
LMH0026 (HTSSOP Package)
APPLICATIONS
•
SDTV/HDTV and 3 Gbps Serial Digital Video
Interfaces for:
–
–
Digital Video Routers and Switchers
Digital Video Processing and Editing
Equipment
–
–
DVB-ASI Equipment
Video Standards and Format Converters
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH0346
SNLS248J –APRIL 2007–REVISED APRIL 2013
www.ti.com
Typical Application
CABLE DRIVER
LMH0302
CABLE
EQUALIZER
LMH0344
3 Gbps/HD/SD
RECLOCKER
LMH0346
CABLE DRIVER
LMH0302
CABLE
EQUALIZER
LMH0344
3 Gbps/HD/SD
RECLOCKER
LMH0346
3 Gbps/HD/SD
CROSSPOINT
SWITCH
CABLE DRIVER
LMH0302
SERIAL
DATA
CABLE
EQUALIZER
LMH0344
3 Gbps/HD/SD
RECLOCKER
LMH0346
CABLE DRIVER
LMH0302
CABLE
EQUALIZER
LMH0344
3 Gbps/HD/SD
RECLOCKER
LMH0346
Block Diagram
SCO_EN
BYPASS/AUTO BYPASS
RATE0
HD
SD/
CONTROL LOGIC
LOCK DETECT
RATE1
V
CCO
BYPASS
50
50
XTAL IN/EXT CLK
SCO/SDO2
SCO/SDO2
XTAL OUT
LOOP FILTER 1
VCO / PLL
LOOP FILTER 2
O/P MUTE
V
CCO
50
50
SDO
SDO
SDI
SDI
RETIMER / FIFO
2
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SNLS248J –APRIL 2007–REVISED APRIL 2013
Connection Diagram
20
1
2
LF1
LF2
SCO_EN
SD/HD
19
18
17
16
15
3
V
CCO
RATE0
RATE1
SDI
4
SDO
SDO
5
6
LMH0346MH
V
CCO
SDI
7
14
13
12
11
V
CC
SCO/SDO2
SCO/SDO2
8
BP/AUTO-BP
OP MUTE
9
LOCK DET
XTAL OUT
10
XTAL IN/EXT CLK
The exposed die attach pad is the negative electrical terminal for this device. It must be connected to the negative
power supply voltage.
Figure 1. 20-Pin HTSSOP
See Package Number PWP
24
23
22
21
20
V
LF2
RATE0
RATE1
SDI
1
2
3
4
5
6
7
19
18
17
16
15
14
13
CCO
SDO
SDO
LMH0346SQ
(top view)
V
CCO
SCO/SDO2
SDI
V
CC
SCO/SDO2
LOCK DET
BP/AUTO-BP
8
9
10
11
12
The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the
negative power supply voltage.
Figure 2. 24-Pin WQFN
See Package Number NHZ
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PIN DESCRIPTIONS
HTSSOP
Pin
WQFN
Pin
Name
Description
1
2
3
4
5
6
7
24
1
LF1
Loop Filter.
Loop Filter.
LF2
2
RATE 0
RATE 1
SDI
Data Rate select input. This pin has an internal pulldown.
Data Rate select input. This pin has an internal pulldown.
Data Input True.
3
4
5
SDI
Data Input Complement.
6
VCC
Positive power supply.
Bypass/Auto Bypass mode select. Bypasses reclocking when high. This
pin has an internal pulldown.
8
9
7
8
BYPASS/AUTO BYPASS
OUTPUT MUTE
Data and Clock Output Mute Input. Mutes the output when low. This pin
has an internal pullup.
10
11
12
13
14
15
16
17
18
19
9
XTAL IN/EXT CLK
XTAL OUT
LOCK DETECT
SCO/SDO2
SCO/SDO2
VCCO
Crystal or External Oscillator Input.
Crystal Oscillator Output.
12
13
14
15
16
17
18
19
20
PLL Lock Detect Output (active high).
Serial Clock or Serial Data Output 2 Complement.
Serial Clock or Serial Data Output 2 True.
Positive power supply (Output Driver).
Data Output Complement.
SDO
SDO
Data Output True.
VCCO
Positive power supply (Output Driver).
Data Rate Range Output. Output is high for SD and low for HD or 3G.
SD/HD
Serial Clock or Serial Data 2 Output select. Sets second output to output
the clock when high and the data when low. This pin has an internal
pulldown.
20
21
SCO_EN
—
—
10, 11, 23
22
VEE
Negative power supply.
RSVD
VEE
Reserved for future use. Do not connect.
Connect exposed DAP to negative power supply (ground).
DAP
DAP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage (VCC–VEE
)
4.0V
Logic Input Voltage (Vi)
VEE−0.15V to VCC+0.15V
−5 mA
Logic Input Current (single input)
Vi = VEE−0.15V
Vi = VCC+0.15V
+5 mA
Logic Output Voltage (Vo)
V
EE−0.15V to VCC+0.15V
±8 mA
Logic Output Source/Sink Current
Serial Data Output Sink Current (ISDO
Package Thermal Resistance
)
24 mA
θJA 20-pin HTSSOP
θJA 24-pin WQFN
θJC 20-pin HTSSOP
θJC 24-pin WQFN
26.6°C/W
33.0°C/W
2.4°C/W
3.2°C/W
Storage Temperature Range
Junction Temperature
−65°C to +150°C
+125°C
Lead Temperature (Soldering 4 Sec)
ESD Rating
+260°C (Pb-free)
8 kV
HBM
MM
400V
CDM
2 kV
(1) “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS specify acceptable device operating conditions.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC–VEE
)
3.3V ±5%
VEE to VCC
Logic Input Voltage
Differential Serial Input Voltage
800 mV ±10%
16 mA max.
Serial Data or Clock Output Sink Current (ISO
Operating Free Air Temperature (TA)
)
−40°C to +85°C
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DC ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
Symbol
VIH
Parameter
Conditions
Reference
Min
2
Typ
Max
VCC
0.8
Units
V
Input Voltage High Level
Input Voltage Low Level
Input Current High Level
Input Current Low Level
Logic inputs
VIL
VEE
V
IIH
VIH = VCC
VIL = VEE
47
65
µA
µA
V
IIL
−18
−25
VOH
VOL
VSDID
Output Voltage High Level IOH = −2 mA
Logic outputs
SDI
2
Output Voltage Low Level IOL = +2 mA
VEE + 0.6
1600
V
Serial Input Voltage,
Differential
See(3)
200
VEE+0.95
620
mVP-P
V
VCMI
Input Common Mode
Voltage
VSDID = 200 mV(3)
100Ω differential load
V
CC−0.2
VSDOD
VSCOD
Serial Data Output
Voltage, Differential
SDO, SDO2
SCO
750
525
750
880
mVP-P
mVP-P
mVP-P
Serial Clock Output
Voltage, Differential
100Ω differential load,
400
650
2970 MHz(3)
100Ω differential load,
1485 or 270 MHz Mbps
VCMO
ICC
Output Common Mode
Voltage
100Ω differential load
SDO, SCO
VCC−
VSDOD
V
Supply Current
2970 Mbps
111
126
mA
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to
VEE (equal to zero volts).
(2) Typical values are stated for: VCC = +3.3V, TA = +25°C.
(3) This parameter is ensured by characterization over voltage and temperature limits.
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AC ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)
Symbol
BRSD
Parameter
Serial Data Rate
Serial Data Rate
Conditions
SMPTE 259M, C
SMPTE 292M
Reference
SDI, SDO
Min
Typ
Max
Units
270
Mbps
BRSD
1483,
1485
Mbps
Mbps
UIP-P
UIP-P
UIP-P
UIP-P
UIP-P
UIP-P
BRSD
TOLJIT
TOLJIT
TOLJIT
TOLJIT
TOLJIT
TOLJIT
Serial Data Rate
SMPTE 424M
2967,
2970
Serial Input Jitter
Tolerance
270 Mbps(2)(3)(4)
SDI
>6
>0.6
>6
Serial Input Jitter
Tolerance
270 Mbps(2)(3)(5)
Serial Input Jitter
Tolerance
1483 or 1485 Mbps(2)(3)(4)
1483 or 1485 Mbps(2)(3)(5)
2967 or 2970 Mbps(2)(3)(4)
2967 or 2970 Mbps(2)(3)(5)
Serial Input Jitter
Tolerance
>0.6
>6
Serial Input Jitter
Tolerance
Serial Input Jitter
Tolerance
>0.6
tJIT
tJIT
tJIT
Serial Data Output Jitter
Serial Data Output Jitter
Serial Data Output Jitter
270 Mbps(3)(6)
1483 or 1485 Mbps(3)(7)
2967 or 2970 Mbps(3)(8)
SDO
0.01
0.03
0.06
0.03
0.04
0.08
UIP-P
UIP-P
UIP-P
BWLOOP Loop Bandwidth
270 Mbps,
<0.1dB Peaking
275
1.5
kHz
MHz
MHz
MHz
MHz
MHz
MHz
1485 Mbps,
<0.1dB Peaking
2970 Mbps,
<0.1dB Peaking
2.75
270
FCO
FCO
FCO
FCO
FCO
tJIT
Serial Clock Output
Frequency
270 Mbps data rate
1483 Mbps data rate
1485 Mbps data rate
2967 Mbps data rate
2970 Mbps data rate
SCO
Serial Clock Output
Frequency
1483
1485
2967
Serial Clock Output
Frequency
Serial Clock Output
Frequency
Serial Clock Output
Frequency
2970
2
MHz
Serial Clock Output Jitter
3
psRMS
Serial Clock Output
Alignment with respect to
Data Interval
See(3)
See(3)
SDO, SCO
SCO
40
45
60
%
Serial Clock Output Duty
Cycle
55
15
%
TACQ
tr, tf
Acquisition Time
Input rise/fall time
See(9)
ms
ns
10%–90%
Logic inputs
1.5
(1) Typical values are stated for: VCC = +3.3V, TA = +25°C.
(2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
(3) This parameter is ensured by characterization over voltage and temperature limits.
(4) Refer to “A1” in Figure 1 of SMPTE RP 184-1996.
(5) Refer to “A2” in Figure 1 of SMPTE RP 184-1996.
(6) PRBS 210−1, input jitter = 31 psP-P
(7) PRBS 210−1, input jitter = 24 psP-P
(8) PRBS 210−1, input jitter = 22 psP-P
(9) Measured from first SDI transition until Lock Detect (LD) output goes high (true).
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AC ELECTRICAL CHARACTERISTICS (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)
Symbol
tr, tf
Parameter
Input rise/fall time
Input rise/fall time
Conditions
20%–80%, 270 Mbps(10)
Reference
SDI
Min
Typ
Max
Units
1500
ps
tr, tf
20%–80%, 1483 or 1485
Mbps(10)
270
135
ps
ps
tr, tf
Input rise/fall time
20%–80%, 2967 or 2970
Mbps(10)
tr, tf
tr, tf
Output rise/fall time
Output rise/fall time
10%–90%
20%–80%(3)(11)
Logic outputs
SDO, SCO
1.5
90
ns
ps
130
FREF
Reference Clock
Frequency
27
MHz
ppm
FTOL
Reference Clock
Frequency Tolerance
±50
(10) This specification is ensured by design.
(11) RL = 100Ω differential.
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SNLS248J –APRIL 2007–REVISED APRIL 2013
DEVICE DESCRIPTION
The LMH0346 3 Gbps HD/SD SDI Reclocker is used in many types of digital video signal processing equipment.
Supported serial digital video standards are SMPTE 259M (C), SMPTE 292M, and SMPTE 424M. Corresponding
serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI data at 270
Mbps may also be retimed. The LMH0346 retimes the serial data stream to suppress accumulated jitter. It
provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial
data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial data output
select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output
mute.
Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and
produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω
differential loads. The differential output level is 750 mVP-P into 100Ω AC or DC-coupled differential loads. Logic
inputs and outputs are LVCMOS compatible.
The device package is a 20-pin HTSSOP or a 24-pin WQFN. Both package options have an exposed die attach
pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the negative electrical
terminal for the device. This terminal must be connected to the negative power supply or circuit ground.
Serial Data Inputs, Serial Data and Clock Outputs
SERIAL DATA INPUT AND OUTPUTS
The differential serial data input, SDI, accepts serial digital video data at the rates specified in Table 1. The serial
data input is differential LVPECL compatible. The input is intended to be DC interfaced to devices such as the
LMH0344 adaptive cable equalizer. The input is not internally terminated or biased. The input may be AC-
coupled if a suitable input bias voltage is provided. Figure 3 shows the equivalent input circuit for SDI and SDI.
The LMH0346 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide
low jitter, differential, retimed data to devices such as the LMH0302 cable driver. Output SCO/SDO2 is
multiplexed and can provide either a second serial data output or a serial clock output. Figure 4 shows the
equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2.
The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the
SCO/SDO2 output provides a serial clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial
data.
Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic
low level. SCO/SDO2 also mutes when the Bypass mode is activated and this output is operating as the serial
clock output (SCO_EN input is high). When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite
differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have
internal 50Ω pull-ups and are suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω
un-center-tapped, differentially terminated networks.
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V
CC
20 kW
80 kW
1 pF
V
CC
V
CC
2 kW
2 kW
SDI
SDI
Figure 3. Equivalent SDI Input Circuit (SDI, SDI)
V
CC
V
CC
V
CC
50W
50W
SDO, SCO/SDO2
SDO, SCO/SDO2
Figure 4. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
OPERATING SERIAL DATA RATES
This device operates at serial data rates of 270 Mbps, 1483 Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The
device does not lock to harmonics of these rates. The device does not lock and automatically enters the
reclocker bypass mode for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps, and 540 Mbps.
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second
retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being
processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the
corresponding serial data bit interval within 10% of the center of the data interval.
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Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low
level. This output functions as the serial clock output when the SCO_EN input is a logic-high level. The SCO_EN
input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled).
SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated
and this output is functioning as a serial clock output (SCO_EN is high), the output will also be muted. If an
unsupported data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the
output is invalid.
Control Inputs and Indicator Outputs
SERIAL DATA RATE SELECTOR
The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have
internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition.
This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired
operating serial data rate. The LMH0346 then enters either the Auto-Rate Detect mode or a single operating rate.
Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2
coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. Auto-
Rate Detect mode may be used for any supported data rate, including DVB-ASI.
Table 1. Data Rate Select Input Codes
Rate [1:0] Code
Data Rate or Mode
Auto-Rate Detect mode
270 Mbps
Comments
00
01
10
May be used to support DVB-ASI operation
1483/1485 Mbps, 2967/2970 Mbps
LOCK DETECT
The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be
connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being
received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 2.
OUTPUT MUTE
The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock
Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data
and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see
Table 2. OUTPUT MUTE has an internal pull-up device to enable the output by default.
BYPASS/AUTO BYPASS
The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this
input is low, the device automatically bypasses the reclocking function when the device is in an unlocked
condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto
Bypass input is set high, Lock Detect will remain low. See Table 2. BYPASS/AUTO BYPASS has an internal pull-
down device.
Table 2. Control Functionality
LOCK DETECT
OUTPUT MUTE
BYPASS/AUTO BYPASS
DEVICE STATUS
PLL unlocked, reclocker bypassed
0
1
X
0
1
1
X
0
1
PLL locked to supported data rate, reclocker not bypassed
Outputs muted
0
X
X
0
LOCK DETECT
LOCK DETECT
Outputs muted
PLL locked to supported data rate, reclocker not bypassed
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SD/HD
The SD/HD output indicates whether the LMH0346 is processing SD or HD / 3 Gbps data rates. It may be used
to control another device such as the LMH0302 cable driver. When this output is high it indicates that the data
rate is 270 Mbps. When low, the indicated data rate is 1483, 1485, 2967, or 2970 Mbps. The SD/HD output is a
registered function and is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is
not locked (the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/HD output is
undefined for a short time after lock detect assertion or deassertion due to a data rate change on SDI. See
Figure 5 for a timing diagram showing the relationship between SDI, Lock Detect, and SD/HD.
SDI
NO DATA
270 MBPS DATA
NO DATA
1485 MBPS DATA
NO DATA
T
ACQ
T
T
T
2
2
ACQ
Lock
Detect
T
1
T
1
T
1
SD/HD
SDI
NO DATA
270 MBPS DATA
1485 MBPS DATA
2970 MBPS DATA
270 MBPS DATA
T
T
T
T
ACQ
ACQ
ACQ
ACQ
T
T
T
2
2
2
Lock
Detect
T
1
T
1
T
1
T
1
T
1
SD/HD
T
T
T
= Acquisition Time, defined in the AC Electrical Characteristics Table
ACQ
= Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27 MHz clock period)
= Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD/HD output is not valid during this time.
1
2
Figure 5. SDI, Lock Detect, and SD/HD Timing
SCO_EN
Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial clock or second serial
data output. SCO/SDO2 functions as a serial clock when SCO_EN is high. This pin has an internal pull-down
device. The default state (low) enables the SCO/SDO2 output as a second serial data output.
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CRYSTAL OR EXTERNAL CLOCK REFERENCE
The LMH0346 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel
resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.
Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a
suitable crystal are given in Table 3.
Table 3. Crystal Parameters
Parameter
Value
Frequency
27 MHz
Frequency Stability
Operating Mode
Load Capacitance
Shunt Capacitance
Series Resistance
±50 ppm @ recommended drive level
Fundamental mode, Parallel Resonant
18–20 pF
7 pF
40Ω max.
100 µW
Recommended Drive Level
Maximum Drive Level
500 µW
Operating Temperature Range
−10°C to +60°C
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APPLICATION INFORMATION
Figure 6 shows an application circuit for the LMH0346 along with the LMH0344 3 Gbps HD/SD SDI Adaptive
Cable Equalizer and LMH0302 3 Gbps HD/SD SDI Cable Driver.
V
CC
V
CC
RATE0
RATE1
56 nF
SCO_EN
20
1
2
SCO_EN
SD/HD
LF1
19
18
17
16
15
A
LF2
LMH0344 Adaptive
Cable Equalizer
3
V
CCO
RATE0
RATE1
SDI
4
Coaxial Cable
1.0 mF
B
C
75W
SDO
SDO
5
SDO
SDI
LMH0346
6
SDI
V
CCO
100W
7
14
13
12
11
1.0 mF
V
CC
SCO/SDO2
SCO/SDO2
Additional
Outputs
8
6.8 nH
SDI SDO
BP/AUTO-BP
OP MUTE
9
LOCK DET
XTAL OUT
10
75W
XTAL IN/EXT CLK
37.4W
DAP
27 MHz
1.0 mF
39 pF
39 pF
LOCK DET
BP/AUTO-BP
OP MUTE
+3.3V
A
75W
75W
5.6 nH
LMH0302
Cable Driver
Coaxial Cable
Coaxial Cable
4.7 mF
4.7 mF
SD/HD
75W
B
C
SDI
SDO
SDO
100W
75W
75W
SDI
R
REF
75W
5.6 nH
+3.3V
750W
Figure 6. Application Circuit
The LMH0346 inputs are LVPECL compatible. The LMH0346 has a wide input common mode range and in most
cases the input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range
specified in DC ELECTRICAL CHARACTERISTICS. Figure 6 shows an example of a DC coupled interface
between the LMH0344 cable equalizer and the LMH0346. The LMH0344 output common mode voltage and
voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0346. All
that is required is a 100Ω differential termination as shown. The resistor should be placed as close to the
LMH0346 input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap
capacitor to ground in place of the single 100Ω resistor.
14
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The LMH0346 outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second
output that may be set as the serial clock or a second data output. Both outputs are always active. The LMH0346
output should be DC coupled to the input of the receiving device as long as the common mode ranges of both
devices are compatible. Figure 6 shows an example of a DC coupled interface between the LMH0346 and
LMH0302 cable driver. All that is required is a 100Ω differential termination as shown. The resistor should be
placed as close to the LMH0302 input as possible. If desired, this network may be terminated with two 50Ω
resisters and a center tap capacitor to ground in place of the single 100Ω resistor.
The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the
loop filter capacitor should not be changed.
RATE0 and RATE1 have internal pulldowns to select Auto-Rate Detect mode by default. These pins may also be
used to set the device to SD mode or HD/3G mode.
BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be
pulled high to force the LMH0346 to bypass all data.
OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the
outputs.
The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal
should match the parameters described in Table 3. Alternately, a 27MHz LVCMOS compatible clock signal may
be input to XTAL IN/EXT CLK.
The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is
locked.
The SD/HD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0302) in order to
properly set the cable driver’s edge rate for SMPTE compliance. It defaults to HD/3G (low) when the LMH0346 is
not locked.
SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled
high to set the second output as a serial clock.
The ground connection for the LMH0346 is through the large exposed DAP. The DAP must be connected to
ground for proper operation of the LMH0346. This is the only ground connection for the LMH0346MH. It is the
primary ground connection, required for good signal integrity, for the LMH0346SQ.
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REVISION HISTORY
Changes from Revision I (April 2013) to Revision J
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH0346MH/NOPB
LMH0346MHX/NOPB
LMH0346SQ/NOPB
LMH0346SQE/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
WQFN
PWP
PWP
NHZ
NHZ
20
20
24
24
73
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
L0346
L0346
2500 RoHS & Green
1000 RoHS & Green
SN
SN
SN
L0346SQ
L0346SQ
WQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0346MHX/NOPB HTSSOP PWP
20
24
24
2500
1000
250
330.0
178.0
178.0
16.4
12.4
12.4
6.95
4.3
7.1
5.3
5.3
1.6
1.3
1.3
8.0
8.0
8.0
16.0
12.0
12.0
Q1
Q1
Q1
LMH0346SQ/NOPB
LMH0346SQE/NOPB
WQFN
WQFN
NHZ
NHZ
4.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0346MHX/NOPB
LMH0346SQ/NOPB
LMH0346SQE/NOPB
HTSSOP
WQFN
PWP
NHZ
NHZ
20
24
24
2500
1000
250
356.0
208.0
208.0
356.0
191.0
191.0
35.0
35.0
35.0
WQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH0346MH/NOPB
20
73
495
8
2514.6
4.06
Pack Materials-Page 3
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
MECHANICAL DATA
NHZ0024B
SQA24B (Rev A)
www.ti.com
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