LMH0340 [TI]
具有 LVDS 接口的 3G HD/SD DVB-ASI SDI 串行器和驱动器;
| 型号： | LMH0340 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 LVDS 接口的 3G HD/SD DVB-ASI SDI 串行器和驱动器 驱动 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总30页 (文件大小：926K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com
SNLS271I –APRIL 2007–REVISED APRIL 2013
3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface
Check for Samples: LMH0040, LMH0050, LMH0070, LMH0340
1
FEATURES
DESCRIPTION
The LMH0340/0040/0070/0050 SDI Serializers are
part of TI’s family of FPGA-Attach SER/DES products
supporting 5-bit LVDS interfaces with FPGAs. An
FPGA Host will format data with supplied IP such that
the output of the LMH0340 is compliant with the
requirements of DVB-ASI, SMPTE 259M-C, SMPTE
292M and SMPTE 424M standards. See Table 1 for
details on which Standards are supported per device.
2
•
LVDS Interface to Host FPGA
•
•
•
•
•
•
No External VCO or Clock Ref Required
Integrated Variable Output Cable Driver
3.3V SMBus Configuration Interface
Integrated TXCLK PLL Cleans Clock Noise
Small 48-Pin WQFN Package
Industrial Temperature range: -40°C to 85°C
The interface between the SER (Serializer) and the
FPGA consists of a 5 bit wide LVDS data bus, an
LVDS clock and an SMBus interface. The
LMH0340/0040/0070 SER devices include an
integrated cable driver which is fully compliant with all
of the SMPTE specifications listed above. The
LMH0050 has a CML output driver that can drive a
differential transmission line or interface to a cable
driver.
APPLICATIONS
•
SDI Unterfaces for:
–
–
–
–
Video Cameras
DVRs
Video Switchers
Video Editing Systems
The FPGA-Attach SER/DES family is supported by a
suite of IP which allows the design engineer to
quickly develop video applications using the
SER/DES products. The SER is packaged in a
physically small 48-pin WQFN package.
KEY SPECIFICATIONS
•
Output Compliant With SMPTE 424M, SMPTE
292M, SMPTE 259M-C and DVB-ASI (See
Table 1)
•
•
Typical Power Dissipation: 440 mW
30 ps Typical Output Jitter (HD, 3G)
General Block Diagram
SDA
LOCK
SCK
SMB_CS
SMBus
Control
GPIO[2:0]
RESET
DVB_ASI
TX4
TX3
TX2
TXOUT
TX1
TX0
SMPTE Cable Driver
TXCLK
LVDS Receivers
PLL Clock
Generation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013
www.ti.com
Connection Diagram
VDD3V3 1
RSVH_H 2
GPIO_0 3
GPIO_1 4
RSVD_H 5
DVB_ASI 6
VDD2V5 7
GND 8
36 VDD3V3
35 VDD2V5
34 SMB_CS
33 SCK
LMH0340,
LMH0070,
LMH0040,
LMH0050,
32 SDA
31 LOCK
TOP VIEW
(not to scale)
30 RESET
29 GND
48-pin WQFN Package
GND 9
28 VDDPLL
27 LF_CP
26 LF_REF
25 VDD2V5
DAP = GND
GND 10
GPIO_2 11
GND 12
Figure 1. Connection Diagram for 48L WQFN Package
2
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com
SNLS271I –APRIL 2007–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name
Type
Description
LVDS Input Interface
TX[4:0]+
TX[4:0]-
Input, LVDS
Input, LVDS
LVDS Data Input Pins
Five channel wide DDR interface. Internal 100Ω termination.
TXCLK+
TXCLK-
LVDS Clock Input Pins
DDR Interface. Internal 100Ω termination.
Serial Output Interface
TXOUT+
Output, CML
Output, CML
Serial Digital Interface Output Pin
Non-Inverting Output
TXOUT-
Serial Digital Interface Output Pin
Inverting Output
SMBus Interface
SDA
I/O, LVCMOS
Input, LVCMOS
Input, LVCMOS
SMBus Data I/O Pin
SCK
SMBus Clock Input Pin
SMB_CS
SMBus Chip Select Input Pin
Device is selected when High.
Control and Configuration Pins
RESET
Input, LVCMOS
Reset Input Pin
H = normal mode
L = device in RESET
LOCK
Output, LVCMOS
Input, LVCMOS
PLL LOCK Status Output
H = unlock condition
L = Device is Locked
DVB_ASI
DVB_ASI Select Input
H = DVB_ASI Mode enabled
L = Normal Mode enabled
GPIO[2:0]
RSVD_H
I/O, LVCMOS
General Purpose Input / Output
Software configurable I/O pins.
Input, LVCMOS
Configuration Input – Must tie High
Pull High via 5 kΩ resistor to VDD3V3
Analog Inputs
RSET
Input, analog
Serial Output Amplitude Control
Resistor connected from this pin to ground to set the signal amplitude. Nominally
8.06kΩ for 800mV output (SMPTE).
LF_CP
LF_REF
DNC
Input, analog
Input, analog
Loop Filter Connection
Loop Filter Reference
Do Not Connect – Leave Open
Power Supply and Ground
VDD3V3
VDDPLL
VDD2V5
GND
Power
3.3V Power Supply connection
3.3V PLL Power Supply connection
2.5V Power Supply connection
Power
Power
Ground
Ground connection – The DAP (large center pad) is the primary GND connection for
the device and must be connected to Ground along with the GND pins.
Table 1. Feature Table
SMPTE 424M
Support (3G)
SMPTE 292M
Support (HD)
SMPTE 259M
Support (SD)
DVB-ASI
Support
SMPTE compliant
Cable Driver
Device
LMH0340
LMH0040
LMH0070
LMH0050
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VDD3V3
Supply Voltage (VDD2V5
LVCMOS input voltage
)
−0.3V to +4.0V
−0.3V to +3.0V
−0.3V to (VDD3V3+0.3V)
−0.3V to (VDD3V3+0.3V)
-0.3V to +3.6V
-0.3V to +3.6V
+150°C
)
LVCMOS output voltage
SMBus I/O voltage
LVDS Input Voltage
Junction Temperature
Storage Temperature
−65° to 150°C
25°C/W
Thermal Resistance— Junction to Ambient—θJA
ESD Rating—Human Body Model,
1.5 KΩ, 100 pF
≥±8kV
(1) “Absolute Maximum Ratings” are limits beyond which the safety of the device cannot be ensured. It is not implied that the device will
operate up to these limits.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Parameter
Min
Typ
3.3
2.5
Max
3.465
2.625
100
+85
100
297
149
28
Units
V
Supply Voltage (VDD3V3-GND)
Supply Voltage (VDD2V5-GND)
Supply noise amplitude (10 Hz to 50 MHz)
Ambient Temperature
3.135
2.375
V
mVP-P
°C
−40
+25
Case Temperature
°C
TXCLK input frequency
LMH0340
LMH0040
LMH0070
LMH0050
27
27
MHz
MHz
MHz
MHz
cm
26.5
27
27
149
25
LVDS PCB board trace length (mismatch <2%)
Output Driver Pullup Resistor Termination Voltage(1)
2.5
2.625
V
(1) Applies to LMH0340, LMH0040, and LMH0070.
4
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LMH0040, LMH0050
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SNLS271I –APRIL 2007–REVISED APRIL 2013
Electrical Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
Parameter
Condition
Min
Typ
93
Max
102
87
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
IDD2.5
2.5V supply current for LMH0340,
LMH0040, or LMH0070
2.97 Gbps
1.485 Gbps
80
270 Mbps
63
69
2.5V supply current for LMH0050
1.485 Gbps
87
95
270 Mbps
70
75
IDD3.3
3.3V supply current for LMH0340,
LMH0040, or LMH0070
2.97 Gbps
73
85
1.485 Gbps
73
85
270 Mbps
73
85
3.3V supply current for LMH0050
Power Consumption
1.485 Gbps
73
85
270 Mbps
73
85
PD
LMH0340 - 2.97 Gbps
LMH0040 - 1.485 Gbps
LMH0050 - 1.485 Gbps
LMH0050 - 270 Mbps
LMH0070 - 270 Mbps
475
440
460
415
400
545
510
525
485
470
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
Control Pin Electrical Characteristics
Over supply and Operating Temperature ranges unless otherwise specified. Applies to DVB_ASI, RESET, GPIO[2:0] and
(1)
LOCK.
Symbol
VIH
Parameter
Condition
Min
2.0
0
Typ
Max
VDD3V3
0.8
Units
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
VIL
V
VOH
VOL
VCL
IIN
IOH=−2 mA
2.7
3.3
-0.79
-40
V
IOL=2 mA
0.3
-1.5
35
V
ICL=−18 mA
VIN=0.4V, 2.5V or VDD
VOUT=0V
V
-35
μA
mA
IOS
Output Short Circuit Current
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
LVDS Input Electrical Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
VTH
Parameter
Condition
Min
Typ
Max
Units
mV
mV
Ω
Differential Input High threshold
Differential Input Low threshold
Input Impedance
0.05V<VCM<2.4V
+100
VTL
−100
RLVIN
Measured between LVDS pairs
85
100
115
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
Copyright © 2007–2013, Texas Instruments Incorporated
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LMH0040, LMH0050
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SNLS271I –APRIL 2007–REVISED APRIL 2013
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LVDS Switching Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
tCIP
Parameter
Condition
Min
3.2
Typ
2T
1.0
T
Max
37
Units
ns
TxCLKIN Period
See Figure 2
See Figure 3
See Figure 2
See Figure 2
tCIT
TxCLKIN Transition Time
TxCLKIN IN High Time
TxCLKIN IN Low Time
TxIN Transition Time
TxIN Setup to TxCLKIN
TxIN Hold to TxCLKIN
0.5
3.0
1.3T
1.3T
3
ns
tCIH
0.7T
0.7T
0.15
-550
900
ns
tCIL
T
ns
tXIT
ns
(2)
tSTC
tHTC
See Figure 2
ps
ps
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
(2) Parameter uses default settings in registers: 0x24'h and 0x30'h.
t
/2
CIP
+100 mV
-100 mV
TXCLK
0V
t
, t
CIL CIH
t
t
HTC
STC
Hold
Setup
TXn
0V
Figure 2. LVDS Input Timing Diagram
80%
80%
TXCLK
20%
20%
t
t
CIT
CIT
Figure 3. Transmit Clock Transition Times
SMBus Input Electrical Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
VSIL
Parameter
Condition
Min
Typ
Max
0.8
Units
V
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
VSIH
2
4
VSDD
V
(2)
ISPULLUP
Current through pull-up resistor or
current source
mA
VSDD
Nominal Bus Voltage
2.375
−200
−10
3.6
200
10
V
(2)
ISLEAKB
ISLEAKP
CSI
Input Leakage per bus segment
Input Leakage per pin
μA
μA
pF
Ω
(2) (3)
Capacitance for SMBdata and SMBclk
Termination Resistance
10
(4) (3) (2)
RSTERM
VSDD3V3
1000
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
(2) Recommended value—Parameter is not tested.
(3) Recommended maximum capacitance load per bus segment is 400 pF.
(4) Maximum termination voltage should be identical to the device supply voltage.
6
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LMH0040, LMH0050
LMH0070, LMH0340
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SNLS271I –APRIL 2007–REVISED APRIL 2013
SMBus Switching Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
fSMB
Parameter
Condition
Min
10
Typ
Max
Units
kHz
μs
Bus Operating Frequency
100
tBUF
Bus free time between stop and start
condition
4.7
tHD:STA
Hold time after (repeated) start
condition. After this period, the first
clock is generated
At ISPULLUP = MAX
4.0
μs
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tLOW
Repeated Start condition setup time
Stop Condition setup time
Data hold time
4.7
4.0
300
250
4.7
4.0
μs
μs
ns
ns
μs
μs
ns
ns
ns
ms
Data setup time
Clock Low Time
tHIGH
tF
Clock High Time
50
Clock/data fall time
Clock/data rise time
SMB_CS setup time
20% to 80%
300
tR
1000
tSU:CS
tPOR
30
Time in which a device must be
operational after power on
500
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
SMB_CS
t
SU:CS
t
LOW
t
HIGH
t
R
SCK
SDA
t
t
t
t
SU:STA
F
HD:STA
HD:DAT
t
BUF
t
SU:STO
t
SU:DAT
ST
SP
SP
ST
NOTE: (levels are VSIL and VSIH
)
Figure 4. SMBus Timing Parameters
SDI Output Characteristics — LMH0340 / LMH0040 / LMH0070
(1)
Over supply and Operating Temperature ranges unless otherwise specified.
Symbol
VOD
Parameter
Condition
into 75Ω load
LMH0340
Min
720
270
270
Typ
Max
Units
SDI Output Voltage
SDI Output Datarate
800
880
mV
Mbps
Mbps
Mbps
ps
DR
2,970
1,485
LMH0040
LMH0070
270
90
tr
SDI Output Rise Time
SDI Output Fall Time
2.97 Gbps
1.485 Gbps
<1.485 Gbps
2.97 Gbps
1.485 Gbps
<1.485 Gbps
135
220
90
ps
400
400
700
90
1000
135
ps
tf
ps
90
220
ps
700
1000
ps
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
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LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013
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SDI Output Characteristics — LMH0340 / LMH0040 / LMH0070 (continued)
Over supply and Operating Temperature ranges unless otherwise specified. (1)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Δtt
Mismatch between rise and fall time
≥1.485 Gbps
30
ps
(2)
tSD
tJ
Propagation Delay Latency
Peak to Peak Alignment Jitter
See Figure 5
9.5
TXCLK
cycle
≥1.485 Gbps(3)
270 Mbps(3)
30
100
20
50
ps
ps
dB
dB
200
RL
tOS
Output Return Loss — EVK
Specification(4)
Measured 5 MHz to 1485 MHz
15
10
Measured 1485 MHz to 2970
MHz
15
Output Overshoot(2)
2.97 Gbps
1.485 Gbps
270 Mbps
8
5
2
%
%
%
(2) Specification ensured by characterization.
(3) Measured in accordance with SMPTE RP184. 100% production tested.
(4) Output Return Loss specification applies to measurement on the EVK PCB (LMH0340 ALP Daughter Card) per SMPTE requirements.
CML Output Characteristics — LMH0050
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
Parameter
Condition
Min
1175
270
Typ
Max
1450
1485
100
100
50
Units
mV
Mbps
ps
VOD
DR
tr
Output Voltage
into 100 Ω differential load
Data Rate
Output Rise Time
Output Fall Time
tf
ps
tJ
Peak-to-Peak Alignment Jitter
Output Termination Resistance
1.485 Gbps
25
50
ps
ROUT
Output Pin to VDD2V5 Pin
40
60
Ω
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
Device Switching Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol
Parameter
Condition
2.97 Gbps
1.485 Gbps
270 Mbps
Min
Typ
Max
10
Units
ms
tTPLD
Device Lock Time
11
ms
15
ms
(1) Typical Parameters measured at VDD3V3=3.3V, VDD2V5=2.5V, TA=25°C. They are for reference purposes and are not production tested.
TXN
Symbol N
Symbol N+1
Symbol N+2
Symbol N+3
Symbol N+4
t
SD
TXCLK
TXOUT
Symbol N-3
Symbol N-1
Symbol N
Symbol N-4
Symbol N-2
Figure 5. LVDS Interface Propagation Delay
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SNLS271I –APRIL 2007–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
DEVICE OPERATION
The SER is used in digital video signal origination equipment. It is intended to be operated in conjunction with an
FPGA host which preprocesses data for it, and then provides this data over the five bit wide data path. Provided
the host has properly formatted the data for the SER, the output of the device will be compliant with DVB-ASI,
SMPTE 259M-C, SMPTE 292M or SMPTE 424M depending upon the output mode selected.
Texas Instruments offers IP in source code format to perform the appropriate formatting of the data, as well as
evaluation platforms to assist in the development of target applications. For more information please contact your
local Texas Instruments Sales Office/Distributor.
POWER SUPPLIES
The SER has several power supply pins, at 2.5V as well as 3.3V. It is important that these pins all be connected,
and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF capacitors as a minimum, with a
0.1μF capacitor on each power pin. The device has a large contact in the center of the bottom of the package.
This contact must be connected to the system GND as it is the major ground connection for the device. A 22 μF
capacitor is required on the VDDPLL pin which is connected to the 3.3V rail.
Discrete bypassing is ineffective above 30 MHz to 50 MHz in power plane-based distribution systems. Above this
frequency range, the intrinsic capacitance of the power-ground system can be used to provide additional RF
bypassing. To make the best use of this, make certain that there are PCB layers dedicated to the Power supplies
and to GND, and that they are placed next to each other to provide a distributed capacitance between power and
GND.
The SER will work best when powered from linear regulators. The output of linear regulators is generally cleaner
with less noise than switching regulators. Output filtering and power system frequency compensation are
generally simpler and more effective with linear regulators. Low dropout linear regulators are available which can
usually operate from lower input voltages such as logic power supplies, thereby reducing regulator power
dissipation. Cascading of low dropout regulators should not be done since this places the entire supply current
load of both load systems on the first regulator in the cascade and increases its loading and thermal output.
POWER UP
The 3.3V power supply should be brought up before the 2.5V supply. The timing of the supply sequencing is not
important. The device has a power on reset sequence which takes place once both power supplies are brought
up. This sequence will reset all register contents to their default values, and will place the PLLs into link
acquisition mode, attempting to lock on the TXCLK input.
RESET
There are three ways in which the device may be reset. There is an automatic reset which happens on power-up;
there is a reset pin, which when brought low will reset the device, with normal operation resuming when the pin is
driven high again. The third way to reset the device is a soft reset, implemented via a write to the reset register.
This reset will put all of the register values back to their default values, except it will not affect the address
register value if the SMBus default address has been changed.
LVDS INPUTS
The SER has LVDS inputs that conform with the ANSI/TIA/EIA-644–A Standard. These inputs have an internal
100 Ω resistor across the inputs which allows for the closing of a current loop interface from the LVDS driver in
the host. It is recommended that the PCB trace between the FPGA and the transmitter be less than 25cm.
Longer PCB traces may introduce signal degradation as well as channel skew which could cause serialization
errors. This connection between the host and the SER should be over a controlled impedance transmission line
with an impedance which matches the termination resistor – usually 100 Ω. Setup and hold times are specified in
LVDS Switching Characteristics, however there is the ability to change these by use of the CLK delay adjustment
available via the SMBus, and writing to register 0x30'h.
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LVDS DATA ORDER
When serializing the data, the data bit latched in on TX0 is output first, followed by TX1, TX2, TX3 and then TX4.
If starting with a 10 bit word, T0..T9, with T0 being the LSB, and it is desired that this be serialized such that the
LSB is sent out first, then the least significant 5 bit word would be provided to the serializer first, followed by the
most significant word, and the resulting serialized output would have the LSB being sent first, and the 10 bit MSB
(T9) would be transmitted last. If it is desired to reverse the serialization order, such that the bit presented on
TX4 is output first, this mode of operation may be selected via register 0x2E'h.
LOOP FILTER
The SER has an internal PLL which is used to generate the serialization clock from the parallel clock input. The
loop filter for this PLL is external, and for optimum results in Serial Digital Interface applications, a capacitor and
a resistor in series should be connected between pins 26 and 27. Recommended value for the capacitor is
0.1 μF. Recommended value for the resistor is 500 Ω.
PLL FILTER / BYPASS
The SER has an external filter capacitor for the PLL. The recommended value for this capacitor is 22 μF with a
connection to the 3.3V rail.
DVB_ASI MODE
The SER has a special mode for DVB-ASI. In this mode, the input signal on TX4± is treated as a data valid bit, if
high, then the four bit nibbles from TX0-TX3 are taken to form an 8 bit word, which is then converted to a 10 bit
code via an internal 8b10b encoder and this 10 bit word is serialized and driven on the output. The nibble taken
in on the rising edge of the clock is the most significant nibble and the nibble taken in on the falling edge is the
least significant nibble. If TX4± is low, then the input on TX0-TX3 are ignored and the 10b idle character is
inserted in the output stream. The Idle character can be reprogrammed to be any 10 bit code desired via
registers 0x11'h and 0x12'h.
SDI OUTPUT INTERFACING
The serial outputs provide low-skew complimentary or differential signals. The output buffer is a current mode
design, with a high impedance output. To drive a 75Ω transmission line connect a 75Ω resistor from each of the
output pins to 2.5V. This resistor has two functions – it converts the current output to a voltage, which is used to
drive the cable, and it acts as the back termination resistor for the transmission line. The resistor should be
placed as close to the output pin as is practicable. The output driver automatically adjusts its slew rate depending
on the input datarate so that it will be in compliance with SMPTE 259M, SMPTE292M or SMPTE 424M as
appropriate. In addition to output amplitude and rise/fall time specifications, the SMPTE specs require that SDI
outputs meet an Output Return Loss (ORL) specification. There are parasitic capacitances that will be present
both at the output pin of the device and on the application printed circuit board. To optimize the return loss
implement a series network comprised of a parallel inductor and resistor. The actual values for these
components will vary from application to application, but the typical interface circuit shows values that would be a
good starting point. Figure 6 shows an equivalent output circuit for the LMH0340 / LMH0040 / LMH0070. The
collectors present a high impedance current source. The external 75Ω resistors will provide the back termination
resistance as well as converting the current to a voltage – with the addition of the termination resistance at the
load, there will be an overall output resistance of 37.5Ω, which in conjunction with the 24mA current source will
develop the 800mV swings called for in the standard.
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TXOUT+
TXOUT-
2.5V
2.5V
24 mA
Figure 6. Simplified SDI Output Circuit
Care must be taken in the layout of the output circuitry to meet SMPTE return loss specifications as any parasitic
impedances or transmission line discontinuities will result in reflections which will adversely affect the output
return loss. For more details on how to get good output return loss, please refer to the application note
“Successful design with the FPGA-Attach SER/DES”.
0
-10
SMPTE424 Limit
-20
-30
Measured EVK
Return Loss
-40
-50
-60
1.00E+07
1.00E+08
1.00E+09
1.00E+10
FREQUENCY
Figure 7. SDI Output Return Loss (EVK Example)
The amplitude of the output is ensured to be compliant with SMPTE specifications if the specified value of RSET
resistor is used, however if the designer wishes to change the output amplitude, there are two methods by which
this can be done. By changing the value of resistor connected to the RSET pin, the output amplitude will be
adjusted.
1000
950
900
850
800
750
700
650
600
6
7
8
9
10
11
RSET (kW)
Figure 8. Output Voltage vs. RSET
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CML Output Interfacing
The LMH0050 does not include the internal SMPTE cable driver, as its outputs are CML, include internal 50 Ω
pull up resistors, and are intended to drive 100 Ω transmission lines. The LMH0050 outputs may either be
connected to a differential transmission medium such as twisted pair cable, or used to drive an external cable
driver.
Power Down Mode
If the device is not to be used, some power can be saved by writing a ‘0x40h’ to register 0x26'h, and a 0x10'h to
register 0x01'h. The write to register 0x26'h will disable the input buffers of the device, and the write to register
0x01'h will power down the output buffer. In this mode, the device power dissipation can be expected to be
reduced by approximately 30%. There are portions of the circuit which will automatically power down if there is
no clock present on the TXCLK input, so this method can be used to further reduce the power.
SMBus INTERFACE
The configuration bus conforms to the System Management Bus (SMBus) 2.0 specification. SMBus 2.0 includes
multiple options. The optional ARP (Address Resolution Protocol) feature is not supported. The I/O rail is 3.3V
only and is not 5V tolerant. The use of the SMB_CS signal is recommended for applications with multi-drop
applications (multiple devices to a host).
The SMBus is a two wire interface designed for the communication between various system component chips,
additional signals maybe required for chip select function depending upon application. By accessing the control
functions of the circuit via the SMBus, signal count is kept to a minimum while allowing a maximum amount of
versatility. The SMBus has three pins to control it: an SMBus CS pin which enables the SMBus interface for the
device, a Clock and a Data line. In applications where there might be several SER devices, the SDA and SCK
pins can be bussed together and the individual devices to be communicated with may be selected via their
respective SMB_CS pin. The SCK and SDA are both open drain and are pulled high by external pullup resistors.
The SER has several internal configuration registers which may be accessed via the SMBus. These registers are
listed in Table 2.
TRANSFER OF DATA TO THE DEVICE VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
START / STOP / IDLE CONDITIONS
There are three unique states for the SMBus:
START
STOP
IDLE
A HIGH-to-LOW transition on SDA while SCK is High indicates a message START condition
A LOW-to-HIGH transition on SDA while SCK is High indicates a message STOP condition.
If SCK and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are high for
a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
A transaction begins with the host placing the SER SMBus into the START condition. Then a byte (8 bits) is
transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify NACK.
After this the host holds the SCK line Low, and waits for the receiver to raise the SDA line as an ACKnowledge
that the byte has been received.
REGISTER WRITE
To write a data value to a register in the SER, the host writes three bytes to the SER. The first byte is the device
address—the device address is a 7 bit value, and if writing to the SER the last bit (LSB) is set to ‘0’ to signify that
the operation is a write. The second byte written is the register address, and the third byte written is the data to
be written into the addressed register. If additional data writes are performed, the register address is
automatically incremented. At the end of the write cycle the host places the bus in the STOP state.
REGISTER READ
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To read the data value from a register, first the host writes the device address with the LSB set to a ‘0’ denoting
a write, and then the register address is written to the device. The host then reasserts the START condition, and
writes the device address once again, but this time with the LSB set to a ‘1’ denoting a read, and following this
the SER will drive the SDA line with the data from the addressed register. The host indicates that it has finished
reading the data by asserting a ‘0’ for the ACK bit. After reading the last byte, the host will assert a ‘1’ for NACK
to indicate to the SER that it does not require any more data.
Note that the SMBus pins are not 5V compliant and they must be driven by a 3.3V source.
SMBus CONFIGURATIONS
Many different configurations of the SMBus are possible and depend upon the specific requirements of the
applications. Several possible applications are described.
CONFIGURATION 1
The SER SMB_CS may be tied High (always enabled) since it is the only device on the SMBus. See Figure 9.
CONFIGURATION 2
Since the multiple SER devices have the same address, the use of the individual SMB_CS signals is required.
To communicate with a specific device, its SMB_CS is driven High to select the device. After the transaction is
complete, its SMB_CS is driven Low to disable its SMB interface. Other devices on the bus may now be selected
with their respective chip select signals and communicated with. See Figure 10.
CONFIGURATION 3
The addressing field is limited to 7-bits by the SMBus protocol. Thus it is possible that multiple devices may
share the same 7-bit address. An optional feature in the SMBus 2.0 specification supports an Address Resolution
Protocol (ARP). This optional feature is not supported by the LMH0340/0040/0070/0050 devices. Solutions for
this include: the use of the independent SMB_CS signals, independent SMBus segments, or other means. See
Figure 11.
3V3
SMBus
FPGA
Host
Device
3V3
Figure 9. SMBus Configuration 1 — Host to single device
SMBus
Device
SMBus
Device
SMBus
Device
FPGA
Host
3V3
Figure 10. SMBus Configuration 2 — Host to multiple devices with SMB_CS signals
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SMBus
Device
SMBus
Device
SMBus
Device
FPGA
Host
3V3
3V3
3V3
3V3
Figure 11. SMBus Configuration 3 — Host to multiple devices with multiple SMBus Interfaces
GENERAL PURPOSE I/O PINS GPIO[2:0]
The SER has three pins which can be configured to provide direct access to certain register values via a
dedicated pin. For example if a particular application required fast action to the condition of the serializer losing
it’s input clock, the TXCLK detect status bit could be routed directly to an external pin where it might generate an
interrupt for the host processor. GPIO pins can be configured to be in TRI-STATE® (High Impedance) mode, the
buffers can be disabled, and when used as inputs can be configured with a pullup resistor, a pulldown resistor or
no input pin biasing at all. When the GPIO pins are being used as inputs, there is the ability to have an internal
pullup or pull down resistor. This is selected via the GPIO Configuration registers.
Each of the GPIO pins has a register to control it. For each of these registers, the upper 4 bits are used to define
what function is desired of the GPIO pin with options being slightly different for each of the three GPIO pins. The
pins can be used to monitor the status of various internal states of the SER device, to serve as an input from
some external stimulus, and for output to control some external function.
GPIO_0 FUNCTIONS
Allow for the output of a signal programmed by the SMBus
Allow the monitoring of an external signal via the SMBus
Monitor Status of TXCLK signal
Monitor Status of TXCLKDetect
Monitor Power On Reset
GPIO_1 FUNCTIONS
Monitor Power On Reset
Allow for the output of a signal programmed by the SMBus
Allow the monitoring of an external signal via the SMBus
Monitor LOS for data bit 0
Monitor LOS for data bit 1
Monitor LOS for data bit 2
Monitor LOS for data bit 3
Monitor LOS for data bit 4
GPIO_2 FUNCTIONS
Allow for the output of a signal programmed by the SMBus
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Allow the monitoring of an external signal via the SMBus
Serializer Clock output
Bits 2 and 3 are used to determine the status of the internal pullup/pulldown resistors on the device—they are
loaded according to the following truth table:
00: pullup and pulldown disabled
01: pulldown enabled
10: pullup enabled
11: Reserved
Bit 1 is used to enable or disable the input buffer. If the GPIO pin is to be used as an output pin, then this bit
must be set to a ‘0’ disabling the output.
The LSB is used to switch the output between normal output state and high impedance mode. If the GPIO is to
be used as an input pin, this bit must be set to ‘0’ placing the output in high Z mode.
As an example, if you wanted to use the GPIO0 pin to reflect the status of the LOCK pin, you would load the
appropriate register with the value 0001 0001b.
POTENTIAL APPLICATION FOR GPIO PINS
In addition to being useful debug tools while bringing a design up, there are other practical uses to which the
GPIO pins can be put:
Sensing if a cable is connected to an output –
When connecting the BNC cable to the output, connect the shield of the connector to GND via a
capacitor—making it an AC GND, but a DC open. Now connect that shield to one of the GPIO connections which
you configure as an input with a pullup. With no cable on the BNC, the GPIO pin will see a high state, but once a
terminated cable is connected, the shield will be brought down and you will read a low state.
V
V
DD
DD
3.3V
3.3V
p
p
Output
Input
n
n
Figure 12. Simplified LVCMOS Input Circuit
Figure 13. Simplified LVCMOS Output Circuit
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APPLICATION INFORMATION
PCB RECOMMENDATIONS
The SMPTE Serial specifications have very stringent requirements for output return loss on drivers. The output
return loss will be degraded by non-idealities in the connection between the SER (all variants with the exception
of the LMH0050) and the output connector. All efforts should be taken to minimize the trace lengths for this area,
and to assure that the characteristic impedance of this trace is 75Ω.
It is recommended that the PCB traces between the host FPGA and the SER be no longer than 10 inches
(25cm) and that the traces be routed as differential pairs, with very tight matching of line lengths and coupling
within a pair, as well as equal length traces for each of the six pairs. For additional information on layout and
soldering of the WQFN package, please refer to the applications note AN-1187 (SNOA401).
PCB Design do’s and don’ts:
•
DO Whenever possible dedicate an entire layer to each power supply – this will reduce the inductance in the
supply plane.
•
•
•
DO use surface mount components whenever possible
DO place bypass capacitors close to each power pin
DON’T create ground loops – pay attention to the cutouts that are made in your power and ground planes to
make sure that there are not opportunities for loops.
•
•
•
•
•
DON’T allow discontinuities in the ground planes – return currents will follow the path of least resistance – for
high frequency signals this will be the path of least inductance.
DO place the SER outputs as close as possible to the edge of the PCB where it will connect to the outside
world.
DO make sure to match the trace lengths of all differential traces, both between the sides of an individual
pair, and from pair to pair.
DO remember that VIAs have significant inductance – when using a via to connect to a power supply or
ground layer, two in parallel are better than one.
DO connect the slug on the bottom of the package to a solid Ground connection. This contact is used for the
major GND connection to the device as well as serving as a thermal via to keep the die at a low operating
temperature.
•
There is an application note available which discusses layout suggestions for the SER in greater detail.
TYPICAL SMPTE APPLICATIONS CIRCUIT
A typical application circuit for the LMH0340 is shown in Figure 14. Alternately this could also employ the
LMH0040 or LMH0070 Serializers in lower data rate SMPTE applications.
The TX interface between the host FPGA and the SER is composed of a 5-bit LVDS Data bus and its LVDS
clock. This is a point-to-point interface and the SER includes on-chip 100 terminations. Pairs should be of equal
length to minimize any skew impact. The LVDS clock (TXCLK) uses both edges to transfer the data.
An SMBus is also connected from the host FPGA to the SER. If the SMBus is shared, a chip select signal is
used to select the device being addressed. The SCK and SDA signals require a pull up resistor. The SMB_CS is
driven by a GPO signal from the FPGA. Depending on the FPGA I/O it may also require a pull up unless it is a
push / pull output.
Depending upon the application, several other GPIO signals maybe used. This includes the DVB_ASI and
RESET input signals. If these pins are not used, then must be tied off to the desired state. The LOCK signal
maybe used to monitor the SER. If it is unused, leave the pin as a NC (or route to a test point).
The SER includes a SMPTE compliant cable driver. While this is a differential driver, it is commonly used single-
endedly to drive 75 Ω coax cables. External 75 Ω pull up resistors are used to the 2.5V rail. The active output(s)
also includes a matching network to meet the required Output Return Loss SMPTE specification. While
application specific, in general a series 75 Ω resistor shunted by a 6.8 nH inductor will provide a starting value to
design with. The signal is then AC coupled to the cable with a 4.7 µF capacitor. If the complementary output is
not used, simply terminate it after its AC coupling capacitor to ground. This output (even though its inverting) may
still be used for a loop back or 1:2 function due to the nature of the NRZI coding that the SMPTE standards
require. The output voltage amplitude of the cable driver is set by the RSET resistor. For single-ended
applications, an 8.06 kΩ resistor is connected between this pin and ground to set the swing to 800mV.
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The PLL loop filter is external for the SER. A capacitor is connected in series to a resistor between the LF_CP
and LF_REF pins. Typical values are 500 Ω and 0.1 µF.
There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled
High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or
driven.
There are three supply connections (see PLL FILTER / BYPASS and for recommendations). The two main
supplies are the 3.3V rail and the 2.5V rail. There is also a 3.3V connection for the PLL circuitry.
There are multiple Ground connections for the device. The main ground connection for the SER is through the
large center DAP pad. This must be connected to ground for proper device operation. In addition, multiple other
inputs are required to be connected to ground as show in Figure 14 and listed in .
3.3V 2.5V
All Bypass
CAPS not
shown
3.3V
5 kW
2,5
2.5V
DAP,8,9,10,12,13,
21,22,23,24,29
7,15,18,
25,35
1,36
47
+
6.8 nH
75Ö
75Ö
TX4
-
SDI Output
48
45
4.7 mF
16
+
TXOUT+
TX3
-
75Ö
46
43
4.7 mF
17
+
TXOUT-
TX2
-
44
41
75Ö
3.3V
+
TX1
-
42
39
+
TX0
-
28
40
37
V
DDPLL
+
22 mF
TXCLK
-
8.06 kÖ
14
38
RSET
3.3V
0.1 mF
26
27
3.3V
LF_REF
LF_CP
LMH0340
500Ö
1 kÖ
32
1 kÖ
3
SDA
GPIO_0
GPIO_1
GPIO_2
4
33
SCK
11
34
SMB_CS
6
DVB_ASI
LOCK
31
30
19, 20
RESET
DNC
Figure 14. Typical SMPTE Application Circuit
TYPICAL LMH0050 CML APPLICATIONS CIRCUIT
A typical application circuit for the LMH0050 is shown in Figure 15.
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The TX interface between the host FPGA and the SER is composed of a 5-bit LVDS Data bus and its LVDS
clock. This is a point-to-point interface and the SER includes on-chip 100 terminations. Pairs should be of equal
length to minimize any skew impact. The LVDS clock (TXCLK) uses both edges to transfer the data.
An SMBus is also connected from the host FPGA to the SER. If the SMBus is shared, a chip select signal is
used to select the device being addressed. The SCLK and SDA signals require a pull up resistor. The SMB_CS
is driven by a GPO signal from the FPGA. Depending on the FPGA I/O it may also require a pull up unless it is a
push / pull output.
Depending upon the application, several other GPIO signals maybe used. This includes the DVB_ASI and
RESET input signals. If these pins are not used, then must be tied off to the desired state. The LOCK signal
maybe used to monitor the SER. If it is unused, leave the pin as a NC (or route to a test point).
The LMH0050 SER includes a CML cable driver. This is a differential driver, and includes internal 50 Ω pull up
resistors to the 2.5V rail. The output voltage amplitude of the cable driver is set by the RSET resistor. The RSET
resistor recommended value for the LMH0050 is 9.1KΩ. It is intended to drive 100 Ω differential pairs or twisted
pair cables.
The PLL loop filter is external for the SER. A capacitor is connected in series to a resistor between the LF_CP
and LF_REF pins. Typical values are 500 Ω and 0.1 µF.
There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled
High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or
driven.
There are three supply connections (see PLL FILTER / BYPASS and for recommendations). The two main
supplies are the 3.3V rail and the 2.5V rail. There is also a 3.3V connection for the PLL circuitry.
There are multiple Ground connections for the device. The main ground connection for the SER is through the
large center DAP pad. This must be connected to ground for proper device operation. In addition, multiple other
inputs are required to be connected to ground as show in Figure 15 and listed in .
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3.3V 2.5V
All Bypass CAPS
not shown
3.3V
5 kW
2,5
7,15,18,
25,35
DAP,8,9,10,12,13,
21,22,23,24,29
1,36
47
+
TX4
-
48
45
100Ö TWP
16
+
TXOUT+
TX3
-
46
43
17
+
TXOUT-
TX2
-
44
41
+
TX1
-
42
39
3.3V
+
TX0
-
28
40
37
V
DDPLL
+
22 mF
TXCLK
-
9.1 kÖ
14
38
RSET
3.3V
3.3V
0.1 mF
26
27
LF_REF
LF_CP
LMH0050
500Ö
1 kÖ
1 kÖ
32
3
SDA
GPIO_0
GPIO_1
GPIO_2
4
33
34
SCK
11
SMB_CS
6
DVB_ASI
LOCK
31
30
19, 20
DNC
RESET
Figure 15. Typical LMH0050 CML Application Circuit
SERIAL JITTER OPTIMIZATION
The SER is capable of very low jitter operation, however it is dependent on the TXCLK provided by the host in
order to operate, and depending on the quality of the TXCLK provided, the SER output jitter may not be as low
as it could be.
The SER includes circuitry to filter out any TXCLK jitter at frequencies above 1MHz (see Figure 16), however, for
frequencies below 100 kHz, any jitter that is in the TXCLK is passed directly through to the serialized output.
In most cases, passing the TXCLK through the FPGA will add high frequency noise to the signal, which will be
filtered out by the SER, resulting in a clean output, however for better jitter performance, it is best to minimize the
noise that is on the TXCLK that is provided to the SER. This can be done by careful routing of the CLK signals,
both within the FPGA and on the board.
Very clean clocks can be derived from video reference signals through the use of the LMH1981 Sync Separator
and the LMH1982 Clock Generator products from Texas Instruments. These products allow low jitter video
frequency clocks to be generated either independently, or phase locked to a video reference signal.
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2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
1
10
100
1000
10000 100000
JITTER FREQUENCY (kHz)
Figure 16. SER Jitter Transfer Function
Register Descriptions
Table 2 provides details on the device's configuration registers.
Table 2. SER Register Detail Table
ADD
'h
Name
Bits
Field
R/W
Default
Description
00
device_identification The seven MSBs of this register define the SMBus address for the device – the default value is 0x57'h,
but this may be overwritten. The LSB of this register must always be ‘0’ Note that since the address is
shifted over by 1 bit, some systems may address the 57'h as AE'h.
7:1
0
device id
Reserved
r/w
57'h
0'b
SMBus device ID
01
reset
If a ‘1’ is written to bit 0 (LSB) of this register the device will do a soft reset, restoring it’s internal state to
the same as at powerup except device_id register. Once the reset operation is complete, the value in
this register is reset to ‘0’
Bit 4 of this register has a default of 0, if a ‘1’ is written to this location it will disable the analog output
buffer of the device, allowing for some power savings.
7:5
4
Reserved
Analog Dis
Reserved
sw_rst
r/w
r/w
0'b
0'b
Disables Analog
software reset
3:1
0
02
GPIO_0
Configuration
This register configures GPIO_0. Note, if this pin is to be used as an input, then the output must be TRI-
STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4
GPIO_0_mode[3:0]
r/w
0000'b
0000: GPout register
0011: TXCLK LOS
0100: TXCLK Detect
0110: Power On Reset
all others: reserved
3:2
GPIO_0_ren[1:0]
r/w
01'b
00: pullup and pulldown disabled
01: pulldown enabled
10: pullup enabled
11: Reserved
1
0
GPIO_0_sleepz
GPout0 enable
r/w
r/w
0'b
1'b
0: input buffer disabled
1: input buffer enabled
0: output TRI-STATE
1: output enabled
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Table 2. SER Register Detail Table (continued)
ADD
'h
Name
Bits
Field
R/W
Default
Description
03
GPIO_1
Configuration
This register configures GPIO_1. Note, if this pin is to be used as an input, then the output must be TRI-
STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4
GPIO_1_mode[3:0]
r/w
0000'b
0000: Power On Reset
0001: GPout register
0010: pll lock
0100: Data LOS [0]
0101: Data LOS [1]
0110: Data LOS [2]
0111: Data LOS [3]
1000: Data LOS [4]
all others: reserved
3:2
GPIO_1_ren[1:0]
r/w
01'b
00: pullup and pulldown disabled
01: pulldown enabled
10: pullup enabled
11: Reserved
1
0
GPIO_1_sleepz
GPout1 enable
r/w
r/w
0'b
1'b
0: input buffer disabled
1: input buffer enabled
0: output in TRI-STATE mode
1: output enabled
04
GPIO_2
Configuration
This register configures GPIO_2. Note, if this pin is to be used as an input, then the output must be TRI-
STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4
GPIO_2_mode[3:0]
r/w
0000'b
0000: GPout register
0001: always on out
0010: parallel to serial clk out
0011: parallel clock output
0100: TXCLK Digital out
all others: reserved
3:2
GPIO_2_ren[1:0]
r/w
01'b
00: pullup and pulldown disabled
01: pulldown enabled
10: pullup enabled
11: Reserved
1
0
GPIO_2_sleepz
GPout2 enable
r/w
r/w
0'b
0'b
0: input buffer disabled
1: input buffer enabled
0: output TRI-STATEd
1: output enabled
05
06
GP INPUT
If any of the GPIO pins are configured as inputs, then reading from this register provides the values on
those input pins.
7:3
2
Reserved
r
r
r
input data on GPIO_2
input data on GPIO_1
input data on GPIO_0
1
0
GP OUTPUT
If the GPIO pins are configured as general purpose output pins, then writing to this register has the
effect of transferring the bits in this register to the output buffers of the appropriate GPIO pins.
7:3
2
Reserved
r/w
r/w
r/w
0'b
0'b
0'b
output data on GPIO_2
output data on GPIO_1
output data on GPIO_0
1
0
07–10
11
Reserved
DVB_ASI Idle_A
When in DVB-ASI mode, idle characters are inserted into the datastream when there is no valid data to
transmit. The idle character default is K28.5 but if desired, that can be redefined via this register pair.
7:0
r/w
BC'h
K28.5 Idle character used for DVB_ASI
12
DVB_ASI Idle_B
Reserved
DVB-ASI mode, idle character LSBs
7:2
1:0
Reserved
r/w
01'b
K28.5 Idle character used for DVB_ASI
13–1C
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LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013
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Table 2. SER Register Detail Table (continued)
ADD
'h
Name
Bits
Field
R/W
Default
Description
1D
Device Type
Reading from this register will return an 8 bit value which indicates which product from the SER family is
being addressed
7:0
Device
r
xx1xxx00 for the LMH0340
xx1xxx01 for the LMH0040
xx1xxx10 for the LMH0070
xx0xxx01 for the LMH0050
1E-20
21
Reserved
Mode
This register returns the mode that the device is operating in.
7:2
1:0
Reserved
r/w
11 = DVB ASI mode
01,10, 00 = SDI mode
22
DVB_ASI Override
In normal operation, the DVB_ASI mode is selected via the external pin. By setting the 0 bit in this
register, the function of this pin is overridden, and the mode is set via register 21'h instead. After setting
this bit, a channel reset must be executed via reg 0x26h, bit 7
7:1
0
Reserved
r/w
0'b
1: contents of register 21h will override
the DVB_ASI pin
0: Pin control
23
24
Reserved
LVDS Clock Delay
Bypass
This register selects of the TXCLK delay adjust is enabled or bypassed.
7
r/w
0'b
1: Bypasses TXCLK delay
0: Delay Enabled
6:0
Reserved
25
26
Reserved
Powerdown
Individual bits from this register can power down different parts of the SER – to place the part into a low
power standby mode, write a ‘0’ to this register.
7
channel reset
r/w
0'b
Used to reset the channel, needed when
changing between DVB_ASI mode and
normal operating mode via SMBus
6:0
Powerdown
r/w
0x3Fh
for normal operation, write x011 1111b to
this register. For low power mode write
x100 0000b to the register.
27
Event Disable
The SER keeps counts of various types of events. These include FIFO over/underflows, and loss of the
input signals or clocks. This register allows the user to mask these errors from being counted.
7:5
4
Reserved
PLL_CLK_disable
r/w
r/w
0'b
0'b
0'b
0'b
0'b
1: Clock Error disabled
0: Clock Errors counted
3
2
1
0
fifo_error_disable
1: FIFO Errors ignored
0: FIFO Errors counted
TXCLK_detect_disable r/w
1: TXCLK Detect Errors ignored
0: TXCLK Detect Errors counted
CLK_LOS_disable
Data_LOS_disable
r/w
r/w
1: CLK_LOS Errors ignored
0: CLK_LOS Errors counted
1: Data_LOS Errors ignored
0: Data_LOS Errors counted
28
LVDS LOS Override These bits are used to force the LOS indicator regardless of the input signal level on the LVDS pins.
Operation
7:2
1
Reserved
LVDS Preset LOS
r/w
0'b
LVDS Preset LOS
1: Forces LOS to be Low
0: normal mode
0
LVDS Reset LOS
r/w
0'b
LVDS Reset LOS
(has priority over Preset)
1: Forces LOS to be High
0: normal mode
22
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com
SNLS271I –APRIL 2007–REVISED APRIL 2013
Table 2. SER Register Detail Table (continued)
ADD
'h
Name
Bits
Field
R/W
Default
Description
29
LOS Status
Reading the LOS status register will provide a byte which has six bits which represent the presence or
absence of a signal at each of the LVDS inputs to the SER.
7:6
5
Reserved
LOS_CLK
r
r
0'b
0'b
1: No clock present on TXCLK
0: Clock present
4:0
LOS_Data
1:No data present
0: Data Present(one bit per TX channel)
2A
Event Status
The event status register has two user readable bits which indicate if the device is locked, and if there is
a signal present on the TXCLK input.
7:4
3
Reserved
TXCLK_detect
r
r
0'b
0'b
1: TXCLK detected
0: TXCLK not detected
2
PLL_lock
Reserved
1: PLL locked
0: PLL not locked
1:0
2B-2D
2E
Reserved
Reverse Bit Order
This bit can be used to reverse the serialization order, however it will only work properly when the device
is NOT in DVB_ASI mode
7
6
Reserved
Reverse Bit Order
r/w
0'b
1: reverses serialization order
0: normal order
5:0
Reserved
2F
30
Reserved
CLK_Delay
The three msbs from this register are used to insert a programmable delay into the TXCLK path, if the
host FPGA does not provide adequate setup and hold times for the SER, this register can be used to
shift the window in 125ps increments.
7:5
TCLK Delay
r/w
011'b
000'b is minimum delay setting, 111'b is
maximum delay setting, each step is
approx 125ps
4:0
Reserved
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMH0040SQ/NOPB
LMH0040SQE/NOPB
LMH0040SQX/NOPB
LMH0050SQ/NOPB
LMH0050SQE/NOPB
LMH0050SQX/NOPB
LMH0070SQ/NOPB
LMH0070SQE/NOPB
LMH0070SQX/NOPB
LMH0340SQ/NOPB
LMH0340SQE/NOPB
LMH0340SQX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
48
48
48
48
48
48
48
48
48
48
48
48
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
LMH0040
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
250
2500
1000
250
Green (RoHS
& no Sb/Br)
LMH0040
LMH0040
LMH0050
LMH0050
LMH0050
LMH0070
LMH0070
LMH0070
L0340
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
1000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
1000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
L0340
2500
Green (RoHS
& no Sb/Br)
L0340
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0040SQ/NOPB
LMH0040SQE/NOPB
LMH0040SQX/NOPB
LMH0050SQ/NOPB
LMH0050SQE/NOPB
LMH0050SQX/NOPB
LMH0070SQ/NOPB
LMH0070SQE/NOPB
LMH0070SQX/NOPB
LMH0340SQ/NOPB
LMH0340SQE/NOPB
LMH0340SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
48
48
48
48
48
48
48
48
48
48
48
48
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2500
1000
250
2500
1000
250
2500
1000
250
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0040SQ/NOPB
LMH0040SQE/NOPB
LMH0040SQX/NOPB
LMH0050SQ/NOPB
LMH0050SQE/NOPB
LMH0050SQX/NOPB
LMH0070SQ/NOPB
LMH0070SQE/NOPB
LMH0070SQX/NOPB
LMH0340SQ/NOPB
LMH0340SQE/NOPB
LMH0340SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
RHS
48
48
48
48
48
48
48
48
48
48
48
48
1000
250
367.0
213.0
367.0
367.0
213.0
367.0
367.0
213.0
367.0
367.0
213.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
38.0
55.0
38.0
38.0
55.0
38.0
38.0
55.0
38.0
38.0
55.0
38.0
2500
1000
250
2500
1000
250
2500
1000
250
2500
Pack Materials-Page 2
MECHANICAL DATA
RHS0048A
SQA48A (Rev B)
www.ti.com
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