LMG3411R150RWHR [TI]

具有集成驱动器和逐周期过流保护功能的 600V 150mΩ GaN | RWH | 32 | -40 to 150;


型号：	LMG3411R150RWHR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成驱动器和逐周期过流保护功能的 600V 150mΩ GaN \| RWH \| 32 \| -40 to 150 驱动驱动器
文件：	总30页 (文件大小：1613K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

具有集成驱动器和保护功能的 LMG341xR150 600V 150mΩ GaN

1 特性

2 应用

•

TI GaN 工艺通过了实际应用硬开关任务剖面可靠

性加速测试

•

高密度工业电源和消费类电源

用于笔记本电脑、平板电脑、电视机、机顶盒和打

印机的高密度交流/直流适配器

•

支持高密度电源转换设计

•

光伏逆变器

–

与共源共栅或独立 GaN FET 相比具有卓越的系

统性能

工业电机驱动

–

低电感 8mm x 8mm QFN 封装简化了设计和布

局

3 说明

–

可调节驱动强度确保开关性能和 EMI 控制

数字故障状态输出信号

LMG341xR150 GaN 功率级具有集成驱动器和保护功

能，可让设计人员在电力电子系统中实现更高水平的功

率密度和效率。LMG341x 的固有优势超越硅

MOSFET，包括超低输入和输出电容值、可将开关损

耗降低 80% 的零反向恢复以及可降低 EMI 的低开关节

点振铃。这些优势支持诸如图腾柱 PFC 之类的密集高

效拓扑。

仅需 +12V 非稳压电源

•

集成栅极驱动器

–

零共源电感

20ns 传播延迟确保 MHz 级工作频率

工艺经过调整的栅极偏置电压确保可靠性

25V/ns 至 100V/ns 的用户可调节压摆率

逐周期过流保护

LMG341xR150 通过集成一系列独特的特性提供了传

统共源共栅 GaN 和独立 GaN FET 的智能替代产品，

以简化设计、最大限度地提高可靠性并优化任何电源的

性能。集成式栅极驱动器支持 100V/ns 开关（Vds 振

铃几乎为零），低于 100ns 的限流可自行防止意外击

穿事件，过热关断可防止热逃逸，而且系统接口信号可

提供自监控功能。

强大的保护

–

无需外部保护组件

过流保护，响应时间低于 100ns

压摆率抗扰性高于 150V/ns

瞬态过压抗扰度

过热保护

器件信息⁽¹⁾

针对所有电源轨的 UVLO 保护

器件型号

封装

封装尺寸（标称值）

•

器件选项：

LMG341xR150

QFN (32)

8.00mm x 8.00mm

–

LMG3410R150：锁存过流保护

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

LMG3411R150：逐周期过流保护

简化方框图

高于 100V/ns 时的开关性能

Direct-Drive

Slew Rate

600 V

GaN

R_DRV

V_DD

VNEG

Current

LDO, OCP, OTP,

BB UVLO

5 V

FAULT

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNOSD91

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

9.1 Application Information............................................ 12

9.2 Typical Application ................................................. 13

9.3 Paralleling GaN Devices ......................................... 16

9.4 Do's and Don'ts ...................................................... 16

10 Power Supply Recommendations ..................... 17

10.1 Using an Isolated Power Supply........................... 17

10.2 Using a Bootstrap Diode ...................................... 17

11 Layout................................................................... 19

11.1 Layout Guidelines ................................................. 19

11.2 Layout Example .................................................... 20

12 器件和文档支持 ..................................................... 22

12.1 器件支持................................................................ 22

12.2 文档支持 ............................................................... 22

12.3 接收文档更新通知 ................................................. 22

12.4 社区资源................................................................ 22

12.5 商标....................................................................... 22

12.6 静电放电警告......................................................... 22

12.7 Glossary................................................................ 22

13 机械、封装和可订购信息....................................... 22

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 6

Parameter Measurement Information .................. 6

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ......................................... 9

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 12

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (March 2019) to Revision A

Page

•

已更改更改了“预告信息数据表”，添加了 LMG3410R150...................................................................................................... 1

LMG3411R150, LMG3410R150

www.ti.com.cn

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

5 Pin Configuration and Functions

RWH (QFN) PACKAGE

32 PINS

(Top View)

DRAIN

FAULT

PAD

30 RDRV

LPM

BBSW

SOURCE

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

BBSW

DRAIN

FAULT

NO.

Internal buck-boost converter switch pin. Connect an inductor from this point to source

Power transistor drain

1-11

Fault output, push-pull, active low

CMOS-compatible non-inverting gate drive input

5-V LDO output for external digital isolator.

LDO5V

LPM

Enables low-power-mode by connecting the pin to source

Power transistor source, die-attach pad, thermal sink, signal ground reference

SOURCE

12-16, 18-24

Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive

strength to control slew rate,

RDRV

VDD

VNEG

—

12-V power input, relative to source. Supplies 5-V rail and gate drive supply.

Negative supply output, bypass to source with 1-µF capacitor

Not connected, connect to source or leave floating.

—

PAD

Thermal Pad, tie to source with multiple vias.

(1) I = Input, O = Output, P = Power

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

V _DS

V_DS,tr

V _DD

V _IN

Drain-Source Voltage

Transient Drain-Source Voltage

Supply Voltage

600

800

(2)

–0.3

-0.3

–55

–40

IN, LPM Pin Voltage

Storage Temperature

Operating Temperature

5.5

T _STG

T _J

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) <1% duty cycle, <1us, for 1M pulses

6.2 ESD Ratings

VALUE

UNIT

(1)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

±1000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins

±250

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

480

UNIT

V_DS

V_DD

Drain-Source Voltage

Supply Voltage

9.5

DC Drain-Source Current (T_j=125℃)

I_DS

V_IN

IN, LPM Pin Voltage

I_+5V

LDO External Load Current

kΩ

µH

µF

°C

R_DRV

L_DCDC

C_DCDC

T_J

Slew rate control resistor

150

DC-DC buck-boost converter output inductor

DC-DC buck/boost converter output capacitor

Operating Temperature

-40

125

LMG3411R150, LMG3410R150

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

6.4 Thermal Information

LMG3410R150

(1)

THERMAL METRIC

RWH (QFN)

UNIT

32 PINS

R _θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

5.3

°C/W

R _θJC(top)

R _θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, 9.5 V < V_DD< 18 V, LPM = 5 V, V_NEG= -14 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GaN POWER

TRANSISTOR

T_J= 25°C

150

235

R_DS,ON

On-state Resistance

mΩ

T_J= 125°C

IN = 0 V, I_SD= 0.1 A

IN = 0 V, I_SD= 3 A

Third-quadrant mode source-drain

voltage

V_SD

TBD

C_oss

GaN output capacitance

IN = 0 V, V_DS= 400 V, f_SW= 250 kHz

Effective output capacitance, energy

C_oss,er

IN = 0 V, V_DS=0-400 V

Effective output capacitance, time

C_oss,tr

I_D= 3 A, IN = 0 V, V_DS= 0-400 V

Q_rr

Reverse recovery charge

Drain leakage current

V_R= 400 V, I_SD= 3 A, dI_SD/dt = 1 A/ns

Vds=600V, T_J= 25°C

I_DSS

DRIVER SUPPLY

Quiescent current, ultra-low-power

Vds=600V, T_J= 125°C

I_VDD,LPM

V_LPM= 0 V, V_DD= 12 V

µA

mode

Transistor held off

transistor held on

0.5

I_VDD,Q

Quiescent current (average)

V_DD= 12 V, f_SW= 500 KHz, R_DRV=40

kΩ, 50% duty cycle

I_VDD,op

Operating current

V_+5V

5V LDO output voltage

Negative Supply

V_DD= 12 V

4.7

5.3

V_NEG

15-mA load current

-13.9

BUCK BOOST

CONVERTER

I_OUT= 15 mA, V_IN= 12 V, V_OUT= -14

I_DCDC,PK

Peak inductor current

250

200

350

ΔV_NEG

DC-DC output ripple voltage, pk-pk

C_NEG= 1 µF, I_OUT= 15 mA

DRIVER INPUT

Input pin, LPM pin, logic high

threshold

V_IH

TBD

V_IL

Input pin, LPM pin, low threshold

Input pin, LPM pin, hysteresis

Input pull-down resistance

0.8

V_HYST

R_IN,L

R_LPM

0.8

150

kΩ

LPM pin pull-down resistance

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

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Electrical Characteristics (continued)

over operating free-air temperature range, 9.5 V < V_DD< 18 V, LPM = 5 V, V_NEG= -14 V (unless otherwise noted)

PARAMETER

UNDERVOLTAGE LOCKOUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DD,(ON)

V_DD,(OFF)

ΔV_DD,UVLO

FAULT

I_trip

V_DDturnon threshold

V_DDturnoff threshold

UVLO Hysteresis

Turn-on voltage

9.1

8.5

Turn-off voltage

trip point

550

Current Fault Trip Point

Temperature Trip Point

Temperature Trip Hysteresis

165

T_trip

°C

T_tripHys

6.6 Switching Characteristics

over operating free-air temperature range, 9.5 V < V_DD< 18 V, V_NEG= -14 V, V_BUS= 400 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GaN FET

R_DRV= 15 kΩ, I_L= 3 A

100

dv/dt

Turn-on Drain Slew Rate

R_DRV= 55 kΩ, I_L= 3 A

V/ns

R_DRV= 150 kΩ, I_L= 3 A

turn on, I_L= 3 A, R_DRV= 15 kΩ

Δdv/dt

dv/dt

Slew Rate Variation

Edge Rate Immunity

Drain dv/dt, device remains off

inductor-fed, max di/dt = 10 A/ns

150

600

V/ns

STARTUP

t_START

Time until gate responds to IN C_NEG

= 1 µF, C_LDO= 0 µF

Startup Time, V_INrising above UVLO

Propagation delay, turn on

µs

DRIVER

t_pd,on

IN rising to I_DS> 1 A, V_DS= 100 V

R_DRV= 15 kΩ, V_NEG= -14 V

14.4

t_delay,on

t_VDS,ft

t_pd,off

Turn on delay time

VDS fall time

I_DS> 1 A to V_DS< 320 V, R_DRV= 15kΩ

V_DS= 320 V to V_DS= 80 V, I_D= 3 A

IN falling to V_DS> 10 V; I_D= 3 A

V_DS= 10 V to V_DS= 80 V, I_D= 3 A

V_DS= 80 V to V_DS= 320 V, I_D= 3 A

4.4

2.7

Propagation delay, turn off

Turn off delay time

VDS rise time

17.4

5.5

t_delay,off

t_VDS,rt

FAULT

t_curr

11.7

Current Fault Delay

Current Fault Blanking Time

Fault reset time

I_DS> I_THto FAULT low

µs

V_IN>V_IHto end of blanking,

RDRV=15kΩ

t_blank

t_reset

IN held low

250

350

500

7 Parameter Measurement Information

Switching Parameters

The circuit used to measure most switching parameters is shown in 图 1. The top LMG341xR150 in this circuit is

used to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device is the

active device; it is turned on to increase the inductor current to the desired test current. The bottom device is

then turned off and on to create switching waveforms at a specific inductor current. Both the drain current (at the

source) and the drain-source voltage is measured. The specific timing measurement is shown in 图 2. It is

recommended to use the half-bridge as double pulse tester. Excessive 3rd quadrant operation may over heat the

top LMG341xR150.

LMG3411R150, LMG3410R150

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

Parameter Measurement Information (接下页)

Slew

Rate

Direct-Drive

600 V

GaN

R_DRV

500 uH

V_DD

VNEG

LDO, OCP, OTP, Current

BB UVLO

5 V

FAULT

V_BUS

480 V

C_PCB

Slew

Rate

Direct-Drive

600 V

GaN

R_DRV

V_DD

V_DS

VNEG

LDO, OCP, OTP, Current

BB UVLO

5 V

FAULT

PWM input

图 1. Circuit Used to Determine Switching Parameters

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

Parameter Measurement Information (接下页)

50%

t_pd,off

t_pd,on

I_D

t_delay,on

t_delay,off

t_VDS,ft

t_VDS,rt

80%

V_DS

20%

图 2. Measurement to Determine Propagation Delays and Slew Rates

Turn-on Delays

The timing of the turn-on transition has three components: propagation delay, turn-on delay and fall time. The

first component is the propagation delay of the driver from when the input goes high to when the GaN FET starts

turning on (represented by 1 A drain current). The turn-on delay is the delay from when the FET starts turning on

to when the drain voltage swings down by 20 percent. Finally, the V_DSfall time is the time it takes the drain

voltage to slew between 80 percent and 20 percent of the bus voltage. The drive-strength resistor value has a

large effect on turn-on delay and V_DSfall time but does not affect the propagation delay significantly.

Turn-off Delays

The timing of the turn-off transition has three components: propagation delay, turn-off delay and rise time. The

first component is the propagation delay of the driver from when the input goes low to when the GaN FET starts

turning off. The turn-off delay is the delay from when the FET starts turning of (represented by the drain rising

above 10 V) to when the drain voltage swings up by 20 percent. Finally, the V_DSrise time is the time it takes the

drain voltage to slew between 20 percent and 80 percent of the bus voltage. The turn-off delays of the

LMG341xR150 are independent of the drive-strength resistor but the turn-off delay and the V_DSrise time are

heavily dependent on the load current.

Drain Slew Rate

The slew rate, measured in volts per nanosecond, is measured on the turn-on edge of the LMG341xR150. The

slew rate is considered over the V_DSfall time, where the drain falls from 80 percent to 20 percent of the bus

voltage. The drain slew rate is thus given by 60 percent of the bus voltage divided by the V_DSfall time. This drain

slew rate is dependent on the RDRV value and is only slightly affected by drain current.

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

8 Detailed Description

8.1 Overview

LMG341xR150 is a high-performance 600-V GaN transistor with integrated gate driver. The GaN transistor

provides ultra-low input and output capacitance and zero reverse recovery. The lack of reverse recovery enables

efficient operation in half-bridge and bridge-based topologies.

TI utilizes a Direct Drive architecture to control the GaN FET within the LMG341xR150. When the driver is

powered up, the GaN FET is controlled directly with the integrated gate driver. This architecture provides

superior switching performance compared with the traditional cascode approach.

The integrated driver solves a number of challenges using GaN devices. The LMG341xR150 contains a driver

specifically tuned to the GaN device for fast driving without ringing on the gate. The driver ensures the device

stays off for high drain slew rates up to 150 V/ns. In addition, the integrated driver protects against faults by

providing over-current and over-temperature protection. This feature can protect the system in case of a device

failure, or prevent a device failure in the case of a controller error or malfunction.

Unlike silicon MOSFETs, there is no p-n junction from source to drain in GaN devices. That is why GaN devices

have no reverse recovery losses. However, the GaN device can still conduct from source to drain in 3rd quadrant

of operation similar to a body diode but with higher voltage drop and higher conduction loss. 3rd quadrant

operation can be defined as follows; when the GaN device is turned off and negative current pulls the drain node

voltage to be lower than its source. The voltage drop across GaN device during 3rd quadrant operation is high;

therefore, it is recommended to operate with synchronous switching and keep the duration of 3rd quadrant

operation at minimum.

8.2 Functional Block Diagram

DRAIN

VDD

GaN

LDO

UVLO

(+5 V, VDD, VNEG)

LDO5V

FAULT

OCP

OTP

Level Shift

BBSW

LPM

Buck-Boost

Controller

VNEG

RDRV

SOURCE

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

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8.3 Feature Description

The LMG341xR150 includes numerous features to provide increased switching performance and efficiency in

customers' applications while providing an easy-to-use solution.

8.3.1 Direct-Drive GaN Architecture

The LMG341xR150 utilizes a series FET to ensure the GaN module stays off when V_DDis not applied. When this

FET is off, the gate of the GaN transistor is held within a volt of the FET's source. As the silicon FET blocks the

drain voltage, the V_GSof the GaN transistor decreases until it passes its threshold voltage. Then, the GaN

transistor turns off and blocks the remaining drain voltage.

When the LMG341xR150 is powered up, the internal buck-boost converter generates a negative voltage (V_NEG

)

that is sufficient to directly turn off the GaN transistor. In this case, the silicon FET is held on and the GaN

transistor is gated directly with the negative voltage. During operation, this removes the switching loss of silicon

FET.

8.3.2 Internal Buck-Boost DC-DC Converter

An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN

device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,

the converter remains in discontinuous-conduction mode, but may enter continuous-conduction mode during

startup and overload conditions. The converter is controlled internally and requires only a single surface-mount

inductor and output bypass capacitor. For recommendations on the required passives, see Buck-Boost Converter

Design.

8.3.3 Internal Auxiliary LDO

An internal low-dropout regulator is provided to supply external loads, such as digital isolators for the high-side

drive signal. It is capable of delivering up to 5 mA to an external load. A bypass capacitor with 0.1 µF typical is

recommended. If the digital isolator or the LDO output is not used, LMG341xR150 can start up faster with no

bypass LDO capacitor.

8.3.4 Fault Detection

The GaN driver includes built-in over-current protection (OCP), over-temperature protection (OTP) and under

voltage lockout (UVLO).

8.3.4.1 Over-current Protection

The OCP circuit monitors the LMG341xR150's drain current and compares that current signal with an internally-

set limit. Upon detection of the over-current, the family of GaN FETs has two optional protection actions: 1)

latched overcurrent protection; and 2) cycle-by-cycle overcurrent protection.

LMG3410R150 provides 1) latched OCP option, by which the FET is shut off and held off until the fault is reset

by either holding the IN pin low for more than 350 microseconds or removing power from VDD.

LMG3411R150 provides 2) cycle-by-cycle OCP option. In this mode, the GaN FET is shut off and held off when

overcurrent happens but the output fault signal will clear after the input PWM goes low. In the next cycle, the

FET can turn on as normal. The cycle-by-cycle function can be used in cases where steady state operation is

below the OCP level but transient response can still reach high current, while the circuit operation cannot be

paused. It also prevents the power stage from overheating by having overcurrent induced conduction loss.

During cycle-by-cycle operation, after the current reaches the upper limit but the PWM input is still high, the load

current can flow through the third quadrant of the other FET of a half-bridge with no synchronous rectification.

The extra high negative voltage drop (–6V to –8V) from drain to source could lead to high third quadrant loss,

similar to dead time loss but with much longer time. An operation scheme of cycle-by-cycle current limitation is

shown as 图 3.Therefore, it is critical to design the control scheme to make sure the number of switching cycles

in cycle-by-cycle mode is limited, or to change PWM input based on the fault signal to shorten the time in third

quadrant conduction mode of the power stage.

OCP circuit has a 20ns typical blanking at slew rate of 100V/ns to prevent false triggering during switch node

transitions. The blanking time increases with respect to lower slew rates accordingly. This fast response OCP

circuit protects the GaN device even under a hard short-circuit condition.

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

Feature Description (接下页)

Current limit

Inductor

current

V_SW

Input PWM

FAULT

图 3. Cycle-by-cycle OCP Operation

8.3.4.2 Over-Temperature Protection and UVLO

The over-temperature protection circuit measures the temperature of the driver die and trips if the temperature

exceeds the over-temperature threshold (typically 165 °C). Upon an over-temperature condition, the GaN device

is held off until temperature falls below the hysteresis limit, typically 15 degrees below the turn-off threshold.

The FAULT output is a push-pull output indicating the readiness and fault status of the driver. It is held low when

starting up until the safety FET is turned on. In an OCP or OTP fault condition, it is held low until the fault latches

are reset or fault is cleared. If the power supplies go below the UVLO thresholds, power transistor switching is

disabled and FAULT is held low until the power supplies recover.

8.3.5 Drive Strength Adjustment

To allow for an adjustable slew rate to control stability and ringing in the circuit, as well as an adjustment to pass

electro-magnetic compliance (EMC) standards, LMG341xR150 allows the user to adjust its drive strength. A

resistor is connected the RDRV pin and ground. The value of the resistor determines the slew rate of the device

during turn-on between 30V/ns and 100V/ns; The turn-off slew rate is dependent on the load current; therefore, it

is not controlled.

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

8.4 Device Functional Modes

8.4.1 Low-Power Mode

In some applications, it is important to reduce quiescent current during low power mode such as start up or burst.

The LPM pins reduces the quiescent current to support low power modes. When LPM is pulled low, the supply

current in the low-power mode is typically 80µA. Once this pin is pulled high, the buck-boost converter will start

up and LMG341xR150 will be ready to operate within 1 ms.

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMG341xR150 is a single-channel GaN power stage targeting high-voltage applications. It targets hard-

switched and soft-switched applications running from a 350V to 480V bus such as power-factor correction (PFC)

applications. As GaN devices such as the LMG341xR150 have zero reverse-recovery charge, they are well-

suited for hard-switched half-bridge applications, such as the totem-pole bridgeless PFC circuit. It is also well-

suited for resonant DC-DC converters, such as the LLC and phase-shifted full-bridge. As both of these

converters utilize the half-bridge building block, this section will describe how to use the LMG341xR150 in a half-

bridge configuration.

LMG3411R150, LMG3410R150

www.ti.com.cn

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

9.2 Typical Application

12V

600V

1uF

ISO_12V_H

VDD

HVBUS

ISO_RET_H

5V_H

DRAIN

5V_H

VCC1

VCC2

OUTA

OUTB

INC

AGND

22pF

LDO5V

49.9

0.1uF

Top_FET

INA

4.7uF

49.9

ISONC2

ISO_RET_H

IN_H

0.1uF

INB

68pF

FAULT_H

OUTC

EN1

ISONC1

ISONC3

EN2

68pF

AGND

5V_H

FAULT

LPM

SOURCE

GND1

GND2

ISO_RET_H

ISO7731DBQR

RDRV

BBSW

VNEG

AGND

SW_H

VM12V_H

10µH

15k 100V/ns

40.2k 60V/ns

15k

0.022µF

C10 C11

0.022µF 0.022µF

C12

C13

C14

1uF

0.047uF

PAD

ISO_RET_H

LMG3411R150RWHT

ISO_RET_H

12V

VDD

DRAIN

C15

4.7uF

5V_L

LDO5V

C16

0.1uF

ISO_RET_L

Bot_FET

IN_L

49.9

FAULT_L

FAULT

LPM

SOURCE

5V_L

15k 100v/ns

40.2k 60V/ns 15k

RDRV

BBSW

VNEG

SW_L

C17

68pF

C18

22pF

10µH

VM12V_L

C19

1uF

ISO_RET_L

PAD

LMG3411R150RWHT

ISO_RET_L

AGND

图 4. Typical Half-Bridge Application

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

9.2.1 Design Requirements

This design example is for a hard-switched boost converter which is representative of PFC applications. The

system parameters considered are as follows.

表 1. Design Parameters

DESIGN PARAMETER

Input Voltage

EXAMPLE VALUE

200 VDC

400 VDC

5 A

Output Voltage

Input (Inductor) Current

Switching Frequency

100 kHz

9.2.2 Detailed Design Procedure

In high-voltage power converters, correct circuit design and PCB layout is essential to obtaining a high-

performance and even functional power converter. While the general procedure for designing a power converter

is out of the scope of this document, this datasheet describes how to utilize the LMG341xR150 to build efficient,

well-behaved power converters.

9.2.2.1 Slew Rate Selection

The LMG341xR150 supports slew rate adjustment through connecting a resistor from RDRV to source. The

choice of RDRV will control the slew rate of the drain voltage of the device between approximately 25 V/ns and

100 V/ns. The slew rate adjustment is used to control the following aspects of the power stage:

•

Switching loss in a hard-switched converter

Radiated and conducted EMI generated by the switching stage

Interference elsewhere in the circuit coupled from the switch node

Voltage overshoot and ringing on the switch node due to power loop inductance and other parasitics

When increasing the slew rate, the switching power loss will decrease, as the portion of the switching period

where the switch simultaneous conducts high current while blocking high voltage is decreased. However, by

increasing the slew rate of the device, the other three aspects of the power stage get worse. Following the

design recommendations in this datasheet will help mitigate the system-related challenges related to high slew

rate. Ultimately, it is up to the power designer to ensure the chosen slew rate provides the best performance in

his or her end application.

9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply

Using a bootstrap supply for the high-side LMG341xR150 places additional constraints on the startup of the

circuit. Before the high-side LMG341xR150 functions correctly, its VDD, LDO5V and VNEG power supplies must

start up and be functional. Prior to the device powering up, the GaN device operates in cascode mode with

reduced performance. In particular, under high drain slew rate (dv/dt), the transistor can conduct to a small extent

and cause additional power dissipation. The correct startup procedure for a bootstrap-supplied half-bridge

depends on the circuit used.

In a buck converter without pre-bias, where the initial output voltage is zero, the startup procedure is

straightforward. In this case, before switching begins, turn on the low-side device to allow the high-side bootstrap

transistor to charge up. When the FAULT signal goes high, the high-side device has powered up completely, and

normal switching can begin.

In a boost converter or a buck converter with a pre-biased output, it is necessary to operate the circuit in

switching PWM mode while the high-side LMG341xR150 is powering up. With a boost converter, if the low-side

device is held on, the power inductor current will likely run away and the inductor will saturate. To start up a

boost converter, the duty cycle has to be very low and gradually increase to charge the output to the desired

value without the inductor current reaching saturation. This pulse sequence can be performed open-loop or using

a current-mode controller. This startup mode is standard for boost-type converters.

LMG3411R150, LMG3410R150

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

However, with the LMG341xR150, during the boost converter startup, significant shoot-through current can occur

for high drain slew rates while starting up. This shoot-through current is approximately 1.25 µC per switching

event at 50 V/ns, and is comparable to a reverse-recovery event. If this shoot-through current is undesirable, the

drain slew rate of the low-side device must be reduced during startup. In 图 4, the FAULT output from the high-

side device is used to gate MOSFET Q1. When FAULT from the high-side is high, once the device is powered

up, Q1 turns on and reduces the effective resistance connected to RDRV on the low-side LMG341xR150. With

this circuit, the dv/dt of the low-side device can be held low to reduce power dissipation and reduce ringing

during high-side startup, but then increase to reduce switching loss during normal operation.

9.2.2.2 Signal Level-Shifting

As the LMG341xR150 is a single-channel power stage, two devices are used to construct a half-bridge

converter, such as the one shown in 图 4. A high-voltage level shifter or digital isolator must be used to provide

signals to the high-side device. Using an isolator for the low-side device is optional but will equalize propagation

delays between the high-side and low-side signal path, as well as providing the ability to use different grounds for

the power stage and the controller. If an isolator is not used on the low-side device, the control ground and the

power ground must be connected at the LMG341xR150, as described in Layout Guidelines, and nowhere else on

the board. With the high current slew rate of the fast-switching GaN device, any ground-plane inductance

common with the power path may cause oscillation or instability in the power stage without the use of an isolator.

Choosing a digital isolator for level-shifting is an important consideration for fault-free operation. Because GaN

switches very quickly, exceeding 50 V/ns in hard-switching applications, isolators with high common-mode

transient immunity (CMTI) are required. If an isolator suffers from a CMTI issue, it can output a false pulse or

signal which can cause shoot-through. In addition, choosing an isolator that is not edge-triggered can improve

circuit robustness. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause

circuit malfunctioning.

On/off keyed isolators are preferred, such as the TI ISO78xxF series, as a high CMTI event would only cause a

short (few nanosecond) false pulse, which can be filtered out. To allow for filtering of these false pulses, an R-C

filter at the driver input is recommended to ensure these false pulses can be filtered. If issues are observed,

values of 1 kΩ and 22 pF can be used to filter out any false pulses.

9.2.2.3 Buck-Boost Converter Design

The Buck-boost converter generates the negative voltage necessary to turn off the direct-drive GaN FET. While it

is controlled internally, it requires an external power inductor and output capacitor. The converter is designed to

use a 10 µH inductor and a 1 µF output capacitor. As the peak current of the buck-boost is limited to less than

350 mA, the inductor chosen must have a saturation current above 350 mA. A TDK Corporation

VLS201610HBX-100M-1 10 µH SMT inductor in a 0806 package is recommended. This inductor is connected

between the BBSW pin and ground. A 1 µF, 25V 0603 bypass capacitor is required between V_NEGand ground.

Due to the voltage coefficient of X7R capacitors, a 1 µF capacitor will provide the required minimum 0.45 µF

capacitance when operating.

9.2.3 Application Curves

V_DS(50 V/div)

I_D(2.5 A/div)

V_DS(50 V/div)

I_D(1.25 A/div)

V_OUT= 400V

I_L= 5 A

R_DRV= 40 kW

V_BUS= 400 V

I_L= 5 A

R_DRV= 40 kW

Time (5 ns/div)

D006

D007

图 5. Turn-on Waveform in Application Example

图 6. Turn-off Waveform in Application Example

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

9.3 Paralleling GaN Devices

LMG341xR150s can be paralleled directly in soft-switching applications. As for hard-switching applications, small

decoupling inductors should be utilized to parallel the two half-bridge LMG341xR150s. This type of setup

prevents current and thermal unbalances among the parallel devices due to any propagation delay and gate-

source threshold voltage mismatches, and other factors.

9.4 Do's and Don'ts

The successful use of GaN devices in general and the LMG341xR150 in particular depends on proper use of the

device. When using the LMG341xR150, DO:

•

Read and fully understand the datasheet, including the application notes and layout recommendations

Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance

Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance

Use the proper size decoupling capacitors and locate them close to the IC as described in the Layout

Guidelines section

•

Use a signal isolator to supply the input signal for the low side device. If not, ensure the signal source is

connected to the signal GND plane which is tied to the power source only at the LMG341xR150 IC

Use the FAULT pin to determine power-up state and to detect over-current and over-temperature events and

safely shut off the converter.

To avoid issues in your system when using the LMG341xR150, DON'T:

•

Use a single-layer or two-layer PCB for the LMG341xR150 as the power-loop and bypass capacitor

inductances will be excessive and prevent proper operation of the IC

•

Reduce the bypass capacitor values below the recommended values

Allow the device to experience drain transients above 600 V as they may damage the device

Allow significant third-quadrant conduction when the device is OFF or unpowered, which may cause

overheating. Self-protection feature cannot protect the device in this mode of operation

•

Ignore the FAULT pin output.

LMG3411R150, LMG3410R150

www.ti.com.cn

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

10 Power Supply Recommendations

The LMG341xR150 requires an unregulated 12-V supply to power its internal driver and fault protection circuitry.

The low-side supply can be supplied from the local controller supply. The high-side device's supply must come

from an isolated supply or bootstrap supply.

10.1 Using an Isolated Power Supply

Using an isolated power supply to power the high-side device has the advantage that it will work regardless of

continued power-stage switching or duty cycle. It can also power the high-side device before power-stage

switching begins, eliminating the power-loss concern of switching with an unpowered LMG341xR150 (see

Startup and Slew Rate with Bootstrap High-Side Supply for details). Finally, a properly-selected isolated supply

will contribute fewer parasitics to the switching power stage, increasing power-stage efficiency. However, the

isolated power supply solution is larger and more expensive than the bootstrap solution.

The isolated supply can be constructed from an output of a flyback or FlyBuck™ converter, or using an isolated

power module. When using an unregulated supply, ensure that the input to the LMG341xR150 does not exceed

the maximum supply voltage. If necessary, a 18 V zener to clamp the VDD voltage supplied by the isolated

power converter. Minimizing the inter-winding capacitance of the isolated power supply or transformer is

necessary to reduce switching loss in hard-switched applications.

10.2 Using a Bootstrap Diode

When used in a half-bridge configuration, a floating supply is necessary for the top-side switch. Due to the

switching performance of LMG341xR150, a transformer-isolated power supply is recommended. With caution, a

bootstrap supply can be used with the recommendations in this section.

10.2.1 Diode Selection

LMG341xR150 has no reverse-recovery charge and little output charge. Hard-switched circuits using

LMG341xR150 also exhibit high voltage slew rates. A compatible bootstrap diode must exhibit low output charge

and, if used in a hard-switching circuit, very low reverse-recovery charge.

For soft-switching applications, the MCC UFM15PL ultra-fast silicon diode can be used. The output charge of 2.7

nC is small in comparison with the switching transistors, so it will have little influence on switching performance.

In a hard-switching application, the reverse recovery charge of the silicon diode may contribute an additional loss

to the circuit.

For hard-switched applications, a silicon carbide diode can be used to avoid reverse-recovery effects. The Cree

C3D1P7060Q SiC diode has an output charge of 4.5 nC and a reverse recovery charge of about 5 nC. There will

be some losses using this diode due to the output charge, but these will not dominate the switching stage’s

losses.

10.2.2 Managing the Bootstrap Voltage

In a synchronous buck, totem-pole PFC, or other converter where the low-side switch occasionally operates in

third-quadrant mode, it is important to consider the bootstrap supply. During the dead time, the bootstrap supply

charges through a path that includes the third-quadrant voltage drop of the low-side LMG341xR150. This third-

quadrant drop can be large, which may over-charge the bootstrap supply in certain conditions. The V_DDsupply of

LMG341xR150 must not exceed 18 V in bootstrap operation.

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

Using a Bootstrap Diode (接下页)

DRAIN

V_DD

V_F

SOURCE

DRAIN

V_DD

V_F

SOURCE

图 7. Charging Path for Bootstrap Diode

The recommended bootstrap supply connection includes a bootstrap diode and a series resistor with an optional

zener as shown in 图 8. The series resistor limits the charging current at startup and when the low-side device is

operating in third-quadrant mode. This resistor must be chosen to allow sufficient current to power the

LMG341xR150 at the desired operating frequency. At 100 kHz operation, a value of approximately 5.1 ohms is

recommended. At higher frequencies, this resistor value should be reduced or the resistor omitted entirely to

ensure sufficient supply current.

DRAIN

+12 V

V_DD

V_F

SOURCE

图 8. Suggested Bootstrap Regulation Circuit

Using a series resistor with the bootstrap supply will create a charging time constant in conjunction with the

bypass capacitance on the order of a microsecond. When the dead time, or third-quadrant conduction time, is

much lower than this time constant, the bootstrap voltage will be well-controlled and the optional zener clamp in

图 8 will not be necessary. If a large deadtime is needed, a 14-V zener diode can be used in parallel with the V_DD

bypass capacitor to prevent damaging the high-side LMG341xR150.

10.2.3 Reliable Bootstrap Start-up

In some applications such as boost converter, the low side LMG341xR150 may need to start switching at high

frequency while high side LMG341xR150 is not fully biased. If low side GaN device turn-on speed is adjusted to

achieve high slew rate, the high side GaN device can turn-on unintentionally as high dv/dt can charge high side

GaN device drain to source capacitance. For reliable operation, the slew rate should be slowed down to 30 V/ns

by changing the resistance of RDRV pin of the low side LMG341xR150 until high side LMG341xR150's bias is

fully settled. This can be monitored through the FAULT output of high side LMG341xR150.

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ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

11 Layout

11.1 Layout Guidelines

The layout of the LMG341xR150 is critical to its performance and functionality. Because the half-bridge

configuration is typically used with these GaN devices, layout recommendations will be considered with this

configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the

layout to achieve suitable performance.

11.1.1 Power Loop Inductance

The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes

large di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic

interference (EMI) can be reduced, as well as reducing voltage stress on the devices.

This loop inductance is minimized by locating the power devices as close together as possible. The bus

capacitance is positioned in line with the two devices, either below the low-side device or above the high-side

device, on the same side of the PCB. The return path (PGND in this case) is located on the second layer on the

PCB in close proximity to the top layer. By using an inner layer and not the bottom layer, the vertical dimension

of the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus

capacitance carries the high-frequency switching current to the inner layer while minimizing impedance.

11.1.2 Signal Ground Connection

The LMG341xR150's SOURCE pin is also signal ground reference. The signal GND plane should be connected

to SOURCE with low impedance kelvin connection. In addition, the return path for the passives associated to the

driver (e.g. bypass capacitance) must be connected to the GND plane. In 图 9, local signal GND planes are

located on the second copper layer to act as the return for the local circuitry. The local signal GND planes are

isolated from the high-current SOURCE plane except the kelvin connection at the source pin through enough low

impedance vias.

11.1.3 Bypass Capacitors

The gate drive loop impedance must also be minimized to yield strong performance. Although the gate driver is

integrated on package, the bypass capacitance for the driver is placed externally on the PCB board. As the GaN

device is turned off to a negative voltage, the impedance of the negative source is included in the crucial turn-off

path. As the critical hold-off path passes through this external bypass capacitor attached to V_NEG, this capacitor

must be located close to the LMG341xR150. In the 图 9, V_NEGbypass capacitors C9 and C26 are located

immediately adjacent to the pins on the IC with a direct connection to the SOURCE pin.

The bypass capacitors for the input supply (C8 and C23) and the 5V regulator (C5 and C7) must also be located

immediately next to the IC with a close connection to the ground plane.

11.1.4 Switch-Node Capacitance

GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching

loss. To preserve this low switching loss, additional capacitance added to the output node must be minimized.

The PCB capacitance at the switch node can be minimized by following these guidelines:

•

Minimize overlap between the switch-node plane and other power and ground planes

Thin the GND return path under the high-side device somewhat while still maintaining a low-inductance path

Choose high-side isolator ICs and bootstrap diodes with low capacitance

Locate the power inductor as close to the power stage as possible

Power inductors should be constructed with a single-layer winding to minimize intra-winding capacitance

If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and

the power stage to effectively shield the power stage from the additional capacitance

•

If a back-side heat-sink is used, restrict the switch-node copper coverage on the bottom copper layer to the

minimum area necessary to extract the needed heat

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

Layout Guidelines (接下页)

11.1.5 Signal Integrity

The control signals to the LMG341xR150 must be protected from the high dv/dt that the GaN power stage

produces. Coupling between the control signals and the drain may cause circuit instability and potential

destruction. Route the control signals (IN, FAULT and LPM) over a ground plane located on an adjacent layer.

For example, in the layout in 图 9, all the signals are routed on the top layer directly over the signal GND plane

on the first inner copper layer.

The signals for the high-side device are often particularly vulnerable. Coupling between these signals and system

ground planes could cause issues in the circuit. Keep the traces associated with the control signals away from

drain copper. For the high-side level shifter, ensure no copper from either the input or output side extends

beneath the isolator or the device's CMTI may be compromised.

11.1.6 High-Voltage Spacing

Circuits using the LMG341xR150 involve high voltage, potentially up to 600V. When laying out circuits using the

LMG341xR150, understand the creepage and clearance requirements in your application and how they apply to

the power stage. Functional (or working) isolation is required between the source and drain of each transistor,

and between the high-voltage power supply and ground. Functional isolation or perhaps stronger isolation (such

as reinforced isolation) may be required between the input circuitry to the LMG341xR150 and the power

controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your

isolation requirements.

If a heatsink is used to manage thermal dissipation of the LMG341xR150, ensure necessary electrical isolation

and mechanical spacing is maintained between the heatsink and the PCB.

11.1.7 Thermal Recommendations

The LMG341xR150 is a lateral transistor grown on a Si substrate. The thermal pad is connected to the Source

node. The LMG341xR150 may be used in applications with significant power dissipation, for example, hard-

switched power converters. In these converters, cooling using just the PCB may not be sufficient to keep the part

at a reasonable temperature. To improve the thermal dissipation of the part, TI recommends a heatsink is

connected to the back of the PCB to extract additional heat. Using power planes and numerous thermal vias, the

heat dissipated in the LMG341xR150(s) can be spread out in the PCB and effectively passed to the other side of

the PCB. A heat sink can be applied to bare areas on the back of the PCB using an adhesive thermal interface

material (TIM). The soldermask from the back of the board underneath the heatsink can be removed for more

effective heat removal.

Please refer to the High Voltage Half Bridge Design Guide for LMG3410x Smart GaN FET application note for

more recommendations and performance data on thermal layouts.

11.2 Layout Example

Correct layout of the LMG341xR150 and its surrounding components is essential for correct operation. The

layout shown here reflects the power stage schematic in 图 4. It may be possible to obtain acceptable

performance with alternate layout schemes, however this layout has been shown to produce good results and is

intended as a guideline.

LMG3411R150, LMG3410R150

www.ti.com.cn

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

Layout Example (接下页)

图 9. Example Half-Bridge Layout

LMG3411R150, LMG3410R150

ZHCSJF9A –MARCH 2019–REVISED JUNE 2019

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

《LMG3411 智能 GaN FET 的高压半桥设计指南》应用手册。

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 商标

FlyBuck, E2E are trademarks of Texas Instruments.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2000

250

(1)

(2)

(3)

(4/5)

(6)

LMG3410R150RWHR

LMG3410R150RWHT

LMG3411R150RWHR

LMG3411R150RWHT

ACTIVE

VQFN

RWH

RoHS-Exempt

& Green

NIPDAU

Level-3-260C-168HRS

-40 to 150

LMG3410

Samples

R150

ACTIVE

RWH

RoHS-Exempt

& Green

NIPDAU

LMG3410

R150

RWH

2000

250

RoHS-Exempt

& Green

LMG3411

R150

RWH

RoHS-Exempt

& Green

LMG3411

R150

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jul-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMG3410R150RWHR

LMG3411R150RWHR

VQFN

RWH

2000

330.0

16.4

8.3

2.25

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMG3410R150RWHR

LMG3411R150RWHR

VQFN

RWH

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE OUTLINE

RWH0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

8.1

7.9

PIN 1 INDEX AREA

8.1

7.9

1.0

0.8

(0.2) TYP

SEATING PLANE

3.75 0.1

PKG

0.05

0.00

0.08 C

(2.75)

(0.65)

0.65

0.55

32X

4X 0.85

0.85

0.75

0.1

C A B

6.2 0.1

0.05

5.2

PKG SYMM

16X 0.65

PIN 1 ID

0.45

0.35

24X

0.1

C A B

0.05

0.65

0.55

0.1

4X 0.65

2X 1.3

C A B

0.05

4X 0.75

2X 2.85

4221569/D 08/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RWH0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.75)

(0.8) TYP

(1.875)

4X (0.8)

2X (1.05)

24X (0.4)

22X ( 0.2)

VIA

(7.6)

PKG SYMM

(6.2)

(0.595)

(1.19)

TYP

20X (0.65)

(0.4)

4X (0.85)

(0.8) TYP

(R0.05) TYP

(1.225)

4X (0.6)

PKG

PAD

2X (2.85)

4X (0.75)

(7.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221569/D 08/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

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EXAMPLE STENCIL DESIGN

RWH0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

(1.8)

(0.314)

SEE DETAIL A

24X (0.4)

(0.2)

TYP

4X (1.19)

(7.6)

PKG SYMM

(R0.05) TYP

20X (0.65)

10X (0.99)

4X (0.85)

10X (1.6)

4X (0.6)

4X (0.75)

2X (2.85)

(0.76)

(7.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:10X

METAL

PASTE

DETAIL A

4X, SCALE: 30X

4221569/D 08/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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LMG3411R150RWHR [TI]

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