LMC6482AI MDA [TI]
CMOS 双路轨到轨输入和输出运算放大器 | Y | 0 | -40 to 85;
| 型号： | LMC6482AI MDA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CMOS 双路轨到轨输入和输出运算放大器 | Y | 0 | -40 to 85 放大器 运算放大器 |
| 文件： | 总31页 (文件大小：2189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMC6482-MIL
SNOSD61 –JUNE 2017
LMC6482-MIL CMOS Dual Rail-to-Rail Input and Output Operational Amplifier
1 Features
3 Description
The LMC6482-MIL device provides a common-mode
range that extends to both supply rails. This rail-to-rail
performance combined with excellent accuracy, due
to a high CMRR, makes it unique among rail-to-rail
input amplifiers. The device is ideal for systems, such
as data acquisition, that require a large input signal
range. The LMC6482-MIL is also an excellent
upgrade for circuits using limited common-mode
range amplifiers such as the TLC272 and TLC277.
1
•
Typical Unless Otherwise Noted
•
Rail-to-Rail Input Common-Mode Voltage Range
(Ensured Over Temperature)
•
Rail-to-Rail Output Swing (Within 20-mV of Supply
Rail, 100-kΩ Load)
•
•
•
•
•
•
•
Ensured 3-V, 5-V, and 15-V Performance
Excellent CMRR and PSRR: 82 dB
Ultralow Input Current: 20 fA
Maximum dynamic signal range is assured in low
voltage and single supply systems by the rail-to-rail
output swing of the LMC6482-MIL. The rail-to-rail
output swing is ensured for loads down to 600 Ω of
the device. Ensured low-voltage characteristics and
low-power dissipation make the LMC6482-MIL
especially well-suited for battery-operated systems.
LMC6482-MIL is also available in a VSSOP package,
which is almost half the size of a SOIC-8 device. See
High Voltage Gain (R L = 500 k Ω): 130 dB
Specified for 2-kΩ and 600-Ω Loads
Power-Good Output
Available in VSSOP Package
2 Applications
•
•
•
•
•
Data Acquisition Systems
Transducer Amplifiers
the LMC6484 data sheet for
operational amplifier with these same features.
a quad CMOS
Hand-held Analytic Instruments
Medical Instrumentation
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
9.81 mm × 6.35 mm
Active Filter, Peak Detector, Sample and Hold, pH
Meter, Current Source
SOIC (8)
LMC6482-MIL
VSSOP (8)
PDIP (8)
•
Improved Replacement for TLC272, TLC277
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Rail-to-Rail Input
Rail-to-Rail Output
A1
œ0.18 V
A2
œ0.18 V
3V
3V
0V
0V
500mV
50ꢀs
500mV
50ꢀs
C001
C002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMC6482-MIL
SNOSD61 –JUNE 2017
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Table of Contents
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ............................................... 20
Power Supply Recommendations...................... 27
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics for V+ = 5 V....................... 4
6.6 Electrical Characteristics for V+ = 3 V....................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
8
9
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 29
11.1 Trademarks........................................................... 29
11.2 Electrostatic Discharge Caution............................ 29
11.3 Glossary................................................................ 29
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
DATE
REVISION
NOTES
*
Initial release.
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5 Pin Configuration and Functions
D, DGK and P Packages
8-Pin SOIC, VSSOP and PDIP
(Top View)
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
OUTPUT A
O
I
Output for Amplifier A
2
INVERTING INPUT A
NONINVERTING INPUT A
V–
Inverting input for Amplifier A
Noninverting input for Amplifier A
Negative supply voltage input
Noninverting input for Amplifier B
Inverting input for Amplifier B
Output for Amplifier B
3
I
4
P
I
5
NONINVERTING INPUT B
INVERTING INPUT B
OUTPUT B
6
I
7
O
P
8
V+
Positive supply voltage input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
±Supply Voltage
(V−) −0.3
(V+) +0.3
V
16
V
(3)
Current at Input Pin
−5
5
mA
mA
mA
°C
°C
°C
(4) (5)
Current at Output Pin
−30
30
Current at Power Supply Pin
40
Lead Temperature (Soldering, 10 sec.)
260
150
150
(6)
Junction Temperature
Storage temperature, Tstg
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(5) Do not short circuit output to V+, when V+ is greater than 13 V or reliability will be adversely affected.
(6) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
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6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
15.5
125
UNIT
V
Supply Voltage
3
Junction Temperature Range
LMC6482M
–55
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.4 Thermal Information
LMC6482-MIL LMC6482-MIL LMC6482-MIL
THERMAL METRIC(1)
D (SOIC)
8 PINS
155
DGK (VSSOP)
8 PINS
P (PDIP)
8 PINS
90
UNIT
RθJA
Junction-to-ambient thermal resistance
194
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics for V+ = 5 V
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M.
TJ = 25°C
MIN TYP(2)
At Temperature Extremes(1)
PARAMETER
TEST CONDITIONS
UNIT
MAX(3)
MIN TYP(2)
MAX(3)
DC Electrical Characteristics
Input Offset
Voltage
0.11
1
3
3.8
VOS
mV
TCVOS Input Offset
Voltage
μV/°C
Average Drift
(4)
(4)
IB
Input Current
See
See
0.02
0.01
3
10
5
pA
pA
Input Offset
Current
IOS
CIN
Common-Mode
Input
pF
Capacitance
RIN
Input
Resistance
10
TeraΩ
0 V ≤ VCM ≤ 15 V
65
65
65
82
82
82
60
60
60
V+ = 15 V
Common-Mode
Rejection Ratio
CMRR
dB
0 V ≤ VCM ≤ 5 V
V+ = 5 V
Positive Power 5 V ≤ V+ ≤ 15 V,
+PSRR Supply
V− = 0 V
dB
dB
Rejection Ratio VO = 2.5 V
Negative Power
65
82
60
−5 V ≤ V− ≤ −15 V, V+ = 0 V
−PSRR Supply
Rejection Ratio
VO = −2.5 V
(1) See Recommended Operating Conditions for operating temperature ranges.
(2) Typical Values represent the most likely parametric norm.
(3) All limits are specified by testing or statistical analysis.
(4) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
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Electrical Characteristics for V+ = 5 V (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M.
TJ = 25°C
MIN TYP(2)
V− − 0.3
At Temperature Extremes(1)
PARAMETER
TEST CONDITIONS
V+ = 5 V and 15 V
UNIT
MAX(3)
MIN TYP(2)
MAX(3)
−0.25
0
Input Common-
Mode Voltage
Range
For CMRR ≥ 50 dB
VCM
V
V+
+
V+ + 0.3
V+
0.25
120
35
RL = 2 kΩ(5)(4)
Sourcing
Sinking
666
75
60
18
25
8
Large Signal
Voltage Gain
AV
VO
V/mV
RL = 600 Ω(5)(4) Sourcing
50
300
35
Sinking
15
Output Swing
V+ = 5 V
4.8
4.9
0.1
4.7
0.3
14.7
0.16
14.1
0.5
20
4.7
RL = 2 kΩ to V+/2
V
V
V
V
0.18
0.5
0.32
1
0.24
0.65
0.45
1.3
V+ = 5 V
4.5
14.4
13.4
4.24
14.2
13
RL = 600 Ω to V+/2
V+ = 15 V
RL = 2k Ω to V+/2
V+ = 15 V
RL = 600 Ω to V+/2
Output Short
Circuit Current
V+ = 5 V
Sourcing, VO = 0 V
Sinking, VO = 5 V
16
11
10
8
ISC
mA
mA
15
Sourcing, VO = 0 V
28
30
30
30
20
22
Output Short
Circuit Current
V+ = 15 V
ISC
Sinking,
VO = 12 V(6)
Both Amplifiers
V+ = +5 V,
1
1.4
1.6
1.9
2
VO = V+/2
IS
Supply Current
mA
Both Amplifiers
V+ = 15 V,
1.3
VO = V+/2
AC Electrical Characteristics
(7)
SR
Slew Rate
See
0.9
1.3
1.5
0.54
V/μs
Gain-Bandwidth V+ = 15 V
Product
GBW
MHz
φm
Phase Margin
50
15
Deg
dB
Gm
Gain Margin
(8)
Amp-to-Amp
Isolation
See
150
37
dB
Input-Referred
Voltage Noise
F = 1 kHz
Vcm = 1 V
en
In
nV/√Hz
pA/√Hz
Input-Referred
Current Noise
F = 1 kHz
0.03
F = 10 kHz, AV = −2
RL = 10 kΩ,
VO = 4.1 VPP
0.01%
0.01%
Total Harmonic
Distortion
T.H.D.
F = 10 kHz, AV = −2
RL = 10 kΩ,
VO = 8.5 VPP
V+ = 10 V
(5) V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For Sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For Sinking tests, 3.5 V ≤ VO ≤ 7.5 V.
(6) Do not short circuit output to V+, when V+ is greater than 13 V or reliability will be adversely affected.
(7) V + = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew
rates.
(8) Input referred, V+ = 15 V and RL = 100 kΩ connected to 7.5 V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP
.
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6.6 Electrical Characteristics for V+ = 3 V
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M.
At Temperature
TJ = 25°C
TYP(2)
Extremes(1)
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX(3)
MIN
TYP(2) MAX(3)
DC Electrical Characteristics
Input Offset
Voltage
0.9
3
3.8
VOS
mV
Input Offset
TCVOS Voltage
Average Drift
2
0.02
0.01
74
μV/°C
Input Bias
Current
IB
pA
pA
Input Offset
Current
IOS
Common
Mode
Rejection
Ratio
0 V ≤ VCM ≤ 3 V
60
60
CMRR
PSRR
VCM
dB
Power Supply 3 V ≤ V+ ≤ 15 V, V− = 0 V
Rejection
Ratio
80
dB
Input
For CMRR ≥ 50 dB
V− −0.25
V+ V+ + 0.25
0
V
V
Common-
Mode Voltage
Range
2.8
0.2
V
V
V
V
RL = 2 kΩ to V+/2
RL = 600 Ω to V+/2
VO
Output Swing
2.5
2.7
0.37
0.6
1.2
IS
Supply Current Both Amplifiers
0.825
1.6 mA
AC Electrical Characteristics
(4)
SR
Slew Rate
See
0.9
1
V/μs
Gain-
MHz
GBW
Bandwidth
Product
Total
F = 10 kHz, AV = −2
T.H.D. Harmonic
Distortion
RL = 10 kΩ, VO = 2 VPP
0.01%
(1) See Recommended Operating Conditions for operating temperature ranges.
(2) Typical Values represent the most likely parametric norm.
(3) All limits are specified by testing or statistical analysis.
(4) Connected as voltage Follower with 2-V step input. Number specified is the slower of either the positive or negative slew rates.
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6.7 Typical Characteristics
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Input Current vs. Temperature
Figure 3. Sourcing Current vs. Output Voltage
Figure 4. Sourcing Current vs. Output Voltage
Figure 6. Sinking Current vs. Output Voltage
Figure 5. Sourcing Current vs. Output Voltage
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 7. Sinking Current vs. Output Voltage
Figure 8. Sinking Current vs. Output Voltage
Figure 10. Input Voltage Noise vs. Frequency
Figure 9. Output Voltage Swing vs. Supply Voltage
Figure 11. Input Voltage Noise vs. Input Voltage
Figure 12. Input Voltage Noise vs. Input Voltage
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 13. Input Voltage Noise vs. Input Voltage
Figure 14. Crosstalk Rejection vs. Frequency
Figure 15. Crosstalk Rejection vs. Frequency
Figure 16. Positive PSRR vs. Frequency
Figure 17. Negative PSRR vs. Frequency
Figure 18. CMRR vs. Frequency
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 19. CMRR vs. Input Voltage
Figure 20. CMRR vs. Input Voltage
Figure 21. CMRR vs. Input Voltage
Figure 22. ΔvOS vs. CMR
Figure 24. Input Voltage vs. Output Voltage
Figure 23. ΔvOS vs. CMR
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 25. Input Voltage vs. Output Voltage
Figure 26. Open-Loop Frequency Response
Figure 27. Open-Loop Frequency Response
Figure 28. Open-Loop Frequency Response vs. Temperature
Figure 29. Maximum Output Swing vs. Frequency
Figure 30. Gain and Phase vs. Capacitive Load
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 31. Gain and Phase vs. Capacitive Load
Figure 32. Open-Loop Output Impedance vs. Frequency
Figure 34. Slew Rate vs. Supply Voltage
Figure 33. Open-Loop Output Impedance vs. Frequency
Figure 35. Noninverting Large Signal Pulse Response
Figure 36. Noninverting Large Signal Pulse Response
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 37. Noninverting Large Signal Pulse Response
Figure 38. Noninverting Small Signal Pulse Response
Figure 40. Noninverting Small Signal Pulse Response
Figure 42. Inverting Large Signal Pulse Response
Figure 39. Noninverting Small Signal Pulse Response
Figure 41. Inverting Large Signal Pulse Response
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 43. Inverting Large Signal Pulse Response
Figure 44. Inverting Small Signal Pulse Response
Figure 45. Inverting Small Signal Pulse Response
Figure 46. Inverting Small Signal Pulse Response
Figure 47. Stability vs. Capacitive Load
Figure 48. Stability vs. Capacitive Load
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Typical Characteristics (continued)
VS = 15 V, Single Supply, TA = 25°C unless otherwise specified
Figure 49. Stability vs. Capacitive Load
Figure 50. Stability vs. Capacitive Load
Figure 51. Stability vs. Capacitive Load
Figure 52. Stability vs. Capacitive Load
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7 Detailed Description
7.1 Overview
The LMC6482-MIL is a dual CMOS operational amplifier that supports both rail-to-rail inputs and outputs. It may
be operated in both dual supply mode and single supply mode.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Amplifier Topology
The LMC6482-MIL incorporates specially designed wide-compliance range current mirrors and the body effect to
extend input common-mode range to each supply rail. Complementary paralleled differential input stages, like the
type used in other CMOS and bipolar rail-to-rail input amplifiers, were not used because of their inherent
accuracy problems due to CMRR, crossover distortion, and open-loop gain variation.
The LMC6482-MILs input stage design is complemented by an output stage capable of rail-to-rail output swing
even when driving a large load. Rail-to-rail output swing is obtained by taking the output directly from the internal
integrator instead of an output buffer stage.
7.3.2 Input Common-Mode Voltage Range
Unlike Bi-FET amplifier designs, the LMC6482-MIL does not exhibit phase inversion when an input voltage
exceeds the negative supply voltage. Figure 53 shows an input voltage exceeding both supplies with no resulting
phase inversion on the output.
An input voltage signal exceeds the LMC6482-MIL power supply voltages with no output phase inversion.
Figure 53. Input Voltage
The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly
exceeding this absolute maximum rating, as in Figure 54, can cause excessive current to flow in or out of the
input pins possibly affecting reliability.
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Feature Description (continued)
A ±7.5-V input signal greatly exceeds the 3-V supply in Figure 55 causing no phase inversion due to RI.
Figure 54. Input Signal
Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input
resistor (RI) as shown in Figure 55.
RI input current protection for voltages exceeding the supply voltages.
Figure 55. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
7.3.3 Rail-to-Rail Output
The approximated output resistance of the LMC6482-MIL is 180-Ω sourcing and 13-0Ω sinking at VS = 3 V and
110-Ω sourcing and 80-Ω sinking at Vs = 5 V. Using the calculated output resistance, maximum output voltage
swing can be estimated as a function of load.
7.4 Device Functional Modes
The LMC6482-MIL may be used in applications where each amplifier channel is used independently, or in
applications in which the channels are cascaded. See Typical Applications for more information.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Upgrading Applications
The LMC6484 quads and LMC6482-MIL duals have industry-standard pin outs to retrofit existing applications.
System performance can be greatly increased by the features of the LMC6482-MIL. The key benefit of designing
in the LMC6482-MIL is increased linear signal range. Most op-amps have limited input common-mode ranges.
Signals that exceed this range generate a nonlinear output response that persists long after the input signal
returns to the common-mode range.
Linear signal range is vital in applications such as filters where signal peaking can exceed input common-mode
ranges resulting in output phase inversion or severe distortion.
8.1.2 Data Acquisition Systems
Low power, single supply data acquisition system solutions are provided by buffering the ADC12038 with the
LMC6482-MIL (Figure 56). Capable of using the full supply range, the LMC6482-MIL does not require input
signals to be scaled down to meet limited common-mode voltage ranges. The LMC4282 CMRR of 82 dB
maintains integral linearity of a 12-bit data acquisition system to ±0.325 LSB. Other rail-to-rail input amplifiers
with only 50 dB of CMRR will degrade the accuracy of the data acquisition system to only 8 bits.
Operating from the same supply voltage, the LMC6482-MIL buffers the ADC12038 maintaining excellent accuracy.
Figure 56. Buffering the ADC12038 With the LMC6482-MIL
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Application Information (continued)
8.1.3 Instrumentation Circuits
The LMC6482-MIL has the high input impedance, large common-mode range and high CMRR needed for
designing instrumentation circuits. Instrumentation circuits designed with the LMC6482-MIL can reject a larger
range of common-mode signals than most in-amps. This makes instrumentation circuits designed with the
LMC6482-MIL an excellent choice of noisy or industrial environments. Other applications that benefit from these
features include analytic medical instruments, magnetic field detectors, gas detectors, and silicon-based
transducers.
A small valued potentiometer is used in series with Rg to set the differential gain of the 3-op-amp instrumentation
circuit in Figure 57. This combination is used instead of one large valued potentiometer to increase gain trim
accuracy and reduce error due to vibration.
Figure 57. Low Power 3-Op-Amp Instrumentation Amplifier
A 2-op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 58. Low sensitivity trimming
is made for offset voltage, CMRR, and gain. Low cost and low power consumption are the main advantages of
this 2-op-amp circuit.
Higher frequency and larger common-mode range applications are best facilitated by a 3-op-amp instrumentation
amplifier.
Figure 58. Low-Power Two-Op-Amp Instrumentation Amplifier
8.1.4 Spice Macromodel
A spice macromodel is available for the LMC6482-MIL. This model includes accurate simulation of the following:
•
•
•
•
•
Input common-mode voltage range
Frequency and transient response
GBW dependence on loading conditions
Quiescent and dynamic supply current
Output swing dependence on loading conditions
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Application Information (continued)
Many more characteristics are listed on the macromodel disk.
Contact your local TI sales office to obtain an operational amplifier spice model library disk.
8.2 Typical Applications
8.2.1 3-V Single Supply Buffer Circuit
Figure 59. 3-V Single Supply Buffer Circuit
8.2.1.1 Design Requirements
For best performance, ensure that the input voltage swing is between V+ and V-.
Ensure that the input does not exceed the common-mode input range.
To reduce the risk of destabilizing the output, use resistive isolation on the output when driving capacitive loads
(see the Detailed Design Procedure section).
When large feedback resistors are used, it may be necessary to compensate for parasitic capacitance on the
input. See the Detailed Design Procedure section.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Capacitive Load Compensation
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 60. This simple
technique is useful for isolating the capacitive inputs of multiplexers and A/D converters.
Figure 60. Resistive Isolation of a 330-pF Capacitive Load
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Typical Applications (continued)
Figure 61. Pulse Response of the LMC6482-MIL Circuit in Figure 60
8.2.1.2.1.1 Capacitive Load Tolerance
The LMC6482-MIL can typically directly drive a 100-pF load with VS = 15 V at unity gain without oscillating. The
unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-
amps. The combination of the output impedance of the op-amp and the capacitive load induces phase lag. This
results in either an underdamped pulse response or oscillation.
Improved frequency response is achieved by indirectly driving capacitive loads, as shown in Figure 62.
Compensated to handle a 330pF capacitive load.
Figure 62. LMC6482-MIL Noninverting Amplifier
R1 and C1 serve to counteract the loss of phase margin by feeding forward the high-frequency component of the
output signal back to the amplifiers inverting input, thereby preserving phase margin in the overall feedback loop.
The values of R1 and C1 are experimentally determined for the desired pulse response. The resulting pulse
response is shown in Figure 63.
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Typical Applications (continued)
Figure 63. Pulse Response of
LMC6482-MIL Circuit in Figure 62
8.2.1.2.1.2 Compensating for Input Capacitance
It is quite common to use large values of feedback resistance with amplifiers that have ultralow input current, like
the LMC6482-MIL. Large feedback resistors can react with small values of input capacitance due to transducers,
photo diodes, and circuits board parasitics to reduce phase margins.
Figure 64. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor
(as in Figure 64), Cf, is first estimated by:
(1)
or
R1 CIN ≤ R2 Cf
(2)
which typically provides significant overcompensation.
Printed-circuit-board stray capacitance may be larger or smaller than that of a bread-board, so the actual
optimum value for Cf may be different. The values of Cf should be checked on the actual circuit. (Refer to the
LMC660 quad CMOS amplifier data sheet for a more detailed discussion.)
8.2.1.2.1.3 Offset Voltage Adjustment
Offset voltage adjustment circuits are illustrated in Figure 65 and Figure 66. Large value resistances and
potentiometers are used to reduce power consumption while providing typically ±2.5 mV of adjustment range,
referred to the input, for both configurations with VS = ±5 V.
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Typical Applications (continued)
ë+
w4
w3
5ë
500 kW
V
IN
-
1
2
[a/6482
-5ë
V
OUT
1 MW
1 kW
+
499W
500 kW
V
OUT
R4
R3
= -
ë-
V
IN
ë-
Figure 65. Inverting Configuration Offset Voltage Adjustment
Figure 66. Noninverting Configuration Offset Voltage Adjustment
8.2.1.3 Application Curves
Figure 68. Rail-To-Rail Output
Figure 67. Rail-To-Rail Input
8.2.2 Typical Single-Supply Applications
The circuit in Figure 69 uses a single supply to half-wave rectify a sinusoid centered about ground. RI limits
current into the amplifier caused by the input voltage exceeding the supply voltage. Full-wave rectification is
provided by the circuit in Figure 71.
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Typical Applications (continued)
Figure 69. Half-Wave Rectifier With Input Current
Protection (RI)
Figure 70. Half-Wave Rectifier Waveform
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Typical Applications (continued)
In Figure 75 dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold
capacitor. The droop rate is primarily determined by the value of CH and diode leakage current. The ultralow
input current of the LMC6482-MIL has a negligible effect on droop.
Figure 71. Full-Wave Rectifier With Input Current
Protection (RI)
Figure 72. Full-Wave Rectifier Waveform
Figure 73. Large Compliance Range Current
Source
Figure 74. Positive Supply Current Sense
Figure 75. Low-Voltage Peak Detector With Rail-To-Rail Peak Capture Range
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Typical Applications (continued)
The high CMRR (82 dB) of the LMC6482-MIL allows excellent accuracy throughout the rail-to-rail dynamic
capture range of the circuit.
Figure 76. Rail-To-Rail Sample and Hold
The low-pass filter circuit in Figure 77 can be used as an anti-aliasing filter with the same voltage supply as the
A/D converter.
Filter designs can also take advantage of the LMC6482-MIL ultralow input current. The ultralow input current
yields negligible offset error even when large value resistors are used. This in turn allows the use of smaller
valued capacitors which take less board space and cost less.
Figure 77. Rail-To-Rail Single Supply Low Pass Filter
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9 Power Supply Recommendations
The LMC6482-MIL can be operated over a supply range of 3 V to 15 V. To achieve noise immunity as
appropriate to the application, it is important to use good PCB layout practices for power supply rails and planes,
as well as using bypass capacitors connected between the power supply pins and ground.
10 Layout
10.1 Layout Guidelines
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultralow input current of the
LMC6482-MIL, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PCB, even
through it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LM6482s inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, and so forth connected to the
inputs of the op-amp, as in Figure 78. To have a significant effect, guard rings should be placed on both the top
and bottom of the PCB. This PC foil must then be connected to a voltage which is at the same voltage as the
amplifier inputs, because no leakage current can flow between two points at the same potential. For example, a
PCB trace-to-pad resistance of 1012 Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5-V bus adjacent to the pad of the input. This would cause a 250 times degradation from the
actual performance of the LMC6482-MIL. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011 Ω would cause only 0.05 pA of leakage current. See Figure 79 through Figure 81 for typical
connections of guard rings for standard op-amp configurations.
The designer should be aware that when it is inappropriate to lay out a PCB for the sake of just a few circuits,
another technique is even better than a guard ring on a PCB: Do not insert the input pin of the amplifier into the
PCB at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you
may have to forego some of the advantages of PCB construction, but the advantages are sometimes well worth
the effort of using point-to-point up-in-the-air wiring. See Figure 82.
10.2 Layout Example
Figure 78. Example of Guard Ring in PCB Layout Typical Connections of Guard Rings
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Layout Example (continued)
Figure 79. Inverting Amplifier Typical Connections of Guard Rings
Figure 80. Noninverting Amplifier Typical Connections of Guard Rings
Figure 81. Follower Typical Connections of Guard Rings
(Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB.)
Figure 82. Air Wiring
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMC6482AI MDA
ACTIVE
DIESALE
Y
0
324
RoHS & Green
Call TI
Level-1-NA-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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