LMC6044IMX/NOPB [TI]
四路、15.5V、100kHz 运算放大器 | D | 14 | -40 to 85;
| 型号： | LMC6044IMX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四路、15.5V、100kHz 运算放大器 | D | 14 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总25页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6044
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SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
LMC6044 CMOS Quad Micropower Operational Amplifier
Check for Samples: LMC6044
1
FEATURES
APPLICATIONS
2
•
•
•
•
•
Low Supply Current: 10 μA/Amp (Typ)
Operates from 4.5V to 15.5V Single Supply
Ultra Low Input Current: 2 fA (Typ)
Rail-to-Rail Output Swing
•
•
•
•
•
•
•
Battery Monitoring and Power Conditioning
Photodiode and Infrared Detector Preamplifier
Silicon Based Transducer Systems
Hand-Held Analytic Instruments
Input Common-Mode Range Includes Ground
pH Probe Buffer Amplifier
Fire and Smoke Detection Systems
Charge Amplifier for Piezoelectric Transducers
DESCRIPTION
Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6044. Providing input
currents of only 2 fA typical, the LMC6044 can operate from a single supply, has output swing extending to each
supply rail, and an input voltage range that includes ground.
The LMC6044 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to
latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it
ideal for single-supply battery-powered systems.
Other applications for the LMC6044 include bar code reader amplifiers, magnetic and electric field detectors, and
hand-held electrometers.
This device is built with National's advanced Double-Poly Silicon-Gate CMOS process.
See the LMC6041 for a single, and the LMC6042 for a dual amplifier with these features.
Connection Diagram
14-Pin PDIP/SOIC
Instrumentation Amplifier
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2013, Texas Instruments Incorporated
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature (Soldering, 10 sec.)
Current at Input Pin
±Supply Voltage
16V
See(3)
See(4)
260°C
±5 mA
Current at Output Pin
±18 mA
Current at Power Supply Pin
Power Dissipation
35 mA
See(5)
Storage Temperature Range
Junction Temperature(5)
ESD Tolerance(6)
−65°C to +150°C
110°C
500V
Voltage at I/O Pin (V+)
+0.3V, (V−) −0.3V
(1) Absolute Maximum Ratings indicate limts beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 110°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(5) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA
.
(6) Human body model, 1.5 kΩ in series with 100 pF.
Operating Ratings
LMC6044AI, LMC6044I
Supply Voltage
14-Pin PDIP
−40°C ≤ TJ ≤ +85°C
4.5V ≤ V+ ≤ 15.5V
85°C/W
Temperature Range
(1)
Thermal Resistance (θJA
)
14-Pin SOIC
115°C/W
Power Dissipation
See(2)
(1) All numbers apply for packages soldered directly into a PC poard.
(2) For operating at elevated temperatures, the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA
.
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Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
LMC6044AI
Limit(2)
LMC6044I
Limit(2)
Units
(Limit)
Typical(1)
VOS
1
3
6
mV
Input Offset Voltage
3.3
6.3
max
TCVOS
Input Offset Voltage
Average Drift
1.3
μV/°C
IB
Input Bias Current
Input Offset Current
Input Resistance
0.002
0.001
>10
4
2
4
2
pA max
IOS
RIN
TeraΩ
dB
CMRR
75
68
66
62
60
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12.0V
V+ = 15V
min
dB
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
VO = 2.5V
+PSRR
−PSRR
CMR
75
94
68
62
66
60
min
dB
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
VO = 2.5V
84
74
83
73
min
V
−0.4
−0.1
−0.1
V+ = 5V & 15V
For CMRR ≥ 50 dB
0
0
max
V
Input Common-Mode
Voltage Range
V+ − 1.9V
1000
500
V+ − 2.3V
V+ − 2.5V
400
V+ − 2.3V
V+ − 2.4V
300
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
V
AV
Sourcing
Sinking
300
200
RL = 100 kΩ(3)
180
90
120
70
Large Signal Voltage Gain
1000
250
200
100
Sourcing
Sinking
160
80
RL = 25 kΩ(3)
100
50
60
40
VO
4.987
0.004
4.980
0.010
14.970
0.007
14.950
0.022
4.970
4.950
0.030
0.050
4.920
4.870
0.080
0.130
14.920
14.880
0.030
0.050
14.900
14.850
0.100
0.150
4.940
4.910
0.060
0.090
4.870
4.820
0.130
0.180
14.880
14.820
0.060
0.090
14.850
14.800
0.150
0.200
V+ = 5V
RL = 100 kΩ to 2.5V
min
V
max
V
min
V
V
+ = 5V
RL = 25 kΩ to 2.5V
max
V
Output Swing
V+ = 15V
min
V
RL = 100 kΩ to V+/2
max
V
V+ = 15V
min
V
RL = 25 kΩ to V+/2
max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
LMC6044AI
Limit(2)
LMC6044I
Limit(2)
Units
(Limit)
Typical(1)
ISC
22
16
10
16
8
13
8
mA
min
mA
min
mA
min
mA
min
μA
Sourcing, VO = 0V
Output Current
V+ = 5V
21
40
39
40
52
13
8
Sinking, VO = 5V
Sourcing, VO = 0V
Sinking, VO = 13V(4)
ISC
15
10
24
8
15
10
21
8
Output Current
V+ = 15V
IS
65
72
85
94
75
82
98
107
Four Amplifiers
VO = 1.5V
max
μA
Supply Current
Four Amplifiers
V+ = 15V
max
(4) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
Parameter
Conditions
LMC6044AI
Limit(2)
LMC6044I
Limit(2)
Units
(Limit)
Typical(1)
SR
0.02
0.015
0.010
V/μs
min
Slew Rate
See(3)
0.010
0.007
GBW
Gain-Bandwidth Product
Phase Margin
0.10
60
MHz
φm
Deg
Amp-to-Amp Isolation
See(4)
115
dB
en
in
Input-Referred Voltage Noise F = 1 kHz
83
nV/√Hz
pA/√Hz
Input-Referred Current Noise
F = 1 kHz
0.0002
F = 1 kHz, AV = −5
RL = 100 kΩ, VO = 2 Vpp
±5V Supply
T.H.D.
Total Harmonic Distortion
0.01
%
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates.
(4) Input referred V+ = 15V and RL = 100 kΩ connected to V+/2. Each amp excited in turn with 100 Hz to produce VO = 12 VPP
.
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Typical Performance Characteristics
VS = ±7.5V, TA = 25°C unless otherwise specified
Offset Voltage vs
Temperature of Five
Representative Units
Supply Current vs
Supply Voltage
Figure 1.
Figure 2.
Input Bias Current vs
Input Common-Mode
Voltage
Input Bias Current
vs Temperature
Figure 3.
Figure 4.
Input Common-Mode
Voltage Range vs
Temperature
Output Characteristics
Current Sinking
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Output Characteristics
Output Characteristics
vs Frequency
Current Sourcing
Figure 7.
Figure 8.
CMRR
vs
Frequency
Crosstalk Rejection vs
Frequency
Figure 9.
Figure 10.
Power Supply Rejection
CMRR
vs
Temperature
Ratio
vs
Frequency
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Open-Loop Voltage Gain
Open-Loop
Frequency Response
vs Temperature
Figure 13.
Figure 14.
Gain and Phase
Responses
vs
Gain and Phase
Responses vs
Temperature
Load
Capacitance
Figure 15.
Figure 16.
Gain Error
(VOS
Common-Mode Error vs
Common-Mode Voltage of
Three Representative Units
vs
VOUT
)
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Non-Inverting Slew
Rate
vs
Temperature
Inverting Slew Rate
vs Temperature
Figure 19.
Figure 20.
Non-Inverting Large
Signal Pulse Response
(AV = +1)
Non-Inverting Small
Signal Pulse Response
Figure 21.
Figure 22.
Inverting Large-Signal
Pulse Response
Inverting Small Signal
Pulse Response
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Stability
Stability
vs
Capacitive Load
vs
Capacitive Load
Figure 25.
Figure 26.
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SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
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APPLICATION HINTS
AMPLIFIER TOPOLOGY
The LMC6044 incorporates a novel op-amp design topology that enables it to maintain rail to rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain outupt buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6044 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the
LMC6044.
Although the LMC6044 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and
even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce
phase margins.
When high input impedance are demanded, guarding of the LMC6044 is suggested. Guarding input lines will not
only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK.)
Figure 27. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around
the feedback resistor (as in Figure 27) such that:
(1)
or
R1 CIN ≤ R2 Cf
(2)
Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on
compensating for input capacitance.
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 28.
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Figure 28. LMC6044 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 28, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 29). Typically, a pull up
resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 29. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6044, typically less than 2 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
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Figure 30. Example of Guard Ring in P.C. Board Layout
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6044's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 30. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the
LMC6044's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 33 for typical connections of guard
rings for standard op-amp configurations.
Figure 31. Inverting Amplifier Typical Connections of Guard Rings
Figure 32. Non-Inverting Amplifier Typical Connections of Guard Rings
Figure 33. Follower Typical Connections of Guard Rings
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The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 34.
Typical Single-Supply Applications
(V+ = 5.0 VDC
)
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 34. Air Wiring
The extremely high input impedance, and low power consumption, of the LMC6044 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH
probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
The circuit in Figure 35 is recommended for applications where the common-mode input range is relatively low
and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an
independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less
than 40 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board
layout an important part of the overall system design (see PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-
IMPEDANCE WORK). Referring to Figure 35, the input voltages are represented as a common-mode input VCM
plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making
the ratio of R1/R2 equal to R3/R4. So that where,
(3)
A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result
in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the
gain equation can be simplified:
(4)
Due to the “zero-in, zero-out” performance of the LMC6044, and output swing rail-rail, the dynamic range is only
limited to the input common-mode range of 0V to VS–2.3V, worst case at room temperature. This feature of the
LMC6044 makes it an ideal choice for low-power instrumentation systems.
A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 36. Provisions have been
made for low sensitivity trimming of CMRR and gain.
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(V+ = 5.0 VDC
)
Figure 35. Two Op-Amp Instrumentation Amplifier
Figure 36. Low-Power Two-Op-Amp Instrumentation Amplifier
Figure 37. Low-Leakage Sample-and-Hold
Figure 38. Instrumentation Amplifier
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(V+ = 5.0 VDC
)
Figure 39. 1 Hz Square-Wave Oscillator
Figure 40. AC Coupled Power Amplifier
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMC6044-MDC
LMC6044AIM
ACTIVE
NRND
DIESALE
SOIC
Y
D
0
100
55
RoHS & Green
Call TI
Level-1-NA-UNLIM
-40 to 85
-40 to 85
Samples
14
Non-RoHS
& Green
Call TI
SN
Level-1-235C-UNLIM
LMC6044
AIM
LMC6044AIM/NOPB
LMC6044AIMX/NOPB
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
55
RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMC6044
AIM
Samples
Samples
2500 RoHS & Green
55 RoHS & Green
2500 RoHS & Green
25 RoHS & Green
SN
LMC6044
AIM
LMC6044IM/NOPB
LMC6044IMX/NOPB
LMC6044IN/NOPB
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
D
D
N
14
14
14
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-NA-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMC6044IM
LMC6044IM
LMC6044IN
Samples
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC6044AIMX/NOPB
LMC6044IMX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
9.35
9.35
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMC6044AIMX/NOPB
LMC6044IMX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
356.0
367.0
356.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMC6044AIM
LMC6044AIM
D
D
D
D
N
SOIC
SOIC
SOIC
SOIC
PDIP
14
14
14
14
14
55
55
55
55
25
495
495
495
495
502
8
8
4064
4064
4064
4064
11938
3.05
3.05
3.05
3.05
4.32
LMC6044AIM/NOPB
LMC6044IM/NOPB
LMC6044IN/NOPB
8
8
14
Pack Materials-Page 3
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