LM74721-Q1 [TI]
具有有源整流功能的汽车类无 TVS、低 IQ 反向电池保护理想二极管控制器;
| 型号： | LM74721-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有有源整流功能的汽车类无 TVS、低 IQ 反向电池保护理想二极管控制器 电池 控制器 二极管 电视 |
| 文件： | 总27页 (文件大小：1972K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74721-Q1
ZHCSOW5B –SEPTEMBER 2021 –REVISED JULY 2022
LM74721-Q1 具有有源整流特性的无TVS 低IQ 汽车类反向电池保护理想二极管
控制器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
LM74721-Q1 理想二极管控制器可驱动和控制外部背
对背N 沟道MOSFET，从而模拟具有电源路径开/关控
制和过压保护功能的理想二极管整流器。3V 至 65V 的
宽输入电源电压可保护和控制 12V 汽车类电池供电的
ECU。该器件可承受并保护负载免受低至 –33V（直
流）负电源电压的影响。集成的理想二极管控制器
(GATE) 可驱动第一个 MOSFET 来代替肖特基二极
管，以实现反向输入保护和输出电压保持功能。集成的
VDS 钳位功能可实现输入无 TVS 的系统设计，从而在
汽车应用中实现符合 ISO7637 标准的脉冲抑制。具有
快速导通和关断比较器的强大升压稳压器可确保在汽车
测试（如 ISO16750 或 LV124）期间实现稳健、高效
的 MOSFET 开关性能，期间 ECU 会收到输入短时中
断以及频率高达 100kHz 的交流叠加输入信号。运行期
间的低静态电流 35µA（最大值）可实现常开型系统设
计。在电源路径中使用了第二个 MOSFET 的情况下，
该器件允许使用 EN 引脚实现负载断开控制。在EN 处
于低电平时，静态电流降至 3.3μA（最大值）。该器
件具有可调节过压切断保护功能，可提供负载突降保
护。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 3V 至65V 输入范围
• 反向输入保护低至-33V
• 针对输入的无TVS 运行集成VDS 钳位，从而实现
符合ISO7637 标准的脉冲抑制
• 低静态电流：运行时35µA（最大值）
• 3.3µA（最大值）低关断电流（EN = 低电平）
• 17 mV 阳极至阴极正向压降调节下，理想二极管正
常运行
• 驱动外部背对背N 沟道MOSFET
• 集成型30mA 升压稳压器
• 快速响应反向电流阻断：0.5 µs
• 高达100 kHz 的有源整流
• 可调节过压保护
• 采用节省空间的12 引脚WSON 封装
• 与LM74720-Q1 引脚对引脚兼容
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
• 汽车电池保护
– ADAS 域控制器
– 摄像头、雷达ECU
– 出色的音频放大器
– 抬头显示
LM74721-Q1
WSON (12)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VBATT
Q1
VBATT
12 V
VOUT
VOUT
IIN
GATE
A
C
VS CAP LX
PD
VSNS
SW
VGATE
R1
BATT_MON
R2
LM74721-Q1
GND
VGATE -VBATT
EN
ON OFF
OV
无TVS 条件下的ISO7637-2 脉冲1 性能
适用于12V 电池供电汽车类应用的低IQ、无TVS 理想
二极管
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDC2
LM74721-Q1
ZHCSOW5B –SEPTEMBER 2021 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical 12-V Reverse Battery Protection
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics................................................8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Shutdown Mode........................................................16
Application...................................................................17
9.3 What to Do and What Not to Do .............................. 22
10 Power Supply Recommendations..............................23
10.1 Transient Protection................................................23
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 接收文档更新通知................................................... 25
12.2 支持资源..................................................................25
12.3 Trademarks.............................................................25
12.4 Electrostatic Discharge Caution..............................25
12.5 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (February 2022) to Revision B (July 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
Changes from Revision * (September 2021) to Revision A (February 2022)
Page
• 更新了数据表标题...............................................................................................................................................1
• Updated the Load Disconnect Switch Control (PD) description....................................................................... 14
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5 Pin Configuration and Functions
12
11
10
1
2
3
4
GATE
A
C
VS
CAP
VSNS
SW
RTN
9
8
7
LX
Exposed
Thermal
Pad
PD
5
6
OV
EN
GND
图5-1. WSON 12-Pin DRR Transparent Top View
表5-1. Pin Functions
PIN
LM74721-Q1
TYPE
DESCRIPTION
NAME
DRR-12 (WSON)
Diode controller gate drive output. Connect to the GATE of the external
MOSFET.
GATE
1
O
A
2
3
I
I
Anode of the ideal diode. Connect to the source of the external MOSFET.
Voltage sensing input
VSNS
Voltage sensing disconnect switch terminal. VSNS and SW are internally
connected through a switch. Use SW as the top connection of the battery
sensing or OV resistor ladder network. When EN is pulled low, the switch is
OFF, disconnecting the resistor ladder from the battery line, thereby cutting off
the leakage current. If the internal disconnect switch between VSNS and SW
is not used, then short them together and connect to C pin.
SW
4
I
Adjustable overvoltage threshold input. Connect a resistor ladder across SW
to OV terminal. When the voltage at OV exceeds the overvoltage cutoff
threshold, then the PD is pulled low turning OFF the HSFET. PD is driven high
when the sense voltage goes below the OV falling threshold.
OV
EN
5
6
I
I
EN Input. Connect to A or C pin for always ON operation. In this mode, the
device consumes an IQ of 35 µA (maximum) that can be driven externally
from a micro controller I/O. Pulling this pin low below 0.5 V enters the device
in low Iq shutdown mode.
GND
PD
7
8
G
O
Connect to the system ground plane.
Pull down connection for the external HSFET. Connect to the GATE of the
external FET. Leave PD pin floating if the load disconnect FET is not used.
Switch node of the internal boost regulator. This node must be kept small on
the PCB for good performance and low EMI. Connect the boost inductor
between this pin and the DRAIN connection of the external FET.
LX
9
I
Boost Regulator Output. This pin is used to provide a drive voltage to the gate
driver of the ideal diode stage as well as drive supply for the HSFET. Connect
a 1-µF capacitor between this pin and the VS pin.
CAP
VS
10
O
I
11
12
Supply voltage pin. Place 0.1-µF capacitor from VS pin to GND.
Cathode of the ideal diode. Connect to the DRAIN of the external MOSFET.
The voltage sensed at this pin is used to control the external MOSFET GATE.
This pin must be locally bypassed with at least 1 µF.
C
I
RTN
Thermal Pad
Leave exposed pad floating. Do not connect to GND plane.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
–(VCLAMP
+
Input Pins
A to GND
70
1)
Input Pins
Input Pins
Input Pins
Input Pins
VS, C to GND
70
70
–0.3
–0.3
V(A)
VSNS, SW, EN, OV to GND, V(A) > 0 V
VSNS, SW, EN, OV to GND, V(A) ≤0 V
C to GND, V(A) ≤0 V
V
(70 + V(A)
)
)
(70 + V(A)
–1
–(VCLAMP
+
Input Pins
RTN to GND
0.3
10
1)
Input Pins
IVSNS, ISW
–1
–1
mA
Input Pins
IEN, IOV, V(A) > 0 V
IEN, IOV, V(A) ≤0 V
CAP to C
Input Pins
Internally limited
–0.3
Output Pins
Output Pins
Output Pins
Output Pins
Output to Input Pins
15.9
CAP to A
VCLAMP + 15.9
–0.3
–0.3
–0.3
–5
GATE to A
15
85
V
LX, CAP, PD to GND
C to A
VCLAMP
150
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
–40
–40
°C
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
Corner pins (GATE, EN, GND,
C)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged device model (CDM),
per AEC Q100-011
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
65
UNIT
A to GND
VS, C to GND
EN to GND
A
–60
Input Pins
65
V
65
–60
0.1
1
External capacitance
External Inductor
µF
µH
CAP to VS
LX
100
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
V
External MOSFET max
VDS rating
60
External MOSFET max
GATE to A
15
VGS rating
TJ
Operating junction temperature range(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM74721-Q1
THERMAL METRIC(1)
DRR (WSON)
UNIT
12 PINS
61.6
50
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
32.7
1.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (botton) thermal resistance
32.7
6.9
ΨJB
RθJC
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VA, V(VS) SUPPLY VOLTAGE
VCLAMP
V(A POR)
V(C–A) clamp voltage
VA POR Rising threshold
VA POR Falling threshold
Minimum Voltage at VS
VS POR Rising
34.5
3.1
43
3.4
2.6
3.85
2.9
3
V
V
2.2
V(VS)
2.58
2.35
2.8
2.6
2
2.95
2.85
3.3
VS POR Falling
I(SHDN)
Shutdown Supply Current
V(EN) = 0 V
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤TJ ≤+85°C
27
27
32
35
µA
I(Q)
Total System Quiescent Current
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤TJ ≤+125°C
ENABLE INPUT
V(EN_IH)
Enable input high threshold
Enable input low threshold
Enable Hysteresis
2
V
V(EN_IL)
0.5
0.85
485
55
1.2
V(EN_Hys)
mV
nA
I(EN)
Enable sink current
V(EN) = 12 V
155
VANODE to VCATHODE
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(AC_REG)
V(AC_FWD)
Regulated Forward V(AC) Threshold
9
16.4
22.7
V(AC) threshold from RCB to Forward
conduction
75
105
140
mV
V(AC) threshold for reverse current
blocking
V(AC_REV)
–12
–5.65
–1.3
GATE DRIVE
V(GATE) - V(A)
3V < V(VS) < 65V
V(A) –V(C) = –20 mV,
(GATE) –V(A) = 100 mV
9.5
14
13
39
V
A
I(GATE_Pull down)
I(GATE)
Peak Pulldown current
2.5
26
V
Regulation max sink current
GATE pulldown resistance
µA
V(A) –V(C) = 0 V, V(GATE) –V(A) = 5 V
V(A) –V(C) = –20 mV,
RGATE
1.2
Ω
V
(GATE) –V(A) = 100 mV
BOOST REGULATOR CHARGE PUMP
Boost output rising threshold
Hysteresis
13
1.1
29
15.5
V
V
(CAP) – V(c)
I(CAP)
I(LX)
Boost load capacity
mA
mA
Ω
V
(CAP) –V(VS) = 7.5 V
V(VS) = 12 V
V(VS) = 3 V
110
1.3
140
170
210
5.1
Peak inductor current limit threshold
Low side switch On-Resistance
R(LX)
2.7
BATTERY SENSING (VSNS, SW) AND OVER VOLTAGE DETECTION (OVP, PD)
Battery sensing disconnect switch
resistance
R(SW)
104
226
430
Ω
V(OVR)
V(OVF)
V(OV_Hys)
I(OV)
Overvoltage threshold input, rising
Overvoltage threshold input, falling
OV Hysteresis
1.13
1.03
1.231
1.125
110
50
1.33
V
1.215
mV
nA
µA
OV Input leakage current
Pullup current
0 V < V(OV) < 5 V
3V < VS < 65V
110
60
I(PD_SRC)
43
55
7
50
Peak Pulldown current
DC Pulldown current
88
117
14
I(PD_SINK)
CATHODE
I(C)
V(OV) > V(OVR)
mA
10
9.4
15
18
V(A) = 12 V, V(A) –V(C) = –100 mV
V(A) = –14 V, V(C) = 14 V
CATHODE sink current
µA
10.6
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6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(A) ↑V(A_POR) to V(GATE-A) > 5V,
C(GATE-A) = 10 nF
VA_POR(DLY)
tReverse delay
tForward recovery
A (low to high) to GATE Turn-On delay
200
Reverse voltage detection to Gate Turn-
Off delay
V(A) –V(C) = +30 mV to –100
mV, V(GATE-A) <1V, C(GATE-A) = 10 nF
0.47
1.9
0.81
Forward voltage detection to Gate Turn-
On delay
V(A) –V(C) = –100 mV to 700
mV, V(GATE-A) >5V, C(GATE-A) = 10 nF
µs
2.9
tEN_OFF(DLY)PD EN to PD Delay
tOV_OFF(DLY)PD OV to PD Deglitch
6.5
0.9
38
12
1.5
65
EN ↓to PD ↓
OV ↑to PD ↓
tPD_Pk
Peak Pulldown duration
11
I(PD_SINK,Pk) ↑to I(PD_SINK,DC)
↓
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6.7 Typical Characteristics
650
600
550
500
450
400
350
300
250
200
150
100
50
8
7
6
5
4
3
2
1
0
−40C
25C
85C
125C
150C
−40C
25C
85C
125C
150C
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VA (V)
图6-1. Operating Quiescent Current vs Supply Voltage
图6-2. Shutdown Supply Current vs Supply Voltage
3.5
3
2.5
2
1.5
VS PORR
VS PORF
1
-50
0
50
100
150
200
Temperature (C)
图6-3. VA POR Threshold vs Temperature
图6-4. VS POR Threshold vs Temperature
14
40
35
30
25
20
15
10
5
VS = 12 V
VS = 3 V
13
12
11
(VCAP−VS) R
(VCAP−VS) F
10
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (C)
Temperature (C)
图6-5. Boost Comparator Threshold vs Temperature
图6-6. Boost Loading Capacity vs Temperature
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6.7 Typical Characteristics (continued)
1.2
1
1.3
1.2
1.1
1
0.8
0.6
0.4
0.2
VOV_R
VOV_F
-50
0
50
100
150
200
Temperature (C)
-50
0
50
100
150
200
Temperature (C)
图6-8. PD Turn-off Delay During OV
图6-7. OV Threshold vs Temperature
8
7
6
5
4
3
2
4
3
2
1
0
C(GATE − A) = 4.7 nF
C(GATE − A) = 10 nF
C(GATE − A) = 22 nF
C(GATE − A) = 33 nF
C(GATE − A) = 47 nF
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (C)
Temperature (C)
图6-9. PD Turn-off Delay During EN
图6-10. Forward Turn-on Delay vs Temperature
90
60
5
RPD = 270
RPD = 330
4.5
4
30
0
3.5
3
-30
-60
-90
2.5
2
-10
0
10
20
30
40
50
V(A− C) mV
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
图6-11. Gate Current vs Forward Voltage Drop
图6-12. PD Turn-off Delay vs Supply Voltage
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6.7 Typical Characteristics (continued)
42
5
0
41.2
40.4
39.6
38.8
38
-5
-10
-15
-20
-25
-30
-35
−40C
25C
85C
125C
150C
-50
-10
30
70
110
150
-35
-30
-25
-20
VANODE (V)
-15
-10
-5
0
Free-Air Temperature (C)
图6-13. VCLAMP vs Temperature
图6-14. Anode Leakage Current vs Reverse Anode Voltage
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7 Parameter Measurement Information
30 mV
VA > VC
0 mV
VC > VA
–100 mV
VGATE
1 V
0 V
ttGATE_OFF(DLY)
t
700 mV
VA > VC
0 mV
VC > VA
–100 mV
VGATE
5 V
0 V
ttGATE_ON(DLY)
t
VOVR + 0.1 V
0 V
VPD
0 V
ttOV_OFF(DLY)PD
t
图7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74721-Q1 ideal diode controller drives and controls external N-Channel MOSFET to emulate an ideal
diode rectifier. The wide input supply of 3 V to 65 V allows protection and control of 12-V automotive battery
powered ECUs. IQ during operation (EN = High) is < 35 µA and < 3.3 µA during shutdown mode (EN = Low).
The device can withstand and protect the loads from negative supply voltages down to –33-V DC. Integrated
VDS clamp feature enables input TVS less system designs for automotive ISO7637 pulse suppression. An
integrated ideal diode controller (GATE) drives the first MOSFET to replace a Schottky diode for reverse input
protection and output voltage holdup. A strong 30-mA boost regulator and short turn ON and turn OFF delay
times of comparator ensures fast transient response, ensuring robust and efficient MOSFET switching
performance during automotive testing, such as ISO16750 or LV124, where an ECU is subjected to input short
interruptions and AC superimpose input signals up to 100-kHz frequency.
The LM74721-Q1 controls the GATE of the MOSFET to regulate the forward voltage drop at 17 mV. The linear
regulation scheme in these devices enables graceful control of the GATE voltage and turns off of the MOSFET
during a reverse current event and ensures zero DC reverse current flow.
Low quiescent current (< 35 µA) in operation enables always ON system designs. With a second MOSFET in the
power path, the device allows load disconnect control using EN pin. Quiescent current reduces to < 3.3 μA with
EN low.
8.2 Functional Block Diagram
Q1
Q2
VBATT
VOUT
18 V
GATE
C
VS CAP
LX
PD
A
VSNS
SW
VC-A CLAMP
50 µA
EN
Boost
Converter and
control
Reverse Current
Protection controller and
Gate Driver
EN
R1
BATT_MON
VA + 10 V
100 mA
12 mA
R2
OV
+
RTN
OV
1.23 V
R3
EN
–
1.12 V
VS
+
2.8 V
2.6 V
–
OV
+
–
EN
EN
VA
VCAP
VA
VA + 10 V
2 V
Bias Rails
RTN
0.5 V
Reverse
Protection Logic
LM74721-Q1
GND
8.3 Feature Description
8.3.1 Reverse Battery Protection (A, C, GATE)
A, C, GATE comprises of ideal diode stage. Connect the Source of the external MOSFET to A, Drain to C and
Gate to GATE pin. The LM74721-Q1 has integrated reverse input protection down to –33 V.
In LM74721-Q1 the voltage drop across the MOSFET is continuously monitored between the A and C pins, and
the GATE to A voltage is adjusted as needed to regulate the forward voltage drop at 17 mV (typical) for
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LM74721-Q1. This closed loop regulation scheme enables graceful turn-off of the MOSFET during a reverse
current event and ensures zero DC reverse current flow. This scheme ensures robust performance during slow
input voltage ramp down tests. Along with the linear regulation amplifier scheme, the LM74721-Q1 also
integrates a fast reverse voltage comparator. When the voltage drop across A and C reaches V(AC_REV)
threshold, then the GATE goes low within 0.5 µs (typical). This fast reverse voltage comparator scheme ensures
robust performance during fast input voltage ramp down tests such as input micro-shorts. The external MOSFET
is turned ON back when the voltage across A and C hits V(AC_FWD) threshold within 1.9 µs (typical) for LM74721-
Q1. For ideal diode only designs, connect LM74721-Q1 as shown in 图8-1
Q1
VBATT
12 V
VOUT
GATE C VS CAP LX
PD
A
VSNS
SW
R1
BATT_MON
R2
LM74721-Q1
EN
ON OFF
GND
OV
图8-1. Configuring LM74721-Q1 for Ideal Diode Only
8.3.1.1 Input TVS Less Operation: VDS Clamp
The LM74721-Q1 features an integrated VDS clamp that operates the external MOSFET as an active clamp to
dissipate the automotive ISO7637 pulse 1 transient.
When the ISO7637 pulse 1 is applied at the input:
• The GATE goes low and turns OFF the MOSFET after the voltage drop across A and C reaches V(AC_REV)
threshold.
• After the voltage across Drain and Source of the MOSFET reaches VCLAMP level (34-V minimum), it is turned
ON back in saturation, operating as an active clamp and dissipates the ISO7637 pulse 1 energy.
图8-2 shows circuit operation during ISO7637 pulse 1.
Note that the reverse current flows from VOUT back to input during the ISO7637 pulse 1 test dropping the VOUT
.
The output filter must be designed to ensure that VOUT does not go negative during ISO7637 pulse 1 test. For
all the other ISO7637 pulses that is pulse 2a, 2b, 3a, 3b, the input and output filter components suppress these
pulses.
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VCLAMP
ISO7637 Pulse 1
-
+
13.5 V
VOUT
COUT
VIN
CIN
VIN
0 V
C3
Q1
L1
C2
C VS CAP LX
- (VCLAMP – VOUT
)
GATE
A
13.5 V
VOUT
PD
EN
VSNS
SW
0 V
R1
BATT_MON
LM74721-Q1
GND
R2
R3
ON
OFF
OV
图8-2. LM74721-Q1 Ideal Diode Circuit Operation During ISO7637 Pulse 1
8.3.2 Load Disconnect Switch Control (PD)
The PD pin provides a 50-µA drive and 88-mA peak pulldown strength for the load disconnect switch stage.
Connect the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.
For inrush current limiting, connect CdVdT capacitor and R1 as shown in 图8-3.
Q1
Dz
18 V
COUT
R1
CdVdT
RPD
50 µA
PD
Fault
Off
88 mA
10 mA
GND
图8-3. Inrush Current Limiting
The CdVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current
limiting. Use 方程式1 to calculate CdVdT capacitance value.
C
(dVdT) = IPD_DRV × COUT
IINRUSH
(1)
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where IPD_DRV is 50 μA (typical), IINRUSH is the inrush current, and COUT is the output load capacitance. An extra
resistor, R1, in series with the CdVdT capacitor improves the turn-off time.
PD is pulled low during the following conditions:
• During an OV event with the OV pin voltage rising above the V(OVR) threshold
• When the EN pin is pulled low with V(EN) driven lower than V(EN_IL) level
• When the voltage at VS pin drops below the V(VS POR) falling threshold
During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the
external Zener (Dz).
Use 方程式2 to calculate the peak power dissipated in the LM74721-Q1 at the instance of PD pulldown.
PPD_peak = VOUT × IPD_SINK
(2)
where
• IPDSINK_peak is the peak sink current of 88 mA (typical)
In the system designs with input voltage above 48 V, TI recommends to place a resistor, RPD, in series with the
PD pin as shown in 图 8-3. The peak power dissipation during the pulldown events gets distributed in RPD and
the internal PD switch. A resistor value in the range of 270 Ω to 330 Ω can be selected to limit the device power
dissipation within the safe limits.
8.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
A disconnect switch is integrated between VSNS and SW pins. This switch is turned OFF when EN pin is pulled
low. This action helps to reduce the leakage current through the resistor divider network during system shutdown
state (IGN_OFF state).
Connect a resistor ladder as shown in 图 8-4 for battery voltage sensing and overvoltage threshold
programming.
VBATT
A
VSNS
EN
SW
R1
BATT_MON
LM74721-Q1
R2
R3
OV
+
PD_OFF
1.23 V
1.12 V
–
图8-4. Programming Overvoltage Threshold and Battery Voltage Sensing
8.3.4 Boost Regulator
The LM74721-Q1 integrates a boost converter to provide voltage necessary to drive the external N-channel
MOSFETs for the ideal diode and the load disconnect stages. The boost converter uses hysteretic mode control
scheme for the output voltage (VCAP-VVS) regulation along with the constant peak inductor current limit (ILX).
When the CAP–VS voltage is below its nominal value of typically 11.9 V, the low side switch of the boost is
turned on and the inductor current rises with the slope of VS/L approximately. After the current hits the limit of
140 mA (typical), then the low side switch is turned off and the inductor current discharges to the output till it
reaches zero. The low side switch is turned on again and the switching cycle repeats until the CAP–VS voltage
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has risen above the boost rising threshold of 13 V (typical). After this threshold level is reached, the boost
converter switching is turned OFF to reduce the quiescent current.
For the boost converter to be enabled, the EN pin voltage must be above the specified input high threshold,
V(ENR). The boost converter has a maximum output load capacity of 30-mA typical. If EN pin is pulled low, then
the boost converter remains disabled.
8.4 Shutdown Mode
The LM74721-Q1 enters shutdown mode when the EN pin voltage is below the specified input low threshold,
V(EN_IL). Both the gate drivers (GATE and PD) and the boost regulator are disabled in shutdown mode. During
shutdown mode, the LM74721-Q1 enters low IQ operation with a total input quiescent consumption of 2 µA
(typical).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
LM74721-Q1 controls two N-channel power MOSFETs with GATE used to control diode MOSFET to emulate an
ideal diode and PD controlling second MOSFET for power path cutoff when disabled or during an overvoltage
protection and provide inrush current limiting. IQ during operation (EN = High) is < 35 µA and < 3.3 µA during
shutdown mode (EN = Low). LM74721-Q1 can be placed into low quiescent current mode using EN = low, where
both GATE and PD are turned OFF.
9.2 Typical 12-V Reverse Battery Protection Application
图 9-1 shows a typical application circuit of LM74721-Q1 configured to provide TVS less reverse battery
protection.
Q1
VOUT
VBATT
12 V
C3
1 µF
50 V
CLOAD
660 µF
(220 µF × 3)
C2
1 µF
50 V
C1
L1
100 µH
1 µF
50 V
GATE C VS CAP
LX
A
VSNS
SW
PD
R1
90.9 k
LM74721-Q1
GND
BATT_MON
R2
12.6 k
EN
ON
OFF
OV
图9-1. Typical Application Circuit for 12-V TVS-less Reverse Battery Protection
9.2.1 Design Requirements for 12-V Battery Protection
表9-1 lists the system design requirements.
表9-1. Design Parameters –12-V Reverse Battery Protection and Overvoltage Protection
DESIGN PARAMETER
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V cold crank and 35-V load
dump
Operating input voltage range
Output power
Output current range
Input capacitance
Output capacitance
50 W
4-A nominal, 5-A maximum
0.1-µF minimum
220 µF × 3
2-V peak-peak, 30 kHz
(maximum)
AC super imposed test
ISO 7637-2 with pulse 1 maximum level of –100-V peak level and
10-Ωgenerator impedance, ISO 16750-2 and LV124
Automotive transient immunity compliance
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9.2.2 Detailed Design Procedure
9.2.2.1 Boost Converter Components (C2, C3, L1)
Place a minimum of a 1-µF capacitor across drain of the FET to GND (C2) and across CAP pin of LM74721-Q1
to drain of the FET (C3). Use a 100-µH inductor (L1) with saturation current rating > 175 mA. Example:
XPL2010-104ML from coil craft.
9.2.2.2 Input and Output Capacitance
TI recommends a minimum input capacitance C1 of 1 µF and output capacitance COUT of 0.1 µF.
9.2.2.3 Hold-Up Capacitance
Usually bulk capacitors are placed on the output due to various reasons, such as uninterrupted operation during
power interruption or micro-short at the input, hold-up requirements for doing a memory dump before turning of
the module and filtering requirements as well. This design considers minimum bulk capacitors requirements for
meeting functional status "A" during LV124 E10 test case 2 100-µs input interruption. To achieve functional pass
status A, acceptable voltage droop in the output of LM74721-Q1 is based on the UVLO settings of downstream
DC/DC converters. For this design, 1-V drop in output voltage for 100 µs is considered and the minimum hold-up
capacitance required is calculated by:
C
(HOLD_UP_MIN) = ILOAD_MAX × 100µs
dVOUT
(3)
Minimum hold-up capacitance required for 1-V drop in 100 µs is 500 µF. 3 × 220-µF electrolytic capacitors are
selected.
Also during ISO7637-2 pulse 1 transient event, LM74721-Q1 operates external MOSFET in active clamp mode,
allowing reverse current to flow from output to back to the input source. The output hold-up capacitor also
ensures output voltage does not swing negative when device is operating VDS clamp mode.
9.2.2.4 MOSFET Selection: Q1
For selecting the blocking MOSFET Q1, important electrical parameters are the maximum continuous drain
current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX)
Safe Operating Area (SOA), the maximum source current through body diode and the drain-to-source ON
resistance RDS(ON)
,
.
The maximum continuous drain current (ID) rating must exceed the maximum continuous load current.
To reduce the MOSFET conduction losses, MOSFET with the lowest possible RDS(ON) is preferred, but selecting
a MOSFET based on low RDS(ON) cannot be beneficial always. Higher RDS(ON) provides increased voltage
information to LM74721-Q1 reverse current comparator at a lower reverse current. Reverse current detection is
better with increased RDS(ON). Choosing a MOSFET with forward voltage drop of less than 50 mV at maximum
current is a good starting point.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. With LM74721-Q1, the maximum differential voltage across the MOSFET is
VCLAMP (maximum) of 43 V. TI recommends a minimum of 60-V VDS rated. This includes all the automotive
transient events and any anticipated fault conditions.
During the ISO7637 pulse 1, the maximum VDS seen by the external MOSFET Q1 is VDSCLAMP (max) that is 43
V. Use 方程式4 to calculate the peak current during ISO7637-2 pulse 1.
IISO_PEAK = (VISO + VOUT –VDSCLAMP(max)) / RS
(4)
Where
• VISO is the negative peak of the ISO7637-2 pulse 1
• VOUT is the initial level of the VBATT before ISO pulse is applied
• VDSCLAMP is maximum VCLAMP threshold of LM74721-Q1
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• RS is the ISO7637 pulse generator input impedance (10 Ω)
For ISO7637-2 pulse 1 with amplitude of –100 V, VOUT nominal voltage of 13.5 V the peak current seen by
MOSFET Q1 comes around 7 A.
The current profile tapers down from 7 A to 0 A from the peak of 7 A as shown in 图 9-5. The resulting average
current (IISO_AVG) can be approximated as one third of the peak current that is around 2.4 A. The VDS clamp
operation lasts for about 1 ms (maximum). Selecting a MOSFET with SOA characteristics covering the load line
of 43 V which can support drain current greater than (IISO_PEAK / 2) for 1 ms is a good starting point. For this
particular design example, MOSFET which can support greater than 3.5 A of drain current at 43-V VDS on SoA
curve is suitable.
图 9-2 shows typical SoA characteristics plot highlighting maximum drain current supported by the MOSFET for
the duration of 1 ms. MOSFET data sheet SoA curves are typically plotted at ambient temperature, so consider
sufficient margin over MOSFET parameters calculated values to ensure safe operation over desired operating
temperature range.
图9-2. Typical MOSFET SoA Characteristics
As external MOSFET dissipates ISO7637-2 pulse 1 energy, a special attention must be given while calculating
maximum power dissipation and effective temperature rise. Use 方程式 5 to calculate an average power
dissipation across the MOSFET.
PD_AVG = VDSCLAMP(max) × IISO_AVG
(5)
For given design example, average power dissipation comes around.
PD_AVG = 43 V × 2.4 A = 103.2 W
(6)
Typical ISO7637-2 pulse 1 transient lasts for 2 ms with total time period of 200 ms between two consecutive
pulses (duty cycle of 1%). The effective temperature rise due to power dissipation across MOSFET during
ISO7637-2 pulse 1 event can be calculated by looking at transient thermal impedance curve in a MOSFET data
sheet. 图 9-3 shows an example of how to estimate transient thermal impedance of a MOSFET for ISO7637-2
pulse 1 event.
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图9-3. Typical MOSFET Transient Thermal Impedance
The maximum VGS LM74721-Q1 can drive is 13.9 V, so a MOSFET with 15-V minimum VGS rating must be
selected.
Based on the design requirements and MOSFET selection criteria BUK7Y4R8-60E, SQJ460AEP, STL130N6F7
are some of the 60-V MOSFET options that can be selected.
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9.2.3 Application Curves
VBATT
VOUT
IIN
VGATE
VGATE -VBATT
图9-4. ISO 7637-2 Pulse 1
Time (4 ms/DIV)
图9-5. Response to ISO 7637-2 Pulse 1
VBATT
VBATT
VOUT
VGATE
VOUT
VGATE
IIN
IIN
Time (100 µs/DIV)
Time (200 ms/DIV)
图9-6. Response to ISO 7637-2 Pulse 2A
图9-7. Response to ISO 7637-2 Pulse 2B
VBATT
VBATT
VOUT
VOUT
VGATE
VGATE
IIN
IIN
Time (100 ms/DIV)
Time (40 µs/DIV)
图9-8. Response to LV124 E-06 (AC Superimpose 图9-9. Response to LV124 E-10 (Input Micro Short,
Test)
100 us)
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9.3 What to Do and What Not to Do
Leave the exposed pad (RTN) of the IC floating. Do not connect the exposed pad to the GND plane. Connecting
RTN to GND disables the reverse polarity protection feature.
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10 Power Supply Recommendations
10.1 Transient Protection
When the MOSFET is turned OFF during conditions such as reverse current blocking in the system designs
where there is an output C-L-C filter (for EMI filtering) as shown in 图 10-1, the voltage across COUT can swing
negative based on the values of L2 ,COUT and the initial reverse current in L2 before the MOSFET turns OFF.
Use a low VF Schottky diode D1 across COUT to GND and place a R-C filter with 100 Ω and 0.1 µF at Vs pin,
ensuring the device pins does not exceed the Absolute Maximum Ratings.
Q1
L2
VOUT
VBATT
12 V
C2
*
R3
C3
*
L1
COUT
CBULK
CIN
D1
C4
GATE C VS
CAP LX
PD
A
VSNS
SW
R1
LM74721-Q1
BATT_MON
R2
EN
ON
OFF
GND
OV
* Optional components needed for suppression of transients
图10-1. Circuit Implementation with Optional Protection Components for LM74721-Q1
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11 Layout
11.1 Layout Guidelines
• Connect A, GATE and C pins of LM74721-Q1 close to the MOSFET SOURCE, GATE and DRAIN pins for the
ideal diode stage, c.
• Use thick and short traces for source and drain of the MOSFET to minimize resistive losses because the high
current path of for this solution is through the MOSFET.
• Have the PowerPAD™ integrated circuit package (exposed pad) of the MOSFET soldered directly to the top
plane for best thermal performance. Other planes, such as the bottom side of the circuit board, can be used
to increase heat sinking. Thermal considerations: during the VDS clamp operation, the MOSFET acts as an
active clamp with pulse power dissipation.
• Connect the GATE pin of the LM74721-Q1 to the MOSFET GATE with short trace.
• Minimize the loops formed by capacitor across CAP pin and DRAIN of the FET and C3 to GND by placing
these capacitors as close as possible. Keep the GND side of the C3 capacitor close to GND pin of LM74721-
Q1. Boost converter switching currents flow into LX, CAP, GND pins and C3 (across DRAIN of the FET to
GND).
• Place transient suppression components like output Schottky close to C pin of LM74721-Q1.
11.2 Layout Example
S
S
Q1
S
VIN PLANE
G
VOUT PLANE
GATE
C
C2
VS
CAP
A
L1
VSNS
C3
LX
PD
SW
CIN
COUT
OV
EN
BATT_MON
GND
GND PLANE
图11-1. LM74721-Q1 Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74721QDRRRQ1
ACTIVE
WSON
DRR
12
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
L74721
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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