LM74202QPWPRQ1 [TI]
具有集成 FET 的 4.2V 至 40V、2.2A 300uA IQ 汽车理想二极管 | PWP | 16 | -40 to 125;型号: | LM74202QPWPRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成 FET 的 4.2V 至 40V、2.2A 300uA IQ 汽车理想二极管 | PWP | 16 | -40 to 125 光电二极管 |
文件: | 总39页 (文件大小:1966K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
具有过压和过流保护的 LM74202-Q1 40V、2.2A 集成式理想二极管
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
LM74202-Q1 器件是一款功能丰富的紧凑型 40V 集成
式理想二极管,具有一整套保护 特性。宽电源输入范
围允许控制 12V 汽车电池驱动 应用。此器件可以承受
并保护由高达 ±40V 的正负电源供电的负载。负载、电
源和器件保护还具有许多可编程 特性 ,包括过流保
护、浪涌电流控制、过压保护和欠压阈值保护。此器件
内部可靠的保护控制模块以及 40V 额定电压简化了针
对 ISO 标准脉冲测试的系统设计。
–
–
–
–
温度等级 1:–40°C ≤ TA ≤ +125°C
AEC-Q100-012 A 级短路可靠性
HBM ESD 分类等级 2
CDM ESD 分类等级 C6
•
•
•
•
•
4.2V 至 40V 工作电压,最大值 42V
集成反向输入极性保护,低至 -40V
总 RON 为 150mΩ 的集成背对背 MOSFET
高达 55V 的瞬态抗扰度
借助关断引脚,可以从外部控制内部 FET 的启用和禁
用,还可以将器件置于低电流关断模式。为实现系统状
态监视和下游负载控制,此器件提供故障输出和精密电
流监视输出。MODE 引脚可用于在三种电流限制故障
响应(断路器、闭锁以及自动重试模式)之间灵活地对
器件进行配置。此器件可监视 V(IN) 和 V(OUT),以便在
V(IN) < (V(OUT)-10mV) 时提供反向电流阻断。该功能
可在输出端发生电池短路故障期间保护系统总线不受过
压影响,并且有助于在电源故障和欠压条件下满足保持
电压的要求。
0.1A 至 2.23A 可调节电流限制
(1A 时精确度为 ±5%)
•
•
•
•
•
•
•
ISO7637 和 ISO16750-2 测试期间的负载保护
电池短路和接地短路保护
反向电流阻断,可提供输出对电池短路保护
IMON 电流指示器输出(精度为 ±8.5%)
低静态电流(工作时为 285µA,关断时为 16µA)
可调节的 UVLO、OVP 切断、浪涌电流控制
可选电流限制故障响应选项(自动重试、闭锁、CB
模式)
此器件采用 5mm × 4.4mm 16 引脚 HTSSOP,额定工
作温度范围为 -40°C 至 +125°C。
•
采用易于使用的 16 引脚 HTSSOP 封装
2 应用
器件信息(1)
•
•
•
•
前置摄像头,后置摄像头
器件型号
封装
封装尺寸(标称值)
驾驶辅助 ECU
LM74202-Q1
HTSSOP (16)
5.00mm x 4.40mm
远程信息处理控制单元
蜂窝式模块资产跟踪
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
12V 条件下的 ISO16750-2 负载突降脉冲 5b 性能
简化原理图
VOUT
COUT
OUT
IN
150 mΩ
CIN
RFLTb
R1
UVLO
OVP
FLT
Health Monitor
ON/OFF Control
Load Monitor
+
LM74202-Q1
VIN
SHDN
œ
dVdT
R2
TVS
IMON
ILIM
MODE
RTN
GND
RIMON
RILIM
CdVdT
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSFD0
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
1
2
3
4
5
6
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
10 Power Supply Recommendations ..................... 29
10.1 Transient Protection.............................................. 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 31
12 器件和文档支持 ..................................................... 32
12.1 文档支持................................................................ 32
12.2 接收文档更新通知 ................................................. 32
12.3 社区资源................................................................ 32
12.4 商标....................................................................... 32
12.5 静电放电警告......................................................... 32
12.6 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 32
7
8
4 修订历史记录
日期
修订版本
说明
2019 年9 月
*
初始发行版
2
Copyright © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View
OUT
OUT
FLT
16
IN
IN
1
2
3
4
15
14
13
UVLO
NC
NC
PowerPAD™
Integrated Circuit
Package
12
11
dVdT
ILIM
OVP
5
6
MODE
7
8
10
9
IMON
GND
SHDN
RTN
Pin Functions
PIN
NAME
IN
TYPE
DESCRIPTION
NO.
1, 2
P
Input supply voltage. See IN, OUT, RTN and GND Pins section.
Input for setting the programmable Undervoltage Lockout threshold. An undervoltage event
turns off the internal FET and asserts FLT to indicate power failure. If the Undervoltage
Lockout function is not needed, the UVLO terminal must be connected to the IN terminal.
See Undervoltage Lockout (UVLO) section.
3
UVLO
I
No internal connection. These pins can be connected to RTN for enhanced thermal
performance.
4, 13 NC
—
Input for setting the programmable Overvoltage Protection threshold. An overvoltage event
turns off the internal FET and asserts FLT to indicate the overvoltage fault. See Overvoltage
Protection (OVP) section.
5
6
7
OVP
I
I
I
MODE
SHDN
Mode selection pin for overload fault response. See the Device Functional Modes section.
Shutdown pin. Pulling SHDN low enters the device into low-power shutdown mode. Cycling
SHDN pin voltage resets the device that has latched off due to a fault condition. See Low
Current Shutdown Control (SHDN) section.
Reference for device internal control circuits. If reverse input polarity protection is not
required, this pin can be connected to GND. See IN, OUT, RTN and GND Pins section.
8
9
RTN
GND
—
—
Connect GND to system ground. See IN, OUT, RTN and GND Pins section.
Analog current monitor output. This pin sources a scaled down ratio of current through the
internal FET. A resistor from this pin to RTN converts current to proportional voltage. If pin is
unused, leave pin floating. See Current Monitoring section.
10
IMON
O
A resistor from this pin to RTN sets the overload and short-circuit current limit. See the
Overload and Short Circuit Protection section.
11
12
14
ILIM
dVdT
FLT
I/O
I/O
A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In and In-
Rush Current Control section.
Fault event indicator. Indicator is an open drain output. If indicator is unused, leave indicator
floating. See FAULT Response section.
O
P
15,16 OUT
PowerPAD
Power output of the device. See IN, OUT, RTN and GND Pins section.
PowerPAD integrated circuit package must be connected to RTN plane on PCB using
multiple vias for enhanced thermal performance. PowerPAD is not internally connected to
RTN. Do not use the PowerPAD as the only electrical connection to RTN.
—
Copyright © 2019, Texas Instruments Incorporated
3
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)(1)
MIN
MAX
42
UNIT
V
IN, IN-OUT
-42
-55
-0.3
-0.3
-42
10
IN, IN-OUT (350ms transient), TA = 25°C
[IN, OUT, FLT, UVLO, SHDN] to RTN
[OVP, dVdT, ILIM, IMON, MODE] to RTN
RTN
55
42
5
0.3
IFLT, IdVdT, ISHDN
Sink current
mA
Internally
limited
Internally
limited
IdVdT, IILIM, IIMON
Source Current
Operating junction temperature
Transient junction temperature
Storage Temperature
-40
-65
-65
150
T(TSD)
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model
All pins
±1000
(CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
-40
0
NOM
MAX
40
UNIT
IN
UVLO, OUT, FLT
Input voltage range
Resistance
40
V
OVP, dVdT, ILIM, IMON, SHDN
0
4
ILIM
5.36
1
120
kΩ
IMON
IN, OUT
dVdT
TJ
0.1
10
-40
1
µF
nF
°C
External capacitance
Operating junction temperature range
25
125
6.4 Thermal Information
LM74202-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
38.6
22.7
18.2
0.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
YJB
18
RθJC(bot)
1.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
6.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(IN)
Operating input voltage
4.2
3.89
55
40
4.14
305
V
V
VPORR
Internal POR Threshold, Rising
Internal POR Hysteresis
4
VPORHys
275
mV
VIN = 12V
IQON
Supply Current with device enabled
285
16
390
µA
Enabled: V(SHDN) = 2 V,
VIN = 12V, V(SHDN) = 0 V
V(IN) = -40 V, V(OUT) = 0 V
IQOFF
IVINR
Supply Current with device disabled
Reverse Input supply current
32
50
µA
µA
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(UVLOR)
V(UVLOR)
I(UVLO)
UVLO Threshold Voltage, Rising
UVLO Threshold Voltage, Falling
UVLO Input leakage current
1.175
1.08
1.19
1.1
1.25
1.126
100
V
V
0 V ≤ V(UVLO) ≤ 40 V
–100
nA
LOW IQ SHUTDOWN (SHDNb) INPUT
V(SHDN)
Output voltage
I(SHDN) = 0.1µA
2
2.7
3.4
V
V
SHDN Threshold Voltage for Low
IQ Shutdown, Falling
V(SHUTF)
0.45
V(SHUTFR)
I(SHDN)
SHDN Threshold, Rising
Input current
0.96
V
V(SHDN) = 0.4 V
-10
µA
OVER VOLTAGE PROTECTION (OVP) INPUT
Factory Set OV Clamp Select
V(SEL_OVP)
Threshold
180
200
240
mV
V
Over-Voltage Threshold Voltage,
Rising
V(OVPR)
1.175
1.19
1.225
Over-Voltage Threshold Voltage,
V(OVPF)
Falling
1.085
–100
1.125
100
I(OVP)
OVP Input Leakage Current
0V ≤ V(OVP) ≤ 4V
0
nA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT Charging Current
V(dVdT) = 0 V
4
4.7
28
5.82
25.5
µA
Ω
SHDN = 0 V, with I(dVdT) = 10mA
sinking
R(dVdT)
dVdT Discharging Resistance
GAIN(dVdT)
dVdT to OUT Gain
△V(OUT) /△V(dVdT)
23.75
24.63
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM Bias Voltage
1
0.1
1
V
A
R(ILIM) = 120 kΩ, V(IN)-V(OUT)=1V
R(ILIM) = 12 kΩ, V(IN)-V(OUT)=1V
R(ILIM) = 8 kΩ, V(IN)-V(OUT)=1V
R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=1V
0.085
0.95
0.115
1.05
I(OL)
1.425
2.11
1.5
2.23
1.575
2.35
Overload Current Limit
R(ILIM)= OPEN, Open Resistor Current
Limit
I(OL_R-OPEN)
I(OL_R-SHORT)
0.055
0.095
R(ILIM)= SHORT, Shorted Resistor
Current Limit
I(CB)
I(CB)
Circuit breaker detection threshold
Circuit breaker detection threshold
R(ILIM) = 120 kΩ, MODE = open
R(ILIM) = 5.36 kΩ, MODE = open
R(ILIM) = 120 kΩ, V(IN)-V(OUT)=5V
R(ILIM) = 8 kΩ, V(IN)-V(OUT)=5V
R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=5V
0.045
2
0.073
2.21
0.1
0.11
2.4
A
A
A
A
A
0.08
1.425
2.11
0.12
1.575
2.35
I(SCL)
Short-Circuit Current Limit
1.5
2.23
Copyright © 2019, Texas Instruments Incorporated
5
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.87 x
I(FASTRIP)
Fast-trip comparator threshold
I(OL)
+
A
0.015
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain Factor I(IMON):I(OUT)
PASS FET OUTPUT (OUT)
0.1A ≤ I(OUT) ≤ 2A
72
130
78
78.28
85 µA/A
168
0.1A ≤ I(OUT) ≤ 2A,TJ = 25°C
150
150
150
RON
IN to OUT Total ON Resistance
0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 85°C
0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 125°C
220
265
mΩ
V(IN) = 40 V, V(SHDN)= 0 V, V(OUT) = 0
V, Sourcing
Ilkg(OUT)
OUT Leakage Current in Off State
OUT Leakage Current in Off State
12
11
µA
V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24
V, Sinking
-11
-40
Ilkg(OUT)
µA
V(IN) = -40 V, V(SHDN)= 0 V, V(OUT) = 0
V, Sinking
-18
-10
96
50
V(IN)-V(OUT) Threshold for Reverse
Protection Comparator, Falling
V(REVTH)
V(FWDTH)
-16.2
85
-5
mV
mV
V(IN)-V(OUT) Threshold for Reverse
Protection Comparator, Rising
110
FAULT FLAG (FLTb): ACTIVE LOW
R(FLT) FLT Pull-Down Resistance
I(FLT) FLT Input Leakage Current
THERMAL SHUT DOWN (TSD)
V(OVP) = 2 V, I(FLT) = 5mA sinking
350
Ω
0 V ≤ V(FLT) ≤ 40 V
–200
200
nA
TSD Threshold, rising
157
°C
°C
T(TSD)
TSD hysteresis
10.1
MODE
MODE = 402 kΩ to RTN
Current limiting with latch
Circuit breaker mode with
auto-retry
MODE = Open
MODE_SEL
Thermal fault mode selection
Current limiting with auto-
retry
MODE = Short to RTN
6.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
UVLO INPUT
UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV,
C(dvdt) = Open
UVLO_tON(dly)
80
UVLO Turn On Delay
µs
µs
80+14.
5 x
C(dvdt)
UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV,
UVLO_tON(dly)
UVLO_toff(dly)
C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
UVLO Turn-Off delay
UVLO↓ (100mV below V(UVLOF)) to FLT ↓
9
SHUTDOWN INPUT
6
Copyright © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
Timing Requirements (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
350+14
.5 x
C(dvdt)
SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV,
SHDN_ton(dly)
C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
SHUTDOWN Exit delay
µs
µs
SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt)
Open
=
SHDN_ton(dly)
355
10
SHUTDOWN Entry delay SHDN_toff(dly)
SHDN ↓ (below V(SHUTF) to FLT ↓
OVP INPUT
OVP Exit delay
tOVP(dly)
tOVP(dly)
OVP ↓(20mV below V(OVPF)) to V(OUT) = 100mV
OVP↑ (20mV above V(OVPR)) to FLT ↓
205
2
µs
µs
OVP Disable delay
CURRENT LIMIT
Fast-Trip Comparator
Delay
tFASTTRIP(dly)
I(OUT) = 1.5x I(FASTRIP)
170
ns
REVERSE CURRENT BLOCKING COMPARATOR
(V(IN)-V(OUT)) ↓ (100mV overdrive below V(REVTH)) to
internal FET OFF
1.29
40
µs
µs
µs
tREV(dly)
(V(IN)-V(OUT)) ↓ (10mV overdrive below V(REVTH)) to
FLT ↓
RCB comparator delay
(V(IN)-V(OUT)) ↑ (10mV overdrive above V(FWDTH)) to
FLT ↑
tFWD(dly)
60
THERMAL SHUTDOWN
Retry Delay in TSD
tretry
540
ms
OUTPUT RAMP TIME
SHDN↑ to V(OUT) = V(IN)
1.6
10
ms
ms
Output Ramp Time
tdVdT
SHDN↑ to V(OUT) = V(IN), with C(dVdT) = 47nF
FAULT FLAG
FLT assertion delay in
circuit breaker mode
MODE = OPEN,Delay from I(out)>I(lim) to FLT ↓(and
internal FET turned off)
tCB(dly)
4
ms
ms
Retry Delay in circuit
breaker mode
MODE= OPEN, C(dVdT) = Open. I(out)>I(lim). Delay
from FLT ↓ to V(dVdT) = 50mV (Rising)
tCBretry(dly)
540
tPGOODR
tPGOODF
Delay for rising FLT edge
Delay for falling FLT edge
1.8
ms
µs
PGOOD delay time
900
版权 © 2019, Texas Instruments Incorporated
7
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
6.7 Typical Characteristics
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
4.2
4.05
3.9
294
291
288
285
282
279
276
273
270
267
264
POR Threshold Rising (V)
POR Threshold Falling (V)
3.75
3.6
3.45
-60
-30
0
30 60
Temperature (°C)
90
120
150
D001
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
D002
图 2. Supply Current ON (IQON) vs Supply Voltage (VIN
)
图 1. POR Threshold (VPOR) vs Temperature
1.3
20
UVLO Threshold Rising (V)
UVLO Threshold Falling (V)
1.25
18
16
14
12
10
8
1.2
1.15
1.1
1.05
1
-40
0
40 80
Temperature (°C)
120
160
D004
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
D003
图 3. Supply Current OFF (IQOFF) vs Supply Voltage (VIN
)
图 4. UVLO Thresholds (VUVLOR, VUVLOF) vs Temperature
1.28
24.52
OVP Threshold Rising (V)
OVP Threshold Falling (V)
1.24
24.54
24.56
24.58
24.6
1.2
1.16
1.12
1.08
1.04
24.62
-40
0
40 80
Temperature (°C)
120
160
-50
-25
0
25 50
Temperature (°C)
75
100
125
D005
D006
图 5. OVP Thresholds (VOVPR, VOVPF) vs Temperature
图 6. GAIN(dVdT) vs Temperature
8
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Typical Characteristics (接下页)
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
2.5
10
8
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
2
1.5
1
6
4
0.5
0
2
0
25
50 75
RILIM (kOhm)
100
125
0
D007
0
6
12
18
24
30
36
42
VIN (V)
D008
TA = -40 to 125 °C
图 8. ILIM Accuracy vs Supply Voltage
图 7. ILIM vs RILIM
4.5
4
79.25
79
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
78.75
78.5
78.25
78
3.5
3
2.5
2
77.75
77.5
77.25
77
1.5
1
0.5
0
76.75
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D009
D010
图 9. ILIM Accuracy vs Temperature with VIN = 12 V
图 10. GAIN(IMON) vs Temperature
180
240
220
200
180
160
140
120
100
160
140
120
100
80
60
40
20
0
0
0.25 0.5 0.75
1 1.25 1.5 1.75
IOUT (A)
2
2.25
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D011
D012
图 11. IMON vs IOUT
图 12. RON vs Temperature
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Typical Characteristics (接下页)
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
-4
-4.5
-5
-5
-5.5
-6
-6.5
-7
-5.5
-6
-7.5
-8
-6.5
-7
-8.5
-9
-7.5
-8
-9.5
-10
-10.5
-8.5
-9
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D013
D014
V(OUT) = 24 V
V(IN) = 0 V
VSHDN = 0 V
V(OUT) = 0 V
V(IN) = –24 V
VSHDN = 0 V
图 13. Ilkg(OUT) vs Temperature with VIN = 0 V
图 14. Ilkg(OUT) vs Temperature with VIN = –24 V
11.6
11.4
11.2
11
95.4
95.2
95
94.8
94.6
94.4
94.2
94
10.8
10.6
10.4
10.2
10
93.8
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D015
D016
图 15. VREVTH vs Temperature
图 16. VFWDTH vs Temperature
4.5
4
100000
10000
1000
100
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
TA = -40 èC
TA = 25 èC
TA = 85 èC
TA = 105 èC
TA = 125 èC
3.5
3
2.5
2
1.5
1
10
1
0.5
0
0.2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
1
2
3
4
5 6 7 8 10
Power Dissipation (W)
20 30 40 50 70 100
D017
D018
Taken on 2-layer PCB with 0.07-mm thick copper and copper area of
10.5 cm2 connected to PowerPAD.
图 17. ILIM Accuracy vs Temperature with VIN = 24 V
图 18. Thermal Shutdown Time vs Power Dissipation
10
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ZHCSK76 –SEPTEMBER 2019
7 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
-20 mV
110 mV
V(IN) -V(OUT)
V(IN) -V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
0
time
tFWD(dly)
I(FASTRIP)
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
0
time
tOVP(dly)
tFASTRIP(dly)
图 19. Timing Waveforms
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8 Detailed Description
8.1 Overview
LM74202-Q1 is an ideal diode with integrated back-to-back FETs and enhanced built-in protection circuitry. It
provides robust protection for all systems and applications powered from 4.2 V to 40 V. The device integrates
reverse battery input, reverse current, overvoltage, undervoltage, overcurrent and short circuit protection. The
precision overcurrent limit (±5% at 1A) helps to minimize over design of the input power supply, while the fast
response short circuit protection immediately isolates the load from input when a short circuit is detected. The
device allows the user to program the overcurrent limit threshold between 0.1 A and 2.23 A with an external
resistor. The device monitors the bus voltage for brown-out and overvoltage protection, asserting the FLTb pin to
notify downstream systems.
The device is designed to protect systems such as ADAS camera supplies against sudden output short to battery
events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when output short to
battery fault condition or input power fail condition is detected. The internal robust protection control blocks of the
LM74202-Q1 device along with its ±40 V rating helps to simplify the system designs for the various ISO and
LV124 compliance ensuring complete protection of the load and the device.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected. The LM74202-Q1 device is also designed to control redundant power supply
systems.
Additional features of the LM74202-Q1 device include:
•
•
•
•
•
•
•
•
Reverse input battery protection
Reverse current blocking
Current monitor output for health monitoring of the system
Electronic circuit breaker operation with overload timeout using MODE pin
A choice of latch off or automatic restart mode response during current limit fault using MODE pin
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)
12
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8.2 Functional Block Diagram
OUT
IN
150 mΩ
-10 mV
+
+
PORb
Charge
Pump
+100 mV
4 V
3.72 V
X78.2 µ
Current
Sense
CP
UVLOb
UVLO
1.19 V
1.1 V
REVERSE
SWEN
Gate Control Logic
Current Limit Amp
IMON
TSD
Thermal
Shutdown
+
Fast-Trip Comp
(Threshold=1.8 x IOL)
1.19 V
1.1 V
OVP
1 V
OLR
SHDNb
ILIM
OVP
Short detect
Ramp Control
24.6 x
SWEN
Avdd
FLT
I(LOAD) ≥ I(CB)
* Only for Latch Mode
OLR
SET
Timeout
5 µA
4 msec
timer
S
Q
dVdT
RTN
85 Ω
UVLOb
PORb
TSD
CLR
R
Q
1.8 msec
900 µs
RdVdT
PORb
Fault Latch
Avdd
SHDNb
Gate Enhanced (tPGOOD
)
OLR
400 kΩ
Avdd
Overload fault response
select detection
Reverse Input Polarity
Protection circuit
VSHUTx
GND
SHDNb
RTN
+
LM74202-Q1
MODE
SHDN
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
This section describes the undervoltage comparator input. When the voltage at UVLO pin falls below V(UVLOF)
during input power fail or input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The
UVLO comparator has a hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider
network from IN supply to UVLO terminal to RTN as shown in 图 20.
V(IN)
IN
LM74202-Q1
R1
UVLO
+
+
UVLOb
1.19 V
1.1 V
R2
OVP
RTN
OVP
1.19 V
1.1 V
R3
GND
图 20. UVLO and OVP Thresholds Set by R1, R2 and R3
If the undervoltage lockout (UVLO) function is not needed, the UVLO terminal must be connected to the IN
terminal. UVLO terminal must not be left floating.
The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables
the internal circuitry when the IN terminal voltage falls below internal POR threshold V(PORF). The internal POR
threshold has a hysteresis of 275 mV.
8.3.2 Overvoltage Protection (OVP)
The device incorporates circuitry to protect the system during overvoltage conditions. This device features an
overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects
the downstream load. To program the OVP threshold, connect a resistor divider from IN supply to OVP terminal
to RTN as shown in 图 21. OVP Overvoltage Cut-off response is shown in 图 22. OVP pin must not be left
floating. If OVP pin could be floating due to dry soldering, an additional zener diode at the output will be required
for protection from over voltage.
14
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Feature Description (接下页)
V(IN)
IN
LM74202-Q1
UVLOb
R1
UVLO
+
+
1.19 V
R2
1.1 V
OVP
OVP
1.19 V
R3
1.1 V
RTN
GND
图 21. OVP Threshold Setting
图 22. OVP Overvoltage Cut-Off
Programmable overvoltage clamp can also be achieved using LM74202-Q1 by connecting the resistor ladder
from Vout to OVP to RTN as shown in 图 23 . This results in clamping of output voltage close to OVP set-point
by resistors R1 and R2. as shown in 图 24. This scheme will also help in achieving minimal system Iq during off
state. For this OVP configurataion, use R1 > 90 kΩ.
V(IN)
V(OUT)
IN
LM74202-Q1
UVLOb
UVLO
R1
(>90 kꢀ )
+
+
1.19 V
1.1 V
OVP
OVP
R2
OVP
1.19 V
1.1 V
RTN
GND
图 24. Programmable Overvoltage Clamp Response
图 23. Programmable OV Clamp
If the OVP pin is connected to GND, the device will clamp the output voltage to 37.5 V (typical).
8.3.3 Reverse Battery Protection
To protect the electronic systems from reverse battery voltage due to miswiring, often a power component like a
schottky diode is added in series with the supply line as shown in 图 25. These additional discretes result in a
lossy and bulky protection solution. The LM74202-Q1 devices feature fully integrated reverse input supply
protection and does not need an additional diode. These devices can withstand a reverse voltage of –40 V
without damage. 图 26 illustrates the reverse input polarity protection functionality.
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Feature Description (接下页)
OUTPUT
INPUT
INPUT
OUTPUT
LM74202-Q1
Hot-Swap Controller
GND
GND
图 25. Reverse Battery Protection Circuits - Discrete vs LM74202-Q1
图 26. Reverse Input Supply Protection at –40 V
8.3.4 Hot Plug-In and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the supply voltage and prevents unintended resets of the system
power. The controlled start-up also helps to eliminate conductive and radiative interferences. An external
capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on as shown
in 图 27 and 图 28.
16
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ZHCSK76 –SEPTEMBER 2019
Feature Description (接下页)
LM74202-Q1
4 V
5 µA
dVdT
RTN
RdVdT
SWENb
C(dVdT)
GND
图 27. Output Ramp Up Time tdVdT is Set by C(dVdT)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 23.9 V / 1.6 ms. A capacitor can be
connected from dVdT pin to RTN to program the output voltage slew rate slower than 23.9 V / 1.6 ms. Use 公式
1 and 公式 2 to calculate the external C(dVdT) capacitance.
公式 1 governs slew rate at start-up.
æ
ç
ö
÷
C dVdT
dV
OUT
æ
ö
÷
÷
ø
(
)
(
)
I(dVdT)
=
´ ç
ç
ç
è
÷
ø
Gain dVdT
dt
(
)
è
where
•
I(dVdT) = 4.7 µA (typical)
dV
(
dt
OUT
)
•
•
Gain(dVdT) = dVdT to VOUT gain = 24.6
(1)
(2)
(3)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using 公式 2.
tdVdT = 8.7 × 103 × V(IN) × C(dVdT)
The inrush current can be calculated by 公式 3
IINRUSH = COUT/[8.7 x 103 x CdVdT
]
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Feature Description (接下页)
VIN
CdVdT = 22 nF
COUT = 47 µF
RILIM = 5.36 kΩ
图 28. Hot Plug-In and In-Rush Current Control at 24-V Input
8.3.5 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
8.3.5.1 Overload Protection
The device offers following choices for the overload protection fault response:
•
•
Active current limiting (Auto-retry and Latch-off modes)
Electronic Circuit Breaker with overload timeout (Auto-retry mode)
See the configurations in 表 1 to select a specific overload fault response.
表 1. Overload Fault Response Configuration
MODE Pin Configuration
Open
Overload Protection Type
Electronic circuit breaker with auto-retry
Active current limiting with auto-retry
Shorted to RTN
A 402-kΩ resistor across MODE pin to RTN
Active current limiting with latch-off
pin
8.3.5.1.1 Active Current Limiting
When the active current limiting mode is selected, during overload events, the device continuously regulates the
load current to the overcurrent limit I(OL) programmed by the R(ILIM) resistor as shown in 公式 4.
12
IOL
=
R(ILIM
)
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(4)
During an overload condition, the internal current-limit amplifier regulates the output current to I(LIM). The FLT
signal assert after a delay of tPGOODF. The output voltage droops during the current regulation, resulting in
increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown
threshold (T(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is
reset by either of the following conditions:
18
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ZHCSK76 –SEPTEMBER 2019
•
•
Cycling V(IN) below V(PORF)
Toggling SHDN
When the device is configured in auto-retry mode, it commences an auto-retry cycle tCBretry(dly) ms after TJ <
[T(TSD) – 10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes
normal operation. 图 29 and 图 30 illustrates the behavior of the system during current limiting with auto-retry
functionality.
IMON
V_OUT
FLTb
I_IN
Load transition from 22 Ω to
12 Ω
MODE pin connected to RTN
RILIM = 5.36 kΩ
RILIM = 8 kΩ
图 29. Auto-Retry MODE Fault Behavior
图 30. Response During Coming Out of Overload Fault
8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
In this mode, during overload events, the device allows the overload current to flow through the device until
I(LOAD) < I(FASTRIP). The circuit breaker threshold I(CB) can be programmed using the R(ILIM) resistor, as shown in 公
式 5.
12
I(CB) =
+ 0.03A
R(ILIM
)
where
•
•
I(CB) is circuit breaker current threshold in A
R(ILIM) is the current limit resistor in kΩ
(5)
The device commences an auto-retry cycle after a delay of tCBretry(dly). The FLT signal remains asserted until the
fault condition is removed and the device resumes normal operation. 图 31 and 图 32 illustrate behavior of the
system during electronic circuit breaker with auto-retry functionality.
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IMON
V_OUT
FLTb
I_IN
MODE left floating
Load Transition from 22 Ω to 12 Ω
Load Transition from 22 Ω to 12 Ω , RILIM = 8 kΩ
RILIM = 8 kΩ
图 31. Circuit Breaker Functionality
图 32. Zoomed at the Instance of Load Step
8.3.5.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases very rapidly. As the current-
limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). The fast-trip comparator turns off the internal FET after a duration of
tFASTTRIP(dly), when the current through the FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid
short-circuit peak current. The fast-trip threshold is internally set to 87% higher than the programmed overload
current limit (I(FASTRIP) = 1.87 × I(OL) + 0.015). The fast-trip circuit holds the internal FET off for only a few
microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output
current to I(OL). Then the device behaves similar to overload condition. 图 33 and 图 34 illustrate the behavior of
the system when the current exceeds the fast-trip threshold.
VIN = 24 V, RILIM = 5.36 kΩ
图 33. Output Hot Short Functionality at 24-V Input
图 34. Zoomed at the Instance of Output Short
20
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ZHCSK76 –SEPTEMBER 2019
8.3.5.2.1 Start-Up With Short-Circuit On Output
When the device is started with a short-circuit on the output end, it limits the load current to the current limit I(OL)
,
and behaves similarly to the overload condition. 图 35 illustrates the behavior of the device in this condition. This
feature helps in quick isolation of the fault and hence ensures stability of the DC bus.
V_IN
V_OUT
FLTb
I_IN
MODE pin connected to RTN
VIN = 24 V RILIM = 5.36 kΩ
图 35. Start-Up With Short on Output
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8.3.5.3 FAULT Response
The FLT open-drain output asserts (active low) under following conditions:
•
•
•
Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions
When the device enters low current shutdown mode when SHDN is pulled low
During start-up when the internal FET GATE is not fully enhanced (for example: VOUT has not reached VIN).
The FLT output does not assert in the event of reverse voltage on Input.
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An
internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in
dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced and VOUT has reached VIN. The PGOOD signal has deglitch time incorporated to
ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising
deglitch delay is determined by tPGOOD(degl) = Maximum {(900 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and
tPGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) resets
FLT.
8.3.5.3.1 Look Ahead Overload Current Fault Indicator
With the device configured in current limit operation and when the overload condition exists for more than
tPGOODF, the FLT asserts to warn of impending turnoff of the internal FETs due to the subsequent thermal
shutdown event. 图 36 and 图 37 depict this behavior. The FLT signal remains asserted until the fault condition is
removed and the device resumes normal operation.
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
图 36. Look Ahead Overload Current Fault Indication
图 37. Output Turnoff Due to Thermal Shutdown With FLT
Asserted in Advance
8.3.5.4 Current Monitoring
The current source at IMON terminal is internally configured to be proportional to the current flowing from IN to
OUT. This current can be converted into a voltage using a resistor R(IMON) from IMON terminal to RTN terminal.
The IMON voltage can be used as a means of monitoring current flow through the system. The maximum voltage
range (V(IMONmax) for monitoring the current is limited to minimum of ([V(IN) – 1.5 V, 4 V]) to ensure linear output.
This puts a limitation on maximum value of R(IMON) resistor and is determined by 公式 6.
Min [(V(IN) - 1.5), 4 V]
R
(
IMONmax
)
=
1.8 ì I
(
LIM
)
ì GAIN
(
IMON
)
(6)
22
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ZHCSK76 –SEPTEMBER 2019
The output voltage at IMON terminal is calculated using 公式 7 and 公式 8.
For IOUT > 50 mA,
V
(
IMON
)
= I
[
(
OUT
)
ìGAIN
(
IMON
)
ìR
(
IMON
)
]
Where,
•
•
•
GAIN(IMON) is the gain factor I(IMON):I(OUT)
I(OUT) is the load current
I(MON_OS) = 2 µA (Typical)
(7)
For IOUT < 50 mA (typical), IMON output current is close to I(MON_OS) and 公式 8 provides the voltage output with
RIMON
.
V
(
IMON
)
= (I(IMON _ OS))ìR(IMON)
(8)
This pin must not have a bypass capacitor to avoid delay in the current monitoring information.
In case of reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC
input to limit the current through the ESD protection structures of the ADC.
8.3.5.5 IN, OUT, RTN and GND Pins
The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the
power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus
transients. The recommended input operating voltage range is 4.2 V to 40 V. Similarly all OUT pins must be
connected together and to the load. V(OUT), in the ON condition, is calculated using 公式 9.
V
(
OUT
)
= V
(
IN
)
- RON ì I
(
(
OUT
)
)
Where,
•
RON is the total ON resistance of the internal FETs.
(9)
The GND pin must be connected to the system ground. RTN is the device ground reference for all the internal
control blocks. Connect the device support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO
and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between
RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection
feature. if negative input voltage is applied on IN pins with RTN pin connected to GND, the device can get
damaged.
8.3.5.6 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 540 ms after TJ < [T(TSD) – 10°C]. During the thermal
shutdown, the fault pin FLT pulls low to indicate a fault condition.
版权 © 2019, Texas Instruments Incorporated
23
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
8.3.5.7 Low Current Shutdown Control (SHDN)
The internal FETs and hence the load current can be switched off by pulling the SHDN pin below V(SHUTF)
threshold with a micro-controller GPIO pin as shown in 图 38. The device quiescent current reduces to 16 μA
(typical) in shutdown state. To assert SHDN low, the pull down must sink at least 10 µA at 400 mV. To enable
the device, SHDN must be pulled up to V(SHUTR) threshold. Once the device is enabled, the internal FETs turns
on with dVdT mode.
LM74202-Q1
AVdd
Rpu
from µC
GPIO
SHDN
GND
+
SHDNb
VSHUTx
OFF ON
图 38. Shutdown Control
8.4 Device Functional Modes
The device responds differently to overload and short circuit conditions. The operational differences are
explained in 表 2.
表 2. Device Operational Differences Under Different MODE Configurations
A 402-KΩ Resistor Connected
Between Mode And RTN Pins
(Current Limit With Latchoff)
Mode Connected To RTN
(Current Limit With Auto-Retry)
Mode Pin Configuration
Start-up
Mode Pin = Open
Inrush current controlled by dVdT
Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set
by R(ILIM)
by R(ILIM)
by R(ILIM)
Fault timer runs when current is
limited to I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
If TJ > T(TSD), device turns off
If TJ > T(TSD), device turns off
Device turns off if TJ > T(TSD)
before timer expires
Overcurrent response
Current is limited to I(OL) level as Current is limited to I(OL) level as Current is allowed through the
set by R(ILIM)
set by R(ILIM)
device if I(LOAD) < I(FASTTRIP)
Power dissipation increases as
V(IN) – V(OUT) increases
Power dissipation increases as
V(IN) – V(OUT) increases
Fault timer runs when the current
increases above I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
Device turns off when TJ > T(TSD) Device turns off when TJ > T(TSD) Device turns off if TJ > T(TSD)
before timer expires
Device attempts restart 540 ms
after TJ < [T(TSD) – 10°C]
Device remains off
Device attempts restart 540 ms
after TJ < [T(TSD) – 10°C].
Short-circuit response
Fast turnoff when I(LOAD) > I(FASTRIP)
Quick restart and current limited to I(OL), follows standard start-up
24
版权 © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is an automotive ideal diode, typically used for load protection in automotive applications. It can
operate from 12-V battery with programmable current limit, overvoltage, undervoltage and reverse polarity
protections. The device provides robust protection against reverse current and transients (such as ISO 7637-2
Pulse 1 and ISO 16750-2 Pulse 5b) due to cables and switches in different automotive systems such as an ECU.
The device also provides robust protection for output short to battery, output short to GND, reverse battery and
input overvoltage.
The Detailed Design Procedure section can be used to select component values for the device.
9.2 Typical Application
IN
OUT
D2
VIN: 4.2 V - 32 V
OUT
FLT
CIN
1 µF
COUT
47 µF
150 mΩ
RFLTb
100 k
R1
97.6 k
UVLO
OVP
Health Monitor
R3
LM74202-Q1
SMBJ28CA
ON/OFF Control
SHDN
IMON
dVdT
Load
Monitor
(1)OVP
R2
5.11 k
MODE
RTN
ILIM
RIMON
20 k
CdVdT
12 nF
GND
RILIM
5.36 k
R4
(1) OVP connection for Programmable over voltage clamp. See Overvoltage Protection (OVP).
图 39. 12-V, 2-A Ideal Diode Load Protection Circuit for Automotive ECU
9.2.1 Design Requirements
表 3 shows the Design Requirements for LM74202-Q1. In addition to below requirements, the circuit is designed
to provide protection for transients as per ISO 7637-2 Pulse 1 and ISO 16750-2 Pulse 5b.
表 3. Design Requirements
DESIGN PARAMETER
Typical input voltage
EXAMPLE VALUE
V(IN)
4.2 to 32 V
4 V
V(UV)
V(OV)
I(LIM)
Undervoltage lockout set point
Overvoltage cutoff set point
Current limit
24 V
2.23 A
47 µF
2 A
C(OUT)
I(LOAD)
Load capacitance
Load current
9.2.2 Detailed Design Procedure
9.2.2.1 Step by Step Design Procedure
To begin the design process, the designer must know the following parameters:
•
Operating voltage range
版权 © 2019, Texas Instruments Incorporated
25
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
•
•
•
•
Maximum output capacitance
Start-up time
Maximum current limit
Transient voltage levels
9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range
To provide operation in cold crank conditions for automotive batteries, the UVLO is set to POR value (4 V) by
connecting UVLO to IN pin and OVP threshold is set from resistors connected from IN pins to provide protection
from transient during ISO 16750 Pulse 5b. During the ISO 16750 5b transient, output voltage is cut-off at 24 V
and provides protection to load from high input voltage during the transient. The overvoltage threshold is
calculated by 公式 10.
VOVPR = R2/(R1 + R2) × VOV
where
•
•
Overvoltage threshold rising, VOVPR = 1.19 V
VOV is overvoltage protection voltage (= 24 V)
(10)
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R23) must be chosen to be 20x greater than the leakage
current of OVP pin.
9.2.2.3 Programming the Current-Limit Threshold—R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using 公式 4.
R(ILIM) = 5.36 kΩ was selected to set ILIM to 2.23 A.
9.2.2.4 Programming Current Monitoring Resistor—RIMON
The voltage at IMON pin V(IMON) represents the voltage proportional to the load current. This can be connected to
an ADC of the downstream system for health monitoring of the system. The R(IMON) must be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using 公式 11.
V(IMONmax)
I(LIM) ì75 ì10-6
R(IMON) =
(11)
For current monitoring up-to a current of 2.2 A, and considering the operating input voltage range of ADC from 0
V to 4 V, V(IMONmax) is 4 V and R(IMON) is selected as 20 kΩ.
9.2.2.5 Limiting the Inrush Current
To limit the inrush current and power dissipation during start-up, an appropriate value of CdVdT must be selected.
The inrush current during start-up is estimated by 公式 12. A 12nF capacitance is selected for CdVdT to keep
inrush current less than 0.5 A.
IINRUSH = COUT / [8.7 × 103 × CdVdt
]
(12)
9.2.2.5.1 Selection of Input TVS for Transient Protection
To protect the device and the load from input transients exceeding the absolute maximum ratings of the device, a
TVS diode is required at input of the device. To meet the requirements of protection for ISO 16750 pulse 5b and
ISO 7637 pulse 1 as per 表 4, SMBJ28CA is selected for protection from transients.
表 4. Input TVS Selection for Transients
ISO 7637 Pulse 1
and Reverse Battery
Parameter
ISO 16750 Pulse 5b
Maximum Transient Voltage of Pulse
(VT)
A bidirectional TVS is required to protect
from positive and negative transients
35 V
-150V
Ri = Source impedance.
For ISO 16750 Pulse 5b; Ri = 0.5 Ω
For ISO 7637 Pulse 1;Ri = 10 Ω
Pulse Current through TVS (IPulse
)
(VT - VC)/(Ri)
(VT - VC)/(Ri)
26
版权 © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
表 4. Input TVS Selection for Transients (接下页)
ISO 7637 Pulse 1
ISO 16750 Pulse 5b
Parameter
and Reverse Battery
To keep input voltage below absolute
maximum rating of the device. See 公式 13
for VC
Clamping voltage of TVS (VC) at Pulse
current IPulse
< 55 V
> 32V
> –(55 - VOUT-Max) V
To operate with maximum operating input
voltage and to protect from maximum
reverse battery voltage
Breakdown voltage of TVS (VBR
)
> 14V
VC = VBR + IPulse × [VClamp-max - VBR]/[IPP - IT]
where
•
•
•
•
VC is the clamping voltage of TVS at IPulse current through it.
VBR is break down voltage of TVS with IT test current through it.
VClamp-max is maximum clamping voltage of TVS at peak pulse current IPP
VBR, IT, VClamp-max and IPP are the specifications of the TVS diode.
(13)
9.2.3 Application Curves
图 40. Protection from Output Short to GND [VIN = 12 V,
图 41. Protection from Output short to Battery [VIN
=
ILIM = 2.23 A, MODE = RTN]
Floating, VOUT = 12 V, ILIM = 2.23 A, MODE = RTN ]
图 42. Protection from ISO 7637-2 Pulse 1 [12 V Battery,
Transient Voltage = –150 V , RLOAD = 14 Ω]
图 43. Protection from ISO 16750-2 Pulse 5b [12 V Battery,
Transient Voltage = 35 V , RLOAD = 14 Ω]
版权 © 2019, Texas Instruments Incorporated
27
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
图 44. Protection from Reverse Battery [VIN = -12 V, VOUT
0 V, ILIM = 2.23 A ]
=
图 45. Protection from overvoltage at Input [VIN = 36 V,
RLOAD = 14 Ω, ILIM = 2.23 A ]
28
版权 © 2019, Texas Instruments Incorporated
LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
10 Power Supply Recommendations
The device is designed for the supply voltage range of 4.2 V ≤ VIN ≤ 40 V. Power supply must be rated higher
than the current limit set to avoid voltage droops during overcurrent and short circuit conditions.
10.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A ceramic capacitor at input (C(IN)) with value more than 1µF to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with 公式 14.
L IN
( )
Vspike Absolute = V IN + I Load
´
(
)
( )
(
)
C IN
( )
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(14)
Automotive applications could require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients include ISO 7637 Pulse 1, Output
short to battery, Output short to GND and reverse battery at input.
The circuit implementation with optional protection components (TVS Diode at Input and schottky diode at
output) is shown in 图 46. For protection from automotive transients similar to ISO 7637 Pulse 1, Output short to
battery , output short to GND and reverse battery, use CIN ≥ 1 µF and COUT ≥ 3.3 µF. For selection of TVS diode
and other components, see Application Information.
INPUT
IN
OUT
OUTPUT
CIN
COUT
R4
R1
R2
(≥ 1 µF)
150 mꢀ
(≥ 3.3 µF)
UVLO
FLT
*
*
LM74202-Q1
OVP
MODE
dVdT
SHDN
IMON
ILIM
GND
RTN
R3
RILIM
RIMON
CdVdT
* Optional components needed for suppression of transients
图 46. Circuit Implementation for Automotive Transient Protection
版权 © 2019, Texas Instruments Incorporated
29
LM74202-Q1
ZHCSK76 –SEPTEMBER 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
•
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND. Use CIN ≥ 1 µF for automotive transient protection. See Transient Protection.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the device. See 图 47 for PCB layout example with HTSSOP package.
•
High current carrying power path connections must be as short as possible and must be sized to carry atleast
twice the full-load current.
•
•
RTN, which is the reference ground for the device must be a copper plane or island.
Locate all the device support components R(ILIM), C(dVdT), R(IMON), and MODE, UVLO, OVP resistors close to
their connection pin. Connect the other end of the component to the RTN with shortest trace length.
•
•
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
•
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
30
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LM74202-Q1
www.ti.com.cn
ZHCSK76 –SEPTEMBER 2019
11.2 Layout Example
Top Layer
Bottom layer GND plane
Via to Bottom Layer
Track in bottom layer
Top Layer RTN Plane
Bottom Layer RTN Plane
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
OUT
IN
IN
OUT
FLT
VOUT PLANE
VIN PLANE
UVLO
N.C
N.C
PWP
OVP
dVdT
MODE
SHDN
RTN
ILIM
IMON
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
图 47. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB
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31
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ZHCSK76 –SEPTEMBER 2019
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档:
•
《LM76202-Q1 EVM 用户指南》
12.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74202QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
M74202Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
6
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
PIN 1 INDEX
SEATING
PLANE
A
0.1 C
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
0.25
GAGE PLANE
1.2 MAX
2X 1.15 MAX
NOTE 5
0.15
0.05
0.75
0.50
8
9
0 -8
A
15
DETAIL A
TYPICAL
2X 0.3 MAX
NOTE 5
2.46
2.16
17
THERMAL
PAD
1
16
2.66
2.36
4223630/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.66)
METAL COVERED
BY SOLDER MASK
16X (1.5)
SYMM
1
16
(0.6) TYP
16X (0.45)
(R0.05) TYP
SYMM
(5)
NOTE 9
17
(1.2)
TYP
(2.46)
14X (0.65)
9
8
0.2) TYP
(
(1.2) TYP
VIA
SEE DETAILS
(5.8)
SOLDER MASK
DEFINED PAD
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4223630/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.66)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
16X (1.5)
1
16
16X (0.45)
(R0.05) TYP
(2.46)
SYMM
17
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SEE TABLE FOR
SYMM
(5.8)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.97 X 2.75
2.66 X 2.46 (SHOWN)
2.43 X 2.25
0.125
0.15
0.175
2.25 X 2.08
4223630/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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