LM5149 [TI]
具有超低 IQ 和集成式有源 EMI 滤波器的 80V 同步降压直流/直流控制器;
| 型号： | LM5149 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低 IQ 和集成式有源 EMI 滤波器的 80V 同步降压直流/直流控制器 控制器 |
| 文件： | 总73页 (文件大小：6366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5149
ZHCSLO6A –DECEMBER 2020 –REVISED JANUARY 2023
LM5149 具有超低IQ 和集成式有源EMI 滤波器的80V 同步降压直流/直流控制器
1 特性
2 应用
• 功能安全型
• 楼宇自动化
• 工业运输
• 无线基础设施
• 测试和测量
– 可帮助进行功能安全系统设计的文档
• 两个集成式EMI 缓解机制
– 有源EMI 滤波器，可提高低频下的EMI 性能
– 可选双随机展频(DRSS)，可增强低频和高频频
带上的EMI 降低性能
3 说明
LM5149 是一款 80V 超低 IQ 同步降压直流/直流控制
器，适合高电流单输出应用。该控制器使用峰值电流模
式控制架构，可实现简单环路补偿、快速瞬态响应和出
色的负载和线路调节性能。LM5149 可设置为以交错双
相模式运行，实现精确的电流共享，适合高电流应用。
该器件可在低至 3.5V 的 VIN 和接近 100% 的占空比
（如果需要）下运行。
– EMI 平均降低了25dBµV
– 将外部差分模式输入滤波器尺寸减小了50% 并
降低了系统成本
– 针对CISPR 32 B 类要求进行了优化
• 多功能同步降压直流/直流控制器
– 宽输入电压范围为3.5V 至80V
– 1% 精度、固定3.3V/5V/12V 或0.8V 至55V 可
调输出电压
– 150°C 最大结温
– 关断模式电流：2.3µA
LM5149 有两个独特的 EMI 降低特性：有源 EMI 滤波
器和双随机展频 (DRSS)。有源 EMI 滤波器可检测直
流输入总线上的任何噪声或纹波电压，并注入异相消除
信号以减少干扰。DRSS 将低频三角调制与高频随机
调制相结合，可分别在低频和高频频带上降低 EMI。
此项混合技术符合业界通用的 EMC 测试中指定的多种
分辨率带宽(RBW) 设置。
– 空载睡眠电流：9.5µA
– 最多可堆叠两个相位
– 先进的压降（含频率折返）
• 开关频率范围为100kHz 至2.2MHz
– 同步输入和同步输出功能
• 固有保护特性，可实现稳健的设计
– 内部断续模式过流保护
封装信息
封装(1)
封装尺寸（标称值）
器件型号
LM5149
RGY（VQFN，24） 3.50mm × 5.50mm
– 使能和PGOOD 功能
– VCC、VDDA 和栅极驱动UVLO 保护
– 内部或外部环路补偿
– 具有迟滞功能的热关断保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录
• 使用LM5149 并借助WEBENCH® Power Designer
创建定制设计方案
LIN
VIN = 5.5 V...36 V
0.68 µH
CINJ
RINC
0.47 F
0.47
CSEN
0.1
CDAMP1
47
Tie to VOUT
or GND
CIN
3 ꢀ 10
F
F
F
RDAMP
CINC
0.1
CVCC
2.2
3
F
F
VCCX VCC
VIN
EN
CBOOT
HO
CAEFC
RAEFC
CBOOT
0.1
VDDA
Q1
VOUT = 5 V
IOUT = 8 A
RFB
24.9 k
F
RS
5 m
LO
FB
1 nF 200
0.68
Q2
H
SW
CO
CCOMP
2.7 nF
RCOMP
10 k
RAEFDC
49.9 k
EXTCOMP
4 ꢀ 47
F
LM5149
LO
PGND
CHF
N/A
ISNS+
VOUT
INJ
SENSE
To AEF
sense point
REFAGND
PG/SYNCOUT
PFM/SYNC
VCC
AEFVDDA
RAEFVDD
3
AVSS CNFG
RT
VDDA
AGND
CAEFVDD
2.2
* VOUT tracks VIN if VIN < 5.2 V
F
RCNFG
24.9 k
RRT
9.52 k
CVDDA
0.1
CISPR 25 Class 5 Peak
Start 150 kHz
Stop 30 MHz
F
CISPR 25 Class 5 Average
典型应用原理图
CISPR 25 EMI 性能- 150kHz 至30MHz
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBV4
LM5149
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ZHCSLO6A –DECEMBER 2020 –REVISED JANUARY 2023
Table of Contents
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Applications.................................................. 37
9.3 Power Supply Recommendations.............................56
9.4 Layout....................................................................... 56
10 Device and Documentation Support..........................62
10.1 Device Support....................................................... 62
10.2 Documentation Support.......................................... 63
10.3 接收文档更新通知................................................... 64
10.4 支持资源..................................................................64
10.5 Trademarks.............................................................64
10.6 静电放电警告.......................................................... 64
10.7 术语表..................................................................... 64
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Active EMI Filter..........................................................9
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
Information.................................................................... 64
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2020) to Revision A (January 2023)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 说明（续）
LM5149 的其他特性包括 150°C 最大工作结温、可在轻负载条件下降低电流消耗的用户可选二极管仿真功能、用
于故障报告和输出监控的开漏电源正常标志、精密使能输入、单调启动至预偏置负载、集成VCC 偏置电源稳压器
和自举二极管、3ms 内部软启动时间和带自动恢复功能的热关断保护。
LM5149 控制器采用3.5mm × 5.5mm 热增强型24 引脚VQFN 封装，该封装具有外露焊盘，有助于散热。
6 Pin Configuration and Functions
INJ
CNFG
RT
2
3
4
5
23
22
21
20
19
18
17
16
15
14
SEN
AEFVDDA
VOUT
EXTCOMP
FB
ISNS+
Exposed
Pad
EN
6
7
(EP)
PFM/SYNC
PG/SYNCOUT
VCCX
AGND
VDDA
VCC
8
9
CBOOT
SW
PGND
LO
10
11
Connect the exposed pad to AGND and PGND on the PCB.
图6-1. 24-Pin VQFN RGY Package (Top View)
表6-1. Pin Functions
PIN
NAME
I/O(1)
DESCRIPTION
NO.
1
AVSS
INJ
G
O
Active EMI bias ground connection
Active EMI injection output
2
Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved
operation. After start-up, use CNFG to enable AEF.
3
4
5
CNFG
RT
1
I
Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz
and 2.2 MHz.
The output of the transconductance error amplifier. If used, connect the compensation network from
EXTCOMP to AGND.
EXTCOMP
O
Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB using a 24.9 kΩor 49.9 kΩto VDDA
to set the output voltage to 5 V or 12 V, respectively. Install a resistor divider from VOUT to AGND to set
the output voltage setpoint between 0.8 V and 55 V. The regulation voltage at FB is 0.8 V.
6
FB
I
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表6-1. Pin Functions (continued)
PIN
NAME
I/O(1)
DESCRIPTION
NO.
7
AGND
VDDA
VCC
PGND
LO
G
O
P
Analog ground connection. Ground return for the internal voltage reference and analog circuits.
Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
VCC bias supply pin. Connect ceramic capacitors between VCC and PGND.
Power ground connection pin for low-side power MOSEFT gate driver
Low-side power MOSFET gate driver output
8
9
10
11
12
13
G
O
P
VIN
Supply voltage input source for the VCC regulators
HO
O
High-side power MOSFET gate driver output
Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor,
the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
14
15
16
SW
P
P
P
CBOOT
VCCX
High-side driver supply for bootstrap gate drive
Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the
internal VCC regulator is disabled.
An open-collector output that goes low if VOUT is outside the specified regulation window. The PG/
SYNCOUT pin of the primary controller in dual-phase mode provides a 180° phase-shifted SYNCOUT
signal.
17
18
19
20
21
PG/SYNCOUT
PFM/SYNC
EN
P
I
Connect PFM/SYNC to VDDA to enable diode emulation mode. Connect PFM to GND to operate the
LM5149 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM/SYNC can also be
used as a synchronization input to synchronize the internal oscillator to an external clock.
An active-high precision input with rising threshold of 1 V and hysteresis current of 10 µA. If the EN
voltage is less than 0.5 V, the LM5149 is in shutdown mode, unless a SYNC signal is present on PFM/
SYNC.
I
Current sense amplifier input. Connect the ISNS+ to the inductor side of the external current sense
resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a Kelvin
connection.
ISNS+
I
Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the
current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is
used).
VOUT
I
22
23
24
AEFVDDA
SENSE
P
I
Active EMI bias power. Connect a ceramic capacitor between AEFVDDA and AVSS.
Active EMI sense input
REFAGND
G
Active EMI reference ground
(1) P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40℃to 150℃(unless otherwise noted). (1)
MIN
–0.3
–0.3
–0.3
–5
MAX
UNIT
V
VOUT, ISNS+ to AGND
VOUT to ISNS+
60
0.3
V
HO to SW
VHB + 0.3
V
Output voltage
HO to SW, transient < 20ns
LO to GND
V
VVCC + 0.3
V
–0.3
–1.5
–0.3
–0.3
–5
LO to PGND, transient < 20ns
VIN to PGND
V
85
85
V
SW to PGND
V
SW to PGND, transient < 20 ns
CBOOT to SW
V
6.5
V
–0.3
–5
CBOOT to SW, transient < 20 ns
EN to PGND
V
85
6.5
5.5
5.5
85
V
–0.3
–0.3
–0.3
–0.3
0.3
Input voltage
VCC, VCCX, VDDA, PG, FB, PFM/SYNC, RT, EXTCOMP to AGND
AEFVDDA to AVSS
V
V
INJ to REFAGND
V
SEN to REFAGND
V
REFAGND to AVSS
-0.3
0.3
5.5
150
150
V
CNFG to AGND
V
–0.3
–40
–55
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/
JEDEC JS-002 (2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over operating junction temperature range junction temperature range of –40℃to 150℃(unless otherwise noted).
MIN
NOM
MAX
UNIT
V
VIN
Input supply voltage range
Output voltage range
SW to PGND
3.5
80
VOUT
0.8
55
V
80
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
CBOOT to SW
5
5
5.25
5.25
80
V
FB, EXTCOMP, RT to AGND
EN to PGND
V
V
VCC, VCCX, VDDA to PGND
VOUT, ISNS+ to PGND
PGND to AGND
5.25
55
V
V
0.3
5
V
AEFVDDA to AVSS
INJ to REFAGND
V
5
V
SEN to REFAGND
80
V
REFAGND to AVVS
CNFG to AGND
0.3
5.5
150
V
V
TJ
Operating junction temperature
°C
7.4 Thermal Information
RGY (VQFN)
24 PINS
37.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
32
15.5
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ΨJT
15.5
ΨJB
RθJC(bot)
5.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics.
7.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 8 V to 18 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY (VIN)
IQ-VIN1
VIN shutdown current
VIN standby current
VEN = 0 V
2.3
3.8
µA
µA
IQ-VIN2
124
Non-switching, 0.5 ≤VEN ≤1 V
1.03 V ≤VEN ≤ 80 V, VVOUT = 3.3 V, in
ISLEEP1
Sleep current, 3.3 V
Sleep current, 5.0 V
9.5
9.9
19.7
19.9
µA
µA
regulation, no-load, not switching, VPFM
SYNC = VDDA
/
1.03 V ≤VEN ≤ 80 V, VVOUT = 5 V, in
regulation, no-load, not switching,
ISLEEP2
VPFM SYNC = VDDA
/
ENABLE (EN)
VSDN
Shutdown to standby threshold
Enable voltage rising threshold
Enable hysteresis
VEN rising
0.5
1.0
V
V
VEN-HIGH
VEN rising, enable switching
VEN = 1.1 V
0.95
1.05
IEN-HYS
µA
–12
–10
–8
INTERNAL LDO (VCC)
VVCC-REG
VCC regulation voltage
IVCC = 0 mA to 100 mA
4.7
3.3
5
5.3
3.5
V
V
VVCC-UVLO
VCC UVLO rising threshold
3.4
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7.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 8 V to 18 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
148
170
MAX
UNIT
mV
VVCC-HYST
IVCC-REG
VCC UVLO hysteresis
Internal LDO short-circuit current limit
115
mA
INTERNAL LDO (VDDA)
VVDDA-REG
VVDDA-UVLO
VVDDA-HYST
RVDDA
VDDA regulation voltage
4.75
3
5
3.2
120
5.5
5.25
3.3
V
V
VDDA UVLO rising
VDDA UVLO hysteresis
VDDA resistance
VVCC rising, VVCCX = 0 V
VVCCX = 0 V
VVCCX = 0 V
mV
Ω
EXTERNAL BIAS (VCCX)
VVCCX-ON
VVCCX-HYST
RVCCX
VCCX rising threshold
4.1
4.3
130
2
4.4
V
mV
Ω
VCCX hysteresis voltage
VCCX resistance
REFERENCE VOLTAGE
VREF
Regulated FB voltage
795
800
808
mV
OUTPUT VOLTAGE (VOUT)
RFB = 0 Ω, VIN = 3.8 V to 80 V , internal
VOUT-3.3V-INT
VOUT-3.3V-EXT
VOUT-5V-INT
VOUT-5V-EXT
VOUT-12V-INT
VOUT-12V-EXT
3.3-V output voltage setpoint
3.267
3.267
4.95
3.3
3.3
5.0
5.0
12
3.33
3.33
V
V
V
V
V
V
compensation
RFB = 0 Ω, VIN = 3.8 V to 80 V , internal
compensation
3.3-V output voltage setpoint
5-V output voltage setpoint
RFB = 24.9 kΩ, VIN = 5.5 V to 80 V, internal
compensation
5.05
5-V output voltage setpoint
RFB = 24.9 kΩ, VIN = 5.5 V to 80 V, internal
compensation
4.95
5.05
RFB = 48.7 kΩ, VIN = 24 V to 80 V, Internal
compensation
12-V output setpoint
12-V output setpoint
11.88
11.88
12.12
12.12
RFB = 48.7 kΩ, VIN = 24 V to 80 V, external
compensation
12
RFB-OPT1
RFB-OPT2
5-V output select
12-V output select
23
47
25
50
27
53
kΩ
kΩ
ERROR AMPLIFIER (COMP)
EA transconductance, external
gm-EXTERNAL
FB to COMP
1020
1200
30
µS
µS
compensation
EA transconductance, internal
compensation
gm-INTERNAL
EXTCOMP 10 kΩ to VDDA
IFB
Error amplifier input bias current
COMP clamp voltage
EA source current
75
nA
V
VCOMP-CLAMP
ICOMP-SRC
ICOMP-SINK
RCOMP
VFB = 0 V
2.1
180
180
400
50
VCOMP = 1 V, VFB = 0.6 V
VCOMP = 1 V, VFB = 1 V
EXTCOMP 10 kΩ to VDDA
EXTCOMP 10 kΩ to VDDA
EXTCOMP 10 kΩ to VDDA
µA
µA
kΩ
pF
pF
EA sink current
Internal compensation
Internal compensation
Internal compensation
CCOMP
CCOMP-HF
1
PULSE FREQUENCY MODULATION (PFM)
VPFM-LO
VPFM-HI
VZC-SW
PFM detection threshold low
PFM detection threshold high
Zero-cross threshold
0.8
V
V
2.0
-5.5
100
mV
PFM/SYNC = 0 V, 1000 SW cycles after first
HO pulse
VZC-DIS
Zero-cross threshold disable
Frequency sync range
mV
kHz
ns
RRT = 10 kΩ, ±20 % of the nominal oscillator
frequency
FSYNCIN
tSYNC-MIN
tSYNCIN-HO
1740
20
2700
250
Minimum pulse-width of external
synchronization signal
Delay from PFM falling edge to HO rising
edge
45
ns
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7.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 8 V to 18 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPFM-FILTER
SYNCIN to PFM mode
13
45
µs
DUAL RANDOM SPREAD SPECTRUM (DRSS)
Switching frequency percentage change
Modulation frequency
7
%
ΔfC
fm
8.2
16.2
2.42
kHz
SWITCHING FREQUENCY
VRT
RT pin regulation voltage
0.5
220
2.2
100
600
50
V
kHz
MHz
kHz
mV/µs
mV/µs
ns
10 kΩ < RRT < 100 kΩ
FSW1
Switching frequency 1
Switching frequency 2
Switching frequency 3
Internal slope compensation 1
Internal slope compensation 2
Minimum on-time
RRT = 97.6 kΩto AGND
VIN = 12 V, RRT= 9.52 kΩto AGND
RRT=220 kΩto AGND
RRT = 9.52 kΩ
FSW2
1.98
FSW3
SLOPE1
SLOPE2
tON(min)
RRT = 97.6 kΩ
50
tOFF(min)
Minimum off-time
90
ns
POWER GOOD (PG)
VPG-UV
Power Good UV trip level
Power Good OV trip level
Power Good UV hysteresis
Power Good OV hysteresis
OV filter time
Falling with respect to the regulated voltage
Rising with respect to the regulation voltage
Rising with respect to the regulated output
Rising with respect to the regulation voltage
VOUT rising
90%
92%
110%
3.6%
3.4%
25
94%
VPG-OV
108%
112%
VPG-UV-HYST
VPG-OV-HYST
t-PG-RISING-DLY
t-PG-FALL-DLY
VPG-OL
µs
µs
V
UV filter time
VOUT falling
25
PG voltage
Open collector, IPG/SYNC = 2 mA
0.8
0.8
SYNCHRONIZATION OUTPUT (PG pin)
RCNFG = 54.9 kΩ or 71.5 kΩ to GND
(primary), ISYNCOUT = 2 mA
VSYNCOUT-LO
VSYNCOUT-HO
tSYNCOUT
SYNCO-LO low-state voltage
V
V
RCNFG = 54.9 kΩ or 71.5 kΩ to GND
(primary), ISYNCOUT = 2 mA
SYNCO-HO high-state voltage
2.0
1.9
Delay from HO rising edge to SYNCOUT
(PG/SYNCOUT in SYNC mode)
2.1
µs
VPFM = 0 V, FSW set by RRT = 100 kΩ
STARTUP (Soft Start)
tSS-INT
Internal fixed soft-start time
Internal diode forward drop
3
4.6
4.3
ms
BOOT CIRCUIT
VBOOT-DROP
ICBOOT = 20 mA, VCC to CBOOT
VEN = 5 V, VCBOOT-SW = 5 V
0.63
2.88
0.8
V
CBOOT to SW quiescent current, not
switching
IBOOT
µA
VBOOT-SW-UV-R
VBOOT-SW-UV-F
VBOOT-SW-UV-HYS
CBOOT-SW UVLO rising threshold
CBOOT-SW UVLO falling threshold
CBOOT-SW UVLO hysteresis
VCBOOT-SW rising
VCBOOT-SW falling
2.83
2.5
50
V
V
mV
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH
VHO-LOW
tHO-RISE
tHO-FALL
IHO-SRC
IHO-SINK
HO high-state output voltage
106
50
7
mV
mV
ns
ns
A
IHO = –100 mA, VHO-HIGH = VCBOOT –VHO
IHO = 100 mA
HO low-state output voltage
HO rise time (10% to 90%)
HO fall time (90% to 10%)
HO peak source current
HO peak sink current
CLOAD = 2.7 nF
CLOAD = 2.7 nF
7
VHO = VSW = 0 V, VVCC = VCBOOT = 5 V
VVCC = 5 V
2.2
3.2
A
LOW-SIDE GATE DRIVER (LO)
VLO-LOW
VLO-HIGH
tLO-RISE
tLO-FALL
LO low-state output voltage
ILO = 100 mA
50
130
7
mV
mV
ns
LO high-state output voltage
LO rise time (10% to 90%)
LO fall time (90% to 10%)
ILO = –100 mA
CLOAD = 2.7 nF
CLOAD = 2.7 nF
7
ns
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7.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 8 V to 18 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VLO = 0 V, VVCC = 5 V
VVCC = 5 V
MIN
TYP
MAX
UNIT
A
ILO-SRC
ILO-SINK
LO peak source current
LO peak sink current
2.2
3.2
A
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime
tDEAD2 LO off to HO on deadtime
INTERNAL HICCUP MODE
20
20
ns
ns
HICDLY
Hiccup mode activation delay
HICCUP mode fault
512
cycles
cycles
V
ISNS+ –VVOUT > 60 mV
ISNS+ –VVOUT > 60 mV
HICCYCLES
16384
V
OVERCURRENT PROTECTION
VCS-TH
Current limit threshold
Measured from ISNS+ to VOUT
49
9
60
65
10
15
73
mV
ns
tDELAY-ISNS+
GCS
ISNS+ delay to output
CS amplifier gain
10.8
V/V
nA
IBIAS-ISNS+
CONFIGURATION
RCNFG-OPT1
RCNFG-OPT2
RCNFG-OPT3
RCNFG-OPT4
RCNFG-OPT5
CS amplifier input bias current
Primary, no Spread Spectrum
Primary, with Spread Spectrum
Primary, Interleaved, no Spread Spectrum
Primary, Interleaved, with Spread Spectrum
Secondary
28.7
40.2
53.6
69.8
87
29.4
41.2
54.9
71.5
90.9
31
43.2
57.6
73.2
93.1
kΩ
kΩ
kΩ
kΩ
kΩ
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
175
15
°C
°C
TJ-HYS
(1) Specified by design. Not production tested.
7.6 Active EMI Filter
TJ = –40°C to 150°C, VAEFVDDA = 5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Active EMI Filter
VAEF-RUVLO-R
VAEF-UVLO-F
VAEF-HYST
AOL
Voltage AEF UVLO rising threshold
Voltage AEF UVLO falling threshold
Voltage AEF UVLO hysteresis
DC gain
4.15
3.5
V
V
650
mV
68
2
dB
MHz
V
fBW
Unity gain bandwidth
300
2.5
VAEF-HIGH
VAEF-LOW
VAEF-REF
AEF voltage rising threshold
AEF voltage falling threshold
AEF reference voltage
Enable AEF
Disable AEF
0.8
V
V
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7.7 Typical Characteristics
100
100
90
80
70
60
50
95
90
85
80
75
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0
1
2
3
4
5
6
7
8
9
10
0.001
0.01
0.1
1
10
Load Current (A)
FSW = 440 kHz
图7-1. Efficiency vs Load
Load Current (A)
VOUT = 5 V
VOUT = 5 V
FSW = 440 kHz
图7-2. Efficiency vs Load, Log Scale
5
4
3
2
1
0
150
140
130
120
110
100
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
0.5 V ≤VEN < 1 V
VEN = 0 V
图7-4. Standby Current vs Temperature
图7-3. Shutdown Current vs Temperature
15
12
9
6
3
0
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
VVOUT = 3.3 V
图7-5. Sleep Current vs Temperature
1.05 V ≤VEN ≤80 V
VVOUT = 5 V
图7-6. Sleep Current vs Temperature
1.03 V ≤VEN ≤80 V
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7.7 Typical Characteristics (continued)
5.05
5.025
5
4.975
4.95
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
图7-8. Fixed 5-V Output Voltage vs Temperature
图7-7. Fixed 3.3-V Output Voltage vs Temperature
812
112
111
110
109
108
107
106
105
104
Rising
Falling
808
804
800
796
792
788
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
图7-9. Feedback (FB) Voltage vs Temperature
图7-10. PG OV Thresholds vs Temperature
98
97
96
95
94
93
92
91
90
5.2
5.15
5.1
IVCC = 0 mA
IVCC = 100 mA
Falling
Rising
5.05
5
4.95
4.9
4.85
4.8
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
图7-12. VCC Regulation Voltage vs Temperature
图7-11. PG UV Thresholds vs Temperature
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7.7 Typical Characteristics (continued)
3.6
250
200
150
100
50
Rising
Falling
3.5
3.4
3.3
3.2
3.1
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
图7-14. VCC Current Limit vs Temperature
图7-13. VCC UVLO Thresholds vs Temperature
5.1
3.3
3.25
3.2
Rising
Falling
5.05
5
3.15
3.1
4.95
3.05
3
4.9
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
图7-15. VDDA Regulation Voltage vs Temperature
图7-16. VDDA UVLO Thresholds vs Temperature
4.6
4.5
4.4
4.3
4.2
4.1
4
70
65
60
55
50
Rising
Falling
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
图7-17. VCCX On and Off Thresholds vs Temperature
图7-18. Current Sense (CS) Threshold vs Temperature
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7.7 Typical Characteristics (continued)
80
70
60
50
40
30
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
图7-19. Current Sense (CS) Amplifier Gain vs Temperature
图7-20. Minimum On Time (HO) vs Temperature
5
2.5
2.4
2.3
2.2
2.1
2
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (C)
Junction Temperature (C)
RRT = 9.09 kΩ
图7-21. Soft-start Time vs Temperature
图7-22. Switching Frequency vs Temperature
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8 Detailed Description
8.1 Overview
The LM5149 is a switching controller that features all of the functions necessary to implement a high-efficiency
synchronous buck power supply operating over a wide input voltage range from 3.5 V to 80 V. The LM5149 is
configured to provide a fixed 3.3-V, 5-V, or 12-V output, or an adjustable output between 0.8 V to 55 V. This
easy-to-use controller integrates high-side and low-side MOSFET gate drivers capable of sourcing and sinking
peak currents of 2.2 A and 3.2 A, respectively. Adaptive dead-time control is designed to minimize body diode
conduction during switching transitions.
Current-mode control using a shunt resistor or inductor DCR current sensing provides inherent line feedforward,
cycle-by-cycle peak current limiting, and easy loop compensation. Current-mode control using a shunt resistor or
inductor DCR current sensing also supports a wide duty cycle range for high input voltage and low-dropout
applications as well as application requiring a high step-down conversion ratio (for example, 10-to-1). The
oscillator frequency is user-programmable between 100 kHz to 2.2 MHz, and the frequency can be synchronized
as high as 2.5 MHz by applying an external clock to the PFM/SYNC pin.
An external bias supply can be connected to VCCX to maximize efficiency in high input voltage applications. A
user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further
improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include
current limiting, thermal shutdown, UVLO, and remote shutdown capability.
The LM5149 incorporates several features to simplify compliance with various EMI standards, for example,
CISPR 11 and CISPR 32 Class B requirements. Active EMI filter and dual random spread spectrum (DRSS)
techniques reduce the peak harmonic EMI signature.
The LM5149 is provided in a 24-pin VQFN package with an exposed pad to aid in thermal dissipation.
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8.2 Functional Block Diagram
VIN
CLK
HICCUP
FAULT TIMER
512 CYCLES
PFM/SYNC
PLL and
OSCILLATORS
VREF 0.8 V
SYNCOUT
BIAS
VCCX
VCC
ILIM
DEM/FPWM
HICCUP
VOUT
VDDA
CONTROL
VDDA
RT amp
+
DRSS
ENABLE
DUAL RANDOM
SPREAD SPECTURM
(DRSS)
500 mV
INJ
SEN
-
RT
ACTIVE EMI FILTER
(AEF)
AEFVDD
REFAGND
AVSS
AEF ENABLE
CONFG
DECODER
CNFG
SECONDARY
INTERLEAVED
EN
-
VCC
ILIM
+
CURRENT
LIMIT
GAIN = 10
60 mV
+
-
+
ISNS+
VOUT
CBOOT
UVLO
-
SLOPE
CBOOT
COMP
RAMP
SECONDARY
INTERLEAVE
COMP/ENABLE
3.3 V
5 V
FB
DECODE
R/MUX
12 V
DEM/FPWM
HICCUP
HO
SW
DRIVER
FB
SYNCOUT
SECONDARY
EXTERNAL EA
gm 1200 µS
+
-
-
PWM
R
S
Q
Q
PG/SYNCOUT
+
+
VREF
-
CLK
0.880 V
0.736 V
PGO
+
INTERNAL EA
gm 30 µS
PG
VCC
PG
DELAY
25ms
LEVEL
SHIFT
ADAPTIVE
DEADTIME
-
+
+
-
DRIVER
LO
PGUV
+
EXTCOMP
_
PGND
SOFT-START
AGND
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN)
The LM5149 operational input voltage range is from 3.5 V to 80 V. The device is intended for step-down
conversions from 12-V, 24-V, and 48-V supply rails. The application circuit in 图 9-5 shows all the necessary
components to implement an LM5149 based wide-VIN single-output step-down regulator using a single supply.
The LM5149 uses an internal LDO to provide a 5-V VCC bias rail for the gate drive and control circuits
(assuming the input voltage is higher than 5 V with additional voltage margin necessary for the subregulator
dropout specification).
In high input voltage applications, take extra care to ensure that the VIN and SW pins do not exceed their
absolute maximum voltage rating of 85 V during line or load transient events. Voltage excursions that exceed the
applicable voltage specifications can damage the device.
Care must be taken in applications where there are fast input transients that cause the voltage at VIN to
suddenly drop more than 2 V below the VOUT setpoint. The LM5149 has an internal ESD diode from the VOUT
to the VIN pins that can conduct under such conditions causing the output to discharge. To prevent damage to
the internal ESD diode under the said conditions, TI recommends adding a Schottky diode in series with the VIN
pin of the LM5149 to prevent reverse current flow from VOUT to VIN.
As VIN approaches VOUT, the LM5149 skips tOFF cycles to allow the controller to extend its duty cycle up to
approximately 99%. Refer to 图8-1.
Use 方程式1 to calculate when the LM5149 enters dropout mode.
t
P
V
= V
×
(1)
IN
OUT
t
− t
OFF
P
• tP is the oscillator period
• tOFF is the minimum off time, typical 90 ns
VIN
VOUT
PWM Mode
Low Dropout Mode
~99% Duty Cycle
one
tOFF skip
two
tOFF skip
three
tOFF skip
up to 15
tOFF skip
up to 15
tOFF skip
HO-SW
图8-1. Dropout Mode Operation
8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
The LM5149 contains an internal high-voltage VCC bias regulator that provides the bias supply for the PWM
controller and the gate drivers for the external MOSFETs. The input voltage pin (VIN) can be connected directly
to an input voltage source up to 80 V. However, when the input voltage is below the VCC setpoint level, the VCC
voltage tracks VIN minus a small voltage drop.
The VCC regulator output current limit is 115 mA (minimum). At power up, the controller sources current into the
capacitor connected at the VCC pin. When the VCC voltage exceeds 3.3 V and the EN pin is connected to a
voltage greater than 1 V, the soft-start sequence begins. The output remains active unless the VCC voltage falls
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below the VCC UVLO falling threshold of 3.1 V (typical) or EN is switched to a low state. Connect a ceramic
capacitance from VCC to PGND. The recommended range of the VCC capacitor is from 2.2 µF to 10 µF.
An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF ceramic capacitor
or higher to achieve a low-noise internal bias rail. Normally, VDDA is 5 V. However, there is one condition where
VDDA regulates at 3.3 V: this is in PFM mode with a light or no load on the output.
Minimize the internal power dissipation of the VCC regulator by connecting VCCX to a 5-V output or to an
external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. Tie VCCX to PGND if it is unused. Do not connect VCCX to a voltage greater than 6.5
V. If using active EMI filter with AEFVDDA powered from VCC, do not connect VCCX to a voltage greater than
5.5 V. If an external supply is connected to VCCX to power the LM5149, VIN must be greater than the external
bias voltage during all conditions to avoid damage to the controller.
8.3.3 Precision Enable (EN)
The EN pin can be connected to a voltage as high as 80 V. The LM5149 has a precision enable function. When
the EN voltage is greater than 1 V, switching is enabled. If the EN pin is pulled below 0.5 V, the LM5149 is in
shutdown with an IQ of 2.3 μA (typical) current drawn from VIN. When the EN voltage is between 0.5 V and 1 V,
the LM5149 is in standby mode, the VCC regulator is active, and the controller is not switching. When the
controller is in standby mode, the non-switching input quiescent current is 124 μA (typical). The LM5149 is
enabled with a voltage greater than 1.0 V on the EN pin. However, many applications benefit from using a
resistor divider RUV1 and RUV2, as shown in 图 8-2, to establish a precision UVLO level. TI does not recommend
leaving the EN pin floating.
Use 方程式2 and 方程式3 to calculate the UVLO resistors given the required input turn-on and turn-off voltages.
V
- V
IN(off)
IN(on)
RUV1
=
IHYS
(2)
(3)
VEN
- VEN
RUV2 = RUV1
∂
V
IN(on)
VDDA
VIN
10 µA
RUV1
EN
19
+
1V
Enable
RUV2
Comparator
图8-2. Programmable Input Voltage UVLO Turn-On
8.3.4 Power-Good Monitor (PG)
The LM5149 includes an output voltage monitoring signal for VOUT to simplify sequencing and supervision. The
power-good signal is used for start-up sequencing of downstream converters, fault protection, and output
monitoring. The power-good output (PG) switches to a high-impedance open-drain state when the output voltage
is in regulation. The PG switches low when the output voltage drops below the lower power-good threshold (92%
typical) or rises above the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false
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tripping of the power-good signal during transients. TI recommends a pullup resistor of 100 kΩ(typical) from PG
to the relevant logic rail. PG is asserted low during soft start and when the buck controller is disabled.
When the LM5149 is configured as a primary controller, the PG/SYNC pin becomes a synchronization clock
output for the secondary controller. The synchronization signal is 180° out-of-phase with the primary HO driver
output.
8.3.5 Switching Frequency (RT)
Program the LM5149 oscillator with a resistor from RT to AGND to set an oscillator frequency between 100 kHz
and 2.2 MHz. Calculate the RT resistance for a given switching frequency using 方程式4.
106
- 53
FSW (kHz)
RT (kW) =
45
(4)
Under low VIN conditions when the on time of the high-side MOSFET exceeds the programmed oscillator period,
the LM5149 extends the switching period until the PWM latch is reset by the current sense ramp exceeding the
controller compensation voltage.
方程式5 gives the approximate voltage level at which this occurs.
tSW
V
= VOUT ∂
IN(min)
tSW - tOFF(min)
(5)
where
• tSW is the switching period.
• tOFF(min) is the minimum off time of 90 ns.
8.3.6 Active EMI Filter
Active EMI filter provides a higher level of EMI attenuation and a smaller solution size than a standard passive
π-filter. Passive π-filters use large inductors and capacitors to attenuate the ripple and noise on the input DC
bus. Passive filters are typically most effective at reducing the switching frequency harmonics to comply with EMI
in the low-frequency range, less than 30 MHz.
Active EMI filter has a high gain, wide bandwidth amplifier, and a low output impedance that can source and sink
current. It senses (at the SEN pin) any disturbance on the DC input bus and injects (at the INJ pin) a cancellation
signal out of phase with the noise source to reduce the conducted emissions.
To maintain low IQ at light loads, the LM5149 automatically enables active EMI filter when the load current is
greater than 40% of the current limit value, and disables the active EMI filter when the load current is less then
30% of the current limit value. Disable active EMI filter is by pulling the CNFG pin below 0.8 V after the LM5149
has been configured.
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LF
CSEN
CINJ
CINC
ZS
RAEFC
CAEFC
CIN
ZL
RAEFDC
SEN
RINC
INJ
VREF
Active EMI Filter
图8-3. Active EMI Filter
8.3.7 Dual Random Spread Spectrum (DRSS)
The LM5149 provides a digital spread spectrum, which reduces the EMI of the power supply over a wide
frequency range. DRSS combines a low-frequency triangular modulation profile with a high frequency cycle-by-
cycle random modulation profile. The low-frequency triangular modulation improves performance in lower radio-
frequency bands, while the high-frequency random modulation improves performance in higher radio frequency
bands.
Spread spectrum works by converting a narrowband signal into a wideband signal that spreads the energy over
multiple frequencies. Because industry standards require different EMI receiver resolution bandwidth (RBW)
settings for different frequency bands, the RBW has an impact on the spread spectrum performance. For
example, the CISPR 25 spectrum analyzer RBW in the frequency band from 150 kHz to 30 MHz is 9 kHz. For
frequencies greater than 30 MHz, the RBW is 120 kHz DRSS is able to simultaneously improve the EMI
performance in the low and high RBWs with its low-frequency triangular modulation profile and high frequency
cycle-by-cycle random modulation, respectively. DRSS can reduce conducted emissions by 15 dBμV in the
CISPR 25 low-frequency band (150 kHz to 30 MHz) and 5 dBμV in the high-frequency band (30 MHz to 108
MHz).
To enable DRSS, connect either a 41.2-kΩ or 71.5-kΩ resistor from CNFG to AGND. DRSS is disabled when
an external clock is applied to the PFM/SYNC pin.
Frequency
(a) Low-frequency
triangular modulation
(b) High-frequency
randomized modulation
(c) Low-frequency triangular + high-
frequency
randomized modulations
fs(t)
2∆fs
Low RBW
High RBW
t
Spread spectrum OFF
Spread spectrum ON
图8-4. Dual Random Spread Spectrum Implementation
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8.3.8 Soft Start
The LM5149 has an internal 3-ms soft-start timer (typical). The soft-start feature allows the regulator to gradually
reach the steady-state operating point, thus reducing start-up stresses and surges.
8.3.9 Output Voltage Setpoint (FB)
The LM5149 output can be independently configured for one of three fixed output voltages without external
feedback resistors, or adjusted to the desired voltage using an external resistor divider. Set the output to 3.3 V
by connecting FB directly to VDDA. Alternatively, set the output to either 5 V or 12 V by installing a 24.9-kΩ or
49.9-kΩresistor between FB and VDDA, respectively. See 表8-1.
表8-1. Feedback Configuration Resistors
PULLUP RESISTOR TO VDDA
VOUT SETPOINT
3.3 V
0 Ω
5 V
12 V
24.9 kΩ
49.9 kΩ
Not installed
External FB divider setting
The configuration settings are latched and cannot be changed until the LM5149 is powered down (with the VCC
voltage decreasing below its falling UVLO threshold) and then powered up again (VCC rises above 3.4 V
typical). Alternatively, set the output voltage with an external resistive divider from the output to AGND. The
output voltage adjustment range is between 0.8 V and 55 V. The regulation voltage at FB is 0.8 V (VREF). Use 方
程式6 to calculate the upper and lower feedback resistors, designated as RFB1 and RFB2, respectively.
≈
∆
«
’
VOUT
VREF
RFB1
=
-1 ∂R
÷
FB2
◊
(6)
The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ.
If low-IQ operation is required, take care when selecting the external feedback resistors. The current
consumption of the external divider adds to the LM5149 sleep current (9.5 µA typical). The divider current
reflected to VIN is scaled by the ratio of VOUT/VIN.
8.3.10 Minimum Controllable On Time
There are two limitations to the minimum output voltage adjustment range: the LM5149 voltage reference of
0.8 V and the minimum controllable switch-node pulse width, tON(min)
.
tON(min) effectively limits the voltage step-down conversion ratio VOUT / VIN at a given switching frequency. For
fixed-frequency PWM operation, the voltage conversion ratio must satisfy 方程式7.
VOUT
> tON(min) ∂FSW
V
IN
(7)
where
• tON(min) is 50 ns (typical).
• FSW is the switching frequency.
If the desired voltage conversion ratio does not meet the above condition, the LM5149 transitions from fixed
switching frequency operation to a pulse-skipping mode to maintain output voltage regulation. For example, if
the desired output voltage is 5 V with an input voltage of 24 V and switching frequency of 2.1 MHz, use 方程式 8
to verify that the conversion ratio.
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(8)
For wide-VIN applications and low output voltages, an alternative is to reduce the LM5149 switching frequency to
meet the requirement of 方程式7.
8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP)
The LM5149 has a high-gain transconductance amplifier that generates an error current proportional to the
difference between the feedback voltage and an internal precision reference (0.8 V). The control loop
compensation is configured two ways. The first is using the internal compensation amplifier, which has a
transconductance of 30 µS. Internal compensation is configured by connecting the EXTCOMP pin through a 10-
kΩ resistance to VDDA. If a 10-kΩ resistor is not detected, the LM5149 defaults to the external loop
compensation network. The transconductance of the amplifier for external compensation is 1200 µS. This is
latched and cannot be reconfigured after programmed unless power to the device is recycled. Use an external
compensation network if higher performance is required to meet a stringent transient response specification. To
reconfigure the compensation (internal or external), remove power and allow VCC to drop below its VCCUVLO
threshold, which is 3.3 V typical.
A type-II compensation network is generally recommended for peak current-mode control.
8.3.12 Slope Compensation
The LM5149 provides internal slope compensation for stable operation with peak current-mode control and a
duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal
to one times the inductor downslope using 方程式9.
VOUT (V)∂RS(mW)
LO-IDEAL (ꢀH) =
24 ∂FSW (MHz)
(9)
• A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and
cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses
and peak currents.
• A higher inductance value generally decreases the peak-to-peak inductor current, reducing switch peak and
RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.
8.3.13 Inductor Current Sense (ISNS+, VOUT)
There are two methods to sense the inductor current of the buck power stage. The first uses a current sense
resistor (also known as a shunt) in series with the inductor, and the second avails of the DC resistance of the
inductor (DCR current sensing).
8.3.13.1 Shunt Current Sensing
图8-5 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the
inductor current to provide accurate overcurrent protection across the operating temperature range. For optimal
current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between
the inductor and the output, with a Kelvin connection to the LM5149 current sense amplifier.
If the peak voltage signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 60 mV, the current
limit comparator immediately terminates the HO output for cycle-by-cycle current limiting. Calculate the shunt
resistance using 方程式10.
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VCS-TH
RS
=
DIL
2
IOUT(CL)
+
(10)
where
• VCS-TH is current sense threshold of 60 mV.
• IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the
overcurrent comparator during load transients.
• ΔIL is the peak-to-peak inductor ripple current.
VIN
LO
RS
VOUT
CO
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
图8-5. Shunt Current Sensing Implementation
The soft-start voltage is clamped 150 mV above FB during an overcurrent condition. Sixteen overcurrent events
must occur before the SS clamp is enabled. This action makes sure that SS can be pulled low during brief
overcurrent events, preventing output voltage overshoot during recovery.
8.3.13.2 Inductor DCR Current Sensing
For high-power applications that do not require accurate current-limit protection, inductor DCR current sensing is
preferable. This technique provides lossless and continuous monitoring of the inductor current using an RC
sense network in parallel with the inductor. Select an inductor with a low DCR tolerance to achieve a typical
current limit accuracy within the range of 10% to 15% at room temperature. Components RCS and CCS in 图 8-6
create a low-pass filter across the inductor to enable differential sensing of the voltage across the inductor DCR.
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VIN
LO
RS
VOUT1
CO
RCS
CCS
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
图8-6. Inductor DCR Current Sensing Implementation
The voltage drop across the sense capacitor in the s-domain is given by 方程式 11. When the RCSCCS time
constant is equal to LO/RDCR, the voltage developed across the sense capacitor, CCS, is a replica of the inductor
DCR voltage and accurate current sensing is achieved. If the RCSCCS time constant is not equal to the LO/RDCR
time constant, there is a sensing error as follows:
• RCSCCS > LO/RDCR →the DC level is correct, but the AC amplitude is attenuated.
• RCSCCS < LO/RDCR →the DC level is correct, but the AC amplitude is amplified.
• RCSCCS = LO/RDCR →the DC level and AC amplitude are correct.
LO
1+ s∂
RDCR
DIL
2
≈
’
VCS(s) =
∂RDCR ∂∆IOUT(CL) +
÷
◊
1+ s∂RCS ∂CCS
«
(11)
Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network,
thus reducing the susceptibility of noise pickup from the switch node. Carefully observe 节 9.4.1 to make sure
that noise and DC errors do not corrupt the current sense signals applied between the ISNS+ and VOUT pins.
8.3.14 Hiccup Mode Current Limiting
The LM5149 includes an internal hiccup-mode protection function. After an overload is detected, 512 cycles of
cycle-by-cycle current limiting occurs. The 512-cycle counter is reset if four consecutive switching cycles occur
without exceeding the current limit threshold. After the 512-cycle counter has expired, the internal soft start is
pulled low, the HO and LO driver outputs are disabled, and the 16384-cycle counter is enabled. After the counter
reaches 16384, the internal soft start is enabled and the output restarts. The hiccup-mode current limit is
disabled during soft start until the FB voltage exceeds 0.4 V.
8.3.15 High-Side and Low-Side Gate Drivers (HO, LO)
The LM5149 contains gate drivers and an associated high-side level shifter to drive the external N-channel
power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode, DBOOT, and
bootstrap capacitor, CBOOT. During the conduction interval of the low-side MOSFET, the SW voltage is
approximately 0 V and CBOOT charges from VCC through the internal DBOOT. TI recommends a 0.1-μF ceramic
capacitor connected with short traces between the CBOOT and SW pins.
The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and
LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn
on, the adaptive dead-time logic first disables HO and waits for the HO voltage to drop below 2 V typical. LO is
allow to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the LO
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voltage has dropped below 2 V. This technique ensures adequate dead-time for any size N-channel power
MOSFET implementations, including parallel MOSFET configurations.
Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected
high-side MOSFET determines the appropriate bootstrap capacitance value CBOOT in accordance with 方程式
12.
QG
CBOOT
=
DVCBOOT
(12)
where
• QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
• ΔVCBOOT is the voltage variation of the high-side MOSFET driver after turn-on.
To determine CBOOT, choose ΔVCBOOT so that the available gate drive voltage is not significantly impacted. An
acceptable range of ΔVCBOOT is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic
capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.
8.3.16 Output Configurations (CNFG)
The LM5149 can be configured as a primary controller (interleaved mode) or as a secondary controller for
paralleling the outputs for high-current applications with a resistor RCNFG. This resistor also configures if spread
spectrum is enabled or disabled. See 表 8-2. After the VCC voltage is above 3.3 V (typical), the CNFG pin is
monitored and latched. The configuration cannot be changed on the fly – the LM5149 must be powered down,
and VCC must drop below 3.3 V. 图8-7 shows the configuration timing diagram.
When the LM5149 is configured as a primary controller with spread spectrum enabled (RCNFG of 41.2 kΩ or
71.5 kΩ), the LM5149 cannot be synchronized to an external clock.
表8-2. Configuration Modes
PRIMARY or
SECONDARY
RCNFG
SPREAD SPECTRUM
DUAL PHASE
Primary
OFF
ON
Disabled
Disabled
Enabled
Enabled
Enabled
29.9 kΩ
41.2 kΩ
54.9 kΩ
71.5 kΩ
90.9 kΩ
Primary
Primary
OFF
ON
Primary
Secondary
N/A
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图8-7. Configuration Timing
After the configuration has been latched, the CNFG pin become an enable input for the active EMI filter, where a
logic high (> 2 V) enables the active EMI filter and a logic low (< 0.8 V) disables AEF.
8.3.17 Single-Output Dual-Phase Operation
To configure for dual-phase operation, two controllers are required. The LM5149 can only be configured in a
single or dual-phase configuration where both outputs are tied together. Additional phases cannot be added.
Refer to 图 8-8. Configure the first controller (CNTRL1) as a primary controller and the second controller
(CNTRL2) as a secondary. To configure CNTRL1 as a primary controller, install a 54-kΩ or a 71.5-kΩ resistor
from CNFG to AGND. To configure the CNTRL2 as a secondary controller, install a 90.9-kΩresistor from CNFG
to AGND. This disables the error amplifier of CNTRL2, placing it into a high-impedance state. Connect the
EXTCOMP pins of the primary and secondary controllers together. The internal compensation amplifier feature is
not supported when the controller is in dual-phase mode.
In dual-phase mode, the PG/SYNC pin of the primary controller becomes a SYNCOUT. Refer to the 节7.5 for
voltage levels. Connect PG of the primary to PFM/SYNC (SYNCIN) of the secondary controller. The PG/
SYNCOUT signal of the primary controller is 180° out-of-phase and facilitates interleaved operation. RT is not
used for the oscillator when the LM5149 is in secondary controller mode, but instead is used for slope
compensation. Therefore, select the RT resistance to be the same as that of the primary controller. The oscillator
is derived from the primary controller. When in primary/secondary mode, enable both controllers simultaneously
for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8 V) for phase shedding if needed
at light load to increase the efficiency.
Configure PFM mode by connecting the PFM/SYNC of the primary to VDDA and the FB of the secondary to
VDDA as shown in 图 8-8. Configure FPWM mode by connecting PFM/SYNC of the primary and FB of the
secondary both to AGND. An external synchronization signal can be applied to the primary PFM/SYNC
(SYNCIN), and the secondary FB must be configured for FPWM. If an external SYNCIN signal is applied after
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start-up while in primary/secondary mode, there is a two-clock cycle delay before the LM5149 locks on to the
external synchronization signal.
图8-8. Schematic Configured for Single-Output Dual-Phase Operation
VOUT
RPGOOD
20 k
SYNCOUT
PGOOD/
SYNCOUT
PGOOD/
SYNCOUT
VDDA
PFM/SYNC
EN
PFM/SYNC
EN
VOUT
EN CH1
EN CH2
Primary
Secondary
Controller
Controller
RFB1
VDDA
FB
CNFG
CNFG
FB
RCNFG1
54.9 k
RCNFG2
90.9 k
EXTCOMP
EXTCOMP
RFB2
PFM pulse skipping
is used to reduce the IQ current and the light-load efficiency. When this occurs, the primary controller disables its
synchronization clock output, so phase shedding is not supported. Phase shedding is supported in FPWM only.
In FPWM, enable or disable the secondary controller as needed to support higher load current or better light-
load efficiency, respectively. When the secondary is disabled and then re-enabled, its internal soft-start is pulled
low and the LM5149 goes through a normal soft-start sequence.
When the LM5149 is configured for a single-output dual-phase operation using the internal 3.3-V feedback
resistor divider, the internal bootstrap UV circuit can source current out of the SW pin, charging up the output
capacitors approximately to 3.6 V. If this behavior is undesirable, the user can add a 100-kΩresistor from VOUT
to GND to bleed off the charge on the output capacitors.
For more information, see Benefits of a Multiphase Buck Converter technical brief and Multiphase Buck Design
From Start to Finish application report.
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8.4 Device Functional Modes
8.4.1 Sleep Mode
The LM5149 operates with peak current-mode control such that the compensation voltage is proportional to the
peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As a
result, the compensation voltage does not demand the driver output pulses on a cycle-by-cycle basis. When the
LM5149 controller detects 16 missed switching cycles, it enters sleep mode and switches to a low IQ state to
reduce the current drawn from the input. For the LM5149 to go into sleep mode, the controller must be
programmed for diode emulation (tie PFM/SYNC to VDDA).
The typical controller IQ in sleep mode is 9.5 μA with a 3.3-V output.
8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
A synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode has the
capability to sink negative current from the output during conditions of, light-load, output overvoltage, and pre-
bias start-up conditions. The LM5149 provides a diode emulation feature that can be enabled to prevent reverse
(drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation mode, the low-side
MOSFET is switched off when reverse current flow is detected by sensing the SW voltage using a zero-cross
comparator. The benefit of this configuration is lower power loss during light-load conditions; the disadvantage of
diode emulation mode is slower light-load transient response.
Diode emulation is configured with the PFM/SYNC pin. To enable diode emulation and thus achieve low-IQ
current at light loads, connect PFM/SYNC to VDDA. If FPWM with continuous conduction mode (CCM) operation
is desired, tie PFM/SYNC to AGND. Note that diode emulation is automatically engaged to prevent reverse
current flow during a prebias start-up. A gradual change from DCM to CCM operation provides monotonic start-
up performance.
To synchronize the LM5149 to an external source, apply a logic-level clock to the PFM/SYNC pin. The LM5149
can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there is an RT
resistor and a synchronization signal, the LM5149 ignores the RT resistor and synchronizes to the external
clock. Under low-VIN conditions when the minimum off time is reached, the synchronization signal is ignored,
allowing the switching frequency to be reduced to maintain output voltage regulation.
8.4.3 Thermal Shutdown
The LM5149 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs. When entering thermal shutdown, the device:
1. Turns off the high-side and low-side MOSFETs.
2. PG/SYNCOUT switches low.
3. Turns off the VCC regulator.
4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
15°C (typical).
This is a non-latching protection and as such, the device cycles into and out of thermal shutdown if the fault
persists.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Power Train Components
A comprehensive understanding of the buck regulator power train components is critical to successfully
completing a synchronous buck regulator design. The following sections discuss the output inductor, input and
output capacitors, power MOSFETs, and EMI input filter.
9.1.1.1 Buck Inductor
For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to
50% of the maximum DC output current at nominal input voltage. Choose the inductance using 方程式 13 based
on a peak inductor current given by 方程式14.
≈
’
÷
◊
VOUT
VOUT
LO
=
∂ 1-
∆
DIL ∂FSW
V
IN
«
(13)
(14)
DIL
2
IL(peak) = IOUT
+
Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current and higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.1.2 Output Capacitors
Ordinarily, the output capacitor energy storage of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series
resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load
transient response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by 方程式15.
DIL
2
COUT
í
2
8 ∂FSW DVOUT - RESR ∂ DIL
(15)
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图 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to
match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of
charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up
transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds
to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL
dt
VOUT
LF
= -
inductor current, iL(t)
DIOUT
DQC
IOUT2
load current,
iOUT(t)
diOUT DIOUT
=
dt
tramp
inductor current, iL(t)
IOUT2
DQC
diL
dt
VIN - VOUT
LF
DIOUT
=
load current, iOUT(t)
IOUT1
tramp
图9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 12-V input to low output voltage (for example, 3.3 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT / L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance must be larger than:
2
LO ∂ DIOUT
COUT
í
2
2
V
+ DVOVERSHOOT - VOUT
(
)
OUT
(16)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic
capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces
contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have
low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates.
However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop
quite significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in 方程式 15 gives a quick estimation of the minimum ceramic capacitance necessary to
meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
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common choice for a 5-V output. Use 方程式 16 to determine if additional capacitance is necessary to meet the
load-off transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.1.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-
frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in
the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and
the source of the low-side MOSFET. The input capacitor RMS current for a single-channel buck regulator is
given by 方程式17.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(17)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the input
capacitors must be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT
−
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by 方程式18.
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(18)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by 方程式19.
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
(19)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with
high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic
decoupling capacitors are usually sufficient for 12-V battery automotive applications. Select the input bulk
capacitor based on its ripple current rating and operating temperature range.
Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple
current cancellation and reduced input capacitor current stress. The above equations represent valid
calculations when one output is disabled and the other output is fully loaded.
9.1.1.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-
state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition
times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and
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output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and QG is
commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package ensures that the
MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM5149 application are as follows:
• RDS(on) at VGS = 4.5 V
• Drain-source voltage rating, BVDSS, typically 40 V, 60 V , or 80 V, depending on the maximum input voltage
• Gate charge parameters at VGS = 4.5 V
• Output charge, QOSS, at the relevant input voltage
• Body diode reverse recovery charge, QRR
• Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive
amplitude of the LM5149 provides an adequately enhanced MOSFET when on and a margin against Cdv/dt
shoot-through when off.
The MOSFET-related power losses for one channel are summarized by the equations presented in 表 9-1,
where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the
influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic
inductances and SW node ringing, are not included. Consult the LM5149 Quickstart Calculator.
表9-1. MOSFET Power Losses
POWER LOSS MODE
HIGH-SIDE MOSFET
LOW-SIDE MOSFET
DIL2
12
DIL2
12
≈
’
≈
’
MOSFET conduction(2)
2
2
∆
÷
÷
◊
Å ∆
÷
÷
◊
P
= D∂ IOUT
+
∂RDS(on)1
P
= D ∂ IOUT
+
∂RDS(on)2
cond1
cond2
(3)
∆
«
∆
«
»
…
ÿ
F Ÿ
⁄
V
IN ∂FSW
2
DIL
2
DIL
2
≈
’
≈
’
P
=
I
-
∂ tR + I
+
∂ t
MOSFET switching
Negligible
PGate2 = VCC ∂FSW ∂QG2
sw1
∆ OUT
÷
◊
∆ OUT
÷
◊
«
«
MOSFET gate drive(1)
PGate1 = VCC ∂FSW ∂QG1
MOSFET output
charge(4)
PCoss = FSW ∂ VIN ∂Qoss2 + Eoss1 -Eoss2
»
…
ÿ
dt2 Ÿ
⁄
DIL
2
DIL
2
≈
’
≈
’
Body diode
conduction
P
= VF ∂FSW
I
+
∂ tdt1 + I
∆ OUT
-
∂ t
N/A
condBD
∆ OUT
÷
◊
÷
◊
«
«
Body diode
PRR = VIN ∂FSW ∂QRR2
reverse recovery(5)
(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the
relevant driver resistance of the LM5149.
(2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
(3) D' = 1–D is the duty cycle complement.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged without losses by
the inductor current at high-side MOSFET turnoff. During turn-on, however, a current flows from the input to charge the output
capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on
Coss2
.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on time (or D interval) and typically
incurs most of the switching losses. The high-side (control) MOSFET is therefore imperative to choose a high-
side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-
side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge,
and typically two-thirds of the net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or during
the 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current
just communicates from the channel to the body diode or vice versa during the transition deadtimes. LM5149,
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with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such
losses scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low RDS(on) is critical. In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM5149 is well suited to drive TI's portfolio of NexFET™ power MOSFET.
9.1.1.5 EMI Filter
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the
filter output impedance must be less than the absolute value of the converter input impedance.
2
V
IN(min)
ZIN = -
P
IN
(20)
The passive EMI filter design steps are as follows:
• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter.
• Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in
a high-current design.
• Calculate input filter capacitor CF.
图9-2. Passive π-Stage EMI Filter for Buck Regulator
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by 方程式21.
≈
’
IL(PEAK)
1
∆
∆
«
÷
÷
◊
Attn = 20log
∂sin
p
∂DMAX
∂
- VMAX
(
)
1ꢀV
p
2 ∂FSW ∂CIN
(21)
where
• VMAX is the allowed dBμV noise level for the applicable conducted EMI specification, for example CISPR 32
Class B.
• CIN is the existing input capacitance of the buck regulator.
• DMAX is the maximum duty cycle.
• IPEAK is the peak inductor current.
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For filter design purposes, the current at the input can be modeled as a square-wave. Determine the passive
EMI filter capacitance CF from 方程式22.
2
Attn
≈
∆
∆
’
÷
÷
40
1
10
CF =
LIN
2p
∂FSW
∆
∆
«
÷
÷
◊
(22)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small so that the input filter does not significantly affect the loop gain
of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
passive filter is given by 方程式23.
1
fres
=
2
p ∂ LIN ∂CF
(23)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD must
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added input damping
is needed when the output impedance of the filter is high at the resonant frequency (Q of the filter formed by LIN
and CIN is too high). Use an electrolytic capacitor CD for input damping with a value given by 方程式24.
CD í 4 ∂CIN
(24)
Select the input damping resistor RD using 方程式25.
LIN
RD
=
CIN
(25)
9.1.1.6 Active EMI Filter
Active EMI filtering uses a capacitive multiplier to reduce the magnitude of the LC filtering components. Extra
compensation components are needed, but the reduction in LC size outweigh the required network. The active
EMI filter design steps are as follows:
• Calculate the required attenuation of the EMI filter at the switching frequency, similar to the passive EMI filter.
• Select input filter inductor LIN between 0.47 µH and 4.7 µH, lower than the passive EMI inductor.
• Use recommended values for sensing and compensation components CSEN, CAEFC, RAEFC, CINC, and RINC
• Calculate active EMI injection capacitor CINJ
• Calculate active EMI damping resistor RDAMP
• For low-frequency designs (FSW < 1 MHz), calculate the active EMI damping capacitance CDAMP
.
.
.
.
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LIN
VIN-EMI
VIN
CINJ
CSEN
CINC
CD
CIN
CDAMP
RDAMP
GND
RINC
RD
CAEFC RAEFC
Active EMI pins
RAEFVDD
CAEFVDD
RAEFDC
INJ
AEFVDDA
VCC
SEN
REFAGND
AVSS
图9-3. Active EMI Filter for a Buck Regulator
备注
TI does not recommending placing a capacitor from VIN-EMI to GND. However, if a capacitor from
IN-EMI to GND is required, ensure a capacitor with greater than 100 mΩ of ESR is used. Capacitors
V
with less than 100 mΩof ESR, such as ceramics, can cause the active EMI filter to become unstable.
The active EMI filter is intended to cancel differential-mode noise in steady-state conditions. Large
pertubations or low-frequency transients on the VIN-EMI node can potentially limit the amplifier noise
canceling ability.
Use 方程式 21 to determine the attenuation required. 表 9-2 lists the recommended compensation and sensing
component values. Use low FSW component values if FSW ≤ 1 MHz and high FSW component values if FSW
>
1MHz.
表9-2. Recommended Active EMI Compensation Component Values
AEF COMPONENT
LOW FSW
0.1 µF
1 kΩ
HIGH FSW
0.1 µF
200 Ω
5 nF
DESCRIPTION
Sensing capacitor
Compensation
Compensation
Compensation
Compensation
Decoupling
CSEN
RAEFC
CAEFC
1 nF
RINC
0.47 Ω
0.1 µF
3 Ω
0.47 Ω
0.1 µF
3 Ω
CINC
RAEFVDD
CAEFVDD
2.2 µF
2.2 µF
Decoupling
Select the desired LIN. Determine the Active EMI filter capacitance CINJ from 方程式26.
2
Attn
≈
∆
∆
’
÷
÷
40
1
10
CINJ
=
CSEN
2p
∂FSW
∆
÷
÷
◊
∂LIN ∆
CAEFC
«
(26)
Determine the Active EMI damping resistor RDAMP from 方程式27.
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CSEN LIN
∂
RDAMP
=
CAEFC CINJ
(27)
Determine the Active EMI damping capacitance CDAMP from 方程式28. CDAMP is not needed for FSW > 1 MHz.
1
CDAMP
=
∂CINJ
2
(28)
9.1.2 Error Amplifier and Compensation
图 9-4 shows a type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the EA
open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance, CBW, as
shown by 方程式29.
g ∂RO-EA
m
GEA(openloop)(s) = -
1+ s∂RO-EA ∂CBW
(29)
The EA high-frequency pole is neglected in the above expression. 方程式 30 calculates the compensator
transfer function from output voltage to COMP node, including the gain contribution from the (internal or external)
feedback resistor network.
≈
’
÷
◊
s
gm ∂RO-EA ∂ 1+
∆
Ù
vc (s)
w
z1
VREF
VOUT
«
Gc (s) =
= -
∂
Ù
vout (s)
≈
’ ≈
’
s
s
1+
∂ 1+
∆
∆
«
÷ ∆
÷ ∆
◊ «
÷
÷
◊
wp1
wp2
(30)
where
• VREF is the feedback voltage reference of 0.8 V.
• gm is the EA gain transconductance of 1200 µS.
• RO-EA is the error amplifier output impedance of 64 MΩ.
1
wZ1
wp1
wp2
=
=
=
RCOMP ∂CCOMP
(31)
(32)
1
1
@
RO-EA ∂ C
+ CHF + CBW
RO-EA ∂CCOMP
(
)
COMP
1
1
@
RCOMP ∂CHF
RCOMP ∂ C
C
+ CBW
(
)
COMP
HF
(33)
The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically,
RCOMP << RO-EA and CCOMP >> CBW and CHF, so the approximations are valid.
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VOUT
RFB1
Error Amplifier Model
FB
COMP
œ
gm
VREF
+
wp2
RCOMP
wz1
RO-EA
wp1
RFB2
CHF
CBW
CCOMP
AGND
图9-4. Error Amplifier and Compensation Network
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9.2 Typical Applications
9.2.1 Design 1 –High-Efficiency 2.1-MHz Synchronous Buck Regulator
图9-5 shows the schematic diagram of a single-output synchronous buck regulator with an output voltage of 5 V
and a rated load current of 8 A. In this example, the target half-load and full-load efficiencies are 93.5% and
92.5%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 36 V. The switching
frequency is set at 2.1 MHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA
(tie VCCX to GND in this case).
LIN
0.68 µH
VIN = 5.5 V...36 V
CINJ
CSEN
0.1
CDAMP1
47
Tie to VOUT
or GND
RINC
0.47
CIN
2 ꢀ 10
F
0.47
F
F
F
RDAMP
3
CVCC
2.2
CINC
0.1
F
F
VCCX
VCC
EN
VIN
CBOOT
HO
CAEFC
RAEFC
CBOOT
0.1
VDDA
Q1
VOUT = 5 V
IOUT = 8 A
F
RFB
24.9 k
RS
5 m
LO
FB
1 nF 200
0.68
Q2
H
SW
CO
RCOMP
10 k
CCOMP
2.7 nF
RAEFDC
49.9 k
EXTCOMP
4 ꢀ 47
F
LM5149
LO
PGND
CHF
N/A
ISNS+
VOUT
INJ
SENSE
To AEF
sense point
REFAGND
PG/SYNCOUT
PFM/SYNC
VDDA
AGND
VCC
AEFVDDA
AVSS
RAEFVDD
3
RT
CNFG
CAEFVDD
2.2
* VOUT tracks VIN if VIN < 5.2 V
F
RCNFG
24.9 k
RRT
9.52 k
CVDDA
0.1
F
图9-5. Application Circuit 1 With LM5149 Buck Regulator at 2.1 MHz
备注
This and subsequent design examples are provided herein to showcase the LM5149 controller in
several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See 节9.3 for more detail.
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9.2.1.1 Design Requirements
表 9-3 shows the intended input, output, and performance parameters for this design example. Reference the
LM25149-Q1EVM-2100 evaluation module.
表9-3. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Min transient input voltage
Max transient input voltage
Output voltage
VALUE
8 V to 18 V
5.5 V
36 V
5 V
Output current
8 A
Switching frequency
2.1 MHz
±1%
Output voltage regulation
Standby current, no-load
Shutdown current
12 µA
2.3 µA
3 ms
Soft-start time
The switching frequency is set at 2.1 MHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 60 kHz with a phase margin greater than 50°.
The selected buck regulator powertrain components are cited in 表 9-4, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Power MOSFETs. This design uses a low-DCR metal-powder composite
inductor and ceramic output capacitor implementation.
表9-4. List of Materials for Application Circuit 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
Taiyo Yuden
Murata
UMJ325KB7106KMHT
GCM32EC71H106KA03
CGA6P3X7S1H106K250AB
GCM32ER70J476KE19L
JMK325B7476KMHTR
CGA6P1X7S1A476M250AC
XGL6030-681MEB
CIN
2
10 µF, 50 V, X7S, 1210, ceramic
TDK
Murata
47 µF, 6.3 V, X7R, 1210, ceramic
CO
4
1
Taiyo Yuden
TDK
47 µF, 10 V, X7S, 1210, ceramic
Coilcraft
0.68 μH, 2.9 mΩ, 15.3 A, 6.7 × 6.5 × 3.1 mm
0.56 μH, 3.6 mΩ, 13 A, 6.6 × 6.6 × 4.8 mm
0.68 µH, 4.5 mΩ, 22 A, 6.95 × 6.6 × 2.8 mm
40 V, 4.7 mΩ, 12 nC, SON 5 × 6
LO
Würth Electronik
Cyntec
744373490056
VCMV063T-R68MN2T
CSD18503Q5A
Q1
Q2
1
1
Texas Instruments
Texas Instruments
CSD18511Q5A
40 V, 2.7 mΩ, 35 nC, SON 5 × 6
RS
U1
1
1
Susumu
KRL2012E-M-R005-F-T5
LM5149RGYR
Shunt, 5 mΩ, 0508, 1 W
LM5149 80-V synchronous buck controller with AEF
Texas Instruments
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5149 device with the WEBENCH Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the regulator specifications using the LM5149 Quickstart Calculator available for
download from the LM5149 product folder.
9.2.1.2.3 Buck Inductor
1. Use 方程式34 to calculate the required buck inductance based on a 30% inductor ripple current at nominal
input voltages.
≈
’
VOUT
VOUT
≈
’
5V
5V
∆
÷
÷
◊
LO
=
∂ 1 -
=
∂ 1-
= 0.58ꢀH
∆
÷
◊
∆
«
DILO ∂F
V
2.4A ∂2.1MHz
12V
«
SW
IN nom
(
)
(34)
2. Select a standard inductor value of 0.56 µH or use a 0.68 µH to account for effective inductance derating
with current of molded inductors. Use 方程式35 to calculate the peak inductor current at maximum steady-
state input voltage. Subharmonic oscillation occurs with a duty cycle greater than 50% for peak current-
mode control. For design simplification, the LM5149 has an internal slope compensation ramp proportional
to the switching frequency that is added to the current sense signal to damp any tendency toward
subharmonic oscillation.
≈
∆
«
’
DILO
2
VOUT
VOUT
≈
’
÷
◊
5V
5V
ILO(PK) = IOUT
+
= IOUT
+
∂ 1-
= 8A +
∂ 1-
= 9.53A
∆
÷
÷
◊
∆
2∂LO ∂FSW
V
0.56ꢀH∂ 2.1MHz
18V
«
IN(max)
(35)
3. Based on 方程式9, use 方程式36 to cross-check the inductance to set a slope compensation close to the
ideal one times the inductor current downslope.
VOUT ∂RS
24 ∂FSW
5V ∂5mW
24 ∂2.1MHz
LO(sc)
=
=
= 0.5ꢀH
(36)
9.2.1.2.4 Current-Sense Resistance
1. Calculate the current-sense resistance based on a maximum peak current capability of at least 25% higher
than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients.
Calculate the current sense resistances using 方程式37.
VCS-TH
1.25 ∂ILO(PK) 1.25 ∂9.53A
60mV
RS
=
=
= 5.04mW
(37)
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where
• VCS-TH is the 60-mV current limit threshold.
2. Select a standard resistance value of 5 mΩ for the shunt. An 0508 footprint component with wide aspect
ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB
layout. Carefully adhere to the layout guidelines in 节9.4.1 to make sure that noise and DC errors do not
corrupt the differential current-sense voltages measured at the ISNS+ and VOUT pins.
3. Place the shunt resistor close to the inductor.
4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM5149.
5. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power
MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For
a total propagation delay tDELAY-ISNS+ of 40 ns, use 方程式38 to calculate the worst-case peak inductor
current with the output shorted.
V
IN(max) ∂ tDELAY-ISNS+
VCS-TH
RS
60mV 18V ∂ 45ns
ILO-PK(SC)
=
+
=
+
= 13.5A
LO
5mW
0.56ꢀH
(38)
6. Based on this result, select an inductor with saturation current greater than 16 A across the full operating
temperature range.
9.2.1.2.5 Output Capacitors
1. Use 方程式39 to estimate the output capacitance required to manage the output voltage overshoot during a
load-off transient (from full load to no load) assuming a load transient deviation specification of 1.5% (75 mV
for a 5-V output).
2
2
0.56ꢀH∂ 8A
(
)
(
LO ∂ DIOUT
COUT
í
=
= 47.4ꢀF
2
2
2
2
V
+ DVOVERSHOOT - VOUT
5V + 75mV - 5V
(
)
(
)
)
OUT
(39)
2. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly
with applied voltage, select four 47-µF, 10-V, X7R, 1210 ceramic output capacitors. Generally, when
sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot
during a no-load to full-load transient is also satisfactory.
3. Use 方程式40 to estimate the peak-peak output voltage ripple at nominal input voltage.
2
2
≈
∆
«
’
÷
◊
DILO
8 ∂FSW ∂COUT
≈
∆
«
’
÷
◊
2.54A
2
2
DVOUT
=
+ RESR ∂ DILO
(
=
+ 1mW ∂ 2.54A = 4.3mV
)
(
)
8 ∂ 2.1MHz ∂ 44ꢀF
(40)
where
• RESR is the effective equivalent series resistance (ESR) of the output capacitors.
• 44 µF is the total effective (derated) ceramic output capacitance at 5 V.
4. Use 方程式41 to calculate the output capacitor RMS ripple current using and verify that the ripple current is
within the capacitor ripple current rating.
DILO
2.54A
12
ICO(RMS)
=
=
= 0.73A
12
(41)
9.2.1.2.6 Input Capacitors
A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality
input capacitors are necessary to limit the input ripple voltage. In general, the ripple current splits between the
input capacitors based on the relative impedance of the capacitors at the switching frequency.
1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
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2. Use 方程式42 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle
operating point of 50%.
ICIN(RMS) = IOUT ∂ D∂ 1-D = 8A ∂ 0.5 ∂ 1- 0.5 = 4A
(
)
(
)
(42)
(43)
3. Use 方程式43 to find the required input capacitance.
D∂ 1-D ∂I 0.5∂ 1- 0.5 ∂8A
(
)
(
)
OUT
CIN
í
=
= 9.2 ꢀF
FSW ∂ DV -RESR ∂IOUT
2.1MHz∂ 120mV - 2mW∂8A
(
)
(
)
IN
where
• ΔVIN is the input peak-to-peak ripple voltage specification.
• RESR is the input capacitor ESR.
4. Recognizing the voltage coefficient of ceramic capacitors, select two 10-µF, 50-V, X7R, 1210 ceramic input
capacitors. Place these capacitors adjacent to the power MOSFETs. See Power Stage Layout for more
detail.
5. Use four 10-nF, 50-V, X7R, 0603 ceramic capacitors near the high-side MOSFET to supply the high di/dt
current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and
low effective impedance above 100 MHz. The result is lower power loop parasitic inductance, thus
minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature. Refer
to Layout Guidelines for more detail.
9.2.1.2.7 Frequency Set Resistor
Calculate the RT resistance for a switching frequency of 2.1 MHz using 方程式44. Choose a standard E96 value
of 9.53 kΩ.
106
FSW (kHz)
45
106
2100kHz
45
- 53
- 53
RT (kW) =
=
= 9.4kW
(44)
9.2.1.2.8 Feedback Resistors
If an output voltage setpoint other than 3.3 V or 5 V is required (or to measure a bode plot when using either of
the fixed output voltage options), determine the feedback resistances using 方程式45.
(45)
9.2.1.2.9 Compensation Components
Choose compensation components for a stable control loop using the procedure outlined as follows:
1. Based on a specified loop gain crossover frequency, fC, of 60 kHz, use 方程式46 to calculate RCOMP
assuming an effective output capacitance of 100 µF. Choose a standard value for RCOMP of 10 kΩ.
,
VOUT RS ∂GCS
5V 5mW∂10
0.8V 1200ꢀS
RCOMP = 2
p
∂ fC ∂
∂
∂COUT = 2
p
∂60kHz ∂
∂
∂100ꢀF = 9.82kW
VREF
gm
(46)
2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line
transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the
load pole. Choose a standard value for CCOMP of 2.7 nF.
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10
10
CCOMP
=
=
= 2.65 nF
2
p
∂ fC ∂RCOMP
2
p
∂60kHz ∂10 kW
(47)
Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout
(when the input voltage is less than the output voltage setpoint and VCOMP is railed high).
3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. CBW is the
bandwidth-limiting capacitance of the error amplifier. CHF can not be significant enough to be necessary in
some designs, like this one. CHF can be unpopulated, or used with a small 22 pF for more noise filtering.
1
1
CHF
=
- CBW
=
- 31 pF = 0.8 pF
2
p
∂ fESR ∂RCOMP
2
p
∂500kHz ∂10 kW
(48)
备注
Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from
operation in dropout.
备注
For technical solutions, industry trends, and insights for designing and managing power supplies,
please refer to TI's technical articles.
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9.2.1.3 Application Curves
100
95
90
85
80
75
70
100
90
80
70
60
50
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 8 V
VIN = 12 V
VIN = 18 V
0.001
0.01
0.1
1
8
0
1
2
3
4
5
6
7
8
Load Current (A)
Load Current (A)
5-V output
5-V output
图9-7. Efficiency vs IOUT, Log Scale
图9-6. Efficiency vs IOUT
8-A resistive load
No load
图9-8. Full load Switching
图9-9. PFM Switching
VIN falls to 4 V
5-A load
VIN ramps from 12 to 36 V
5-A load
图9-11. Line Transient Response to VIN = 4 V
图9-10. Line Transient Response to VIN = 36 V
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VIN step to 12 V
8-A resistive load
VIN = 12 V
8-A resistive load
图9-12. Start-Up Characteristic
图9-13. ENABLE ON and OFF Characteristic
VIN = 12 V
FPWM
VIN = 12 V
FPWM
图9-15. Load Transient, 4 A to 8 A
图9-14. Load Transient, 0 A to 8 A
CISPR 25 Class
5
5
Peak
Average
Start 150 kHz
Stop 30 MHz
CISPR 25 Class
VIN = 13.8 V
150 kHz to 30 MHz
7-A resistive load
图9-17. CISPR 25 Class 5 Conducted EMI
VIN = 12 V
8-A resistive load
图9-16. Bode Plot, 5-V Output
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9.2.2 Design 2 –High Efficiency 48-V to 12-V 400-kHz Synchronous Buck Regulator
图9-18 shows the schematic diagram of a single-output synchronous buck regulator with an output voltage of 12
V and a rated load current of 8 A. In this example, the target half-load and full-load efficiencies are 95% and
94%, respectively, based on a nominal input voltage of 48 V that ranges from 12.5 V to 72 V. The switching
frequency is set at 400 kHz by resistor RRT
.
LIN
VIN = 12.5 V...72 V
1 µH
CINJ
CDAMP1
RINC
0.47
CIN
4 ꢀ 4.7
CSEN
Tie to 5 V
or GND
0.47
F
100
F
F
0.1
F
CVCC
2.2
RDAMP
15
CINC
0.1
CDAMP
0.22
F
F
F
VCC
VCCX
VIN
EN
CBOOT
HO
VDDA
CBOOT
CAEFC
RAEFC
RFB
0.1
F
VOUT = 12 V
IOUT = 8 A
Q1
FB
RS
5 m
48.7 k
LO
1 nF 1 k
CCOMP
6.8 nF
RCOMP
4.75 k
6.8
Q2
H
SW
CO
EXTCOMP
RAEFDC
49.9 k
4 ꢀ 22 F
LM5149
LO
PGND
CHF 100 pF
INJ
ISNS+
VOUT
SENSE
To AEF
REFAGND
sense point
PG/SYNCOUT
PFM/SYNC
VDDA
AGND
VCC
Tie to VDDA
or GND
AEFVDDA
AVSS
RAEFVDD
3
RT
CNFG
CAEFVDD
2.2
F
* VOUT tracks VIN if VIN < 12.5 V
RCNFG
24.9 k
CVDDA
0.1
RRT
54.9 k
F
图9-18. Application Circuit 2 With LM5149 Buck Regulator at 400 kHz
9.2.2.1 Design Requirements
表 9-5 shows the intended input, output, and performance parameters for this design example. Reference the
LM5149-Q1EVM-400 evaluation module.
表9-5. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Min transient input voltage
Max transient input voltage
Output voltage
VALUE
15 V to 72 V
12.5 V
80 V
12 V
Output current
8 A
Switching frequency
400 kHz
±1%
Output voltage regulation
No-load standby current
Shutdown current
12 µA
2.3 µA
3 ms
Soft-start time
The switching frequency is set at 400 kHz by resistor RRT. The selected buck regulator powertrain components
are cited in 表9-6, and many of the components are available from multiple vendors. The MOSFETs in particular
are chosen for both lowest conduction and switching power loss, as discussed in detail in Power MOSFETs.
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表9-6. List of Materials for Application Circuit 2
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
TDK
CGA6M3X7S2A475K200
GCM32DC72A475KE02L
CGA6P3X7R1E226M
GCM32EC71E226KE36
VCHA105D-6R8MS6
784325065
CIN
CO
4
4.7 μF, 100 V, X7S, 1210, ceramic
4
1
22 µF, 25 V, X7R, 1210, ceramic
Murata
Cyntec
Wurth
TDK
6.8 μH, 12 mΩ, 13.3 A, 10.85 × 10.0 × 5.2 mm
6.5 μH, 10.5 mΩ, 13 A, 10.5 × 10.0 × 4.5 mm
6.8 μH, 13.3 mΩ, 21.4 A, 10.5 × 10.0 × 6.5 mm
80 V, 19.5 mΩ, 12 nC, SON 5 × 6
LO
SPM10065VT-6R8M-D
NVMFS6H858NLT1G
IAUC28N08S5L230
onsemi
Infineon
Q1
Q2
1
1
80 V, 23 mΩ, 11 nC, SON 5 × 6
onsemi
Infineon
NVMFS6H848NLT1G
IAUC50N08S5L096
KRL2012E-M-R005-F-T5
LM5149RGYR
80 V, 8.8 mΩ, 25 nC, SON 5 × 6
80 V, 9.6 mΩ, 22 nC, SON 5 × 6
RS
U1
1
1
Susumu
Shunt, 5 mΩ, 0508, 1 W
LM5149 80-V synchronous buck controller with AEF
Texas Instruments
9.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
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9.2.2.3 Application Curves
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
60
VIN = 24 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
0.001
0.01
0.1
Load (A)
1
8
0
1
2
3
4
5
6
7
8
Load (A)
12-V output
12-V output
图9-20. Efficiency vs. IOUT, Log Scale
图9-19. Efficiency vs. IOUT
VOUT 50mV/DIV
VOUT 200mV/DIV
SW 20V/DIV
SW 20V/DIV
5 ms/DIV
1 µs/DIV
No load
8-A resistive load
图9-22. PFM Switching
图9-21. Full load Switching
VIN 10 V/DIV
VOUT 50 mV/DIV
VIN 20V/DIV
VOUT 2 V/DIV
IOUT 2 A/DIV
PG 5 V/DIV
1 ms/DIV
20 ms/DIV
VIN step to 48 V
8-A resistive load
VIN ramps from 24 to 72 V
4-A load
图9-23. Start-Up Characteristic
图9-24. Line Transient Response to VIN = 72 V
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VOUT 2 V/DIV
IOUT 2 A/DIV
VOUT 2 V/DIV
EN 2 V/DIV
EN 2 V/DIV
PG 5 V/DIV
PG 5 V/DIV
1 ms/DIV
1 ms/DIV
VIN = 48 V
8-A resistive load
VOUT Pre-biased to 5 V
图9-25. EN Start-Up Characteristic
图9-26. EN Start-Up Pre-bias Characteristic
VOUT 500 mV/DIV
VOUT 500 mV/DIV
IOUT 2 A/DIV
IOUT 2 A/DIV
100 µs/DIV
100 µs/DIV
VIN = 48 V
FPWM
VIN = 48 V
FPWM
图9-27. Load Transient, 0 A to 4 A
图9-28. Load Transient, 4 A to 8 A
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9.2.3 Design 3 –High Efficiency 440-kHz Synchronous Buck Regulator
图 9-29 shows the schematic diagram of a single-output synchronous buck regulator with an output voltage of 5
V and a rated load current of 10 A. In this example, the target half-load and full-load efficiencies are 97% and
95%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 72 V. The switching
frequency is set at 440 kHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA
(tie VCCX to GND in this case).
LIN
VIN = 5.5 V...72 V
1 µH
CINJ
CDAMP1
100
RINC
0.47
CIN
4 ꢀ 4.7
4 ꢀ 10 nF
CSEN
Tie to VOUT
or GND
0.47
F
F
F
0.1
F
CVCC
2.2
RDAMP
17.8
CINC
0.1
CDAMP
0.22
F
F
F
VCC
VCCX
VIN
EN
CBOOT
HO
VDDA
CBOOT
CAEFC
RAEFC
RFB
0.1
F
VOUT = 5 V
IOUT = 10 A
Q1
FB
RS
4 m
24.9 k
LO
1 nF 1 k
CCOMP
15 nF
RCOMP
4.22 k
2.2
Q2
H
SW
CO
EXTCOMP
RAEFDC
49.9 k
4 ꢀ 47 F
LM5149
LO
PGND
CHF 150 pF
INJ
ISNS+
VOUT
SENSE
To AEF
REFAGND
sense point
PG/SYNCOUT
PFM/SYNC
VCC
Tie to VDDA
or GND
AEFVDDA
AVSS
RAEFVDD
3
RT
VDDA
AGND
CNFG
CAEFVDD
2.2
F
* VOUT tracks VIN if VIN < 5.2 V
RCNFG
24.9 k
CVDDA
0.1
RRT
49.9 k
F
图9-29. Application Circuit 3 With LM5149 Buck Regulator at 440 kHz
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9.2.3.1 Design Requirements
表9-7 shows the intended input, output, and performance parameters for this design example.
表9-7. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Min transient input voltage
Max transient input voltage
Output voltage
VALUE
8 V to 72 V
5.5 V
80 V
5 V
Output current
10 A
Switching frequency
440 kHz
±1%
Output voltage regulation
Standby current, no-load
Shutdown current
12 µA
2.3 µA
3 ms
Soft-start time
The switching frequency is set at 440 kHz by resistor RRT. The selected buck regulator powertrain components
are cited in 表9-8, and many of the components are available from multiple vendors. The MOSFETs in particular
are chosen for both lowest conduction and switching power loss, as discussed in detail in Power MOSFETs.
表9-8. List of Materials for Application Circuit 3
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
CGA6M3X7S2A475K200
GCM32DC72A475KE02L
GCM32ER70J476KE19L
JMK325B7476KMHTR
CGA6P1X7S1A476M250AC
XGL6060-222MEC
CIN
2
4.7 μF, 100 V, X7S, 1210, ceramic
Murata
47 µF, 6.3 V, X7R, 1210, ceramic
CO
4
Taiyo Yuden
TDK
47 µF, 10 V, X7S, 1210, ceramic
Coilcraft
Würth Electronik
onsemi
2.2 μH, 4.3 mΩ, 12.5 A, 6.7 × 6.5 × 6.1 mm
2.2 µH, 6.5 mΩ, 10 A, 10 × 11 × 3.8 mm
80 V, 8.8 mΩ, 25 nC, SON 5 × 6, AEC-Q101
80 V, 9.6 mΩ, 22 nC, SON 5 × 6, AEC-Q101
Shunt, 4 mΩ, 0508, 1 W
LO
1
2
74437368022
NVMFS6H848NLT1G
IAUC50N08S5L096
Q1, Q2
Infineon
RS
U1
1
1
Susumu
KRL2012E-M-R004-F-T5
LM5149RGYR
LM5149 80-V synchronous buck controller with AEF
Texas Instruments
9.2.3.2 Detailed Design Procedure
See Detailed Design Procedure.
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9.2.3.3 Application Curves
100
100
90
80
70
60
50
95
90
85
80
75
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0
1
2
3
4
5
6
7
8
9
10
0.001
0.01
0.1
1
10
Load Current (A)
Load Current (A)
5-V output
5-V output
图9-30. Efficiency vs. IOUT
图9-31. Efficiency vs. IOUT, Log Scale
VOUT 20mV/DIV
VOUT 50mV/DIV
SW 5V/DIV
SW 5V/DIV
100 ms/DIV
1 µs/DIV
No load
10-A resistive load
图9-33. PFM Switching
图9-32. Full load Switching
VIN 1 V/DIV
VOUT 1 V/DIV
VIN 10 V/DIV
VOUT 50 mV/DIV
IOUT 1 A/DIV
PG 5 V/DIV
IOUT 5A/DIV
5 ms/DIV
20 ms/DIV
VIN ramps from 12 to 40 V
5-A load
VIN falls to 4 V
1-A load
图9-34. Line Transient Response to VIN = 40 V
图9-35. Line Transient Response to VIN = 4 V
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EN 2V/DIV
VIN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 5A/DIV
IOUT 5A/DIV
1 ms/DIV
1 ms/DIV
VIN = 12 V
10-A resistive load
VIN step to 12 V
10-A resistive load
图9-37. ENABLE ON and OFF Characteristic
图9-36. Start-Up Characteristic
VOUT 500 mV/DIV
VOUT 500 mV/DIV
IOUT 5 A/DIV
IOUT 5 A/DIV
100 µs/DIV
100 µs/DIV
VIN = 12 V
FPWM
VIN = 12 V
FPWM
图9-38. Load Transient, 0 A to 10 A
图9-39. Load Transient, 5 A to 10 A
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9.2.4 Design 4 –Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
图 9-40 shows the schematic diagram of a dual-phase synchronous buck regulator with an output voltage of 3.3
V and a rated load current of 20 A. In this example, the target half-load and full-load efficiencies are 95% and
92%, respectively, based on a nominal input voltage of 12 V that ranges from 4 V to 72 V. The switching
frequency is set at 400 kHz by resistors RRT1 and RRT2
.
VIN = 4 V...72 V
Tie to 5 V
or GND
CIN1
2 × 4.7
F
4 × 10 nF
CVCC1
2.2
VOUT
PFM / FPWM setting
or SYNCIN
F
VCCX
VCC
EN
VIN
PFM/SYNC
FB
CBOOT
HO
RFB1
100 k
CBOOT1
VOUT = 3.3 V
IOUT = 20 A
Q1
0.1
F
RS1
4 m
LO1
2.2
Q2
RFB2
31.6 k
H
SW
CO1
CCOMP
8.2 nF
RCOMP
5.23 k
LM5149
Primary
EXTCOMP
4 × 47
F
LO
PGND
CHF
120 pF
ISNS+
VOUT
INJ
SENSE
REFAGND
PG/SYNCOUT
VDDA
AGND
AEFVDDA
AVSS
RT
CNFG
RCNFG1
71.5 k
RRT1
56.2 k
CVDDA1
0.1
F
VIN
Tie to 5 V
or GND
CIN2
2 × 4.7
4 × 10 nF
F
CVCC2
2.2
F
PFM/SYNC
VIN
EN
VCCX
VCC
CBOOT
HO
CBOOT2
0.1
Q3
Q4
F
RS2
4 m
PFM / FPWM
setting
LO2
2.2
FB
H
SW
CO2
LM5149
(LM5148)
EXTCOMP
4 × 47
F
LO
Secondary
PGND
ISNS+
VOUT
INJ
SENSE
REFAGND
System
PGOOD
PG/SYNCOUT
VDDA
AGND
AEFVDDA
AVSS
RT
CNFG
RCNFG2
RRT2
56.2 k
CVDDA2
0.1
F
90.9 k
图9-40. Application Circuit 4 With Two LM5149 Buck Controllers at 400 kHz
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备注
A design with 3 or more phases is feasible when appropriately phase-shifted clock signals are
available. For example, a 4-phase design requires 4 LM5149 controllers with 0°, 90° and 270°
external SYNC signals to achieve the ideal phase separation of 360° divided by the total number of
phases.
9.2.4.1 Design Requirements
表9-9 shows the intended input, output, and performance parameters for this design example.
表9-9. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Min transient input voltage
Max transient input voltage
Output voltage
VALUE
8 V to 72 V
4 V
80 V
3.3 V
Output current
20 A
Switching frequency
400 kHz
±1%
Output voltage regulation
Standby current, no-load
Shutdown current
44 µA
4.6 µA
3 ms
Soft-start time
The switching frequency is set at 400 kHz by resistors RRT1 and RRT2. The selected buck regulator powertrain
components are cited in 表 9-8, and many of the components are available from multiple vendors. The
MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in
Power MOSFETs.
表9-10. List of Materials for Application Circuit 4
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
CGA6M3X7S2A475K200
GCM32DC72A475KE02L
GCM32ER70J476KE19L
CGA6P1X7S1A476M250AC
GRT32EC70J107ME13
XGL6060-222MEC
CIN
4
4.7 μF, 100 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
Murata
8
4
2
CO
47 µF, 10 V, X7S, 1210, ceramic
TDK
100 µF, 6.3 V, X7S, 1210, ceramic
Murata
Coilcraft
Würth Electronik
onsemi
2.2 μH, 4.3 mΩ, 12.5 A, 6.7 × 6.5 × 6.1 mm
2.2 µH, 6.5 mΩ, 10 A, 10 × 11 × 3.8 mm
80 V, 8.8 mΩ, 25 nC, SON 5 × 6, AEC-Q101
LO1, LO2
74437368022
Q1, Q2, Q3, Q4
RS1, RS2
4
2
NVMFS6H848NLT1G
Susumu
KRL2012E-M-R004-F-T5
Shunt, 4 mΩ, 0508, 1 W
LM5149 80-V synchronous buck controller with AEF
LM5148 80-V synchronous buck controller
Texas Instruments
Texas Instruments
LM5149RGYR
LM5148RGYR
U1, U2
2
9.2.4.2 Detailed Design Procedure
See Detailed Design Procedure.
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9.2.4.3 Application Curves
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
60
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0
2
4
6
8
10
12
14
16
18
20
0.001
0.01
0.1
1
10 20
Load Current (A)
Load Current (A)
3.3-V output
3.3-V output
图9-41. Efficiency vs. IOUT
图9-42. Efficiency vs. IOUT, Log Scale
VIN 5V/DIV
EN 2V/DIV
VOUT 1V/DIV
IOUT 10A/DIV
VOUT 1V/DIV
IOUT 10A/DIV
1 ms/DIV
1 ms/DIV
VIN step to 12 V
20-A load
VIN = 12 V
20-A load
图9-43. VIN Start-Up Characteristic
图9-44. ENABLE ON and OFF Characteristic
VOUT 200 mV/DIV
VOUT 500 mV/DIV
IOUT 10 A/DIV
IOUT 10 A/DIV
100 µs/DIV
100 µs/DIV
VIN = 12 V
FPWM
VIN = 12 V
FPWM
图9-45. Load Transient, 5 A to 15 A
图9-46. Load Transient, 0 A to 20 A
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9.3 Power Supply Recommendations
The LM5149 buck controller is designed to operate from a wide input voltage range of 3.5 V to 80 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the
fully loaded regulator. Estimate the average input current with 方程式49.
POUT
I
=
IN
V ∂
h
IN
(49)
where
• ηis the efficiency.
If the regulator is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. The best way to solve such issues is to reduce the distance from the input supply to the
regulator and use an aluminum or polymer input capacitor in parallel with the ceramics. The moderate ESR of
the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. A
capacitance in the range of 10 µF to 47 µF is usually sufficient to provide parallel input damping and helps to
hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
application report provides helpful suggestions when designing an input filter for any switching regulator.
9.4 Layout
9.4.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuit (with high current and voltage
slew rates) to achieve a robust and reliable design. As expected, certain issues must be considered before
designing a PCB layout using the LM5149. The high-frequency power loop of a buck regulator power stage is
denoted by loop 1 in the shaded area of 图 9-47. The topological architecture of a buck regulator means that
particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the
parasitic inductance of this loop by minimizing its effective loop area. Also important are the gate drive loops of
the high-side and low-side MOSFETs, denoted by 2 and 3, respectively, in 图9-47.
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VIN
#1: High frequency power loop
#2: High-side gate drive loop
#3: Low-side gate drive loop
CIN
#1
CBOOT
VCC
CBOOT
Q1
HO
High-side
gate driver
LO
#2
SW
VOUT
VCC
CVCC
#3
COUT
Q2
LO
Low-side
gate driver
PGND
GND
图9-47. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
9.4.1.1 Power Stage Layout
1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). Insert at least one inner
plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
2. The DC/DC regulator has several high-current loops. Minimize the area of these loops to suppress
generated switching noise and optimize switching performance.
• Loop 1: The most important loop area to minimize is the path from the input capacitor or capacitors
through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the ground
connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-
side MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close to
the drain of the high-side MOSFET (at VIN). Refer to loop 1 of 图9-47.
• Another loop, not as critical as loop 1, is the path from the low-side MOSFET through the inductor and
output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the
source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as
close as possible.
3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,
including pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop 1 in 图9-47 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz)
ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the
input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating limit
for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
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9.4.1.2 Gate-Drive Layout
The LM5149 high-side and low-side gate drivers incorporate short propagation delays, adaptive deadtime
control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall
times to facilitate rapid turn-on and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the gate
drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turn-on, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop 2 of 图9-47.
• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop 3 of 图9-47.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side
MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive
currents can be as high as 3.3 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at
least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from
the LM5149 to the high-side MOSFET, taking advantage of flux cancellation.
• Minimize the current loop path from the VCC and HB pins through their respective capacitors as these
provide the high instantaneous current, up to 3.3 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the CBOOT and SW pins of the LM5149 to minimize the area of
loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM5149 to minimize the area of loop 3 associated with the low-side driver.
9.4.1.3 PWM Controller Layout
With the provison to locate the controller as close as possible to the power MOSFETs to minimize gate driver
trace runs, the components related to the analog and feedback signals as well as current sensing are
considered in the following:
• Separate power and signal traces, and use a ground plane to provide noise shielding.
• Place all sensitive analog traces and components related to COMP, FB, ISNS+, and RT away from high-
voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or
layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense
(ISNS+ and VOUT) traces from power traces and components.
• Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short
as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at
the load.
• Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin
connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if
inductor DCR current sensing is used).
• Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
PGND pin. Locate these capacitors as close as possible to the LM5149.
9.4.1.4 Active EMI Layout
Active EMI layout is critical for enhanced EMI performance. Layout considerations are as follows:
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• Connect AVSS to a quiet GND connection, further from IC if possible. Keep decoupling capacitor CAEFVDDA
close to the AEFVDDA pin and AVSS GND connection. See capacitor C23 in 图9-48.
• Route the SEN and INJ traces differentially as close together as possible on an internal quiet layer. Avoid
noisy layer or layers carrying high-voltage traces.
• Place the active EMI compensation components CAEFC, RAEFC, and RAEFDC close together and near the
VIN-EMI node to the input filter inductor.
• CSEN and CINJ components must be placed directly outside of the compensation loop.
• Place input compensation components RAEFC and CAEFC nearby the other Active EMI components. Ensure
the GND connection is far away from any noise sources. Do not connect the input compensation GND near
the power stage.
• Route REFAGND directly to the GND of the input power connector. Do not tie to the GND plane connection.
The REFAGND trace can partially shield the SEN and INJ differential pair on the way to the input power
connector.
9.4.1.5 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by the following:
• Average gate drive current requirements of the power MOSFETs
• Switching frequency
• Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
• Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM5149 controller
is available in a small 4-mm × 4-mm 24-pin VQFN PowerPAD™ intergrated circuit package to cover a range of
application requirements. 节9.4.1.5 summarizes the thermal metrics of this package.
The 24-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM5149 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5149 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed
on the PCB layer below the power components. Not only does this provide a plane for the power stage currents
to flow but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are
normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW
plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.
9.4.1.6 Ground Plane Design
As mentioned previously, TI recommends using one or more of the inner PCB layers as a solid ground plane. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components is
essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output
capacitors to this ground plane. Connect the PGND and AGND pins of the controller at the DAP and then
connect to the system ground plane using an array of vias under the DAP. The PGND nets contain noise at the
switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and
SW can be restricted to one side of the ground plane, for example on the top layer. The other side of the ground
plane contains much less noise and is ideal for sensitive analog trace routes.
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9.4.2 Layout Example
图9-48 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and Q2,
in SON 5-mm × 6-mm case size. The power stage is surrounded by a GND pad geometry to connect an EMI
shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top
layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic
inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.
The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane on
layer 2, and back to VIN through the 0402 ceramic capacitors C17 through C22. The currents flowing in
opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic
inductance. 图 9-50 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a
multilayer PCB structure. The layer-2 GND plane layer, shown in 图 9-49, provides a tightly-coupled current
return path directly under the MOSFETs to the source terminals of Q2.
Six 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of Q1.
The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint
capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected
to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic loop
inductance.
Place PGND vias close to the
source of the low-side FET
Use PGND keep-out to
minimize eddy currents
Locate controller close
to the power stage
Output Caps
PGND
G S
SW
HO
VOUT
VIN
Low-side
FET
GND
LO
VCC
Inductor
SW
Shunt
S
G
AGND
Input Caps
High-side
FET
VIN
GND
GND
Copper island
connected to AGND pin
Use paralleled 0402/0603 input capacitors close
to the FETs for VIN to PGND decoupling
图9-48. PCB Top Layer –High Density, Single-sided Design
Additional guidelines to improve noise immunity and reduce EMI are as follows:
• Make the ground connections to the LM5149 controller as shown in 图9-48. Create a power ground directly
connected to all high-power components and an analog ground plane for sensitive analog components. The
analog ground plane for AGND and power ground plane for PGND must be connected at a single point
directly under the IC –at the die attach pad (DAP).
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• Connect the MOSFETs (switch node) directly to the inductor terminal with short copper connections (without
vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node
connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This
avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours
shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI
signature.
• Place the 节9.1.1.5 components on the bottom side of the PCB so that they are shielded from the power
stage components on the top side.
图9-49. Layer 2 Full Ground Plane Directly Under the Power Components
Tightly-coupled return path
minimizes power loop impedance
CIN
Q2
Q1
SW
VIN
GND
GND
L1
L2
0.15mm
L3
L4
0.3mm
vias
图9-50. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing 1
1
See Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout for more detail.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
With an input operating voltage as low as 3.5 V and up to 100 V as specified in 表 10-1, the LM(2)514x family of
synchronous buck controllers from TI provides flexibility, scalability and optimized solution size for a range of
applications. These controllers enable DC/DC solutions with high density, low EMI and increased flexibility.
Available EMI mitigation features include dual-random spread spectrum (DRSS) or triangular spread spectrum
(TRSS), split gate driver outputs for slew rate (SR) control, and integrated active EMI filtering (AEF). All
controllers are rated for a maximum operating junction temperature of 150°C and have AEC-Q100 grade 1
qualification.
表10-1. Synchronous Buck DC/DC Controller Family
DC/DC
CONTROLLER
SINGLE or
DUAL
GATE DRIVE
VOLTAGE
VIN RANGE
CONTROL METHOD
SYNC OUTPUT
EMI MITIGATION
LM25141
LM25143
LM25145
LM25148
LM25149
LM5141
LM5143
LM5145
LM5146
LM5148
LM5149
Single
Dual
3.8 V to 42 V
3.5 V to 42 V
6 V to 42 V
Peak current mode
Peak current mode
Voltage mode
5 V
N/A
SR control, TRSS
SR control, TRSS
N/A
5 V
90° phase shift
180° phase shift
180° phase shift
180° phase shift
N/A
Single
Single
Single
Single
Dual
7.5 V
5 V
3.5 V to 42 V
3.5 V to 42 V
3.8 V to 42 V
3.5 V to 65 V
6 V to 75 V
Peak current mode
Peak current mode
Peak current mode
Peak current mode
Voltage mode
DRSS
5 V
AEF, DRSS
SR control, TRSS
SR control, TRSS
N/A
5 V
5 V
90° phase shift
180° phase shift
180° phase shift
180° phase shift
180° phase shift
Single
Single
Single
Single
7.5 V
7.5 V
5 V
5.5 V to 100 V
3.5 V to 80 V
3.5 V to 80 V
Voltage mode
N/A
Peak current mode
Peak current mode
DRSS
5 V
AEF, DRSS
For development support see the following:
• LM5149 Quickstart Calculator
• LM5149 Simulation Models
• For TI's reference design library, visit TI Designs
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
• TI Designs:
– Texas Instruments, ADAS 8-Channel Sensor Fusion Hub Reference Design with Two 4-Gbps Quad
Deserializers
– Texas Instruments, Automotive EMI and Thermally Optimized Synchronous Buck Converter Reference
Design
– Texas Instruments, Automotive High Current, Wide VIN Synchronous Buck Controller Reference Design
Featuring LM5141-Q1
– Texas Instruments, 25W Automotive Start-Stop Reference Design Operating at 2.2 MHz
– Texas Instruments, Synchronous Buck Converter for Automotive Cluster Reference Design
– Texas Instruments, 137W Holdup Converter for Storage Server Reference Design
– Texas Instruments, Automotive Synchronous Buck With 3.3V @ 12.0A Reference Design
– Texas Instruments, Automotive Synchronous Buck Reference Design
– Texas Instruments, Wide Input Synchronous Buck Converter Reference Design With Frequency Spread
Spectrum
– Texas Instruments, Automotive Wide VIN Front-end Reference Design for Digital Cockpit Processing Units
• Technical Articles:
– Texas Instruments, High-Density PCB Layout of DC/DC Converters
– Texas Instruments, Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility
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– Texas Instruments, How to Use Slew Rate for EMI Control
• To view a related device of this product, see the LM5141
10.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5149 device with the WEBENCH Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• User's Guides:
– Texas Instruments, LM5149-Q1 Synchronous Buck Controller High Density EVM
– Texas Instruments, LM25149-Q1 Synchronous Buck Controller High Density EVM
– Texas Instruments, LM5141-Q1 Synchronous Buck Controller EVM
– Texas Instruments, LM5143-Q1 Synchronous Buck Controller EVM
– Texas Instruments, LM5146-Q1 EVM User's Guide
– Texas Instruments, LM5145 EVM User's Guide
• Application Reports:
– Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power
Stage Layout Application Report
– Texas Instruments, AN-2162 Simple Success with Conducted EMI from DC-DC Converters
– Texas Instruments, Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140-
Q1 Dual Synchronous Buck Controller
• Technical Briefs:
– Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
• White Papers:
– Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies
– Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies
– Texas Instruments, Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding
Applications
10.2.1.1 PCB Layout Resources
• Application Reports:
– Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power
Stage Layout
– Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies
– Texas Instruments, AN-1229 Simple Switcher PCB Layout Guidelines
– Texas Instruments, Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
• Seminars:
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ZHCSLO6A –DECEMBER 2020 –REVISED JANUARY 2023
– Texas Instruments, Constructing Your Power Supply –Layout Considerations
10.2.1.2 Thermal Design Resources
• Application Reports:
– Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight
– Texas Instruments, AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad
Packages
– Texas Instruments, Semiconductor and IC Package Thermal Metrics
– Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602
– Texas Instruments, PowerPAD™Thermally Enhanced Package
– Texas Instruments, PowerPAD Made Easy
– Texas Instruments, Using New Thermal Metrics
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
NexFET™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages show mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
64
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Product Folder Links: LM5149
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5149RGYR
ACTIVE
VQFN
RGY
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
LM5149
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5149 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2023
Automotive : LM5149-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5149RGYR
VQFN
RGY
24
3000
330.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGY 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM5149RGYR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 24
5.5 x 3.5 mm, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4203539-5/J
PACKAGE OUTLINE
RGY0024F
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
5.6
5.4
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2.1 0.1
2X 1.5
EXPOSED
THERMAL PAD
SYMM
(0.1) TYP
13
12
11
14
SYMM
25
2X 4.5
4.1 0.1
18X 0.5
2
0.3
0.2
23
24X
24
1
0.1
C A B
PIN 1 ID
(45 X 0.35)
0.5
0.3
24X
0.05
4227032/A 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0024F
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.1)
(0.75)
SYMM
SEE SOLDER MASK
DETAIL
1
24
24X (0.6)
2
23
24X (0.25)
(1.12)
(4.1)
20X (0.5)
(0.68) TYP
(5.3)
SYMM
25
(R0.05) TYP
(
0.2) TYP
VIA
14
11
13
12
(0.8) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227032/A 08/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0024F
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.75)
(0.57) TYP
24X (0.6)
1
24
2
23
24X (0.25)
20X (0.5)
(1.36) TYP
(5.3)
(R0.05) TYP
SYMM
25
6X (1.16)
11
14
13
12
6X (0.94)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 25
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4227032/A 08/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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