LM5104MX/NOPB [TI]
具有 8V UVLO 和自适应延迟的 2A、100V 半桥栅极驱动器 | D | 8 | -40 to 125;
| 型号： | LM5104MX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO 和自适应延迟的 2A、100V 半桥栅极驱动器 | D | 8 | -40 to 125 栅极驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总28页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
LM5104 High-Voltage Half-Bridge Gate Driver With Adaptive Delay
1 Features
3 Description
The LM5104 High-Voltage Gate Driver is designed to
1
•
Drives Both a High-Side and Low-Side N-Channel
MOSFET
drive both the high-side and the low-side N-channel
MOSFETs in a synchronous buck configuration. The
floating high-side driver can work with supply voltages
up to 100 V. The high-side and low-side gate drivers
are controlled from a single input. Each change in
state is controlled in an adaptive manner to prevent
shoot-through issues. In addition to the adaptive
transition timing, an additional delay time can be
added, proportional to an external setting resistor. An
integrated high-voltage diode is provided to charge
high-side gate drive bootstrap capacitor. A robust
level shifter operates at high speed while consuming
low power and providing clean level transitions from
the control logic to the high-side gate driver.
Undervoltage lockout is provided on both the low-side
and the high-side power rails. This device is available
in the standard SOIC and the WSON packages.
•
Adaptive Rising and Falling Edges With
Programmable Additional Delay
•
•
•
•
Single Input Control
Bootstrap Supply Voltage Range up to 118-V DC
Fast Turnoff Propagation Delay (25 ns Typical)
Drives 1000-pF Loads With 15-ns Rise and Fall
Times
•
•
Supply Rail Undervoltage Lockout
SOIC and WSON-10 4-mm × 4-mm Package
2 Applications
•
•
•
•
Current Fed Push-Pull Power Converters
High Voltage Buck Regulators
Device Information(1)
Active Clamp Forward Power Converters
Half-Bridge and Full-Bridge Converters
PART NUMBER
LM5104
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
4.00 mm × 4.00 mm
SOIC (8)
WSON (10)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
HV
HO
HS
LEVEL
SHIFT
DRIVER
UVLO
IN
RT
VDD
UVLO
LO
DRIVER
VSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 14
9.1 Power Dissipation Considerations .......................... 14
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 16
11.1 Trademarks........................................................... 16
11.2 Electrostatic Discharge Caution............................ 16
11.3 Glossary................................................................ 16
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 11
2
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
LO
1
2
3
4
8
7
6
5
V
DD
HB
V
SS
SOIC-8
HO
HS
IN
RT
DPR Package
10-Pin WSON
Top View
1
2
3
4
5
10
9
LO
V
DD
HB
V
SS
8
IN
HO
HS
7
RT
NC
NC
6
Pin Functions
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
SOIC
WSON
Locally decouple to VSS using ESR/ESL capacitor, located
as close to IC as possible.
1
1
VDD
Positive gate drive supply
Connect the positive terminal to bootstrap capacitor to the
HB pin and connect negative terminal to HS. The
Bootstrap capacitor should be placed as close to IC as
possible
2
2
HB
High-side gate driver bootstrap rail
Connect to gate of high-side MOSFET with short low
inductance path.
3
4
3
4
HO
HS
High-side gate driver output
Connect to bootstrap capacitor negative terminal and
source of high-side MOSFET.
High-side MOSFET source connection
Resistor from RT to ground programs the deadtime
between high- and low-side transitions. The resistor
should be located close to the IC to minimize noise
coupling from adjacent traces.
5
7
RT
Deadtime programming pin
Logic 1 equals High-side ON and Low-side OFF. Logic 0
equals High-side OFF and Low-side ON.
6
7
8
8
9
IN
VSS
LO
Control input
Ground return
All signals are referenced to this ground.
Connect to the gate of the low-side MOSFET with a short
low inductance path.
10
Low-side gate driver output
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
18
UNIT
V
VDD to VSS
VHB to VHS
18
V
IN to VSS
VDD + 0.3
VDD + 0.3
V
LO Output
V
HO Output
VHS – 0.3 VHB + 0.3
V
VHS to VSS
−1
100
118
5
V
VHB to VSS
V
RT to VSS
–0.3
–55
V
Junction Temperature
Storage temperature range, Tstg
150
150
°C
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Recommended Operating Conditions
under which operation of the device is specified. Recommended Operating Conditions do not imply performance limits. For performance
limits and associated test conditions, see Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
14
UNIT
V
VDD
9
–1
HS
100
V
HB
VHS + 8
VHS + 14
< 50
V
HS Slew Rate
Junction Temperature
V/ns
°C
–40
125
6.4 Thermal Information
LM5104
THERMAL METRIC(1)
D
DPR
UNIT
8 PINS
114.5
61.1
55.6
9.7
10 PINS
37.9
38.1
14.9
0.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
54.9
n/a
15.2
4.4
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD
VHB = 12 V, VSS = VHS = 0 V, RT = 100kΩ. No Load on LO or HO.
=
PARAMETER
TEST CONDITIONS
MIN(1)
TYP
MAX(1)
UNIT
SUPPLY CURRENTS
IDD
VDD Quiescent Current
VDD Operating Current
LI = HI = 0 V
f = 500 kHz
0.4
1.9
0.6
3
mA
mA
mA
mA
µA
IDDO
IHB
IHBO
IHBS
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
LI = HI = 0 V
f = 500 kHz
0.06
1.3
0.2
3
VHS = VHB = 100 V
f = 500 kHz
0.05
0.08
10
IHBSO
INPUT PINS
VIL
mA
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Pulldown Resistance
0.8
1.8
1.8
V
V
VIH
2.2
RI
100
200
500
kΩ
TIME DELAY CONTROLS
VRT
IRT
Nominal Voltage at RT
2.7
0.75
58
3
1.5
90
3.3
2.25
130
270
V
mA
ns
RT Pin Current Limit
RT = 0 V
TD1
TD2
Delay Timer, RT = 10 kΩ
Delay Timer, RT = 100 kΩ
140
200
ns
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.0
5.7
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
VDH
RD
Low-Current Forward Voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
0.60
0.85
0.8
0.9
1.1
1.5
V
V
Ω
High-Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
VOLL
VOHL
Low-Level Output Voltage
ILO = 100 mA
0.25
0.35
0.4
V
V
ILO = –100 mA
VOHL = VDD – VLO
High-Level Output Voltage
0.55
IOHL
IOLL
Peak Pullup Current
VLO = 0 V
1.6
1.8
A
A
Peak Pulldown Current
VLO = 12 V
HO GATE DRIVER
VOLH
VOHH
Low-Level Output Voltage
IHO = 100 mA
0.25
0.35
0.4
V
V
IHO = –100 mA,
VOHH = VHB – VHO
High-Level Output Voltage
0.55
IOHH
IOLH
Peak Pullup Current
VHO = 0 V
1.6
1.8
A
A
Peak Pulldown Current
VHO = 12 V
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
6.6 Switching Characteristics
MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ = +25°C, VDD = VHB = 12
V, VSS = VHS = 0 V, No Load on LO or HO .
PARAMETER
TEST CONDITIONS
MIN(1)
TYP
MAX(1)
UNIT
tLPHL
tHPHL
Lower Turn-Off Propagation Delay
(IN Rising to LO Falling)
25
56
Upper Turn-Off Propagation Delay
(IN Falling to HO Falling)
ns
25
56
tRC, tFC
tR, tF
tBS
Either Output Rise/Fall Time
CL = 1000 pF
15
0.6
50
Either Output Rise/Fall Time (3V to 9V)
Bootstrap Diode Turn-Off Time
CL = 0.1 µF
µs
ns
IF = 20 mA, IR = 200 mA
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
6.7 Typical Characteristics
100
2.0
1.9
1.7
1.5
1.3
1.1
0.9
0.7
CL = 4400 pF
CL = 1000 pF
V
= 12V
DD
I
DDO
RT = 10k
CL = 2200 pF
10
CL = 470 pF
1
CL = 0 pF
I
HBO
0
1
10
100
1000
-50 -25
0
25 50 75 100 125 150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 1. IDD vs Frequency
Figure 2. Operating Current vs Temperature
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.20
I
, RT = 10k
DD
1.00
0.80
0.60
0.40
0.20
0.00
I
, RT = 10k
DD
I
, RT = 100k
I
DD
, RT = 100k
DD
I , RT = 10k, 100k
HB
I
, RT = 10k, 100k
HB
8
9
10 11 12 13 14 15 16 17 18
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
V
, V (V)
DD HB
Figure 4. Quiescent Current vs Temperature
Figure 3. Quiescent Current vs Supply Voltage
6
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
Typical Characteristics (continued)
100000
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
V
= V = 12V, HS = 0V
HB
DD
HB = 12V,
CL = 4400 pF
HS = 0V
CL = 2200 pF
10000
CL = 1000 pF
1000
SOURCING
SINKING
100
CL = 0 pF
CL = 470 pF
100
FREQUENCY (kHz)
10
0
2
4
6
8
10
12
0.1
1
10
1000
HO, LO (V)
Figure 6. HO & LO Peak Output Current vs Output Voltage
Figure 5. IHB vs Frequency
0.60
1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
T = 150°C
0.55
V
DDH
0.50
0.45
0.40
0.35
0.30
T = 25°C
V
HBH
T = -40°C
-50 -25 0_ 25 50_ 75_100_125_150_
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
TEMPERATURE (oC)
V
(V)
D
Figure 8. Undervoltage Threshold Hysteresis vs
Temperature
Figure 7. Diode Forward Voltage
7.30
7.20
7.10
7.00
6.90
6.80
6.70
6.60
6.50
6.40
6.30
0.700
0.600
V
= V = 8V
HB
DD
0.500
0.400
0.300
0.200
0.100
V
DDR
V
= V = 12V
HB
DD
V
HBR
V
= V = 16V
HB
DD
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Undervoltage Rising Threshold vs Temperature
Figure 10. LO and HO Gate Drive—High-Level Output
Voltage vs Temperature
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
0.400
40.0
38.0
36.0
34.0
32.0
30.0
28.0
26.0
24.0
22.0
20.0
0.350
V
= V = 8V
HB
DD
T
LPHL
0.300
0.250
0.200
0.150
0.100
V
= V = 12V
HB
DD
T
HPHL
V
= V = 16V
HB
DD
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. LO and HO Gate Drive—Low-Level Output
Voltage vs Temperature
Figure 12. Turn Off Propagation Delay vs Temperature
120
110
220
200
180
100
90
80
70
60
50
40
30
20
LO,HO Turn On
Delay (tD)
160
LO,HO Effective Dead
Time (tP + tRT
)
140
120
100
80
LO,HO Turn On
Delay (tD)
60
LO,HO Turn Off
Delay (tD)
LO,HO Turn Off Delay (tD)
40
20
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Timing vs Temperature RT = 10K
Figure 14. Timing vs Temperature RT = 100K
8
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LM5104 High Voltage gate driver is designed to drive both the high side and the low side N-Channel
MOSFETs in a synchronous buck configuration. The floating high-side driver is capable of working with supply
voltages up to 100 V. The high side and low side gate drivers are controlled from a single input. Each change in
state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition
timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high
voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at
high speed while consuming low power and providing clean level transitions from the control logic to the high
side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails.
7.2 Functional Block Diagram
HV
HO
LEVEL
SHIFT
DRIVER
UVLO
HS
IN
RT
VDD
UVLO
LO
DRIVER
VSS
7.3 Feature Description
7.3.1 Adaptive Shoot-Through Protection
LM5104 is a high voltage, high speed dual output driver designed to drive top and bottom MOSFET’s connected
in synchronous buck or half-bridge configuration, from one externally provided PWM signal. LM5104 features
adaptive delay to prevent shoot-through current through top and bottom MOSFETs during switching transitions.
Referring to the timing diagram Figure 16, the rising edge of the PWM input (IN) turns off the bottom MOSFET
(LO) after a short propagation delay (tP). An adaptive circuit in the LM5104 monitors the bottom gate voltage (LO)
and triggers a programmable delay generator when the LO pin falls below an internally set threshold (≈ Vdd/2).
The gate drive of the upper MOSFET (HO) is disabled until the deadtime expires. The upper gate is enabled
after the TIMER delay (tP+TRT), and the upper MOSFET turns-on. The additional delay of the timer prevents
lower and upper MOSFETs from conducting simultaneously, thereby preventing shoot-through.
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
A falling transition on the PWM signal (IN) initiates the turn-off of the upper MOSFET and turn-on of the lower
MOSFET. A short propagation delay (tP) is encountered before the upper gate voltage begins to fall. Again, the
adaptive shoot-through circuitry and the programmable deadtime TIMER delays the lower gate turn-on time. The
upper MOSFET gate voltage is monitored and the deadtime delay generator is triggered when the upper
MOSFET gate voltage with respect to ground drops below an internally set threshold (≈ Vdd/2). The lower gate
drive is momentarily disabled by the timer and turns on the lower MOSFET after the deadtime delay expires
(tP+TRT).
The RT pin is biased at 3V and current limited to 1mA. It is designed to accommodate a resistor between 5K and
100K, resulting in an effective dead-time proportional to RT and ranging from 90ns to 200ns. RT values below 5K
will saturate the timer and are not recommended.
7.3.2 Start-up and UVLO
Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry which monitors the supply
voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5104, the top
and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9 V. Any UVLO condition on
the bootstrap capacitor will disable only the high-side output (HO).
7.4 Device Functional Modes
IN Pin
LO Pin
HO Pin
L
H
L
L
H
H
10
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5104 is one of the latest generation of high-voltage gate drivers which are designed to drive both the
high-side and low-side N-channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck
circuit. The floating high-side driver can operate with supply voltages up to 100 V. This allows for N-channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies.
Table 1. Highlights
FEATURE
BENEFIT
Adaptive Rising and Falling Edges with Programmable Additional
Delay
Allows optimization of gate drive timings to account for device
differences between high-side and low-side positions.
Single Input Control
Direct drive from lower cost PWM controllers
Reduces parts count and PCB real estate
Internal Bootstrap Diode
8.2 Typical Application
(Optional external
fast recovery diode)
V
IN
V
CC
R
GATE
HB
HO
HS
V
V
DD
DD
C
BOOT
IN
OUT1
OUT2
PWM
CONTROLLER
L
LM5104
LO
RT
C
GND
V
SS
Figure 15. LM5104 Driving MOSFETs Connected in Synchronous Buck Configuration
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
PARAMETER
VALUE
LM5104
CSD18531Q5A
10 V
Gate Driver IC
Mosfet
VDD
Qgmax
Fsw
43 nC
200 kHz
95%
DMax
IHBO
10 µA
VDH
1.1 V
VHBR
7.1 V
VHBH
0.4 V
8.2.2 Detailed Design Procedure
ΔVHB = VDD – VDH – VHBL
where
•
•
•
VDD = Supply voltage of the gate drive IC
VDH = Bootstrap diode forward voltage drop
Vgsmin = Minimum gate source threshold voltage
(1)
(2)
(3)
Q
TOTAL
C
BOOT =
DVHB
D
Max
SW
Q
TOTAL = Qgmax+ IHBO
´
F
The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the MOSFET.
0.95
QTOTAL = 43nC +10mA ´
100kHz
(4)
(5)
QTOTAL = 43.01 nC
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the
HB pin voltage above the UVLO voltage for the HB circuit.
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT
.
VHBL = VHBR – VHBH
VHBL = 6.7 V
(6)
(7)
(8)
(9)
ΔVHB = 10 V – 1.1 V – 6.7 V
ΔVHB = 2.2 V
43.01nc
BOOT =
C
2.2V
(10)
(11)
CBOOT = 19.54 nF
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
An additional delay turn-on delay can be programmed using an external resistor, RT. Figure 17 shows the
relationship between the turnon delay time and the resistor value for RT.
12
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
8.2.3 Application Curves
VDD
HB
Adapt
Logic
DLY
Logic
HO
HS
Driver
IN
LO
Adapt DLY
Logic
Driver
Logic
LM5104
VSS
RT
50%
LM5104
IN
WAVEFORMS
tp+TRT
50%
LO
tp
tp
tp+TRT
50%
HO
Td
Td
Figure 16. Application Timing Waveforms
200
V
= 12V, HB = 12V,
DD
CL = 0, HS = 0
175
150
T
HPLH
125
100
75
T
LPLH
10 20 30 40 50 60 70 80 90 100
RT (k:)
Figure 17. Turn On Delay vs RT Resistor Value
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
9 Power Supply Recommendations
9.1 Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
2
PDGATES = 2 • f • CL • VDD
(12)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The plot in Figure 18 shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with Equation 12. This plot can be used to approximate
the power losses due to the gate drivers.
1.000
C
= 4400 pF
L
C
= 2200 pF
L
0.100
0.010
C
= 1000 pF
L
C
L
= 470 pF
C
= 0 pF
L
0.001
0.1
_
1.0
_
10.0_
100.0
1000.0_
SWITCHING FREQUENCY (kHz)
Figure 18. Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation.
14
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
LM5104
www.ti.com
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
Power Dissipation Considerations (continued)
1.000
1.000
0.100
0.010
0.001
C
= 4400 pF
L
C
= 4400 pF
L
0.100
0.010
0.001
C
= 0 pF
L
C
= 0 pF
L
1.0 kHz
10.0 kHz
100.0 kHz
1000.0 kHz
1.0 kHz
10.0 kHz
100.0 kHz
1000.0 kHz
SWITCHING FREQUENCY (kHz)
Figure 19. Diode Power Dissipation VIN = 80V
SWITCHING FREQUENCY (kHz)
Figure 20. Diode Power Dissipation VIN = 40V
The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the
bootstrap diode losses for the intended application. Because the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode (refer to Figure 15) can be helpful in removing power
from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series
inductance and have a significantly lower forward voltage drop than the internal diode.
10 Layout
10.1 Layout Guidelines
The optimum performance of high- and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turnon of the external MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top
MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
–
a) The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
–
b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RT pin must be placed very close to the IC and seperated from high current paths to
avoid noise coupling to the time delay generator which could disrupt timer operation.
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM5104
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
10.2 Layout Example
CBOOT
Q HS
C VDD
LM5104
Q LS
Figure 21. LM5104 Component Placement
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5104M
NRND
SOIC
SOIC
SOIC
D
D
D
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
5104
M
LM5104M/NOPB
LM5104MX/NOPB
ACTIVE
ACTIVE
95
RoHS & Green
SN
SN
5104
M
2500 RoHS & Green
5104
M
LM5104SD/NOPB
LM5104SDX/NOPB
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000 RoHS & Green
4500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
5104SD
5104SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5104MX/NOPB
LM5104SD/NOPB
LM5104SDX/NOPB
SOIC
WSON
WSON
D
8
2500
1000
4500
330.0
178.0
330.0
12.4
12.4
12.4
6.5
4.3
4.3
5.4
4.3
4.3
2.0
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
DPR
DPR
10
10
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5104MX/NOPB
LM5104SD/NOPB
LM5104SDX/NOPB
SOIC
WSON
WSON
D
8
2500
1000
4500
367.0
208.0
367.0
367.0
191.0
367.0
35.0
35.0
35.0
DPR
DPR
10
10
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM5104M
LM5104M
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
LM5104M/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明