LM5066IPMHX/NOPB [TI]
具有更高电流、电压和功率监控精度的 10V 至 80V 热插拔控制器 | PWP | 28 | -40 to 125;
| 型号： | LM5066IPMHX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有更高电流、电压和功率监控精度的 10V 至 80V 热插拔控制器 | PWP | 28 | -40 to 125 控制器 监控 光电二极管 |
| 文件： | 总70页 (文件大小：4244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
LM5066I 具有 I/V/P 监视功能和 PMBus™ 接口的 10 至 80V 热插拔控制器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
10 至 80V 工作电压
LM5066I 可为 10V 至 80V 系统提供强大的保护和精密
的监视功能。 可编程设定 UV、OV、ILIMIT，快速短路
保护能够针对任意应用定制保护。 可编程 FET SOA
保护为 FET 设定任一条件下允许使用的最大功率。 设
置可编程故障定时器 (tFAULT) 以避免误动作，确保正常
启动并限制过载事件的持续时间。
最大绝对持续电压为 100V
26mV 或 50mV ILIM 阈值 (±10%)
可编程场效应管 (FET) 安全运行区域 (SOA) 保护
可编程设定 UV、OV、tFAULT 阈值
外部 FET 温度感测
FET 检测失败
I2C/SMBus 接口
除电路保护外，LM5066I 还可通过 I2C/SMBus 接口向
系统管理主机提供实时电源、电压、电流、温度和故障
数据。 利用符合 PMBus 的命令结构能够轻松地对器
件进行编程。 借助精密遥测可实现智能电源管理功
能，如效率优化和早期故障检测。 LM5066I 还支持
I/V/P 平均功率和峰值功率测量之类的高级功能，从而
提升系统诊断能力。
符合 PMBus™ 以及节点管理 2.0 和 3.0 标准的命
令结构
•
精密的 V IN、VOUT、IIN、PIN 和 VAUX 监视功能
–
V (±1.25%)；I (±1.75%)；P (±2.5%)
•
•
•
•
支持通过 Read_EIN 命令进行监视电能
可编程设定 I/V/P 的平均间隔
LM5066I 与 LM5066 引脚到引脚兼容并提升了遥测精
度，还支持通过 Read_Ein 命令监视电能。 有关详细
的比较结果，请参见Table 1。
采样率为 1kHz 的 12 位模数转换器 (ADC)
工作温度 –40°C < TJ < 125°C
2 应用
器件信息(1)
•
•
•
•
48V 服务器
部件号
LM5066I
封装
PWP (28)
封装尺寸（标称值）
9.70 × 4.40mm2
基站配电
网络路由器和交换机
可编程逻辑控制器 (PLC) 电源管理
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
空白
•
4
。
24V 至 28V 工业系统
简化电路原理图
。
Q
2
VIN
R
SNS
插卡中的 LM5066I
VOUT
48-V Bus
D1
COUT
Z
C
IN
1
Q
1
12 V
PMBus Hotswap
Manages Inrush,
Faults, and
48 V
DC/DC
R5
R6
SENSE
VIN_K
VIN
GATE OUT DIODE
Monitoring
FB
Load 1
Load 2
R1
R2
VDD
R3
R4
UVLO/EN
OVLO
I/V/P info
via PMBus
PGD
Regulate Loads to
Optimize Efficiency
Micro
Controller
ADR2
ADR1
ADR0
CL
VDD
AGND
GND
LM5066I
Plug-in Card
SMBA
SDAO
SDAI
SCL
RETRY
VAUX
SMBus
Interface
PWR
VDD VREF
TIMER
RPWR
CTIMER
1 PF 1 PF
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNVS950
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
目录
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 17
9.5 Programming........................................................... 20
10 Application and Implementation........................ 42
10.1 Application Information.......................................... 42
10.2 Typical Application ............................................... 42
11 Power Supply Recommendations ..................... 59
12 Layout................................................................... 60
12.1 Layout Guidelines ................................................. 60
12.2 Layout Example .................................................... 60
13 器件和文档支持 ..................................................... 62
13.1 商标....................................................................... 62
13.2 静电放电警告......................................................... 62
13.3 术语表 ................................................................... 62
14 机械封装和可订购信息 .......................................... 62
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
8.1 Handling Ratings....................................................... 5
8.2 Recommended Operating Conditions....................... 5
8.3 Thermal Information.................................................. 5
8.4 Electrical Characteristics........................................... 6
8.5 SMBus Communications Timing Requirements and
Definitions .................................................................. 9
8.6 Switching Characteristics........................................ 10
8.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 13
9
5 修订历史记录
Changes from Original (April 2014) to Revision A
Page
•
添加了新的部分....................................................................................................................................................................... 1
2
版权 © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
6 Device Comparison Table
Table 1 summarizes the differences between the LM5066 and the LM5066I. Note that the current monitoring
accuracy of the LM5066I is much better at the ILIM = 26 mV setting, but is comparable at the 50-mV setting. For
many applications with lower power, using the LM5066 at the 50-mV setting is a great option. However, for
higher power applications upgrading to LM5066I and using the ILIM = 26 mV setting will lead to significant power
savings (approximately 24 mV × ILOAD). In addition, the higher accuracy and energy monitoring capability can
enable further improvements in system efficiency, which is critical in high power applications.
Table 1. LM5066 vs LM5066I
KEY PARAMETERS
Voltage monitoring
LM5066
±2.7%
±4.25%
±4.5%
±3%
LM5066I
±1.25%
±1.75%
±.2.5%
±3.5%
Current monitoring (ILIM = 26 mV)
Power monitoring (ILIM = 26 mV)
Current monitoring (ILIM = 50 mV)
Power monitoring (ILIM = 50 mV)
±4.5%
±4.5%
Supports Energy Monitoring via
Read_EIN command
No
Yes
7 Pin Configuration and Functions
PWP Package
28-Pin
Top View
28
27
26
25
24
23
22
21
PGD
1
OUT
2
GATE
NC
3
4
PWR
SENSE
TIMER
RETRY
VIN_K
VIN
5
6
NC
FB
UVLO/EN
7
CL
VDD
ADR0
ADR1
8
OVLO
20
19
18
17
16
15
9
AGND
GND
10
11
12
13
14
SDAI
ADR2
VAUX
DIODE
VREF
SDAO
SCL
SMBA
Solder exposed pad to ground.
Pin Functions
PIN
DESCRIPTION
NAME
NO.
Exposed pad of TSSOP package
Solder to the ground plane to reduce thermal resistance
Exposed Pad
Pad
Output feedback
OUT
1
2
3
Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for
power limiting and to monitor the output voltage.
Gate drive output
Connect to the external MOSFET's gate.
GATE
SENSE
Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS
reaches overcurrent threshold the load current is limited and the fault timer activates.
Copyright © 2014, Texas Instruments Incorporated
3
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
Pin Functions (continued)
PIN
DESCRIPTION
NAME
NO.
Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN_K
4
Positive supply input
This pin is the input supply connection for the device.
VIN
N/C
5
6
No connection
Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. An internal 20-µA
current source provides hysteresis. The enable threshold at the pin is nominally 2.48 V. This pin can also be used
for remote shutdown control.
UVLO/EN
OVLO
7
8
Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. An internal 21-µA
current source provides hysteresis. The disable threshold at the pin is 2.46 V.
Circuit ground
Analog device ground. Connect to GND at the pin.
AGND
GND
9
10
11
Circuit ground
SMBus data input pin
SDAI
Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices.
SMBus data output pin
SDAO
SCL
12
13
14
Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices.
SMBus clock
Clock pin for SMBus
SMBus alert line
Alert pin for SMBus, active low
SMBA
Internal reference
VREF
15
Internally generated precision reference used for analog-to-digital conversion. Connect a 1-µF capacitor on this pin
to ground for bypassing.
External diode
DIODE
VAUX
ADR2
ADR1
ADR0
VDD
16
17
18
19
20
21
Connect this to a diode-configured MMBT3904 NPN transistor for temperature monitoring.
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full-scale input of 2.97 V.
SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
Internal sub-regulator output
Internally sub-regulated 4.85-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing.
Current limit range
CL
FB
22
23
Connect this pin to GND or leave floating to set the nominal over-current threshold at 50 mV. Connecting CL to
VDD sets the overcurrent threshold to be 26 mV.
Power Good feedback
An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at
the pin is nominally 2.46 V. An internal 20-µA current source provides hysteresis.
Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device
will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a
fault.
RETRY
TIMER
24
25
Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing.
Power limit set
PWR
N/C
26
27
An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum
power dissipation allowed in the external series pass MOSFET.
No connection
4
Copyright © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
Pin Functions (continued)
PIN
DESCRIPTION
NAME
NO.
Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above VFBTH (nominally 2.46 V) and the
input supply is within its undervoltage and overvoltage thresholds. Connect to the output rail (external MOSFET
source) or any other voltage to be monitored.
PGD
28
8 Specifications
8.1 Handling Ratings
MIN MAX
UNIT
°C
Tstg
Storage temperature
–65
–2
150
2
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except GATE(2)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3)
kV
Electrostatic
discharge
(1)
VESD
–500
500
V
(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2-kV rating for all pins except GATE
which is rated for 1 kV.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
80
UNIT
V
VIN, SENSE, OUT voltage
Junction temperature
10
–40
125
°C
8.3 Thermal Information
LM5066I
THERMAL METRIC(1)
PWP
28 PINS
35.6
UNIT
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
RθJC(top)
RθJB
19.9
Junction-to-board thermal resistance(4)
16.8
°C/W
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
0.5
ψJB
16.7
RθJC(bot)
2.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
版权 © 2014, Texas Instruments Incorporated
5
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
8.4 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR
=
(1)
20 kΩ. See
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (VIN PIN)
IIN-EN
Input current, enabled
VUVLO = 3 V and VOVLO = 2 V
VVIN increasing
5.6
7.8
7
mA
V
Power-on reset threshold at VVIN to trigger insertion
timer
PORIT
9.0
Power-on reset threshold at VVIN to enable all
functions
POREN
VVIN increasing
VVIN decreasing
8.6
9.9
V
PORHYS
POREN hysteresis
100
mV
VDD REGULATOR (VDD PIN)
IVDD = 0 mA
4.60
4.60
–50
4.90
4.85
–30
4.1
5.15
5.15
–15
V
V
VDD
IVDD = 10 mA
VDDILIM
VDDPOR
VVDD current limit
mA
V
VVDD voltage reset threshold
VVDD rising
UVLO/EN, OVLO PINS
UVLOTH
UVLO threshold
VUVLO falling
VUVLO = 1 V
VUVLO = 3 V
VOVLO rising
VOVLO= 1 V
VOVLO = 1 V
2.41
16
2.48
20
2.55
24
V
UVLOHYS
UVLOBIAS
OVLOTH
OVLOHYS
OVLOBIAS
UVLO hysteresis current
UVLO bias current
µA
µA
V
1
OVLO threshold
2.39
–24
2.46
–21
2.53
–16
1
OVLO hysteresis current
OVLO bias current
µA
µA
POWER GOOD (PGD PIN)
PGDVOL
PGDIOH
FB PIN
FBTH
Output low voltage
ISINK = 2 mA
VPGD = 80 V
100
400
1
mV
µA
Off leakage current
FB threshold
VUVLO = 3 V and VOVLO = 2 V
2.41
–25
2.46
–20
2.52
–15
1
V
FBHYS
FB hysteresis current
Off leakage current
µA
µA
FBLEAK
VFB = 2.3 V
POWER LIMIT (PWR PIN)
VSENSE – VOUT = 48 V, RPWR = 60 kΩ
VSENSE – VOUT = 48 V, RPWR = 20 kΩ
7.4
1.5
9.4
3.5
11.4
5.7
mV
mV
VSENSE – VOUT = 48 V, RPWR = 20 kΩ,
TJ = 0°C to 85°C
Power limit sense voltage (VVIN_K – VSENSE
)
1.85
3.5
5.02
mV
VSENSE – VOUT = 24 V, RPWR = 60 kΩ
VSENSE – VOUT = 24 V, RPWR = 20 kΩ
VPWR = 2.5 V
15
5
18.75
7.23
-20
22.5
10
mV
mV
µA
Ω
IPWR
PWR pin current
RSAT(PWR)
PWR pin impedance when disabled
VUVLO = 2 V
120
GATE CONTROL (GATE PIN)
Source current
Normal operation
VUVLO = 2 V
–40
3.4
–20
4.2
–7.5
5.3
µA
Fault sink current
IGATE
mA
VVIN_K – VSENSE = 60 mV or VVIN < PORIT
,
VGATE = 5 V, OUT = 0 V,
POR circuit breaker sink current
90
160
230
mA
CB/CL ratio bit = 0, CL = 1
VGATE– VOUT
Reverse-bias voltage of GATE to OUT Zener diode,
IZ = –100 µA
VGATEZ
15
11
16.5
13
18
15
V
V
Peak charge pump voltage in normal operation
VGATECP
VGATE– VOUT
(VIN = VOUT
)
OUT PIN
IOUT-EN
OUT bias current, enabled
OUT bias current, disabled
VIN = VOUT, normal operation
60
80
100
–35
µA
µA
(2)
IOUT-DIS
Disabled, OUT = 0 V, VVIN_K = VSENSE
–65
–50
(1) Current out of a pin is indicated as a negative value.
(2) OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.
6
版权 © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
Electrical Characteristics (接下页)
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR
=
(1)
20 kΩ. See
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
CL = VDD
CL = GND
23.4
45
26
50
28.6
55
Current limit threshold voltage
(VVIN_K – VSENSE
VCL
mV
µA
)
Enabled, SENSE = OUT
Disabled, OUT = 0 V
Enabled, OUT = 0 V
20
25
35
ISENSE
SENSE input current
66
190
220
250
CIRCUIT BREAKER
CB/CL ratio bit = 0, ILIM = 50 mV
CB/CL ratio bit = 1, ILIM = 50 mV
CB/CL ratio bit = 0, ILIM = 26 mV
CB/CL ratio bit = 1, ILIM = 26 mV
CB/CL ratio bit = 0, ILIM = 50 mV
CB/CL ratio bit = 1, ILIM = 50 mV
CB/CL ratio bit = 0, ILIM = 26 mV
CB/CL ratio bit = 1, ILIM = 26 mV
1.64
3.28
1.5
3.1
76
1.94
3.87
1.88
3.75
96
2.23
4.45
2.3
Circuit breaker to current limit ratio:
(VVIN_K – VSENSE CB/VCL
RTCB
V/V
mV
)
4.45
116
235
58
155
38
193
48
VCB
Circuit breaker threshold voltage: (VVIN_K – VSENSE)
76
96
116
TIMER (TIMER PIN)
VTMRH Upper threshold
3.74
1
3.9
1.2
4.07
1.4
V
V
Restart cycles
VTMRL
Lower threshold
End of eighth cycle re-enable threshold
0.3
V
Insertion time current
–5.9
0.9
–4.8
1.5
–3.3
2.1
µA
mA
µA
µA
Sink current, end of insertion time
Fault detection current
Fault sink current
ITIMER
TIMER pin = 2 V
–90
1.7
–75
2.5
–60
3.2
DCFAULT
Fault restart duty cycle
0.5%
INTERNAL REFERENCE
VREF
Reference voltage
2.93
2.97
3.02
V
ADC AND MUX
Resolution
12
±4
Bits
LSB
µs
INL
Integral non-linearity
ADC only
tACQUIRE
tRR
Acquisition + conversion time
Acquisition round robin time
Any channel
Cycle all channels
100
1
ms
TELEMETRY ACCURACY
CL = GND
CL = VDD
CL = GND
CL = VDD
50
26
54.4
27.0
13.30
6.70
2.97
725
58
29
mV
mV
µV
µV
V
IINFSR Current input full-scale range
IINLSB
Current input LSB
VAUXFSR
VAUXLSB
VINFSR
VAUX input full-scale range
VAUX input LSB
2.93
86
3.01
91
µV
V
Input voltage full-scale range
Input voltage LSB
88.9
21.7
88.9
21.7
VINLSB
mV
V
VOUTFSR
VOUTLSB
Output voltage full-scale range
Output voltage LSB
86
91
mV
VVIN_K – VSENSE = 22 mV (80% IINFSR),
CL = VDD
–1.75
–6.0
–3.5
%
%
%
+1.75
+6.0
+3.5
VVIN_K – VSENSE = 5 mV (19% IINFSR),
CL = VDD
IINACC
Input current absolute accuracy
VVIN_K – VSENSE = 44 mV (80% IINFSR),
CL = GND
版权 © 2014, Texas Instruments Incorporated
7
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
Electrical Characteristics (接下页)
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR
=
(1)
20 kΩ. See
.
PARAMETER
TEST CONDITIONS
VVIN, VVOUT = 48, 80 V
MIN
–1.25
–2.5
TYP
%
MAX
+1.25
+2.5
UNIT
VIN, VOUT absolute accuracy
VAUX absolute accuracy
VACC
VVIN, VVOUT = 10 V
VAUX = 2.8 V
%
–1.25
%
+1.25
VVIN = 48 V, VVIN_K – VSENSE = 22 mV
(80% IINFSR), CL = VDD
–2.5
–6.5
–4.5
%
%
%
+2.5
+6.5
+4.5
VVIN = 48 V, VVIN_K – VSENSE = 5 mV
(19% IINFSR), CL = VDD
PINACC
Input power accuracy
VVIN = 48V , VVIN_K – VSENSE= 44 mV
(80% IINFSR), CL = GND
REMOTE DIODE TEMPERATURE SENSOR
Temperature accuracy using local diode
TA = 25°C to 85°C
2
9
10
°C
bits
µA
µA
µA
TACC
Remote diode resolution
High level
Low level
250
9.4
25.9
325
IDIODE
External diode current source
Diode current ratio
PMBus PIN THRESHOLDS (SMBA, SDA, SCL)
VIL
Data, clock input low voltage
Data, clock input high voltage
Data output low voltage
Input leakage current
0.9
5.5
0.4
1
V
V
VIH
2.1
0
VOL
ILEAK
ISINK = 3 mA
V
SDAI,SMBA,SCL = 5 V
µA
CONFIGURATION PIN THRESHOLDS (CL, RETRY)
VIH
Threshold voltage
3
V
ILEAK
Input leakage current
CL, RETRY = 5 V
5
µA
8
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8.5 SMBus Communications Timing Requirements and Definitions
PARAMETER
MIN
10
MAX UNIT
ƒSMB
SMBus operating frequency
400
kHz
µs
µs
µs
µs
ns
tBUF
Bus free time between stop and start condition
Hold time after (repeated) start condition. After this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
1.3
0.6
0.6
0.6
85
tHD:STA
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Data hold time
Data setup time
Clock low time-out(1)
100
25
ns
35
ms
µs
µs
ms
ms
ns
Clock low period
Clock high period(2)
Cumulative clock low extend time (slave device)(3)
Cumulative low extend time (master device)(4)
Clock or data fall time(5)
1.5
0.6
tHIGH
tLOW:SEXT
tLOW:MEXT
tF
25
10
20
20
300
300
tR
Clock or data rise time(5)
ns
(1) Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT,MIN of 25 ms. Devices that have
detected a timeout condition must reset the communication no later than tTIMEOUT,MAX of 35 ms. The maximum value must be adhered
to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
(2) tHIGH MAX provides a simple method for devices to detect bus idle conditions.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a
slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from
start-to-ack, ack-to-ack, or ack-to-stop.
(5) Rise and fall time is defined as follows: tR = ( VILMAX – 0.15) to (VIHMIN + 0.15); tF = 0.9 VDD to (VILMAX – 0.15)
t
R
t
F
SCL
t
LOW
V
IH
V
IL
t
t
t
SU;STA
HIGH
SU;STO
t
t
t
SU;DAT
HD;DAT
HD;STA
SDA
V
IH
V
IL
t
BUF
P
S
S
P
图 1. SMBus Timing Diagram
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8.6 Switching Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR
=
20 kΩ.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
µs
UVLO/EN, OVLO PINS
Delay to GATE high
7
6
7
6
9.6
8.5
9.6
8.5
12.2
11
UVLODEL
UVLO delay
Delay to GATE low
Delay to GATE high
Delay to GATE low
12.2
11
µs
OVLODEL
FB PIN
FBDEL
OVLO delay
Delay to PGD high
Delay to PGD low
5
7
7.6
9.2
10
FB Delay
µs
µs
12.5
CURRENT LIMIT
VIN-SENSE stepped from 0 to 80 mV; CL =
GND
tCL
Response time
30
50
CIRCUIT BREAKER
VIN-SENSE stepped from 0 to 150 mV, time
to GATE low, no load
µs
µs
tCB
Response time
0.36
12
0.8
TIMER (TIMER PIN)
tFAULT_DELAY Fault to GATE low delay
TIMER pin reaches the upper threshold
10
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8.7 Typical Characteristics
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
300
250
200
150
100
50
7
6
5
4
VOUT = 48V
VOUT = 0V
VIN = 10V
VIN = 48V
VIN = 80V
0
0
25
50
75
100
125
150
±50
±50
±50
±25
0
25
50
75
100
125
125
125
150
±50
±50
±50
±25
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
C002
C001
Device Enabled
SPACE
图 3. Sense Current vs VOUT and TJ
图 2. Input Current vs VIN and TJ
±10
±15
±20
±25
±30
5.0
4.5
4.0
3.5
3.0
0
25
50
75
100
150
0
25
50
75
100
125
150
±25
±25
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
C003
C004
图 4. Gate Sourcing Current vs TJ
图 5. Gate Sinking Current vs TJ
250
225
200
175
150
125
100
14.0
13.5
13.0
12.5
12.0
0
25
50
75
100
150
0
25
50
75
100
125
150
±25
±25
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
C005
C006
POR event or CB triggered
SPACE
图 6. Gate Sinking Current vs TJ
图 7. Gate Voltage vs TJ
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Typical Characteristics (接下页)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
3.0
2.8
2.6
2.4
2.2
2.0
18.0
17.5
17.0
16.5
16.0
0
25
50
75
100
125
150
±50
±25
0
25
50
75
100
125
150
±50
±25
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
C008
C007
SPACE
Inject 100 µA into gate node. Measure GATE-SOURCE
图 9. UVLO/EN Threshold vs TJ
图 8. Gate Clamping Voltage vs TJ
3.0
3.0
2.8
2.6
2.4
2.2
2.0
2.8
2.6
2.4
2.2
2.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
±50
±25
TJ - Junction Temperature (C)
TJ - Junction Temperature (C)
C009
C010
图 10. OVLO Threshold vs TJ
图 11. Power Good Feedback Threshold vs TJ
60
55
50
45
40
35
30
25
CL = VDD
CL = GND
20
0
25
50
75
100
125
150
±50
±25
TJ - Junction Temperature (C)
C011
图 12. Current Limit Threshold vs TJ
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9 Detailed Description
9.1 Overview
The inline protection functionality of the LM5066I is designed to control the in-rush current to the load after
insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag
on the backplane’s supply voltage and the dV/dt of the voltage applied to the load. The effects on other
circuits in the system are minimized by preventing possible unintended resets. When the circuit card is
removed, a controlled shutdown can be implemented using the LM5066I.
In addition to a programmable current limit, the LM5066I monitors and limits the maximum power dissipation
in the series-pass device to maintain operation within the device safe operating area (SOA). Either current
limiting or power limiting for an extended period of time results in the shutdown of the series-pass device. In
this event, the LM5066I can latch off or repetitively retry based on the hardware setting of the RETRY pin.
When started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function
quickly switches off the series-pass device upon detection of a severe overcurrent condition. Programmable
undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066I when the
system input voltage is outside the desired operating range.
The telemetry capability of the LM5066I provides intelligent monitoring of the input voltage, output voltage,
input current, input power, temperature, and an auxiliary input. The LM5066I also provides a peak capture of
the input power and programmable hardware averaging of the input voltage, current, power, and output
voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage,
current, power, and temperature through the PMBus interface. Additionally, the LM5066I is capable of
detecting damage to the external MOSFET, Q1.
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9.2 Functional Block Diagram
20PA
LM5066I
VDD
REG
2.46 V
VDD
CB
UV
OV
CHARGE
PUMP
1/30
26/50
mV
1/30
VREF
12 bit
ADC
I
DS
PA
20
Current Limit
Threshold
GATE
CONTROL
GATE
2.97
VRef
4.2 mA
160
mA
16.5 V
Current
Limit
VAUX
V
DS
OUT
Power Limit
Threshold
Sense
Current Limit/
Power Limit
Control
Diode
Temp
Sense
DIODE
48/96/193mV
Circuit Breaker
Threshold
4.8 PA
Insertion
Timer
75 PA
Fault
Timer
20PA
MEASUREMENT/
FAULT REGISTORS
TIMER
21PA
1.5 mA
End
Insertion
Time
SCL
SDAI
TELEMETRY
ov
uv
STATE
TIMER AND GATE
LOGIC CONTROL
2.5 PA
Fault
Discharge
MACHINE
SMBUS
INTERFACE
SDAO
2.46 V
2.48 V
SMBA
3.9V
1.2 V
ADDRESS
DECODER
0.3 V
20PA
ADR0
ADR1
ADR2
AGND
GND
Enable
POR
Insertion Timer
POR
7.8V
VIN
8.6 V
VIN
9.3 Feature Description
9.3.1 Current Limit
The current limit threshold is reached when the voltage across the sense resistor RSNS (VIN_K to SENSE)
exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the
GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault
timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the LM5066I resumes usual operation. If the current limit
condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled
using the ALERT_MASK (D8h) register. For proper operation, the RSNS resistor value should be no higher than
200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value
may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).
14
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Feature Description (接下页)
9.3.2 Circuit Breaker
If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor
(RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current
exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q1 is quickly switched off by the 160-mA
pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across RSNS falls below
the circuit breaker (CB) threshold, the 160-mA pulldown current at the GATE pin is switched off, and the gate
voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V
before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.2-mA pulldown current
at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT
BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and
DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is
disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by
setting appropriate bits in the DEVICE_SETUP (D9h) register.
9.3.3 Power Limit
An important feature of the LM5066I is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5066I determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through the RSNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the
GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer
is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than
the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch)
register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled
using the ALERT_MASK (D8h) register.
9.3.4 UVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. Typically the UVLO level at VIN is set with a resistor
divider. Referring to the Functional Block Diagram when VIN is below the UVLO level, the internal 20-µA current
source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the 4.2-mA pulldown current
at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at
UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN
pin above its threshold, Q1 is switched on by the 20-µA current source at the GATE pin if the insertion time delay
has expired.
See the Application and Implementation section for a procedure to calculate the values of the threshold setting
resistors. The minimum possible UVLO level at VIN can be set by connecting the UVLO/EN pin to VIN. In this
case, Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up,
an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the
STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h)
registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK
(D8h) register.
9.3.5 OVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. If VIN raises the OVLO pin voltage above its threshold, Q1
is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin
is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to
provide threshold hysteresis. When VIN is reduced below the OVLO level Q1 is re-enabled. An OVLO condition
toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD
(79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA
pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.
See the Application and Implementation section for a procedure to calculate the threshold setting resistor values.
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Feature Description (接下页)
9.3.6 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of
the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the
UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
9.3.7 VDD Sub-Regulator
The LM5066I contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V
rail used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the
CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply
for the PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive
high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in
order to protect the LM5066I in the event of a short. The sub-regulator requires a ceramic bypass capacitance
having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows.
9.3.8 Remote Temperature Sensing
The LM5066I is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and
collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066I ground. Place
the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass
MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The
temperature is measured by means of a change in the diode voltage in response to a step in current supplied by
the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure
the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and
the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin
connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement.
Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the
effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). By
default, the temperature fault and warning thresholds of the LM5066I are set to 256°C and are effectively
disabled. These thresholds can be reprogrammed through the PMBus interface using the OT_WARN_LIMIT
(51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the
LM5066I are not used, the DIODE pin should be grounded.
Erroneous temperature measurements may result when the device input voltage is below the minimum operating
voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures,
this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q1. In this
case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION
(03h) register.
9.3.9 Damaged MOSFET Detection
The LM5066I is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the
voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is
disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted
because of damage present between the drain and gate and/or drain and source.
16
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9.4 Device Functional Modes
9.4.1 Power-Up Sequence
The VIN operating range of the LM5066I is 10 to 80 V, with a transient capability to 100 V. Referring to the 简化
电路原理图 and 图 13, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off
by an internal 160-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents
an inadvertent turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the
TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins.
During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8-µA current source, and Q1 is
held off by a 4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay
allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin
voltage reaches 3.9 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then
switches on Q1 when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the
insertion time, Q1 the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1. The
maximum voltage from the gate to source of the Q1 is limited by an internal 16.5-V Zener diode.
As the voltage at the OUT pin increases, the LM5066I monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the
load. During the in-rush limiting interval (t2 in 图 13), an internal 75-µA fault timer current source charges CT. If
Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 3.9 V, the 75-µA current source is switched off, and CT is discharged by the internal 2.5-µA current
sink (t3 in 图 13). The in-rush limiting no longer engages unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See the Fault Timer and Restart section for a complete description of the fault
mode.
The LM5066I asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the
volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and remains high until a CLEAR_FAULTS command is received.
V
IN
UVLO
POR
VIN
3.9 V
75 PA
2.5 PA
4.8 PA
TIMER
GATE
160 mA
pull-down
4.2 mA pull-down
20 PA source
I
LIMIT
Load
Current
2.46 V
FB
PGD
t
t
t
3
1
2
In rush
Limiting
Insertion Time
Normal Operation
图 13. Power-Up Sequence (Current Limit Only)
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Device Functional Modes (接下页)
9.4.2 Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q1). During
normal operating conditions (t3 in 图 13), the gate of Q1 is held charged by an internal 20-µA current source. The
charge pump peak voltage is roughly 13.5 V, which forces a VGS across Q1 of 13.5 V under normal operation.
When the system voltage is initially applied, the GATE pin is held low by a 160-mA pulldown current. This helps
prevent an inadvertent turn-on of Q1 through its drain-gate capacitance as the applied system voltage increases.
During the insertion time (t1 in 图 13) the GATE pin is held low by a 4.2-mA pulldown current. This maintains Q1
in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2
in 图 13 the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the
programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the
current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor then discharges,
and the circuit begins normal operation. If the in-rush limiting condition persists such that the TIMER pin reached
3.9 V during t2, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE pin is then held low
until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin
to GROUND or floating). See the Fault Timer and Restart section. If the system input voltage falls below the
UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 4.2-mA pulldown current
to switch off Q1.
9.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 75-µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in 图 13 (fault timeout period). If the fault condition subsides during the fault timeout period before the
TIMER pin reaches 3.9 V, the LM5066I returns to the normal operating mode and CT is discharged by the 1.5-
mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q1 is switched off by a 4.2-mA
pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM5066I latches the GATE pin low at the end of the fault timeout period. CT is then
discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current
until a power-up sequence is externally initiated by cycling the input voltage (VIN), or momentarily pulling the
UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in 图 14. The voltage at
the TIMER pin must be <0.3 V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the
DIAGNOSTIC_WORD (E1h) register remains high while the latched off condition persists.
V
IN
VIN
R1
R2
R3
UVLO/EN
Restart
Control
OVLO
GND
图 14. Latched Fault Restart Control
The LM5066I provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9 and
1.2 V seven times after the fault timeout period, as shown in 图 15. The period of each cycle is determined by the
75-µA charging current, the 2.5-µA discharge current, and the value of the capacitor, CT. When the TIMER pin
reaches 0.3 V during the eighth high-to-low ramp, the 20-µA current source at the GATE pin turns on Q1. If the
fault condition is still present, the fault timeout period and the restart sequence repeat. The RETRY pin allows
selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the
DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16, or infinite may be selected by setting the
appropriate bits in the DEVICE_SETUP (D9h) register.
18
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Device Functional Modes (接下页)
Fault
Detection
I
LIMIT
Load
Current
20 PA
Gate Charge
4.2 mA pulldown
GATE
Pin
PA
2.5
3.9 V
75 PA
TIMER
Pin
1.2 V
0.3 V
1
2
3
7
8
t
Fault Timeout
Period
RESTART
图 15. Restart Sequence
9.4.4 Shutdown Control
The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open
collector or open-drain device, as shown in 图 16. When UVLO/EN pin is released, the LM5066I switches on the
FET with in-rush current and power limiting.
V
IN
VIN
R1
R2
R3
UVLO/EN
Shutdown
Control
OVLO
GND
图 16. Shutdown Control
9.4.5 Enabling/Disabling and Resetting
The output can be disabled at during normal operation by either pulling the UVLO/EN pin to below its threshold
or the OVLO pin above its threshold. This will cause the GATE voltage to be forced low with a pulldown strength
of 4.2 mA. Toggling the UVLO/EN pin also resets the LM5066I from a latched-off state due to an overcurrent or
over-power limit condition that caused the maximum allowed number of retries to be exceeded. While the
UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the volatile memory or
address location of the LM5066I. User-stored values for address, device operation, and warning and fault levels
programmed through the SMBus are preserved while the LM5066I is powered regardless of the state of the
UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION
(03h) register. To re-enable after a fault, the fault condition should be cleared by programing the OPERATION
(03h) register with 0h and then 80h.
The SMBus address of the LM5066I is captured based-on the states of the ADR0, ADR1, and ADR2 pins (GND,
NC, and VDD) during turn on and is latched into a volatile register after VDD has exceeded its POR threshold of
4.1 V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground.
Pulling the VREF pin low also resets the logic and erases the volatile memory of the LM5066I. When released,
the VREF pin charges up to its final value and the address is latched into a volatile register when the voltage at
the VREF exceeds 2.55 V.
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9.5 Programming
9.5.1 PMBus Command Support
The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error
masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in 表 2.
表 2. Supported PMBus Commands
NUMBER
DEFAULT
CODE
NAME
FUNCTION
R/W
OF DATA
BYTES
VALUE
01h
03h
OPERATION
Retrieves or stores the operation status
R/W
1
0
80h
Clears the status registers and re-arms the black box registers for
updating
CLEAR_FAULTS
Send byte
19h
43h
CAPABILITY
Retrieves the device capability
R
1
2
B0h
VOUT_UV_WARN_LIMIT
Retrieves or stores output undervoltage warn limit threshold
R/W
0000h
0FFFh
(256°C)
4Fh
51h
OT_FAULT_LIMIT
OT_WARN_LIMIT
Retrieves or stores over temperature fault limit threshold
Retrieves or stores over temperature warn limit threshold
R/W
R/W
2
2
0FFFh
(256°C)
57h
58h
5Dh
78h
79h
7Ah
7Ch
7Dh
7Eh
7Fh
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
IIN_OC_WARN_LIMIT
STATUS_BYTE
Retrieves or stores input overvoltage warn limit threshold
Retrieves or stores input undervoltage warn limit threshold
Retrieves or stores input current warn limit threshold (mirror at D3h)
Retrieves information about the parts operating status
Retrieves information about the parts operating status
Retrieves information about output voltage status
Retrieves information about input status
R/W
R/W
R/W
R
2
2
2
1
2
1
1
1
1
1
0FFFh
0000h
0FFFh
01h
STATUS_WORD
R
0801h
00h
STATUS_VOUT
R
STATUS_INPUT
R
10h
STATUS_TEMPERATURE
STATUS_CML
Retrieves information about temperature status
Retrieves information about communications status
Retrieves other status information
R
00h
R
00h
STATUS_OTHER
R
00h
Retrieves information about circuit breaker and MOSFET shorted
status
80h
86h
STATUS_MFR_SPECIFIC
READ_EIN
R
R
1
6
10h
00h 00h
00h 00h
00h 00h
Retrieves energy meter measurement
88h
89h
8Bh
8Dh
97h
READ_VIN
READ_IIN
Retrieves input voltage measurement
R
R
R
R
R
2
2
2
2
2
0000h
0000h
0000h
0190h
0000h
Retrieves input current measurement (Mirrors at D1h)
Retrieves output voltage measurement
READ_VOUT
READ_TEMPERATURE_1
READ_PIN
Retrieves temperature measurement
Retrieves averaged input power measurement (mirror at DFh).
54h
49h
0h
99h
MFR_ID
Retrieves manufacturer ID in ASCII characters (TI)
Retrieves part number in ASCII characters. (LM5066I)
R
3
4Ch
4Dh
35h
30h
36h
36h
49h
0h
9Ah
MFR_MODEL
R
8
41h
41h
9Bh
D0h
D1h
D2h
D3h
MFR_REVISION
Retrieves part revision letter or number in ASCII (for example, AA)
Retrieves auxiliary voltage measurement
R
R
2
2
2
2
2
MFR_SPECIFIC_00
READ_VAUX
0000h
0000h
0000h
0FFFh
MFR_SPECIFIC_01
MFR_READ_IIN
Retrieves input current measurement (Mirror at 89h)
Retrieves input power measurement
R
MFR_SPECIFIC_02
MFR_READ_PIN
R
MFR_SPECIFIC_03
MFR_IIN_OC_WARN_LIMIT
Retrieves or stores input current limit warn threshold (Mirror at 5Dh)
R/W
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Programming (接下页)
表 2. Supported PMBus Commands (接下页)
NUMBER
OF DATA
BYTES
DEFAULT
VALUE
CODE
NAME
FUNCTION
R/W
MFR_SPECIFIC_04
MFR_PIN_OP_WARN_LIMIT
D4h
D5h
D6h
D7h
D8h
D9h
Retrieves or stores input power limit warn threshold
Retrieves measured peak input power measurement
Resets the contents of the peak input power register to 0
R/W
R
2
2
0
1
2
1
0FFFh
0000h
MFR_SPECIFIC_05
READ_PIN_PEAK
MFR_SPECIFIC_06
CLEAR_PIN_PEAK
Send byte
R/W
MFR_SPECIFIC_07
GATE_MASK
Allows the user to disable MOSFET gate shutdown for various fault
conditions
0000h
FD04h
0000h
MFR_SPECIFIC_08
ALERT_MASK
Retrieves or stores user SMBA fault mask
R/W
MFR_SPECIFIC_09
DEVICE_SETUP
Retrieves or stores information about number of retry attempts
R/W
0880h
0000h
0000h
0000h
0000h
0000h
MFR_SPECIFIC_10
BLOCK_READ
Retrieves most recent diagnostic and telemetry information in a
single transaction
DAh
R
12
Exponent value AVGN for number of samples to be averaged (N =
2AVGN), range = 00h to 0Ch
MFR_SPECIFIC_11
SAMPLES_FOR_AVG
DBh
DCh
DDh
DEh
DFh
R/W
R
1
2
2
2
2
08h
MFR_SPECIFIC_12
READ_AVG_VIN
Retrieves averaged input voltage measurement
Retrieves averaged output voltage measurement
Retrieves averaged input current measurement
Retrieves averaged input power measurement
0000h
0000h
0000h
0000h
MFR_SPECIFIC_13
READ_AVG_VOUT
R
MFR_SPECIFIC_14
READ_AVG_IIN
R
MFR_SPECIFIC_15
READ_AVG_PIN
R
0880h
0000h
0000h
0000h
0000h
0000h
MFR_SPECIFIC_16
BLACK_BOX_READ
Captures diagnostic and telemetry information, which are latched
when the first SMBA event occurs after faults are cleared
E0h
E1h
E2h
R
R
R
12
2
MFR_SPECIFIC_17
DIAGNOSTIC_WORD_READ
Manufacturer-specific parallel of the STATUS_WORD to convey all
FAULT/WARN data in a single transaction
0880h
0880h
0000h
0000h
0000h
0000h
0000h
MFR_SPECIFIC_18
AVG_BLOCK_READ
Retrieves most recent average telemetry and diagnostic information
in a single transaction
12
9.5.2 Standard PMBus Commands
9.5.2.1 OPERATION (01h)
The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command
can be used to switch the MOSFET on and off under host control. It is also used to re-enable the MOSFET after
a fault triggered shutdown. Writing an OFF command, followed by an ON command, clears all faults and re-
enables the device. Writing only an ON after a fault-triggered shutdown does not clear the fault registers or re-
enable the device. The OPERATION command is issued with the write byte protocol.
表 3. Recognized OPERATION Command Values
VALUE
80h
MEANING
Switch ON
Switch OFF
DEFAULT
80h
00h
N/A
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9.5.2.2 CLEAR_FAULTS (03h)
The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags
and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued,
the SMBA signal may not clear or re-asserts almost immediately. Issuing a CLEAR_FAULTS command does not
cause the MOSFET to switch back on in the event of a fault turnoff; that must be done by issuing an
OPERATION command after the fault condition is cleared. This command uses the PMBus send byte protocol.
9.5.2.3 CAPABILITY (19h)
The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions
supported by the LM5066I. This command is read with the PMBus read byte protocol.
表 4. CAPABILITY Register
VALUE
MEANING
DEFAULT
B0h
Supports packet error check, 400 Kb/s, supports SMBus B0h
alert
9.5.2.4 VOUT_UV_WARN_LIMIT (43h)
The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the
threshold for the VOUT undervoltage warning detection. Reading and writing to this register should use the
coefficients shown in 表 47. Accesses to this command should use the PMBus read or write word protocol. If the
measured value of VOUT falls below the value in this register, VOUT UV warn flags are set and the SMBA signal
is asserted.
表 5. VOUT_UV_WARN_LIMIT Register
VALUE
MEANING
DEFAULT
0000h (disabled)
N/A
0001h to 0FFFh
0000h
VOUT undervoltage warning detection threshold
VOUT undervoltage warning disabled
9.5.2.5 OT_FAULT_LIMIT (4Fh)
The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the threshold
for the overtemperature fault detection. Reading and writing to this register should use the coefficients shown in
表 47. Accesses to this command should use the PMBus read or write word protocol. If the measured
temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched off, OT
FAULT flags set, and the SMBA signal asserted. After the measured temperature falls below the value in this
register, the MOSFET may be switched back on with the OPERATION command. A single temperature
measurement is an average of 16 round-robin cycles; therefore, the minimum temperature fault detection time is
16 ms.
表 6. OT_FAULT_LIMIT Register
VALUE
MEANING
DEFAULT
0FFFh (256°C)
N/A
0000h to 0FFEh
0FFFh
Over-temperature fault threshold value
Over-temperature fault detection disabled
9.5.2.6 OT_WARN_LIMIT (51h)
The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold
for the over-temperature warning detection. Reading and writing to this register should use the coefficients
shown in 表 47. Accesses to this command should use the PMBus read or write word protocol. If the measured
temperature exceeds this value, an over-temperature warning is triggered and the OT WARN flags set in the
respective registers and the SMBA signal asserted. A single temperature measurement is an average of 16
round-robin cycles; therefore, the minimum temperature warn detection time is 16 ms.
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表 7. OT_WARN_LIMIT Register
VALUE
MEANING
DEFAULT
0FFFh (256°C)
N/A
0000h to 0FFEh
0FFFh
Over-temperature warn threshold value
Over-temperature warn detection disabled
9.5.2.7 VIN_OV_WARN_LIMIT (57h)
The VIN_OV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the
threshold for the VIN overvoltage warning detection. Reading and writing to this register should use the
coefficients shown in 表 47. Accesses to this command should use the PMBus read or write word protocol. If the
measured value of VIN rises above the value in this register, VIN OV warn flags are set in the respective
registers and the SMBA signal is asserted.
表 8. VIN_OV_WARN_LIMIT Register
VALUE
MEANING
DEFAULT
0FFFh (disabled)
N/A
0h to 0FFEh
0FFFh
VIN overvoltage warning detection threshold
VIN overvoltage warning disabled
9.5.2.8 VIN_UV_WARN_LIMIT (58h)
The VIN_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the
threshold for the VIN undervoltage warning detection. Reading and writing to this register should use the
coefficients shown in 表 47. Accesses to this command should use the PMBus read or write word protocol. If the
measured value of VIN falls below the value in this register, VIN UV warn flags are set in the respective register,
and the SMBA signal is asserted.
表 9. VIN_UV_WARN_LIMIT Register
VALUE
MEANING
DEFAULT
0000h (disabled)
N/A
1h to 0FFFh
0000h
VIN undervoltage warning detection threshold
VIN undervoltage warning disabled
9.5.2.9 STATUS_BYTE (78h)
The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the
state of the LM5066I. Accesses to this command should use the PMBus read byte protocol. To clear bits in this
register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued.
表 10. STATUS_BYTE Definitions
BIT
7
NAME
BUSY
MEANING
DEFAULT
Not supported, always 0
0
0
0
0
0
0
0
1
6
OFF
This bit is asserted if the MOSFET is not switched on for any reason.
Not supported, always 0
5
VOUT OV
IOUT OC
4
Not supported, always 0
3
VIN UV fault
TEMPERATURE
CML
A VIN undervoltage fault has occurred
A temperature fault or warning has occurred
A communication fault has occurred
2
1
0
None of the above
A fault or warning not listed in bits [7:1] has occurred
9.5.2.10 STATUS_WORD (79h)
The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags
indicating the state of the LM5066I. Accesses to this command should use the PMBus read word protocol. To
clear bits in this register, the underlying fault should be removed and a CLEAR _FAULTS command issued. The
INPUT and VIN UV flags default to 1 on startup; however, they are cleared to 0 after the first time the input
voltage exceeds the resistor-programmed UVLO threshold.
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表 11. STATUS_WORD Definitions
BIT
15
14
13
12
11
10
9
NAME
VOUT
MEANING
An output voltage fault or warning has occurred
Not supported, always 0
DEFAULT
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
IOUT/POUT
INPUT
An input voltage or current fault has occurred
FET is shorted
FET FAIL
POWER GOOD
FANS
The Power Good signal has been negated
Not supported, always 0
CB_Fault
UNKNOWN
BUSY
Circuit breaker fault triggered
8
Not supported, always 0
7
Not supported, always 0
6
OFF
This bit is asserted if the MOSFET is not switched on for any reason.
Not supported, always 0
5
VOUT OV
IOUT OC
VIN UV
4
Not supported, always 0
3
A VIN undervoltage fault has occurred
A temperature fault or warning has occurred
A communication fault has occurred
A fault or warning not listed in bits [7:1] has occurred
2
TEMPERATURE
CML
1
0
None of the above
9.5.2.11 STATUS_VOUT (7Ah)
The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV warn flag.
Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying
fault should be cleared and a CLEAR_FAULTS command issued.
表 12. STATUS_VOUT Definitions
BIT
7
NAME
MEANING
DEFAULT
VOUT OV fault
VOUT OV warn
VOUT UV warn
VOUT UV fault
VOUT max
Not supported, always 0
Not supported, always 0
0
0
0
0
0
0
0
0
6
5
A VOUT undervoltage warning has occurred
Not supported, always 0
4
3
Not supported, always 0
2
TON max fault
TOFF max fault
VOUT tracking error
Not supported, always 0
1
Not supported, always 0
0
Not supported, always 0
9.5.2.12 STATUS_INPUT (7Ch)
The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags
related to input voltage, current, and power. Accesses to this command should use the PMBus read byte
protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command
issued. The VIN UV warn flag defaults to 1 on startup; however, it is cleared to 0 after the first time the input
voltage increases above the resistor-programmed UVLO threshold.
24
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表 13. STATUS_INPUT Definitions
BIT
7
NAME
VIN OV fault
VIN OV warn
VIN UV warn
VIN UV fault
Insufficient voltage
IIN OC fault
MEANING
DEFAULT
A VIN overvoltage fault has occurred
A VIN overvoltage warning has occurred
A VIN undervoltage warning has occurred
A VIN undervoltage fault has occurred
Not supported, always 0
0
0
1
0
0
0
0
0
6
5
4
3
2
An IIN overcurrent fault has occurred
An IIN overcurrent warning has occurred
A PIN overpower warning has occurred
1
IIN OC warn
PIN OP warn
0
9.5.2.13 STATUS_TEMPERATURE (7dh)
The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags
related to the temperature telemetry value. Accesses to this command should use the PMBus read byte protocol.
To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued.
表 14. STATUS_TEMPERATURE Definitions
BIT
7
NAME
Overtemp fault
Overtemp warn
Undertemp warn
Undertemp fault
Reserved
MEANING
An overtemperature fault has occurred
An overtemperature warning has occurred
Not supported, always 0
DEFAULT
0
0
0
0
0
0
0
0
6
5
4
Not supported, always 0
3
Not supported, always 0
2
Reserved
Not supported, always 0
1
Reserved
Not supported, always 0
0
Reserved
Not supported, always 0
9.5.2.14 STATUS_CML (7Eh)
The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to
communication faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this
register, a CLEAR_FAULTS command should be issued.
表 15. STATUS_CML Definitions
BIT
7
NAME
Invalid or unsupported command received
Invalid or unsupported data received
Packet error check failed
DEFAULT
0
0
0
0
0
0
0
0
6
5
4
Not supported, always 0
3
Not supported, always 0
2
Reserved, always 0
1
Miscellaneous communications fault has occurred
Not supported, always 0
0
9.5.2.15 STATUS_OTHER (7Fh)
表 16. STATUS_OTHER Definitions
BIT
NAME
DEFAULT
7
6
5
Reserved: Always 0
Reserved: Always 0
CB Fault
0
0
0
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表 16. STATUS_OTHER Definitions (接下页)
BIT
4
NAME
DEFAULT
Not supported, always 0
Not supported, always 0
Not supported, always 0
Not supported, always 0
Not supported, always 0
0
0
0
0
0
3
2
1
0
9.5.2.16 STATUS_MFR_SPECIFIC (80h)
The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific
status information. Accesses to this command should use the PMBus read byte protocol. To clear bits in this
register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued.
表 17. STATUS_MFR_SPECIFIC Definitions
BIT
7
MEANING
DEFAULT
Circuit breaker fault
0
0
0
1
0
0
0
0
6
External MOSFET shorted fault
Not supported, always 0
Defaults loaded
5
4
3
Not supported, always 0
Not supported, always 0
Not supported, always 0
Not supported, always 0
2
1
0
9.5.2.17 READ_EIN (86h)
The READ_EIN command is a standard PMBus command that returns information the host can use to calculate
average input power consumption. Accesses to this command should use the PMBus block read protocol. The
information provided by this command is independent of any device-specific averaging period. Six data bytes are
returned by this command. The first two bytes are the two's complement signed output of an accumulator that
continuously sums samples of the instantaneous input power. The accumulator value is the summation of the
instantaneous power measurement. These two data bytes are formatted in the DIRECT format. The next data
byte is a rollover count for the accumulator. This byte is an unsigned integer that indicates the number of times
the accumulator has rolled over from its maximum positive unsigned integer (7FFFh) to 0. The last three data
bytes are a 24-bit unsigned integer that counts the number of samples of the instantaneous input power. This
value also rolls over periodically from its maximum positive value to 0. It is up to the host to keep track of the
sample count and account for the rollovers.
The combination of the accumulator and the roller count may overflow after a period of several seconds.
Similarly, the sample count value overflows, but this event only occurs once every few hours.
To convert the data obtained from two separate READ_EIN commands into average power, first convert the
accumulator and rollover count to an unsigned integer (see 公式 1).
Accumulator_23 = (rollover_count << 15) + accumulator
(1)
Note that the overflow of this variable needs to be monitored and properly accounted for. Data from the previous
calculation, along with the sample count values from the corresponding register access, can be used to get the
unscaled average power:
Accumulator _ 23 [n] - Accumulator _ 23 [n -1]
Sample_count [n] - Sample_count [n -1]
where
•
•
•
•
Accumulator_23 [n] = Overflow corrected, 23-bit accumulator data from this read
Sample_count [n] = Sample count data from this read
Accumulator_23 [n – 1] = Overflow corrected, 23-bit accumulator data from previous read
Sample_count [n – 1] = Sample count data from previous read
26
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•
Unscaled average power is now in the same units as the data from the READ_PIN command. Coefficients
from 表 47 are used to convert the unscaled average power to Watts.
(2)
表 18. READ_EIN Definition
BYTE
MEANING
DEFAULT
0
1
2
3
4
5
6
Number of bytes
6
0
0
0
0
0
0
Power accumulator low byte
Power accumulator high byte
Power accumulator rollover count
Sample count low byte
Sample count mid byte
Sample count high byte
9.5.2.18 READ_VIN (88h)
The READ_VIN command is a0 standard PMBus command that returns the 12-bit measured value of the input
voltage. Reading this register should use the coefficients shown in 表 47. Accesses to this command should use
the P0MBus read word protocol. This value is also used internally for the VIN overvoltage and undervoltage
warning detection.
表 19. 0READ_VIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured va0lue for VIN
0000h
9.5.2.19 READ_IIN (89h)
The READ_IIN command is a standard PMBus command that returns the 12-bit measured value of the input
current. Reading this register should use the coefficients shown in 表 47. Accesses to this command should use
the PMBus read word protocol. This value is also mirrored at (D1h).
表 20. READ_IIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for IIN
0000h
9.5.2.20 READ_VOUT (8Bh)
The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the output
voltage. Reading this register should use the coefficients shown in 表 47. Accesses to this command should use
the PMBus read word protocol. This value is also used internally for the VOUT undervoltage warning detection.
表 21. READ_VOUT Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for VOUT
0000h
9.5.2.21 READ_TEMPERATURE_1 (8Dh)
The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of the
temperature measured by the external temperature sense diode. Reading this register should use the coefficients
shown in 表 47. Accesses to this command should use the PMBus read word protocol. This value is also used
internally for the overtemperature fault and warning detection. This data has a range of –256°C to 255°C after
the coefficients are applied.
表 22. READ_TEMPERATURE_1 Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for TEMPERATURE
0000h
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9.5.2.22 READ_PIN (97h)
The READ_PIN command is a standard PMBus command that returns the 12-bit measured value of the input
power. Reading this register should use the coefficients shown in 表 47. Accesses to this command should use
the PMBus read word protocol. This value is also mirrored at (D5h).
表 23. READ_PIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for PIN
0000h
9.5.2.23 MFR_ID (99h)
The MFR_ID command is a standard PMBus command that returns the identification of the manufacturer. To
read the MFR_ID, use the PMBus block read protocol.
表 24. MFR_ID Register
BYTE
NAME
Number of bytes
MFR ID-1
VALUE
03h
0
1
2
3
54h ‘T’
29h ‘I’
00h
MFR ID-2
MFR ID-3
9.5.2.24 MFR_MODEL (9Ah)
The MFR_MODEL command is a standard PMBus command that returns the part number of the chip. To read
the MFR_MODEL, use the PMBus block read protocol.
表 25. MFR_MODEL Register
BYTE
NAME
Number of bytes
MFR ID-1
MFR ID-2
MFR ID-3
MFR ID-4
MFR ID-5
MFR ID-6
MFR ID-7
MFR ID-8
VALUE
08h
0
1
2
3
4
5
6
7
8
4Ch ‘L’
4Dh ‘M’
35h ‘5’
30h ‘0’
36h ‘6’
36h ‘6’
49h 'I'
00h
9.5.2.25 MFR_REVISION (9Bh)
The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To
read the MFR_REVISION, use the PMBus block read protocol.
表 26. MFR_REVISION Register
BYTE
NAME
Number of bytes
MFR ID-1
VALUE
02h
0
1
2
41h ‘A’
41h ‘A’
MFR ID-2
28
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9.5.3 Manufacturer Specific PMBus Commands
9.5.3.1 MFR_SPECIFIC_00: READ_VAUX (D0h)
The READ_VAUX command reports the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal
to 2.97 V to ground are reported at plus full scale (0FFFh). Voltages less than or equal to 0 V referenced to
ground are reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus read word
protocol.
表 27. READ_VAUX Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for VAUX input
0000h
9.5.3.2 MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
The MFR_READ_IIN command reports the 12-bit ADC measured current sense voltage. To read data from the
MFR_READ_IIN command, use the PMBus read word protocol. Reading this register should use the coefficients
shown in 表 47. See the section Reading and Writing Telemetry Data and Warning Thresholds to calculate the
values to use.
表 28. MFR_READ_IIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Measured value for input current sense voltage
0000h
9.5.3.3 MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
The MFR_READ_PIN command reports the upper 12 bits of the VIN × IIN product as measured by the 12-bit
ADC. To read data from the MFR_READ_PIN command, use the PMBus read word protocol. Reading this
register should use the coefficients shown in 表 47. See the section Reading and Writing Telemetry Data and
Warning Thresholds to calculate the values to use.
表 29. MFR_READ_PIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
VALUE for input current x input voltage
0000h
9.5.3.4 MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input overcurrent warning threshold. In the event
that the input current rises above the value set in this register, the IIN overcurrent flags are set in the respective
registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus
read/write word protocol. Reading and writing to this register should use the coefficients shown in 表 47.
表 30. MFR_IIN_OC_WARN_LIMIT Register
VALUE
MEANING
DEFAULT
0FFFh
N/A
0000h to 0FFEh
0FFFh
Value for input overcurrent warn limit
Input overcurrent warning disabled
9.5.3.5 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event
that the input power rises above the value set in this register, the PIN over-power flags are set in the respective
registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus
read/write word protocol. Reading and writing to this register should use the coefficients shown in 表 47.
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表 31. MFR_PIN_OPWARN_LIMIT Register
VALUE
MEANING
DEFAULT
0FFFh
N/A
0000h to 0FFEh
0FFFh
Value for input over power warn limit
Input over power warning disabled
9.5.3.6 MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
The READ_PIN_PEAK command reports the maximum input power measured since a power-on reset or the last
CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus read word protocol.
Use the coefficients shown in 表 47.
表 32. READ_PIN_PEAK Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Maximum value for input current × input voltage since reset or last clear 0000h
9.5.3.7 MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
The CLEAR_PIN_PEAK command clears the PIN PEAK register. This command uses the PMBus send byte
protocol.
9.5.3.8 MFR_SPECIFIC_07: GATE_MASK (D7h)
The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When
the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers are still
updated (STATUS, DIAGNOSTIC) and SMBA is still asserted. This register is accessed with the PMBus
read/write byte protocol.
CAUTION
Inhibiting the MOSFET switch off in response to overcurrent or circuit breaker fault
conditions will likely result in the destruction of the MOSFET. This functionality must be
used with great care and supervision.
表 33. MFR_SPECIFIC_07 Gate Mask Definitions
BIT
7
NAME
DEFAULT
Not used, always 0
Not used, always 0
VIN UV FAULT
0
0
0
0
0
0
0
0
6
5
4
VIN OV FAULT
3
IIN/PFET FAULT
OVERTEMP FAULT
Not used, always 0
2
1
0
CIRCUIT BREAKER FAULT
30
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The IIN/PFET fault refers to the input current fault and the MOSFET power dissipation fault. There is no input
power fault detection, only input power warning detection.
9.5.3.9 MFR_SPECIFIC_08: ALERT_MASK (D8h)
The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each bit
corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an
SMBA being asserted. When the corresponding bit is high, that condition does not cause the SMBA to be
asserted. If that condition occurs, the registers where that condition is captured is still updated (STATUS
registers, DIAGNOSTIC_WORD) and the external MOSFET gate control is still active (VIN_OV_FAULT,
VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus
read/write word protocol. The VIN UNDERVOLTAGE FAULT flag defaults to 1 on startup; however, it clears to 0
after the first time the input voltage increases above the resistor-programmed UVLO threshold.
表 34. ALERT_MASK Definitions
BIT
15
14
13
12
11
10
9
NAME
VOUT UNDERVOLTAGE WARN
IIN LIMIT warn
DEFAULT
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
VIN UNDERVOLTAGE WARN
VIN OVERVOLTAGE WARN
POWER GOOD
OVERTEMP WARN
Not used
8
OVERPOWER LIMIT WARN
Not used
7
6
EXT_MOSFET_SHORTED
VIN UNDERVOLTAGE FAULT
VIN OVERVOLTAGE FAULT
IIN/PFET FAULT
5
4
3
2
OVERTEMPERATURE FAULT
CML FAULT (communications fault)
CIRCUIT BREAKER FAULT
1
0
9.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
The DEVICE_SETUP command can be used to override pin settings to define operation of the LM5066I under
host control. This command is accessed with the PMBus read/write byte protocol.
表 35. DEVICE_SETUP Byte Format
BIT
NAME
MEANING
111 = Unlimited retries
110 = Retry 16 times
101 = Retry 8 times
100 = Retry 4 times
011 = Retry 2 times
010 = Retry 1 time
7:5
Retry setting
001 = No retries
000 = Pin configured retries
0 = High setting (50 mV)
1 = Low setting (26 mV)
4
3
2
Current limit setting
CB/CL ratio
0 = Low setting (1.9x)
1 = High setting (3.9x)
0 = Use pin settings
1 = Use SMBus settings
Current limit configuration
1
0
Unused
Unused
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To configure the current limit setting with this register, it is necessary to set the current limit configuration bit (2)
to 1 to enable the register to control the current limit function and the current limit setting bit (4) to select the
desired setting. If the current limit configuration bit is not set, the pin setting is used. The circuit breaker to current
limit ratio value is set by the CB / CL ratio bit (3). Note that if the current limit configuration is changed, the
samples for the telemetry averaging function are not reset. TI recommends to allow a full averaging update
period with the new current limit configuration before processing the averaged data.
Note that the current limit configuration affects the coefficients used for the current and power measurements
and warning registers.
9.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry
information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the
LM5066I in a single SMBus transaction. The block is 12-bytes long with telemetry information being sent out in
the same manner as if an individual READ_XXX command had been issued (shown in 表 36). The contents of
the block read register are updated every clock cycle (85 ns) as long as the SMBus interface is idle.
BLOCK_READ also specifies that the VIN, VOUT, IIN and PIN measurements are all time-aligned. If separate
commands are used, individual samples may not be time-aligned because of the delay necessary for the
communication protocol.
The block read command is read through the PMBus block read protocol.
32
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表 36. BLOCK_READ Register Format
Byte Count (Always 12)
(1 Byte)
(1 word)
(1 word)
(1 word)
(1 word)
(1 word)
(1 word)
DIAGNOSTIC_WORD
IIN_BLOCK
VOUT_BLOCK
VIN_BLOCK
PIN_BLOCK
TEMP_BLOCK
9.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
The SAMPLES_FOR_AVG command is a manufacturer-specific command for setting the number of samples
used in computing the average values for IIN, VIN, VOUT, and PIN. The decimal equivalent of the AVGN nibble
is the power of 2 samples, (for example, AVGN = 12 equates to N = 4096 samples used in computing the
average). The LM5066I supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and
4096. The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, and PIN simultaneously.
The LM5066I uses simple averaging. This is accomplished by summing consecutive results up to the number
programmed, then dividing by the number of samples. Averaging is calculated according to the following
sequence:
Y = (X(N) + X(N-1) + ... + X(0)) / N
(3)
When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a
whole new sequence begins that requires the same number of samples (in this example, 4096) to be taken
before the new average is ready.
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表 37. SAMPLES_FOR_AVG Register
AVGN (b)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
N = 2AVGN
Averaging / Register Update Period (ms)
1
2
1
2
4
4
8
8
16
16
32
32
64
64
128
256
512
1024
2048
4096
128
256
512
1024
2048
4096
Note that a change in the SAMPLES_FOR_AVG register is not reflected in the average telemetry measurements
until the present averaging interval has completed. The default setting for AVGN is 1000b, or 08h.
The SAMPLES_FOR_AVG register is accessed with the PMBus read/write byte protocol.
表 38. SAMPLES_FOR_AVG Register
VALUE
MEANING
DEFAULT
00h to 0Ch
Exponent (AVGN) for number of samples to average over
00h
9.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
The READ_AVG_VIN command reports the 12-bit ADC measured input average voltage. If the data is not ready,
the returned value is the previous averaged data. However, if there is no previously averaged data, the default
value (0000h) is returned. This data is read with the PMBus read word protocol. This register should use the
coefficients shown in 表 47.
表 39. READ_AVG_VIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Average of measured values for input voltage
0000h
9.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
The READ_AVG_VOUT command reports the 12-bit ADC measured current sense average voltage. The
returned value is the default value (0000h) or previous data when the average data is not ready. This data is
read with the PMBus read word protocol. This register should use the coefficients shown in 表 47.
表 40. READ_AVG_VOUT Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Average of measured values for output voltage
0000h
9.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
The READ_AVG_IIN command reports the 12-bit ADC measured current sense average voltage. The returned
value is the default value (0000h) or previous data when the average data is not ready. This data is read with the
PMBus read word protocol. This register should use the coefficients shown in 表 47.
表 41. READ_AVG_IIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Average of measured values for current sense voltage
0000h
34
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9.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)
The READ_AVG_PIN command reports the 12-bit ADC measured VIN x IIN product. The returned value is the
default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus
read word protocol. This register should use the coefficients shown in 表 47.
表 42. READ_AVG_IIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Average of measured values for current sense voltage
0000h
9.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN
The READ_AVG_PIN command reports the upper 12-bits of the average VIN × IIN product as measured by the
12-bit ADC. The user can read the default value (0000h) or previous data when the average data is not ready.
This data is read with the PMBus read word protocol. This register should use the coefficients shown in 表 47.
表 43. READ_AVG_PIN Register
VALUE
MEANING
DEFAULT
0000h to 0FFFh
Average of measured value for input voltage x input current sense voltage
0000h
9.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
The BLACK BOX READ command retrieves the BLOCK READ data which was latched in at the first assertion of
SMBA by the LM5066I. It is re-armed with the CLEAR_FAULTS command. It is the same format as the
BLOCK_READ registers, the only difference is that its contents are updated with the SMBA edge rather than the
internal clock edge. This command is read with the PMBus block read protocol.
9.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
The READ_DIAGNOSTIC_WORD PMBus command reports all of the LM5066I faults and warnings in a single
read operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to
various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD register. The
READ_DIAGNOSTIC_WORD command should be read with the PMBus read word protocol. The
READ_DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and
AVG_BLOCK_READ operations. Note that if UVLO is pulled low to shutt OFF the FET, the diagnostic word will
return 08E0h.
表 44. DIAGNOSTIC_WORD Format
BIT
15
14
13
12
11
10
9
MEANING
VOUT_UNDERVOLTAGE_WARN
IIN_OP_WARN
DEFAULT
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
VIN_UNDERVOLTAGE_WARN
VIN_OVERVOLTAGE_WARN
POWER GOOD
OVER_TEMPERATURE_WARN
TIMER_LATCHED_OFF
EXT_MOSFET_SHORTED
CONFIG_PRESET
8
7
6
DEVICE_OFF
5
VIN_UNDERVOLTAGE_FAULT
VIN_OVERVOLTAGE_FAULT
IIN_OC/PFET_OP_FAULT
OVER_TEMPERATURE_FAULT
CML_FAULT
4
3
2
1
0
CIRCUIT_BREAKER_FAULT
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9.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average
telemetry information (IIN, VOUT, VIN, and PIN) and temperature to capture all of the operating information of
the part in a single PMBus transaction. The block is 12-bytes long with telemetry information sent out in the same
manner as if an individual READ_AVG_XXX command had been issued (shown in 表 45). AVG_BLOCK_READ
also specifies that the VIN, VOUT, and IIN measurements are all time-aligned whereas there is a chance they
may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ command, use
the SMBus block read protocol.
表 45. AVG_BLOCK_READ Register Format
Byte Count (Always 12)
DIAGNOSTIC_WORD
AVG_IIN
(1 Byte)
(1 word)
(1 word)
(1 word)
(1 word)
(1 word)
(1 word)
AVG_VOUT
AVG_VIN
AVG_PIN
TEMPERATURE
36
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To load
+48
OUT
GATE
DIODE
VAUX
VIN_K SENSE
OVLO
UVLO/EN
GATE MASK
VIN OV FAULT
STATUS_INPUT 7Ch
CMP
CMP
CMP
CMP
CMP
CURRENT LIMIT
2.48
2.46
VIN UV FAULT
STATUS_INPUT 7Ch
STATUS_WORD 79h
STATUS_BYTE 78h
MOSFET
DISSIPATION
LIMIT
IIN OC FAULT
STATUS_INPUT 7Ch
CIRCUIT
BREAKER
IIN
Circuit Breaker FAULT
MOSFET STATUS
STATUS_MFR_SPECIFIC 80h
S/H
MUX
ADC
FET Shorted FAULT
STATUS_MFR_SPECIFIC 80h
VIN_OV_WARN_LIMIT 57h
VIN_UV_WARN_LIMIT 58h
VIN_OV WARNING
STATUS_INPUT 7Ch
CMP
VIN_UV WARNING
STATUS_INPUT 7Ch
CMP
DATA
OUTPUT
SAMPLES_FOR_AVG DBh
READ_AVG_VIN DCh
READ_AVG_IIN DEh
IIN_OC_WARN_LIMIT D3h
PIN_OP_WARN_LIMIT D4h
IIN_OC WARNING
STATUS_INPUT 7Ch
READ_VIN 88h
READ_IIN D1h
FAULT
SYSTEM
CMP
CMP
PIN_OP WARNING
STATUS_INPUT 7Ch
READ_PIN D2h
READ_VOUT 8Bh
TEMPERATURE 8Dh
VAUX D0h
READ_AVG_PIN DFh
READ_AVG_VOUT DDh
VOUT_UV_WARN_LIMIT 43h
OT_WARNING_LIMIT 51h
VOUT_UV WARNING
STATUS_VOUT 7Ah
OT_FAULT_LIMIT
57h
CMP
CMP
AVERAGED
DATA
OT_FAULT_LIMIT
CMP
STATUS_TEMPERATURE 7Dh
STATUS_WORD 79h
STATUS_BYTE 78h
OT_WARNING_LIMIT
STATUS_TEMPERATURE 7Dh
READ_PIN_PEAK D5h
WARNING
LIMITS
CLEAR_PIN_PEAK D6h
WARNING
SYSTEM
PEAK-HOLD
PMBus Interface
图 17. Command / Register and Alert Flow Diagram
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9.5.4 Reading and Writing Telemetry Data and Warning Thresholds
All measured telemetry data and user-programmed warning thresholds are communicated in 12-bit two’s
complement binary numbers read or written in 2-byte increments conforming to the direct format as described in
section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II). The organization of
the bits in the telemetry or warning word is shown in 表 46, where Bit_11 is the most significant bit (MSB) and
Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained
to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the
temperature word ranges from 0 to 65535.
表 46. Telemetry and Warning Word Format
Byte
B7
Bit_7
0
B6
Bit_6
0
B5
Bit_5
0
B4
Bit_4
0
B3
B2
B1
B0
1
2
Bit_3
Bit_11
Bit_2
Bit_10
Bit_1
Bit_9
Bit_0
Bit_8
Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is
accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System
Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the
values received into a reading of volts, amperes, watts, or other units using the following relationship:
1
x =
Y ´10-R - b
(
)
m
where
•
•
•
•
•
X = The calculated real-world value (volts, amps, watt, and so forth)
m = The slope coefficient
Y = A 2-byte two's complement integer received from device
b = The offset, a 2-byte two's complement integer
R = The exponent, a 1-byte two's complement integer
(4)
R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a
register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.
表 47. Telemetry and Warning Conversion Coefficients
Commands
Condition
Format
Number of Data Bytes
m
b
R
Unit
READ_VIN, READ_AVG_VIN
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
DIRECT
2
4617
–140.0
–2
V
READ_VOUT, READ_AVG_VOUT
VOUT_UV_WARN_LIMIT
DIRECT
DIRECT
DIRECT
2
2
2
4602
13774
15076
500.0
73.0
–2
–1
–2
V
V
A
READ_VAUX
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
READ_IN, READ_AVG_IN(1)
MFR_IIN_OC_WARN_LIMIT
CL = VDD
CL = GND
-503.9
DIRECT
DIRECT
2
2
7645
1701
100
–2
–3
A
READ_PIN, READ_AVG_PIN(1)
READ_PIN_PEAK
,
CL = VDD
CL = GND
–4000
W
MFR_PIN_OP_WARN_LIMIT
READ_PIN, READ_AVG_PIN(1)
READ_PIN_PEAK
,
DIRECT
DIRECT
2
2
860.6
–965
0
–3
–3
W
MFR_PIN_OP_WARN_LIMIT
READ_TEMPERATURE_1
OT_WARN_LIMIT
16000
°C
OT_FAULT_LIMIT
(1) The coefficients relating to current/power measurements and warning thresholds shown are normalized to a sense resistor (RS) value of
1 mΩ. In general, the current or power coefficients can be calculated using the relationships shown in 表 48.
38
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表 48. Current and Power Telemetry and Warning Conversion Coefficients (RS in mΩ)
Commands
Condition
Format
Number of Data Bytes
m
b
R
Unit
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
CL = VDD
DIRECT
2
15076 × RS
–503.9
–2
A
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
READ_PIN, READ_AVG_PIN(1)
READ_PIN_PEAK
CL = GND
CL = VDD
DIRECT
DIRECT
2
2
7645 × RS
1701 × RS
100.0
–2
–3
A
,
–4000
W
MFR_PIN_OP_WARN_LIMIT
READ_PIN, READ_AVG_PIN(1)
READ_PIN_PEAK
,
CL = GND
DIRECT
2
860.6 × RS
–965.0
–3
W
MFR_PIN_OP_WARN_LIMIT
(1) The coefficients relating to current/power measurements and warning thresholds shown are normalized to a sense resistor (RS) value of
1 mΩ. In general, the current or power coefficients can be calculated using the relationships shown in 表 48.
Take care to adjust the exponent coefficient, R, such that the value of m remains within the range of –32768 to
32767. For example, if a 5-mΩ sense resistor is used, the correct coefficients for the READ_IIN command with
CL = VDD would be m = 7553, b = –65, R = –1.
9.5.5 Determining Telemetry Coefficients Empirically With Linear Fit
The coefficients for telemetry measurements and warning thresholds presented in 表 47 are adequate for the
majority of applications. Current and power coefficients are dependent on RSNS and must be calculated per
application. 表 48 provides the equations necessary for calculating the current and power coefficients for the
general case. These were obtained by characterizing multiple units over temperature and are considered optimal.
The small signal nature of the current and power measurement makes it more susceptible to PCB parasitics than
other telemetry channels. In addition there is some variation in RSNS and the LM5066I itself. This may cause
slight variations in the optimum coefficients (m, b, and R) for converting from digital values to real world values
(for example, amps and watts). To maximize telemetry accuracy, the coefficients can be calibrated for a given
board using empirical methods. This would determine optimum coefficients to cancel out the error from PCB
parasitics, RSNS variation, and the variation of LM5066I. It is not considered good practice to take measurements
on one board and use the computed coefficients for all units in production, because the RSNS and the LM5066I
on a given board are randomly chosen and do not represent a statistical mean. It is recommended to either
calibrate all boards individually or to use the recommended coefficients from 表 48.
The optimal current coefficients for a specific board can be determined using the following method:
1. While the LM5066I is in normal operation, measure the voltage across the sense resistor using Kelvin test
points and a high accuracy DVM while controlling the load current. Record the integer value returned by the
READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more
voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should
span nearly the full-scale range of the current (for example, voltage across RSNS of 5 and 20 mV).
2. Convert the measured voltages to currents by dividing them by the value of RSNS. For best accuracy, the
value of RSNS should be measured. 表 49 assumes a sense resistor value of 5 mΩ.
表 49. Measurements for Linear Fit Determination of Current Coefficients
Measured Voltage Across
RS (V)
Measured Current
(A)
READ_AVG_IIN
(Integer Value)
0.005
0.01
0.02
1
2
4
568
1108
2185
3. Using the spreadsheet (or a math program) determine the slope and the y-intercept of the data returned by
the READ_AVG_IIN command versus the measured current. For the data shown in 表 47:
–
–
–
READ_AVG_IN value = slope × (Measured Current) + (y-intercept)
Slope = 538.9
Y-intercept = 29.5
4. To determine the m coefficient, simply shift the decimal point of the calculated slope to arrive at integer with
a suitable number of significant digits for accuracy (typically 4) while staying with the range of –32768 to
32767. This shift in the decimal point equates to the R coefficient. For the slope value shown in the previous
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step, the decimal point would be shifted to the right once hence R = –1.
5. After the R coefficient has been determined, the b coefficient is found by multiplying the y-intercept by 10 –R
In this case the value of b = 295.
.
–
–
–
–
Calculated current coefficients:
m = 5389
b = 295
R = –1
1
x =
Y ´10-R - b
(
)
m
where
•
•
•
•
•
X = The calculated real-world value (volts, amps, watts, temperature)
m = The slope coefficient, is the 2-byte, two's complement integer
Y = A 2-byte two's complement integer received from device
b = The offset, a 2-byte two's complement integer
R = The exponent, a 1-byte two's complement integer
(5)
This procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting
measured current for some other parameter (for example, power or voltage).
9.5.6 Writing Telemetry Data
There are several locations that require writing data if their optional usage is desired. Use the same coefficients
previously calculated for your application, and apply them using this method as prescribed by the PMBus revision
section 7.2.2 Sending a Value
Y = mX + b ´10R
(
)
where
•
•
•
•
•
X = The calculated real-world value (volts, amps, watts, temperature)
m = The slope coefficient is the 2-byte, two's complement integer
Y = A 2-byte two's complement integer received from device
b = The offset, a 2-byte two's complement integer
R = The exponent, a 1-byte two's complement integer
(6)
9.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)
The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27
addresses for communicating with the LM5066I. 表 50 depicts 7-bit addresses (eighth bit is read/write bit).
表 50. Device Addressing
ADR2
ADR1
ADR0
DECODED ADDRESS
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
Z
Z
Z
0
0
0
1
1
1
Z
Z
Z
0
Z
0
1
Z
0
1
Z
0
1
Z
0
1
Z
40h
41h
42h
43h
44h
45h
46h
47h
10h
11h
12h
13h
14h
40
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表 50. Device Addressing (接下页)
ADR2
ADR1
ADR0
DECODED ADDRESS
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
Z
Z
Z
0
0
0
1
1
1
0
1
Z
0
1
Z
0
1
Z
0
1
Z
0
1
15h
16h
17h
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
9.5.8 SMBA Response
The SMBA effectively has two masks:
•
•
The alert mask register at D8h
The ARA automatic mask.
The ARA automatic mask is a mask that is set in response to a successful ARA read. An ARA read operation
returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful
ARA read means that this part was the one that returned its address. When a part responds to the ARA read, it
releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its
address, the SMBA signal de-asserts.
The way that the LM5066I releases the SMBA signal is by setting the ARA automatic mask bit for all fault
conditions present at the time of the ARA read. All status registers will still the fault condition, but it does not
generate a SMBA on that fault again until the ARA automatic mask is cleared by the host issuing a
CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on
a part, even if the ARA read is not done. 图 18 depicts a schematic version of this flow.
From other
fault inputs
SMBA
Fault Condition
Alert Mask D8h
From PMBus
Set
ARA Auto Mask
Clear
ARA Operation Flag Succeeded
Clear_Fault Command Received
图 18. Typical Flow Schematic for SMBA Fault
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10 Application and Implementation
10.1 Application Information
The LM5066I is a hotswap with a PMBus interface that provides current, voltage, power, and status information
to the host. As a hotswap, it is used to manage inrush current and protect in case of faults.
When designing a hotswap, three key scenarios should be considered:
•
•
•
Start-up
Output of a hotswap is shorted to ground when the hotswap is on. This is often referred to as a hot-short.
Powering-up a board when the output and ground are shorted. This is usually called a start-into-short.
All of these scenarios place a lot of stress on the hotswap MOSFET and take special care when designing the
hotswap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the following
sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends
to use the LM5066I Design Calculator provided on the product page.
10.2 Typical Application
This section shows two application examples. The requirements are the same, except the second design
requires twice the current and twice the output capacitance. In the 20A design example, a regular design is
attempted using a power limiting based start-up. Unfortunately this results in insufficient margin and the final
design relies on a dv/dt based start-up.
10.2.1 48-V, 10-A PMBus Hotswap Design
This section describes the design procedure for a 48-V, 10-A PMBUS hotswap design.
Q
2
R
VIN
SNS
VOUT
Q
1
D
C
OUT
1
Z
1
C
IN
Only required when
using dv/dt start-up
R
5
SENSE
VIN_K
GATE OUT
DIODE
FB
R
VDD
D
2
1
R
R
3
4
VIN
R
6
UVLO/EN
OVLO
100 k
1k
PGD
C
dv/dt
VDD
LM5066I
ADR2
ADR1
ADR0
R
2
AGND
GND
Q
3
N/C
N/C
CL
RETRY
SMBA
SDAO
SDAI
SMBus
Interface
Auxiliary ADC Input
(0 to 2.97 V)
VAUX
SCL
PWR
VDD
VREF
TIMER
R
PWR
C
TIMER
1 PF
1 PF
图 19. Typical Application Circuit
10.2.1.1 Design Requirements
表 51 summarizes the design parameters that must be known before designing a hotswap circuit. When charging
the output capacitor through the hotswap MOSFET, the FET’s total energy dissipation equals the total energy
stored in the output capacitor (1 / 2CV2). Thus, both the input voltage and output capacitance determine the
stress experienced by the MOSFET. The maximum load current drives the current limit and sense resistor
selection. In addition, the maximum load current, maximum ambient temperature, and thermal properties of the
42
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Typical Application (接下页)
PCB (RθCA) drive the selection of the MOSFET RDSON and the number of MOSFETs used. RθCA is a strong
function of the layout and the amount of copper that is connected to the drain of the MOSFET. Note that the
drain is not electrically connected to the ground plane, and thus the ground plane cannot be used to help with
heat dissipation. This design example uses RθCA = 30°C/W, which is similar to the LM5066I EVM. It is a good
practice to measure the RθCA of a given design after the physical PCBs are available.
Finally, it is important to understand what test conditions the hotswap needs to pass. In general, a hotswap is
designed to pass both a hot-short and a start into a short, which are described in the previous section. Also, TI
recommends to keep the load OFF until the hotswap is fully powered-up. Starting the load early causes
unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start-up.
表 51. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
40 to 60 V
10 A
Maximum load current
Maximum output capacitance of the hotswap
Maximum ambient temperature
MOSFET RθCA (function of layout)
Pass hot-short on output?
220 µF
85°C
30°C/W
Yes
Pass a start into short?
Yes
Is the load off until PG asserted?
Can a hot board be plugged back in?
Yes
Yes
10.2.1.2 Detailed Design-In Procedure
10.2.1.2.1 Select RSNS and CL Setting
LM5066I can be used with a VCL of 26 or 50 mV. Using the 26-mV threshold results in a lower RSNS and lower
I2R losses. The 26-mV option is selected for this design by connecting the CL pin directly to VDD. TI recommends
to target a current limit that is at least 10% above the maximum load current to account for the tolerance of the
LM5066I current limit. Targeting a current limit of 11 A, the sense resistor can be computed as follows:
ILIM
26mV
RSNS,CLC
=
=
= 2.36mW
VCL
11A
(7)
Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense
resistor along with a resistor divider can be used as shown in 图 20.
RSNS
R1
VIN_K
SENSE
图 20. SENSE Resistor Divider
The next larger available sense resistor should be chosen (3 mΩ in this case). The ratio of R1 and R2 can be
computed as follows:
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RSNS,CLC
R2 RSNS - RSNS,CLC 3mW - 2.36mW
R1
2.36mW
=
=
= 3.69
(8)
Note that the SENSE pin pulls 25 μA of current, which creates an offset across R2. TI recommends to keep R2
below 10 Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring
error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance
(RSNS,EFF) using 公式 9 and use that in all equations instead of RSNS
SNS ´R1
R1 + R2
.
R
RSNS,EFF
=
(9)
Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the
next smaller available sense resistor. For this application, a 2-mΩ resistor can be used for a 13-A current limit.
10.2.1.2.2 Selecting the Hotswap FETs
It is critical to select the correct MOSFET for a hotswap design. The device must meet the following
requirements:
•
The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by
transients. For most 48-V systems, a 100-V FET is a good choice.
•
•
The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, and start into short.
RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of
the FET. In fact, TI recommends to keep the steady-state FET temperature below 125°C to allow margin to
handle transients.
•
Maximum continuous current rating should be above the maximum load current and the pulsed-drain current
must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three
requirements also pass these two.
•
A VGS rating of ±20 V is required because the LM5066I can pull up the gate as high as 16 V above source.
For this design, the PSMN4R8-100BSE was selected for its low RDSON and superior SOA. After selecting the
MOSFET, the maximum steady-state case temperature can be computed as follows:
TC,MAX = TA,MAX + RqCA ´IL2OAD,MAX ´RDSON(TJ)
(10)
Note that the RDSON is a strong function of junction temperature, which for most D2PACK MOSFETs is very close
to the case temperature. A few iterations of the previous equations may be necessary to converge on the final
RDSON and TC,MAX value. According to the PSMN4R8-100BSE data sheet, it's RDSON doubles at 110°C. 公式 11
uses this RDSON value to compute the TC,MAX. Note that the computed TC,MAX is close to the junction temperature
assumed for RDSON. Thus, no further iterations are necessary.
C
TC,MAX = 85°C + 30°
´ 10A 2 ´ 2´ 4.8mW = 114°C
(
) (
)
W
(11)
10.2.1.2.3 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the
LM5066I is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across
the sense resistor (VSNS) to a very-low value. VSNS can be computed as shown in 公式 12.
PLIM ´RSNS
VSNS
=
VDS
(12)
To avoid significant degradation of the power limiting, TI does not recommend a VSNS of less than 4 mV. Based
on this requirement, the minimum allowed power limit can be computed as follows:
V
SNS,MIN ´ V
4mV ´ 60V
2mW
IN,MAX
P
=
=
= 120W
LIM,MIN
RSNS
(13)
In most applications, the power limit can be set to PLIM,MIN using 公式 14. Here RSNS and RPWR are in ohms and
PLIM is in watts.
P
LIM ´RSNS - 0.043
120´0.002 - 0.043
7´10-6
RPWR
=
=
= 28143W
7´10-6
(14)
44
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The closest available resistor should be selected. In this case, a 28.2-kΩ resistor was chosen.
10.2.1.2.4 Set Fault Timer
The fault timer runs when the hotswap is in power limit or current limit, which is the case during start-up. Thus,
the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current
limit (ILIM × VDS < PLIM), the maximum start time can be computed with 公式 15.
C
OUT ´ V
IN,MAX
tstart,max
=
ILIM
(15)
For most designs (including this example), ILIM × VDS > PLIM, so the hotswap starts in power limit and transitions
into current limit. In that case, the maximum start time can be computed as in 公式 16.
2
IN,MAX
2
é
ê
ë
ù
é
ù
ú
û
V
COUT
2
P
2
ILIM
220mF (60V)
120W
(13A)
LIM ú
tstart,max
=
´
+
=
´
+
= 3.38ms
ê
ê
ë
2 ú
P
2
120W
ê
ú
LIM
û
(16)
Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer
never times out during start-up, TI recommends to set the fault time (tflt) to be 1.5 × tstart,max or 5.1 ms. This
accounts for the variation in power limit, timer current, and timer capacitance. Thus, CTIMER can be computed as
follows:
t
ƒlt ´itimer
5.1ms´75mA
CTIMER
=
=
= 98.07nF
vtimer
3.9V
(17)
The next largest standards capacitor value for CTIMER is chosen as 100 nF. After CTIMER is chosen, the actual
programmed fault time can be computed as follows:
C
TIMER ´ vtimer
100nF´3.9V
75mA
tƒlt
=
=
= 5.2ms
itimer
(18)
10.2.1.2.5 Check MOSFET SOA
When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all
test conditions. During a hot-short the circuit breaker trips and the LM5066I restarts into power limit until the timer
runs out. In the worst case, the MOSFET’s VDS equals VIN,MAX, IDS equals PLIM / VIN,MAX and the stress event
lasts for tflt. For this design example, the MOSFET has 60 V, 2 A across it for 5.2 ms.
Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for
10 ms. For 5.2 ms, the SOA can be extrapolated by approximating SOA versus time as a power function as
shown below:
ISOA t = a´ tm
( )
30A
6A
æ
ö
ln
ç
÷
ln I
(
t
/ I
t
SOA ( 1)
( )
)
SOA 2
è
ø
m =
=
= -0.7
ln t / t
(
1ms
10ms
æ
ö
)
1
2
ln
ç
÷
è
ø
ISOA
t
( 1) =
30A
0.7
( )
a =
= 30A ´ ms
-0.7
t1m
1ms
( )
ISOA 5.2ms = 30A ´(ms)0.7 ´(5.2ms)-0.7 = 9.46A
(
)
(19)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using 公式 20:
TJ,ABSMAX - TC,MAX
175°C -114°C
175°C - 25°C
ISOA 5.2ms,T
= I
5.2ms,25°C ´
= 9.46A ´
= 3.85A
(
)
(
)
C,MAX
SOA
TJ,ABSMAX - 25°C
(20)
45
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Based on this calculation, the MOSFET can handle 3.85 A, 60 V for 5.2 ms at elevated case temperature, but is
only required to handle 2 A during a hot-short. Thus, there is good margin and the design is robust. In general, TI
recommends that the MOSFET can handle 1.3× more than what is required during a hot-short. This provides
margin to account for the variance of the power limit and fault time.
10.2.1.2.6 Set UVLO and OVLO Thresholds
By programming the UVLO and OVLO thresholds, the LM5066I enables the series-pass device (Q1) when the
input supply voltage (VIN) is within the desired operational range. If VIN is below the UVLO threshold or above the
OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
10.2.1.2.6.1 Option A
The configuration shown in 图 21 requires three resistors (R1 to R3) to set the thresholds.
V
IN
VIN
20 PA
R1
R2
2.48 V
UVLO/EN
OVLO
TIMER AND
GATE
LOGIC CONTROL
2.46 V
R3
21 PA
GND
图 21. UVLO And OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
•
•
•
Choose the upper UVLO threshold (VUVH) and the lower UVLO threshold (VUVL).
Choose the upper OVLO threshold (VOVH).
The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the
values for R1 to R3 are determined. If VOVL must be accurately defined in addition to the other three
thresholds, see Option B. The resistors are calculated as follows:
VUV(HYS)
V
UVH - VUVL
R1=
=
20mA
20mA
(21)
(22)
(23)
R1´ VUVL ´ 2.46V
R3 =
VOVH ´ V
(
- 2.48V
)
UVL
2.48V ´R1
R2 =
- R3
VUVL - 2.48V
The lower OVLO threshold is calculated from:
é
ê
ù
æ
ç
è
ö
2.46V
R3
æ
ö
VOVL
=
R1+ R2 ´
- 21 mA + 2.46V
(
)
ú
÷
ç
÷
è
ø
ê
ë
ú
û
ø
(24)
When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
2.48V
æ
ö
VUVH =2.48V + R1´
+ 20 mA
ç
÷
R2 + R3
è
ø
(25)
2.48V ´ R1+ R2 + R3
(
R2 + R3
)
VUVL
=
(26)
(27)
VUV(HYS) = R1´ 20 mA
46
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2.46V ´ R1+ R2 + R3
(
R3
)
VOVH
=
(28)
2.46V
æ
ö
VOVL
=
- 21 mA ´ R1+ R2 + 2.46V
(
)
ç
÷
R3
è
ø
(29)
(30)
VOV(HYS) = R1+ R2 ´ 21 mA
)
(
10.2.1.2.6.2 Option B
If all four thresholds must be accurately defined, the configuration in 图 22 can be used.
V
IN
VIN
20 PA
R1
UVLO/EN
2.48 V
TIMER AND
GATE
R2
R3
R4
LOGIC CONTROL
2.46 V
GND
OVLO
21 PA
图 22. Programming the Four Thresholds
The four resistor values are calculated as follows:
•
•
•
Choose the upper and lower UVLO thresholds (VUVH) and (VUVL).
VUV(HYS)
V
UVH - VUVL
R1=
=
20 mA
20 mA
(31)
(32)
2.48V ´R1
R2 =
VUVL - 2.48V
Choose the upper and lower OVLO threshold (VOVH) and (VOVL).
OVH - VOVL
V
R3 =
21 mA
(33)
(34)
2.46V ´R3
R4 =
V
- 2.46V
(
)
OVH
When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
é
ù
ú
û
2.48V
R2
æ
ö
VUVH = 2.48V + R1´
+ 20 mA
ê
ç
÷
è
ø
ë
(35)
2.48V ´ R1+ R2
(
R2
)
VUVL
=
(36)
(37)
VUV(HYS) = R1´ 20 mA
2.46V ´ R3 + R4
(
R4
)
VOVH
=
(38)
(39)
é
ù
2.46V
R4
æ
ö
VOVL = 2.46V + R3´
- 21 mA
ê
ú
ç
÷
è
ø
ë
û
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10.2.1.2.6.3 Option C
The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in 图 23. Q1 is switched
on when the VIN voltage reaches the POREN threshold (≊8.6 V). The OVLO thresholds are set using R3, R4.
Their values are calculated using the procedure in Option B.
V
IN
VIN
20 PA
10 kꢀ
2.48 V
UVLO/EN
TIMER AND
GATE
R3
R4
LOGIC CONTROL
2.46 V
GND
OVLO
21 PA
图 23. UVLO = POREN
10.2.1.2.6.4 Option D
The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
For this design example, option B was used and the following options were targeted: VUVH = 38 V, VUVL = 35 V,
VOVH = 65 V, and VOVL = 63 V. The VUVH and VOVL were chosen to be 5% below or above the input voltage range
of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using
the following equations:
V
UVH - VUVL
38V - 35V
R1=
=
= 150kW
20µA
2.48V ´R1
- 2.48V
20µA
2.48V ´150kW
35V - 2.48V
R2 =
=
) (
= 11.44kW
V
(
)
UVL
V
OVH - VOVL
65V - 63V
R3 =
R4 =
=
= 95.24kW
21µA
21µA
2.46V ´R3
2.46V ´95.24kW
65V - 2.46V
=
) (
= 3.75kW
V
(
- 2.46V
)
OVH
(40)
Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74
kΩ.
10.2.1.2.7 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of
the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the
UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
48
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When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is
disabled allowing PGD to rise to VPGD through the pullup resistor, RPG, as shown in 图 25. The pullup voltage
(VPGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a
convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on PGD during power-
up. If a delay is required at PGD, suggested circuits are shown in 图 26. In 图 26(A), capacitor CPG adds delay to
the rising edge, but not to the falling edge. In 图 26(B), the rising edge is delayed by RPG1 + RPG2 and CPG, while
the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2 (图 26(C)) allows for
equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
V
PGD
Q1
V
OUT
OUT
GATE
R
PG
R5
PGD
2.46 V
FB
Power Good
R6
GND
20 PA
PGD
UV
OV
GND
图 24. Programming the PGD Threshold
图 25. Power Good Output
V
V
PGD
V
PGD
PGD
R
PG1
R
R
PG1
PG1
PGD
PGD
PGD
Power
Good
Power
Good
Power
Good
R
PG2
R
PG2
C
C
PG
C
PG
PG
GND
A) Delay at Rising Edge Only
GND
GND
B) Long Delay at Rising Edge,
Short Delay at Falling Edge
C) Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
图 26. Adding Delay to the Power Good Output Pin
TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted
under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are
computed using the following equations:
V
PGDH - VPGDL
38V - 35V
R5 =
=
= 150kW
20µA
20µA
(41)
(42)
2.46V ´R5
- 2.46V
2.46V ´150kW
38V - 2.46V
R6 =
=
) (
= 10.38kW
V
(
)
PGDH
Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.
10.2.1.2.8 Input and Output Protection
Proper operation of the LM5066I hot swap circuit requires a voltage clamping element present on the supply side
of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in 图 27. The TVS is
necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current.
This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET
shutts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage to
under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice.
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If the load powered by the LM5066I hot swap circuit has inductive characteristics, a Schottky diode is required
across the LM5066I’s output, along with some load capacitance. The capacitance and the diode are necessary to
limit the negative excursion at the OUT pin when the load current is shut off.
R
SNS
V
IN
Q1
V
OUT
+48 V
LIVE
POWER
SOURCE
OUT
C
VIN_K SENSE
D
1
VIN
L
Inductive
Load
LM5066I
Z
1
AGND GND
GND
PLUG-IN BOARD
图 27. Output Diode Required for Inductive Loads
10.2.1.2.9 Final Schematic and Component Values
图 19 shows the schematic used to implement the requirements described in the previous section. In addition,
表 52 provides the final component values that were used to meet the design requirements for a 48-V, 10-A
hotswap design. The application curves in the next section are based on these component values.
表 52. Final Component Values (48-V, 10-A Design)
COMPONENT
VALUE
2 mΩ
RSNS
R1
150 kΩ
R2
11.5 kΩ
R3
95.3 kΩ
R4
3.74 kΩ
R5
150 kΩ
R6
10.5 kΩ
RPWR
28.2 kΩ
Q1
PSMN4R8-100BSEJ
MMBT3904
B380-13-F
5.0SMDJ60A
100 nF
Q2
D1
Z1
CTIMER
Optional dv/dt circuit
DNP
50
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10.2.1.3 Application Curves
VIN = 48 V
图 28. Insertion Delay
图 29. Start-Up
VIN = 40 V
VIN = 60 V
图 30. Start-Up
图 31. Start-Up
图 32. Start-Up into Short Circuit
图 33. Under-Voltage
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图 34. Over-Voltage
图 35. Gradual Over-Current
图 36. Loadstep
图 37. Hotshort on Output (Zoomed Out)
图 38. Hotshort on Output (Zoomed In)
图 39. Auto-retry
52
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10.2.2 48-V, 20-A PMBus Hotswap Design
This section describes the design procedure for a 48-V, 20-A PMBUS hotswap design.
Q
2
R
VIN
SNS
VOUT
Q
1
D
C
OUT
1
Z
1
C
IN
Only required when
using dv/dt start-up
R
5
SENSE
VIN_K
GATE OUT
DIODE
FB
R
VDD
D
2
1
R
R
3
4
VIN
R
6
UVLO/EN
OVLO
100 k
1k
PGD
C
dv/dt
VDD
LM5066I
ADR2
ADR1
ADR0
R
2
AGND
GND
Q
3
N/C
N/C
CL
RETRY
SMBA
SDAO
SDAI
SMBus
Interface
Auxiliary ADC Input
(0 to 2.97 V)
VAUX
SCL
PWR
VDD
VREF
TIMER
R
PWR
C
TIMER
1 PF
1 PF
图 40. Typical Application Schematic, LM5066I
10.2.2.1 Design Requirements
表 53. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
40 to 60 V
20 A
Maximum load current
Maximum output capacitance of the hotswap
Maximum ambient temperature
MOSFET RθCA (function of layout)
Pass hot-short on output?
440 µF
85°C
30°C/W
Yes
Pass a start into short?
Yes
Is the load off until PG asserted?
Can a hot board be plugged back in?
Yes
Yes
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Selecting the Sense Resistor and CL Setting
LM5066I can be used with a VCL of 26 or 50 mV. In general using the 26-mV threshold results in a lower RSNS
and lower I2R losses. This option is selected for this design by connecting the CL pin directly to VDD. TI
recommends to target a current limit that is at least 10% above the maximum load current to account for the
tolerance of the LM5066I current limit. Targeting a current limit of 22 A, the sense resistor can be computed as
follows:
ILIM
26mV
RSNS,CLC
=
=
=1.18mΩ
VCL
22A
(43)
For this application, a 1-mΩ resistor can be used for a 26-A current limit.
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10.2.2.2.2 Selecting the Hotswap FETs
For this design, the PSMN4R8-100BSE was selected for its low RDSON and superior SOA. After selecting the
MOSFET, the maximum steady-state case temperature can be computed as follows:
TC,MAX = TA,MAX + RqCA ´IL2OAD,MAX ´RDSON(TJ)
(44)
Note that the RDSON is a strong function of junction temperature, which for most D2PACK MOSFETs are very
close to the case temperature. A few iterations of the previous equations may be necessary to converge on the
final RDSON and TC,MAX value. According to the PSMN4R8-100BSE data sheet, its RDSON doubles at 110°C. 公
式 45 uses this RDSON value to compute the TC,MAX. Note that the computed TC,MAX is already above the absolute
maximum of the FET.
C
TC,MAX = 85°C + 30°
´ 20A 2 ´ 2´ 4.8mW = 200°C
(
) (
)
W
(45)
This suggests that two FETs should be used for the design. During steady-state operation, the MOSFETs are
fully enhanced and share current evenly. Thus, assuming that each FET carries half of the current, the TC,MAX
can be computed with 公式 46. Now TC,MAX is 114°C, which is reasonable.
2
C
20A
æ
ö
TC,MAX = 85°C + 30°
´
´ 2´ 4.8mW = 114°C
(
)
ç
÷
W
2
è
ø
(46)
10.2.2.2.3 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the
LM5066I is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across
the sense resistor (VSNS) to a very-low value. VSNS can be computed as shown in 公式 47.
PLIM ´RSNS
VSNS
=
VDS
(47)
To avoid significant degradation of the power limiting, TI does not recommend a VSNS below 4 mV. Based on this
requirement, the minimum allowed power limit can be computed as follows:
V
SNS,MIN ´ V
4mV ´ 60V
1mW
IN,MAX
P
=
=
= 240W
LIM,MIN
RSNS
(48)
In most applications, the power limit can be set to PLIM,MIN as shown. Here RSNS and RPWR are in ohms and PLIM
is in watts.
P
LIM ´RSNS - 0.043
240´0.001- 0.043
7´10-6
RPWR
=
=
= 28143W
7´10-6
(49)
The closest available resistor should be selected. In this case a 28.2-kΩ resistor was chosen.
10.2.2.2.4 Set Fault Timer
The maximum start time can be computed to 3.37 ms as shown in 公式 50.
2
IN,MAX
2
é
ê
ë
ù
é
ù
ú
û
V
COUT
2
P
2
ILIM
440mF (60V)
240W
(26A)
LIM ú
tstart,max
=
´
+
=
´
+
= 3.37ms
ê
ê
ë
2 ú
P
2
240W
ê
ú
LIM
û
(50)
Note this start-time is based on typical current limit and power limit values. To ensure that the timer never times
out during start-up, TI recommends to set the fault time (TFLT) to be 1.5× tstart,max or 5.1 ms. This accounts for the
variation in power limit, timer current, and timer capacitance. Thus, CTIMER can be computed as follows:
t
ƒlt ´itimer
5.1ms´75mA
CTIMER
=
=
= 98.07nF
vtimer
3.9V
(51)
The next largest available CTIMER is chosen as 100 nF. After CTIMER is chosen, the actual programmed fault time
can be computed as follows:
C
TIMER ´ vtimer
100nF´3.9V
75mA
tƒlt
=
=
= 5.2ms
itimer
(52)
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10.2.2.2.5 Check MOSFET SOA
After the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all
test conditions. During a hot-short, the circuit breaker trips and the LM5066I restarts into power limit until the
timer runs out. In the worst case, the MOSFET’s VDS equals VIN,MAX, IDS equals PLIM / VIN,MAX, and the stress
event lasts for tflt. For this design example, the MOSFET has 60 V, 4 A across it for 5.2 ms.
When the hotswap is in power limit and the FETs are operating in saturation region (VGS close to threshold
voltage), the designer cannot assume that the FETs will share. Even a small VT mismatch causes a large
difference in the current carried by the two MOSFETs. Thus, the SOA checking should be done assuming that all
of the current is flowing through a single FET.
Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for
10 ms. The SOA for 5.2 ms can be extrapolated by approximating SOA versus time as a power function as
shown in the following equations:
ISOA t = a´ tm
( )
30A
6A
æ
ö
ln
ç
÷
ln I
(
t
/ I
t
SOA ( 1)
( )
)
SOA 2
è
ø
m =
=
= -0.7
ln t / t
(
1ms
10ms
æ
ö
)
1
2
ln
ç
÷
è
ø
ISOA
t
( 1) =
30A
0.7
( )
a =
= 30A ´ ms
-0.7
t1m
1ms
( )
ISOA 5.2ms, 25°C = 30A ´(ms)0.7 ´(5.2ms)-0.7 = 9.46A
(
)
(53)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using 公式 54.
TJ,ABSMAX - TC,MAX
175°C -114°C
175°C - 25°C
ISOA 5.2ms,T
= I
5.2ms,25°C ´
= 9.46A ´
= 3.85A
(
)
(
)
C,MAX
SOA
TJ,ABSMAX - 25°C
(54)
Based on this calculation, the MOSFET can handle 3.85 A, 60 V for 5.2 ms at elevated case temperature, but it
is required to handle 4 A during a hot-short. In addition, there is tolerance on the power limit and timer, so using
these settings would not produce a robust hotswap design.
10.2.2.2.6 Switching to dv/dt-Based Start-Up
For designs with large load currents and output capacitances, using a power-limit-based start-up can be
impractical. Fundamentally, increasing load currents reduces the sense resistor, which increases the minimum
power limit. Using a larger output capacitor results in a longer start-up time and requires a longer timer. Thus, a
longer timer and a larger power limit setting is required, which places more stress on the MOSFET during a hot-
short or a start into short. Eventually, there will be no FETs that can support such a requirement.
To avoid this problem, a dv/dt limiting capacitor (Cdv/dt) can be used to limit the slew rate of the gate and the
output voltage. The inrush current can be set arbitrarily small by reducing the slew rate of VOUT. In addition, the
power limit is set to satisfy the minimum power limit requirement and to keep the timer from running during start-
up (make PLIM / VINMAX > IINR). Because the timer does not run during start-up, it can be made arbitrarily small to
reduce the stress that the MOSFET experiences during a start into short or a hot-short.
The D2 prevents the charge of Cdv/dt from interfering with the power limit loop during a hot-short event and Q3
discharges Cdv/dt when the hotswap gate comes down.
10.2.2.2.7 Choosing the VOUT Slew Rate
The inrush current should be kept low enough to keep the MOSFET within its SOA during start-up. Note that the
total energy dissipated in the MOSFET during start-up is constant regardless of the inrush time. Thus, stretching
it out over a longer time always reduces the stress on the MOSFET as long as the load is off during start-up.
When choosing a target slew rate, one should pick a reasonable number, check the SOA, and reduce the slew
rate if necessary. Using 4 V/ms as a starting point, the inrush current can be computed as follows:
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dVOUT
dt
4V
ms
I
= COUT
´
= 440µF´
= 1.76A
INR
(55)
Assuming a maximum input voltage of 60 V, it takes 15 ms to start-up. Note that the power dissipation of the
FET starts at VIN,MAX × IINR and reduce to 0 as the VDS of the MOSFET is reduced. Note that the SOA curves
assume the same power dissipation for a given time. A conservative approach is to assume an equivalent power
profile where PFET = VIN,MAX × IINR for t = tstart-up / 2. In this instance, the SOA can be checked by looking at a 60-
V, 1.76-A, 7.5-ms pulse. Using the same technique as section Check MOSFET SOA, the MOSFET SOA can be
estimated as follows:
ISOA 7.5ms = 30A ´(ms)0.7 ´(7.5ms)-0.7 = 7.32A
(
)
(56)
This value has to also be derated for temperature. For this calculation, it is assumed that TC can equal TC,MAX
when the board is plugged in. This would only occur if a hot board is unplugged, then plugged back in before it
cools off. This is worst case and for many applications, the TA,MAX can be used for this derating.
TJ,ABSMAX - TC,MAX
175°C -114°C
175°C - 25°C
ISOA 7.5ms,T
(
= I
7.5ms,25°C ´
( )
= 7.32A ´
= 2.98A
)
C,MAX
SOA
TJ,ABSMAX - 25°C
(57)
This calculation shows that the MOSFET stays well-within its SOA during a start-up if the slew rate is 4 V/ms.
Note that if the load is off during start-up, the total energy dissipated in the FET is constant regardless of the
slew rate. Thus, a lower slew rate always places less stress on the FET. To ensure that the slew rate is at most
4 V/ms, the Cdv/dt should be chosen as follows:
ISOURCE,MAX
40µA
cdv/dt
=
=
= 10nF
4V / ms
4V / ms
(58)
Next, the typical slew rate and start time can be computed to be 2 V/ms as shown in 公式 59, making the typical
start time 30 ms.
ISOURCE
20µA
10nF
VOUT,dv/dt
=
=
= 2V / ms
c
dv / dt
(59)
10.2.2.2.8 Select Power Limit and Fault Timer
When picking the power limit it needs to meet two requirements:
•
•
Power limit is large enough to avoid operating with VSNS < 4 mV
Power limit is large enough to ensure that the timer does not run during start up. Picking a power limit such
that it is 2× of IINR,MAX × VIN,MAX is good practice.
Thus, the minimum allowed power limit can be computed as follows:
V
SNS,MIN ´ V
æ
ç
è
ö
÷
P
= max
IN,MAX ,2´ VIN,MAX ´I
= max 240W,211.2W = 240W
(
)
LIM,MIN
INR,MAX ø
RSNS
(60)
(61)
Next, the power limit is set to PLIM,MIN using 公式 61. Here RSNS and RPWR are in ohms and PLIM is in watts.
P
LIM ´RSNS - 0.043
240´0.001- 0.043
RPWR
=
=
= 28143W
-6
-6
7´10
7´10
The closest available resistor should be selected. In this case, a 28.2-kΩ resistor was chosen.
Next, a fault timer value should be selected. In general, the timer value should be decreased until there is
enough margin between available SOA and the power pulse the FET experiences during a hot-short. For this
design, a 10-nF CTIMER was chosen corresponding to a 520 µs. The available SOA is extrapolated using the
method described earlier.
56
版权 © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
ISOA t = a´ tm
( )
100A
30A
æ
ö
ln
ç
÷
ln I
(
t
/ I
t
SOA ( 1)
( )
)
SOA 2
è
ø
m =
=
= -0.52
ln t / t
(
0.1ms
1ms
æ
ö
)
1
2
ln
ç
÷
è
ø
ISOA
t
( 2 ) =
30A
0.52
( )
a =
= 30A ´ ms
-0.52
tm2
1ms
( )
ISOA 0.52ms, 25°C = 30A ´(ms)0.52 ´(0.52ms)-0.52 = 42.3A
(
)
(62)
(63)
Next, the available SOA is derated for temperature:
175°C -114°C
ISOA 0.52ms,T
= 42.3A ´
= 17.17A
(
)
C,MAX
175°C - 25°C
Note that only 4 A was required, while the FET can support 17.17 A. This confirms that the design is robust and
has plenty of margin.
10.2.2.2.9 Chose Input and Output Protection and Set Undervoltage, Overvoltage, and Power Good Thresholds
This is identical to the previous design. Refer to Set UVLO and OVLO Thresholds, Power Good Pin, and Input
and Output Protection for these settings.
10.2.2.2.10 Final Schematic and Component Values
图 40 shows the schematic used to implement the requirements described in the 48-V, 20-A PMBus Hotswap
Design section. In addition, 表 54 provides the final component values used to meet the design requirements for
a 48-V, 20-A hotswap design. The application curves in the next section are based on these components.
表 54. Final Component Values (48-V, 20-A Design)
Component
Value
1 mΩ
RSNS
R1
150 kΩ
R2
11.5 kΩ
R3
95.3 kΩ
R4
3.74 kΩ
R5
150 kΩ
R6
10.5 kΩ
RPWR
28.2 kΩ
Q1
2x (PSMN4R8-100BSEJ)
MMBT3904
B380-13-F
5.0SMDJ60A
10 nF
Q2
D1
Z1
CTIMER
Optional dv/dt circuit
Yes
D2
Q3
1N4148W-7-F
MMBT5401LT1G
10 nF
Cdvdt
版权 © 2014, Texas Instruments Incorporated
57
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
10.2.2.3 Application Curves
VIN = 48 V
VIN = 40 V
图 41. Start-Up
图 42. Start-Up
VIN = 60 V
图 43. Start-Up
图 44. Start-Up into Short
图 45. Under-Voltage
图 46. Over-Voltage
58
版权 © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
图 47. Gradual Overcurrent
图 48. Loadstep
图 49. Hot Short on Vout (Zoomed Out)
图 50. Hot Short on Vout (Zoomed In)
11 Power Supply Recommendations
In general, the LM5066I behavior is more reliable if it is supplied from a very regulated power supply. However,
high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is
expected in the end system, TI recommends to place a 1-µF ceramic capacitor to ground close to the source of
the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be
necessary to avoid nuisance trips.
版权 © 2014, Texas Instruments Incorporated
59
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
The following guidelines should be followed when designing the PC board for the LM5066I:
1. Place the LM5066I close to the board’s input connector to minimize trace inductance from the connector to
the MOSFET.
2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066I to help minimize voltage
transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN is just
lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage can easily
occur when the load current is shut off. A small capacitor may be sufficient for low current sense applications
(I < 2 A). TI recommends to test the VIN input voltage transient performance of the circuit by current limiting
or shorting the load and measuring the peak input voltage transient.
3. Place a 1-µF ceramic capacitor as close as possible to VREF pin.
4. Place a 1-µF ceramic capacitor as close as possible to VDD pin.
5. The sense resistor (RSNS) should be placed close to the LM5066I. A trace should connect the VIN pad and
Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin
techniques as shown in 图 52.
6. The high current path from the board’s input to the load (through Q1), and the return path, should be parallel
and close to each other to minimize loop inductance.
7. The AGND and GND connections should be connected at the pins of the device. The ground connections for
the various components around the LM5066I should be connected directly to each other, and to the
LM5066I’s GND and AGND pin connection, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
8. Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and
turn-off.
9. The board’s edge connector can be designed such that the LM5066I detects through the UVLO/EN pin that
the board is being removed, and responds by turning off the load before the supply voltage is disconnected.
For example, in 图 51, the voltage at the UVLO/EN pin goes to ground before VIN is removed from the
LM5066I as a result of the shorter edge connector pin. When the board is inserted into the edge connector,
the system voltage is applied to the LM5066I’s VIN pin before the UVLO voltage is taken high, thereby
allowing the LM5066I to turn on the output in a controlled fashion.
12.2 Layout Example
GND
To
Load
V
IN
R
S
Z1/C1
PGD
PWR
TIMER
RETRY
FB
OUT
GATE
SENSE
VIN_K
VIN
UVLO/EN
OVLO
AGND
GND
SDAI
SDAO
SCL
R1
R2
R3
CL
VDD
ADR0
ADR1
ADR2
VAUX
DIODE
VREF
SMBA
LM5066I
MMBT3904
CARD EDGE
CONNECTOR
PLUG-IN CARD
图 51. Recommended Board Connector Design
60
版权 © 2014, Texas Instruments Incorporated
LM5066I
www.ti.com.cn
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
Layout Example (接下页)
HIGH CURRENT PATH
TO DRAIN OF
MOSFET Q
FROM SYSTEM
INPUT VOLTAGE
SENSE
RESISTOR
1
R
S
VIN
VIN_K
SENSE
图 52. Sense Resistor Connections
版权 © 2014, Texas Instruments Incorporated
61
LM5066I
ZHCSCT1A –APRIL 2014–REVISED AUGUST 2014
www.ti.com.cn
13 器件和文档支持
13.1 商标
PMBus is a trademark of SMIF, Inc.
13.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
62
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5066IPMHE/NOPB
LM5066IPMHX/NOPB
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LM5066I
LM5066I
2500 RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5066IPMHE/NOPB HTSSOP PWP
LM5066IPMHX/NOPB HTSSOP PWP
28
28
250
178.0
330.0
16.4
16.4
6.8
6.8
10.2
10.2
1.6
1.6
8.0
8.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5066IPMHE/NOPB
LM5066IPMHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
28
28
250
208.0
356.0
191.0
356.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0028A
PowerPADTM - 1.1 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
26X 0.65
28
1
9.8
9.6
NOTE 3
2X
8.45
14
B
15
0.30
0.19
28X
1.1 MAX
4.5
4.3
0.1
C A
B
NOTE 4
0.20
0.09
TYP
SEE DETAIL A
3.15
2.75
0.25
GAGE PLANE
5.65
5.25
0.10
0.02
THERMAL
PAD
0 - 8
0.7
0.5
DETAIL A
(1)
TYPICAL
4214870/A 10/2014
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-153, variation AET.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028A
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
(3)
SOLDER
MASK
OPENING
SOLDER MASK
DEFINED PAD
28X (1.5)
28X (1.3)
28X (0.45)
28X (0.45)
1
28
26X
(0.65)
SYMM
(5.5)
(9.7)
SOLDER
MASK
OPENING
(1.3) TYP
14
15
(
0.2) TYP
(1.3)
SEE DETAILS
(0.65) TYP
(0.9) TYP
(6.1)
VIA
SYMM
METAL COVERED
BY SOLDER MASK
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
(5.8)
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214870/A 10/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028A
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.127 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
28X (1.5)
28X (1.3)
28X (0.45)
1
28
26X (0.65)
28X (0.45)
(5.5)
SYMM
BASED ON
0.127 THICK
STENCIL
14
15
SEE TABLE FOR
DIFFERENT OPENINGS
SYMM
(6.1)
FOR OTHER STENCIL
THICKNESSES
(5.8)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.55 X 6.37
3.0 X 5.5 (SHOWN)
2.88 X 5.16
0.127
0.152
0.178
2.66 X 4.77
4214870/A 10/2014
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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