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LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

适用于升压和 SEPIC 稳压器的 LM5022 60V 低侧控制器

1 特性

3 说明

1

•

内部 60V 启动稳压器

LM5022 器件是一款适用于升压和 SEPIC 稳压器的高

压、低侧、N 沟道 MOSFET 控制器。该器件包含实

施单端主要拓扑所需的全部特性。输出电压调节基于

电流模式控制，这不仅简化了环路补偿的设计，同时还

能够提供固有输入电压前馈。LM5022 包含一个启动稳

压器，该稳压器能够在 6V 至 60V 的宽输入范围内工

作。PWM 控制器专为高速性能而设计，包含一个振荡

器，振荡器频率范围高达 2.2MHz，总传播延迟低于

100ns。其他功能还包括误差放大器、精密基准、线

路欠压锁定、逐周期电流限制、斜率补偿、软启动、外

部同步功能和热关断。LM5022 采用 10 引脚 VSSOP

封装。

•

峰值电流为 1A 的金属氧化物半导体场效应晶体管

(MOSFET) 栅极驱动器

•

V_IN范围：6V 至 60V（启动后，最低可以在 3V 下

工作）

•

占空比限值 90%

可编程 UVLO 磁滞

逐周期电流限制

外部器件可同步（交流耦合）

单个电阻振荡器频率设置

斜率补偿

可调节软启动

10 引脚超薄小外形尺寸 (VSSOP) 封装

器件信息⁽¹⁾

器件型号

LM5022

封装

封装尺寸（标称值）

2 应用

VSSOP (10)

3.00mm × 3.00mm

•

升压转换器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

SEPIC 转换器

典型应用

V_IN

L1

D1

V_O

C_IN

C_O

Q1

R_S1

VIN

RT

OUT

R_T

R_UV2

R_SNS

CS

C_CS

C_F

UVLO

SS

GND

C_SS

R_UV1

VCC

R_FB2

COMP

R1

FB

C2

R_FB1

C1

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVS480

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 12

8

9

Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application .................................................. 14

Power Supply Recommendations...................... 28

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Examples................................................... 30

11 器件和文档支持 ..................................................... 32

11.1 器件支持................................................................ 32

11.2 文档支持................................................................ 32

11.3 接收文档更新通知 ................................................. 32

11.4 社区资源................................................................ 32

11.5 商标....................................................................... 32

11.6 静电放电警告......................................................... 32

11.7 Glossary................................................................ 32

12 机械、封装和可订购信息....................................... 32

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision H (December 2016) to Revision I

Page

•

Changed 1 To: C2 in Equation 55........................................................................................................................................ 24

Changes from Revision G (December 2013) to Revision H

Page

•

已添加添加了 ESD 额定值表、特性说明部分、器件功能模式、应用和实施部分、电源建议部分、布局部分、器

件和文档支持部分，以及机械、封装和可订购信息部分 ....................................................................................................... 1

Deleted soldering temperature (215°C Vapor phase maximum and 220°C Infrared maximum) ........................................... 4

Changed Junction to Ambient Thermal Resistance, R_θJA, value From: 200 To: 161.5.......................................................... 4

•

Changed slope compensation amplitude, V_SLOPE, values From: 80 To: 83 (Minimum), From: 105 To: 110 (Typical),

and From: 130 To: 137 (Maximum)........................................................................................................................................ 5

Changes from Revision F (March 2013) to Revision G

Page

•

Changed timing resistor equation. Incorrect change when converting to TI format............................................................. 12

Changes from Revision E (March 2013) to Revision F

Page

•

已更改将美国国家半导体数据表的布局更改为 TI 格式 .......................................................................................................... 1

2

LM5022

www.ti.com.cn

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

5 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

VIN

FB

1

10

9

SS

2

3

4

5

RT/SYNC

CS

COMP

VCC

OUT

8

7

UVLO

GND

6

Not to scale

Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

VIN

I

Source input voltage: Input to the startup regulator. Operates from 6 V to 60 V.

Feedback pin: Inverting input to the internal voltage error amplifier. The noninverting input of the error

amplifier connects to a 1.25-V reference.

2

3

FB

Error amplifier output and PWM comparator input: The control loop compensation components connect

between this pin and the FB pin.

COMP

I/O

O

Output of the internal, high-voltage linear regulator: This pin must be bypassed to the GND pin with a

ceramic capacitor.

4

5

VCC

OUT

Output of MOSFET gate driver: Connect this pin to the gate of the external MOSFET. The gate driver has

a 1-A peak current capability.

O

—

I

6

7

8

GND

UVLO

CS

System ground

Input undervoltage lockout: Set the start-up and shutdown levels by connecting this pin to the input voltage

through a resistor divider. A 20-µA current source provides hysteresis.

I

Current sense input: Input for the switch current used for current mode control and for current limiting.

Oscillator frequency adjust pin and synchronization input: An external resistor connected from this pin to

GND sets the oscillator frequency. This pin can also accept an AC-coupled input for synchronization from

an external clock.

9

RT/SYNC

SS

I

Soft-start pin: An external capacitor placed from this pin to ground is charged by a 10-µA current source,

creating a ramp voltage to control the regulator start-up.

10

3

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

65

UNIT

VIN to GND

V

VCC to GND

16

RT/SYNC to GND

OUT to GND

5.5

–1.5 for < 100 ns

–0.3

All other pins to GND

Power dissipation

7

Internally limited

150

(3)

Junction temperature, T_J

°C

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage

6

7.5

60

14

V

External voltage at V_CC

Junction temperature

–40

125

°C

(1) Device thermal limitations may limit usable range

6.4 Thermal Information

LM5022

THERMAL METRIC⁽¹⁾

DGS (VSSOP)

UNIT

10 PINS

161.5

56

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

81.3

5.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

80

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4

LM5022

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ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

6.5 Electrical Characteristics

Typical limits apply for T_J=25°C and are provided for reference purposes only; minimum and maximum limits apply over the

junction temperature (T_J) range of –40°C to 125°C. V_IN= 24 V and R_T= 27.4 kΩ (unless otherwise noted).⁽¹⁾

PARAMETER

SYSTEM PARAMETERS

V_FBFB pin voltage

STARTUP REGULATOR

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.225

1.25 1.275

V

10 V ≤ V_IN≤ 60 V, I_CC= 1 mA

6.6

5

7

7.4

4

VCC

VCC regulation⁽²⁾

6 V ≤ V_IN< 10V,

VCC Pin Open Circuit

OUT Pin Capacitance = 0,

VCC = 10 V

VCC = 0 V⁽²⁾⁽³⁾

I_CC

Supply current

3.5

35

mA

mV

I_CC-LIM

V_IN- VCC

VCC current limit

15

I_CC= 0 mA, ƒ_SW< 200 kHz,

6 V ≤ V_IN≤ 8.5 V

Dropout voltage across bypass switch

200

V_BYP-HI

Bypass switch turnoff threshold

V_INincreasing

V_INDecreasing

V_IN= 6 V

8.7

260

58

V

V_BYP-HYS

Bypass switch threshold hysteresis

mV

VCC pin output impedance

0 mA ≤ ICC ≤ 5 mA

Z_VCC

V_IN= 8 V

53

Ω

V_IN= 24 V

1.6

5

VCC_-HI

VCC_-HYS

I_VIN

VCC pin UVLO rising threshold

VCC pin UVLO falling hysteresis

Startup regulator leakage

Shutdown current

V

300

150

350

mV

µA

V_IN= 60 V

500

450

I_IN-SD

V_UVLO= 0 V, VCC = Open Circuit

ERROR AMPLIFIER

GBW

A_DC

Gain bandwidth

4

75

17

MHz

dB

DC gain

I_COMP

UVLO

V_SD

COMP pin current sink capability

V_FB= 1.5 V, V_COMP= 1 V

5

mA

Shutdown threshold

1.22

16

1.25

20

1.28

24

V

I_SD-HYS

Shutdown hysteresis current source

µA

CURRENT LIMIT

CS steps from 0 V to 0.6 V, OUT

transitions to 90% of VCC

t_LIM-DLY

Delay from ILIM to output

30

ns

V_CS

Current limit threshold voltage

Leading edge blanking time

CS pin sink impedance

0.45

0.5

65

40

0.55

75

V

ns

Ω

t_BLK

R_CS

Blanking active

SOFT START

I_SS

Soft-start current source

Soft start to COMP offset

7

10

13

µA

V

V_SS-OFF

0.35

0.55

0.75

(1) All Minimum and Maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control. The junction temperature (T_Jin °C) is calculated from the ambient temperature (T_Ain °C) and power

dissipation (P_Din Watts) as follows: T_J= T_A+ (P_D× R_θJA) where R_θJA(in °C/W) is the package thermal impedance provided in Thermal

Information.

(2) VCC provides bias for the internal gate drive and control circuits.

(3) Device thermal limitations may limit usable range.

5

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

Typical limits apply for T_J=25°C and are provided for reference purposes only; minimum and maximum limits apply over the

junction temperature (T_J) range of –40°C to 125°C. V_IN= 24 V and R_T= 27.4 kΩ (unless otherwise noted).⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OSCILLATOR

f_SW

RT to GND = 84.5 kΩ

170⁽⁴⁾

525

200

600

990

230

675

kHz

V

RT to GND = 27.4 kΩ

See⁽⁴⁾

RT to GND = 16.2 kΩ

865

1115

3.8

V_SYNC-HI

Synchronization rising threshold

PWM COMPARATOR

V_COMP= 2 V, CS stepped

from 0 V to 0.4 V

t_COMP-DLY

Delay from COMP to OUT transition

25

ns

D_MIN

Minimum duty cycle

V_COMP= 0 V

0%

D_MAX

Maximum duty cycle

90%

95%

0.33

5.2

A_PWM

COMP to PWM comparator gain

COMP pin open circuit voltage

COMP pin short circuit current

V/V

V

V_COMP-OC

I_COMP-SC

V_FB= 0 V

4.3

0.6

6.1

1.5

V_COMP= 0 V, V_FB= 1.5 V

1.1

mA

SLOPE COMPENSATION

V_SLOPE

Slope compensation amplitude

83

110

137

mV

MOSFET DRIVER

V_SAT-HI

V_SAT-LO

t_RISE

Output high saturation voltage (VCC – VOUT)

I_OUT= 50 mA

0.25

18

0.75

V

Output low saturation voltage (VOUT)

OUT pin rise time

I_OUT= 100 mA

OUT Pin load = 1 nF

ns

t_FALL

OUT pin fall time

15

THERMAL CHARACTERISTICS

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

165

25

°C

T_SD-HYS

(4) Specification applies to the oscillator frequency.

6

LM5022

www.ti.com.cn

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

6.6 Typical Characteristics

V_O= 40 V

V_IN= 24 V

Figure 1. Efficiency, Example Circuit BOM

Figure 2. V_FBvs Temperature

T_A= 25°C

Figure 3. V_FBvs V_IN

Figure 4. V_CCvs V_IN

T_A= 25°C

R_T= 16.2 KΩ

Figure 5. Maximum Duty Cycle vs ƒ_SW

Figure 6. ƒ_SWvs Temperature

7

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

www.ti.com.cn

Typical Characteristics (continued)

T_A= 25°C

Figure 7. R_Tvs ƒ_SW

Figure 8. SS vs Temperature

Figure 9. OUT Pin T_RISEvs Gate Capacitance

Figure 10. OUT Pin T_FALLvs Gate Capacitance

8

LM5022

www.ti.com.cn

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

7 Detailed Description

7.1 Overview

The LM5022 is a low-side, N-channel MOSFET controller that contains all of the features required to implement

single-ended power converter topologies. The LM5022 includes a high-voltage start-up regulator that operates

over a wide input range of 6 V to 60 V. The PWM controller is designed for high-speed capability including an

oscillator frequency range up to 2.2 MHz and total propagation delays less than 100 ns. Additional features

include an error amplifier, precision reference, input undervoltage lockout, cycle-by-cycle current limit, slope

compensation, soft start, oscillator sync capability, and thermal shutdown.

The LM5022 is designed for current-mode control power converters that require a single drive output, such as

boost and SEPIC topologies. The LM5022 provides all of the advantages of current-mode control including input

voltage feedforward, cycle-by-cycle current limiting, and simplified loop compensation.

7.2 Functional Block Diagram

BYPASS

SWITCH

(6 V to 8.7 V)

VCC

VIN

7V SERIES

REGULATOR

5 V

1.25 V

REFERENCE

ENABLE

+

-

UVLO

LOGIC

1.25 V

UVLO

HYSTERESIS

(20 µA)

CLK

RT/SYNC

OSC

DRIVER

45 µA

Max

Duty

Limit

S

R

Q

OUT

GND

0

5 V

5 k

100 kΩ

1.4 V

COMP

FB

1.25 V

PWM

+

-

LOGIC

SS

10 µA

50 kΩ

SS

CS

+

-

0.5 V

2 kΩ

CLK + LEB

9

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

www.ti.com.cn

7.3 Feature Description

7.3.1 High-Voltage Start-Up Regulator

The LM5022 contains an internal high-voltage start-up regulator that allows the VIN pin to be connected directly

to line voltages as high as 60 V. The regulator output is internally current limited to 35 mA (typical). When power

is applied, the regulator is enabled and sources current into an external capacitor, C_F, connected to the VCC pin.

The recommended capacitance range for C_Fis 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the

rising threshold of 5 V, the controller output is enabled. The controller remains enabled until VCC falls below 4.7

V. In applications using a transformer, an auxiliary winding can be connected through a diode to the VCC pin.

This winding must raise the VCC pin voltage to above 7.5 V to shut off the internal start-up regulator. Powering

VCC from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the

controller. The capacitance of C_Fmust be high enough that it maintains the VCC voltage greater than the VCC

UVLO falling threshold (4.7 V) during the initial start-up. During a fault condition when the converter auxiliary

winding is inactive, external current draw on the VCC line must be limited such that the power dissipated in the

start-up regulator does not exceed the maximum power dissipation capability of the controller.

An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the

VCC and the VIN pins together and feeding the external bias voltage (7.5 V to 14 V) to the two pins.

7.3.2 Input Undervoltage Detector

The LM5022 contains an input undervoltage lockout (UVLO) circuit. UVLO is programmed by connecting the

UVLO pin to the center point of an external voltage divider from VIN to GND. The resistor divider must be

designed such that the voltage at the UVLO pin is greater than 1.25 V when V_INis in the desired operating

range. If the undervoltage threshold is not met, all functions of the controller are disabled and the controller

remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20-µA current source

that is switched on or off into the impedance of the setpoint divider. When the UVLO threshold is exceeded, the

current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below

the 1.25-V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin

can also be used to implement a remote enable or disable function. If an external transistor pulls the UVLO pin

below the 1.25-V threshold, the converter is disabled. This external shutdown method is shown in Figure 11.

V_IN

VIN

R_UV2

LM5022

UVLO

ON/OFF

R_UV1

2N7000 or

Equivalent

GND

Figure 11. Enable or Disable Using UVLO

10

LM5022

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ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

Feature Description (continued)

7.3.3 Error Amplifier

An internal high gain error amplifier is provided within the LM5022. The amplifier’s noninverting input is internally

set to a fixed reference voltage of 1.25 V. The inverting input is connected to the FB pin. In non-isolated

applications such as the boost converter the output voltage, V_O, is connected to the FB pin through a resistor

divider. The control loop compensation components are connected between the COMP and FB pins. For most

isolated applications, the error amplifier function is implemented on the secondary side of the converter and the

internal error amplifier is not used. The internal error amplifier is configured as an open-drain output and can be

disabled by connecting the FB pin to ground. An internal 5-kΩ pullup resistor between a 5-V reference and

COMP can be used as the pullup for an opto-coupler in isolated applications.

7.3.4 Current Sensing and Current Limiting

The LM5022 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an

internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5 V, the

MOSFET gate drive is immediately terminated. A small RC filter, placed near the controller, is recommended to

filter noise from the current sense signal. The CS input has an internal MOSFET which discharges the CS pin

capacitance at the conclusion of every cycle. The discharge device remains on an additional 65 ns after the

beginning of the new cycle to attenuate leading edge ringing on the current sense signal.

The LM5022 current sense and PWM comparators are very fast, and may respond to short duration noise

pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated

with the CS filter must be placed very close to the device and connected directly to the pins of the controller (CS

and GND). If a current sense transformer is used, both leads of the transformer secondary must be routed to the

sense resistor and the current sense filter network. The current sense resistor can be placed between the source

of the primary power MOSFET and power ground, but it must be a low inductance type. When designing with a

current sense resistor all of the noise sensitive low-power ground connections must be connected together

locally to the controller and a single connection must be made to the high current power ground (sense resistor

ground point).

7.3.5 PWM Comparator and Slope Compensation

The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier

output. The error amplifier output voltage at the COMP pin is offset by 1.4 V and then further attenuated by a 3:1

resistor divider. The PWM comparator polarity is such that 0 V on the COMP pin results in a zero duty cycle at

the controller output. For duty cycles greater than 50%, current mode control circuits can experience sub-

harmonic oscillation. By adding an additional fixed-slope voltage ramp signal (slope compensation) this

oscillation can be avoided. Proper slope compensation damps the double pole associated with current mode

control (see Control Loop Compensation) and eases the design of the control loop compensator. The LM5022

generates the slope compensation with a sawtooth-waveform current source with a slope of 45 µA × ƒ_SW

,

generated by the clock (see Figure 12). This current flows through an internal 2-kΩ resistor to create a minimum

compensation ramp with a slope of 100 mV × ƒ_SW(typical). The slope of the compensation ramp increases when

external resistance is added for filtering the current sense (R_S1) or in the position R_S2. As shown in Figure 12 and

the Functional Block Diagram, the sensed current slope and the compensation slope add together to create the

signal used for current limiting and for the control loop itself.

11

LM5022

ZHCSHC6I –JANUARY 2007–REVISED DECEMBER 2017

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Feature Description (continued)

I_SW

LM5022

45 µA

0

R_S1

R_S2

2 kΩ

CS

Current

Limit

-

+

0.5V

R_SNS

C_SNS

V_CL

Figure 12. Slope Compensation

In peak current mode control, the optimal slope compensation is proportional to the slope of the inductor current

during the power switch off-time. For boost converters, the inductor current slope while the MOSFET is off is

(V_O– V_IN) / L. This relationship is combined with the requirements to set the peak current limit and is used to

select R_SNSand R_S2in Application and Implementation.

7.3.6 Soft Start

The soft-start feature allows the power converter output to gradually reach the initial steady-state output voltage,

thereby reducing start-up stresses and current surges. At power on, after the VCC and input undervoltage

lockout thresholds are satisfied, an internal 10-µA current source charges an external capacitor connected to the

SS pin. The capacitor voltage ramps up slowly and limits the COMP pin voltage and the switch current.

7.3.7 MOSFET Gate Driver

The LM5022 provides an internal gate driver through the OUT pin that can source and sink a peak current of 1 A

to control external, ground-referenced N-channel MOSFETs.

7.3.8 Thermal Shutdown

Internal thermal shutdown circuitry is provided to protect the LM5022 in the event that the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby

state, disabling the output driver and the VCC regulator. After the temperature is reduced (typical hysteresis is

25°C) the VCC regulator is re-enabled and the LM5022 performs a soft start.

7.4 Device Functional Modes

7.4.1 Oscillator, Shutdown, and SYNC

A single external resistor, R_T, connected between the RT/SYNC and GND pins sets the LM5022 oscillator

frequency. To set the switching frequency (ƒ_SW), R_Tcan be calculated with Equation 1.

1- 8´10^-8´ f_SW

(

=

)

R_T

f_SW´ 5.77´10^-11

where

•

f_SWis in Hz

R_Tis in Ω

(1)

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Device Functional Modes (continued)

The LM5022 can also be synchronized to an external clock. The external clock must have a higher frequency

than the free-running oscillator frequency set by the R_Tresistor. The clock signal must be capacitively coupled

into the RT/SYNC pin with a 100-pF capacitor as shown in Figure 13. A peak voltage level greater than 3.8 V at

the RT/SYNC pin is required for detection of the sync pulse. The sync pulse width must be set between 15 ns to

150 ns by the external components. The R_Tresistor is always required, whether the oscillator is free-running or

externally synchronized. The voltage at the RT/SYNC pin is internally regulated to 2 V, and the typical delay from

a logic high at the RT/SYNC pin to the rise of the OUT pin voltage is 120 ns. R_Tmust be placed very close to the

device and connected directly to the pins of the controller (RT/SYNC and GND).

LM5022

EXTERNAL

CLOCK

C_SS

RT/SYNC

100 pF

R_T

15 ns to 150 ns

EXTERNAL

CLOCK

120 ns

(Typical)

OUT PIN

Figure 13. SYNC Operation

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The most common circuit controlled by the LM5022 is a non-isolated boost regulator. The boost regulator steps

up the input voltage and has a duty ratio D in Equation 2.

V_O- V_IN+ V_D

D=

V_O+ V_D

where

•

V_Dis the forward voltage drop of the output diode

(2)

The following is a design procedure for selecting all the components for the boost converter circuit shown in

Figure 14. The application is in-cabin automotive, meaning that the operating ambient temperature ranges from

–20°C to 85°C. This circuit operates in continuous conduction mode (CCM), where inductor current stays above

0 A at all times, and delivers an output voltage of 40 V ±2% at a maximum output current of 0.5 A. Additionally,

the regulator must be able to handle a load transient of up to 0.5 A while keeping V_Owithin ±4%. The voltage

input comes from the battery or alternator system of an automobile, where the standard range of 9 V to 16 V and

transients of up to 32 V must not cause any malfunction.

8.2 Typical Application

L1

D1

V_IN= 9 V to 16 V

V_O= 40 V

C_IN1,2

C_INX

Q1

C_O1,2

C_OX

R_S1

VIN

RT

OUT

R_T

R_S2

R_UV2

R_SNS

CS

C_CS

UVLO

SS

GND

C_SS

C_F

R_UV1

VCC

R_FB2

COMP

R1

FB

C2

R_FB1

C1

Figure 14. LM5022 Typical Application

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Typical Application (continued)

8.2.1 Design Requirements

For typical low-side controller applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

9 V to 16 V

40 V

Maximum output current

Switching frequency

500 mA

500 kHz

8.2.2 Detailed Design Procedure

Table 2 lists the bill of materials for this design example.

Table 2. BOM for Example Circuit

ID

U1

PART NUMBER

LM5022

TYPE

Low-Side Controller

MOSFET

SIZE

10-pin VSSOP

SO-8

PARAMETERS

60 V

QTY

VENDOR

TI

1

2

1

Q1

Si4850EY

60 V, 31 mΩ, 27 nC

60 V, 2 A

Vishay

Central Semi

TDK

D1

CMSH2-60M

Schottky Diode

Inductor

SMA

L1

SLF12575T-M3R2

C4532X7R1H475M

C5750X7R2A475M

C2012X7R1E105K

12.5 × 12.5 × 7.5 mm

1812

33 µH, 3.2 A, 40 mΩ

4.7 µF, 50 V, 3 mΩ

4.7 µF,100 V, 3 mΩ

1 µF, 25 V

Cin1, Cin2

Co1, Co2

Cf

Capacitor

TDK

Capacitor

2220

TDK

Capacitor

0805

TDK

Cinx

Cox

C2012X7R2A104M

Capacitor

0805

100 nF, 100 V

2

TDK

C1

C2

VJ0805A561KXXAT

VJ0805Y124KXXAT

VJ0805Y103KXXAT

VJ0805Y102KXXAT

CRCW08053011F

CRCW08056490F

CRCW08052002F

CRCW0805101J

Capacitor

Resistor

0805

1210

0805

560 pF 10%

120 nF 10%

10 nF 10%

1 nF 10%

1

Vishay

Panasonic

Vishay

Css

Ccs

R1

3.01 kΩ 1%

649 Ω 1%

Rfb1

Rfb2

Rs1

Rs2

Rsns

Rt

20 kΩ 1%

100 Ω 5%

CRCW08053571F

ERJL14KF10C

3.57 kΩ 1%

100 mΩ, 1%, 0.5 W

33.2 kΩ 1%

2.61 kΩ 1%

10 kΩ 1%

CRCW08053322F

CRCW08052611F

CRCW08051002F

Ruv1

Ruv2

8.2.2.1 Switching Frequency

The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a

lower frequency means larger, more expensive inductors and capacitors is required. A higher switching

frequency generally results in a smaller but less efficient solution, as the power MOSFET gate capacitances must

be charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz

was selected as a good compromise between the size of the inductor and efficiency. PCB area and component

height are restricted in this application. Following Equation 1, a 33.2-kΩ 1% resistor must be used to switch at

500 kHz.

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8.2.2.2 MOSFET

Selection of the power MOSFET is governed by tradeoffs between cost, size, and efficiency. Breaking down the

losses in the MOSFET is one way to determine relative efficiencies between different devices. For this example,

the SO 8-pin package provides a balance of a small footprint with good efficiency (see Q1 in Table 2).

Losses in the MOSFET can be broken down into conduction loss, gate charging loss, and switching loss.

Conduction, or I²R loss (P_C) is approximately Equation 3.

»

…

ÿ

Ÿ

I_O

≈

’

P = D ì

ì R

ì 1.3

DSON

∆

÷

c

1 - D

Ÿ

⁄

«

◊

(3)

The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, the factor of 1.3

can be ignored and the maximum on-resistance of the MOSFET can be used.

Gate charging loss, P_G, results from the current required to charge and discharge the gate capacitance of the

power MOSFET and is approximated with Equation 4.

P_G= VCC × Q_G× f_SW

(4)

Q_Gis the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses

because the actual dissipation occurs in the LM5022 and not in the MOSFET itself. If no external bias is applied

to the VCC pin, additional loss in the LM5022 IC occurs as the MOSFET driving current flows through the VCC

regulator. This loss (P_VCC) is estimated with Equation 5.

P_VCC= (V_IN– VCC) × Q_G× f_SW

(5)

Switching loss (P_SW) occurs during the brief transition period as the MOSFET turns on and off. During the

transition period both current and voltage are present in the channel of the MOSFET. The loss can be

approximated with Equation 6.

P_SW= 0.5 × V_IN× [I_O/ (1 – D)] × (t_R+ t_F) × ƒ_SW

where

•

t_Ris the rise time of the MOSFET

t_Fis the fall time of the MOSFET

(6)

For this example, the maximum drain-to-source voltage applied across the MOSFET is V_Oplus the ringing due to

parasitic inductance and capacitance. The maximum drive voltage at the gate of the high-side MOSFET is VCC,

or 7 V typical. The MOSFET selected must be able to withstand 40 V plus any ringing from drain to source, and

be able to handle at least 7 V plus ringing from gate to source. A minimum voltage rating of 50-V_D-Sand 10-V_G-S

MOSFET is used. Comparing the losses in a spreadsheet leads to a 60 V_D-Srated MOSFET in SO-8 with an

R_DSONof 22 mΩ (the maximum value is 31 mΩ), a gate charge of 27 nC, and rise and falls times of 10 ns and 12

ns, respectively.

8.2.2.3 Output Diode

The boost regulator requires an output diode D1 (see Figure 14) to carrying the inductor current during the

MOSFET off-time. The most efficient choice for D1 is a Schottky diode due to low forward drop and near-zero

reverse recovery time. D1 must be rated to handle the maximum output voltage plus any switching node ringing

when the MOSFET is on. In practice, all switching converters have some ringing at the switching node due to the

diode parasitic capacitance and the lead inductance. D1 must also be rated to handle the average output current,

I_O.

The overall converter efficiency becomes more dependent on the selection of D1 at low duty cycles, where the

boost diode carries the load current for an increasing percentage of the time. This power dissipation can be

calculating by checking the typical diode forward voltage, V_D, from the I-V curve on the diode's data sheet and

then multiplying it by I_O. Diode data sheets also provides a typical junction-to-ambient thermal resistance, R_θJA

,

which can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation

(P_D= I_O× V_D) by R_θJAgives the temperature rise. The diode case size can then be selected to maintain the

Schottky diode temperature below the operational maximum.

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In this example a Schottky diode rated to 60 V and 1 A is suitable, as the maximum diode current is 0.5 A. A

small case such as SOD-123 can be used if a small footprint is critical. Larger case sizes generally have lower

R_θJAand lower forward voltage drop, so for better efficiency the larger SMA case size is used.

8.2.2.4 Boost Inductor

The first criterion for selecting an inductor is the inductance itself. In fixed-frequency boost converters this value

is based on the desired peak-to-peak ripple current, Δi_L, which flows in the inductor along with the average

inductor current, I_L. For a boost converter in CCM I_Lis greater than the average output current, I_O. The two

currents are related by Equation 7.

I_L= I_O/ (1 – D)

(7)

As with switching frequency, the inductance used is a tradeoff between size and cost. Larger inductance means

lower input ripple current, however because the inductor is connected to the output during the off-time only there

is a limit to the reduction in output ripple voltage. Lower inductance results in smaller, less expensive magnetics.

An inductance that gives a ripple current of 30% to 50% of I_Lis a good starting point for a CCM boost converter.

Minimum inductance must be calculated with Equation 8 at the extremes of input voltage to find the operating

condition with the highest requirement.

V_INì D

L₁=

f_SWì Di_L

(8)

By calculating in terms of amperes, volts, and megahertz, the inductance value comes out in micro henries.

To ensure that the boost regulator operates in CCM a second equation is required, and must also be evaluated

with Equation 9 at the corners of input voltage to find the minimum inductance required.

D(1- D) ì V_IN

L ₂=

I_Oì f_SW

(9)

By calculating in terms of volts, amps, and megahertz, the inductance value comes out in µH.

For this design, Δi_Lis set to 40% of the maximum I_L. Duty cycle is evaluated first at V_IN(MIN)and at V_IN(MAX)

.

Second, the average inductor current is evaluated at the two input voltages. Third, the inductor ripple current is

determined. Finally, the inductance can be calculated, and a standard inductor value selected that meets all the

criteria.

1. Inductance for Minimum Input Voltage (Equation 10, Equation 11, and Equation 12)

D_VIN(MIN)= (40 – 9 + 0.5) / (40 + 0.5) = 78% I_L-VIN(MIN)= 0.5 / (1 – 0.78) = 2.3 A Δi_L= 0.4 × 2.3 A = 0.92 A

(10)

(11)

9 ì 0.78

L_{1 - VIN (MIN)}

=

= 15.3 mH

0.5 ì 0.92

0.78 ì 0.22 ì 9

0.5 ì 0.5

L _{2 - VIN (MIN)}

=

= 6.2 mH

(12)

(13)

2. Inductance for Maximum Input Voltage (Equation 13, Equation 14, and Equation 15)

D_VIN(MAX)= (40 – 16 + 0.5) / (40 + 0.5) = 60% I_L-VIN(MIAX)= 0.5 / (1 – 0.6) = 1.25 A Δi_L= 0.4 × 1.25 A = 0.5 A

16 ì 0.6

0.5 ì 0.5

L_{1 - VIN (MIN)}

=

= 38.4 mH

(14)

0.6 ì 0.4 ì 16

0.5 ì 0.5

L _{2 - VIN (MIN)}

=

= 15.4 mH

(15)

Maximum average inductor current occurs at V_IN(MIN), and the corresponding inductor ripple current is 0.92 A_P-P

.

Selecting an inductance that exceeds the ripple current requirement at V_IN(MIN)and the requirement to stay in

CCM for V_IN(MAX)provides a tradeoff that allows smaller magnetics at the cost of higher ripple current at

maximum input voltage. For this example, a 33-µH inductor satisfies these requirements.

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The second criterion for selecting an inductor is the peak current carrying capability. This is the level above

which the inductor saturates. In saturation, the inductance can drop off severely, resulting in higher peak current

that may overheat the inductor or push the converter into current limit. In a boost converter, peak current, I_PK, is

equal to the maximum average inductor current plus one half of the ripple current. First, the current ripple must

be determined under the conditions that give maximum average inductor current with Equation 16.

V_INx D

Di_L=

f_SWì L

(16)

Maximum average inductor current occurs at V_IN(MIN). Using the selected inductance of 33 µH yields Equation 17.

Δi_L= (9 × 0.78) / (0.5 × 33) = 425 mA_P-P

(17)

The highest peak inductor current over all operating conditions is therefore Equation 18.

I_PK= I_L+ 0.5 × Δi_L= 2.3 + 0.213 = 2.51 A

(18)

Hence an inductor must be selected that has a peak current rating greater than 2.5 A and an average current

rating greater than 2.3 A. One possibility is an off-the-shelf 33 µH ±20% inductor that can handle a peak current

of 3.2 A and an average current of 3.4 A. Finally, the inductor current ripple is recalculated with Equation 19 at

the maximum input voltage.

Δi_L-VIN(MAX)= (16 × 0.6) / (0.5 × 33) = 0.58 A_P-P

(19)

8.2.2.5 Output Capacitor

The output capacitor in a boost regulator supplies current to the load during the MOSFET on-time and also filters

the AC portion of the load current during the off-time. This capacitor determines the steady-state output voltage

ripple, ΔV_O, a critical parameter for all voltage regulators. Output capacitors are selected based on their

capacitance, C_O, their equivalent series resistance (ESR) and their RMS or AC current rating.

The magnitude of ΔV_Ois comprised of three parts, and in steady-state the ripple voltage during the on-time is

equal to the ripple voltage during the off-time. For simplicity the analysis is performed for the MOSFET turning off

(off-time) only. The first part of the ripple voltage is the surge created as the output diode D1 turns on. At this

point, inductor and diode current are at peak value, and the ripple voltage increase can be calculated with

Equation 20.

ΔV_O1= I_PK× ESR

(20)

The second portion of the ripple voltage is the increase due to the charging of C_Othrough the output diode. This

portion can be approximated with Equation 21.

ΔV_O2= (I_O/ C_O) × (D / ƒ_SW

)

(21)

The final portion of the ripple voltage is a decrease due to the flow of the diode and inductor current through the

ESR of the output capacitor. This decrease can be calculated with Equation 22.

ΔV_O3= Δi_L× ESR

(22)

The total change in output voltage is Equation 23.

ΔV_O= ΔV_O1+ ΔV_O2– ΔV_O3

(23)

The combination of two positive terms and one negative term may yield an output voltage ripple with a net rise or

a net fall during the converter off-time. The ESR of the output capacitor(s) has a strong influence on the slope

and direction of ΔV_O. Capacitors with high ESR such as tantalum and aluminum electrolytic create an output

voltage ripple that is dominated by ΔV_O1and ΔV_O3, with a shape shown in Figure 15. Ceramic capacitors, in

contrast, have very low ESR and lower capacitance. The shape of the output ripple voltage is dominated by

ΔV_O2, with a shape shown in Figure 16.

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V_O

Âv_O

V_O

Âv_O

I_D

Figure 15. ΔV_OUsing High-ESR Capacitors

Figure 16. ΔV_OUsing Low-ESR Capacitors

For this example the small size and high temperature rating of ceramic capacitors make them a good choice.

The output ripple voltage waveform of Figure 16 is assumed, and the capacitance is selected first. The desired

ΔV_Ois ±2% of 40 V, or 0.8 V_P-P. Beginning with the calculation for ΔV_O2, the required minimum capacitance is in

Equation 24.

C_O-MIN= (I_O/ ΔV_O) x (D_MAX/ f_SW) C_O-MIN= (0.5 / 0.8) x (0.77 / 5 x 10⁵) = 0.96 µF

(24)

The next higher standard 20% capacitor value is 1 µF, however to provide margin for component tolerance and

load transients two capacitors rated 4.7 µF each (C_O= 9.4 µF) is used. Ceramic capacitors rated 4.7 µF ±20%

are available from many manufacturers. The minimum quality dielectric that is suitable for switching power supply

output capacitors is X5R, while X7R (or better) is preferred. Pay careful attention to the DC voltage rating and

case size, as ceramic capacitors can lose 60% or more of their rated capacitance at the maximum DC voltage.

This is the reason that ceramic capacitors are often de-rated to 50% of their capacitance at their working voltage.

The output capacitors for this example has a 100-V rating in a 2220 case size.

The typical ESR of the selected capacitors is 3 mΩ each, and in parallel is approximately 1.5 mΩ. The worst-

case value for ΔV_O1occurs during the peak current at minimum input voltage in Equation 25.

ΔV_O1= 2.5 × 0.0015 = 4 mV

(25)

The worst-case capacitor charging ripple occurs at maximum duty cycle in Equation 26.

ΔV_O2= (0.5 / 9.4 × 10^–6) x (0.77 / 5 × 10⁵) = 82 mV

(26)

Finally, the worst-case value for ΔV_O3occurs when inductor ripple current is highest, at maximum input voltage in

Equation 27.

ΔV_O3= 0.58 × 0.0015 = 1 mV (negligible)

(27)

The output voltage ripple can be estimated by summing the three terms in Equation 28.

ΔV_O= 4 mV + 82 mV - 1 mV = 85 mV

(28)

The RMS current through the output capacitor(s) can be estimated using the following, worst-case equation in

Equation 29.

I_O-RMS= 1.13 ì I_Lì D ì (1-D)

(29)

The highest RMS current occurs at minimum input voltage. For this example the maximum output capacitor RMS

current is calculated with Equation 30.

I_O-RMS(MAX)= 1.13 × 2.3 × (0.78 x 0.22)^0.5= 1.08 A_RMS

(30)

These 2220 case size devices are capable of sustaining RMS currents of over 3 A each, making them more than

adequate for this application.

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8.2.2.6 VCC Decoupling Capacitor

The VCC pin must be decoupled with a ceramic capacitor placed as close as possible to the VCC and GND pins

of the LM5022. The decoupling capacitor must have a minimum X5R or X7R type dielectric to ensure that the

capacitance remains stable over voltage and temperature, and be rated to a minimum of 470 nF. One good

choice is a 1-µF device with X7R dielectric and 1206 case size rated to 25 V.

8.2.2.7 Input Capacitor

The input capacitors to a boost regulator control the input voltage ripple (ΔV_IN) hold up the input voltage during

load transients and prevent impedance mismatch (also called power supply interaction) between the LM5022 and

the inductance of the input leads. Selection of input capacitors is based on their capacitance, ESR, and RMS

current rating. The minimum value of ESR can be selected based on the maximum output current transient,

I_STEP, using Equation 31.

1 - D ìDV

(

)

IN

ESR_MIN

=

2 x I_STEP

(31)

For this example, the maximum load step is equal to the load current or 0.5 A. The maximum permissable ΔV_IN

during load transients is 4%_P-P. ΔV_INand duty cycle are taken at minimum input voltage to give the worst-case

value in Equation 32.

ESR_MIN= [(1 – 0.77) × 0.36] / (2 × 0.5) = 83 mΩ

(32)

The minimum input capacitance can be selected based on ΔV_IN, based on the drop in V_INduring a load transient,

or based on prevention of power supply interaction. In general, the requirement for greatest capacitance comes

from the power supply interaction. The inductance and resistance of the input source must be estimated, and if

this information is not available, they can be assumed to be 1 µH and 0.1 Ω, respectively. Minimum capacitance

is then estimated with Equation 33.

2 ì L _Sì V_Oì I_O

C_MIN

=

V

²ì R_S

IN

(33)

As with ESR, the worst-case, highest minimum capacitance calculation comes at the minimum input voltage.

Using the default estimates for L_Sand R_S, minimum capacitance is calculated with Equation 34.

2 ì 1mì 40ì 0.5

C_MIN

=

= 4.9 mF

9 ²ì 0.1

(34)

The next highest standard 20% capacitor value is 6.8 µF, but because the actual input source impedance and

resistance are not known, two 4.7-µF capacitors is used. In general, doubling the calculated value of input

capacitance provides a good safety margin. The final calculation is for the RMS current. For boost converters

operating in CCM this can be estimated with Equation 35.

I_RMS= 0.29 × Δi_L(MAX)

(35)

From the inductor section, maximum inductor ripple current is 0.58 A, hence the input capacitor(s) must be rated

to handle 0.29 × 0.58 = 170 mA_RMS

.

The input capacitors can be ceramic, tantalum, aluminum, or almost any type, however the low capacitance

requirement makes ceramic capacitors particularly attractive. As with the output capacitors, the minimum quality

dielectric used must X5R, with X7R or better preferred. The voltage rating for input capacitors requirement not be

as conservative as the output capacitors, as the requirement for capacitance decreases as input voltage

increases. For this example, the capacitor selected is 4.7 µF ±20%, rated to 50 V in the 1812 case size. The

RMS current rating of these capacitors is over 2 A each, more than enough for this application.

8.2.2.8 Current Sense Filter

Parasitic circuit capacitance, inductance and gate drive current create a spike in the current sense voltage at the

point where Q1 turns on. To prevent this spike from terminating the on-time prematurely, every circuit must have

a low-pass filter that consists of C_CSand R_S1, shown in Figure 14. The time constant of this filter must be long

enough to reduce the parasitic spike without significantly affecting the shape of the actual current sense voltage.

The recommended range for R_S1is between 10 Ω and 500 Ω, and the recommended range for C_CSis between

100 pF and 2.2 nF. For this example, the values of R_S1and C_CSis 100 Ω and 1 nF, respectively.

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8.2.2.9 R_SNS, R_S2and Current Limit

The current sensing resistor R_SNSis used for steady-state regulation of the inductor current and to sense

overcurrent conditions. The slope compensation resistor is used to ensure control loop stability, and both

resistors affect the current limit threshold. The R_SNSvalue selected must be low enough to keep the power

dissipation to a minimum, yet high enough to provide good signal-to-noise ratio for the current sensing circuitry.

R_SNS, and R_S2must be set so that the current limit comparator, with a threshold of 0.5 V, trips before the sensed

current exceeds the peak current rating of the inductor, without limiting the output power in steady state.

For this example the peak current, at V_IN(MIN), is 2.5 A, while the inductor itself is rated to 3.2 A. The threshold for

current limit, I_LIM, is set slightly between these two values to account for tolerance of the circuit components, at a

level of 3 A. The required resistor calculation must take both the switch current through R_SNSand the

compensation ramp current flowing through the internal 2 kΩ, R_S1and R_S2resistors into account. R_SNSmust be

selected first because it is a power resistor with more limited selection. Equation 36 and Equation 37 must be

evaluated at V_IN(MIN), when duty cycle is highest.

L ì f_SWì V_CL

R _SNS

=

V

- V_INì 3 ì D+ L ì f_SWìI_LIM

(

)

O

(36)

33 ì 0.5 ì 0.5

40 - 9 ì 3 ì 0.78 + 33 ì 0.5 ì 3

R_SNS

=

(

)

where

•

L is in µH

f_SWin MHz

(37)

The closest 5% value is 100 mΩ. Power dissipation in R_SNScan be estimated by calculating the average current.

The worst-case average current through R_SNSoccurs at minimum input voltage/maximum duty cycle and can be

calculated with Equation 38 and Equation 39.

2

»

…

ÿ

Ÿ

I_O

≈

’

P_CS

=

ì R

ì D

∆

÷

^SNSŸ

1 - D

«

◊

⁄

(38)

(39)

P_CS= [(0.5 / 0.22)²× 0.1] × 0.78 = 0.4 W

For this example, a 0.1 Ω ±1%, thick-film chip resistor in a 1210 case size rated to 0.5 W is used.

With R_SNSselected, R_S2can be determined using Equation 40 and Equation 41.

V_CL- I_ILIMì R _SNS

R _S2

=

- 2000 - R _S1

45m ì D

(40)

(41)

0.5 - 3 ì 0.1

45m ì 0.78

R_S2

=

- 2000 - 100 = 3598W

The closest 1% tolerance value is 3.57 kΩ.

8.2.2.10 Control Loop Compensation

The LM5022 uses peak current-mode PWM control to correct changes in output voltage due to line and load

transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response,

and easier control loop compensation.

The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width

modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an

inverting amplifier. Figure 17 shows the regulator control loop components.

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L

+

C_O

R_C

D

V_IN

R_O

+

-

R_SNS

+

-

R_FB2

R1

C2

C1

-

+

R_FB1

+

-

V_REF

Figure 17. Power Stage and Error Amplifier

One popular method for selecting the compensation components is to create Bode plots of gain and phase for

the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the

regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how

changes in compensation or the power stage affect system gain and phase.

The power stage in a CCM peak current mode boost converter consists of the DC gain, A_PS, a single low-

frequency pole, ƒ_LFP, the ESR zero, ƒ_ZESR, a right-half plane zero, ƒ_RHP, and a double pole resulting from the

sampling of the peak current. The power stage transfer function (also called the control-to-output transfer

function) can be written with Equation 42, Equation 43, and Equation 44.

æ

ç

è

öæ

÷ç

øè

ö

÷

ø

s²

s

1+

1-

w_ZESR

w_RHP

G_PS= A_PS

´

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

s

1+

ç1+

+

w²

ç

è

w_LEP

Q_n´ w_n

n

where

•

the DC gain is defined as:

(1 - D) ì R _O

(42)

A _PS

=

2 ì R _SNS

where

R_O= V_O/ I_O

(43)

(44)

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The system ESR zero is calculated with Equation 45.

1

w_ZESR

=

R _Cì C_O

(45)

(46)

The low-frequency pole is calculated with Equation 46.

1

w_LEP

=

0.5 ì R + ESR ì C

(

)

O

The right-half plane zero is calculated with Equation 47.

2

≈

’

V_IN

V_O

R _O

ì

∆

«

÷

◊

w_RHP

=

L

(47)

The sampling double-pole quality factor is calculated with Equation 48.

1

Q_n=

»

ÿ

Ÿ

S _e

p -D + 0.5 + (1 - D)

…

S_{n Ÿ}

…

⁄

(48)

(49)

(50)

(51)

The sampling double corner frequency is calculated with Equation 49.

ω_n= π × f_SW

The natural inductor current slope is calculated with Equation 50.

S_n= R_SNS× V_IN/ L

The external ramp slope is calculated with Equation 51.

S_e= 45 µA × (2000 + R_S1+ R_S2)] × ƒ_SW

In Equation 43, DC gain is highest when input voltage and output current are at the maximum. In this the

example those conditions are V_IN= 16 V and I_O= 500 mA.

DC gain is 44 dB. The low-frequency pole f_P= ω_P/2π is at 423 Hz, the ESR zero f_Z= ω_Z/2π is at 5.6 MHz, and the

right-half plane zero ƒ_RHP= ω_RHP/2π is at 61 kHz. The sampling double-pole occurs at one-half of the switching

frequency. Proper selection of slope compensation (through R_S2) is most evident the sampling double pole. A

well-selected R_S2value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and

phase plots for the power stage are shown in Figure 18 and Figure 19.

SPACE

60

45

30

15

0

180

120

60

0

-60

-120

-180

-15

-30

100

1k

10k

100k

1M

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 18. Power Stage Gain and Phase

Figure 19. Power Stage Gain and Phase

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The single pole causes a rolloff in the gain of –20 dB/decade at lower frequency. The combination of the RHP

zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends

towards –90° at lower frequency but then increases to –180° and beyond from the RHP zero and the sampling

double pole. The effect of the ESR zero is not seen because its frequency is several decades above the

switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP

zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero

frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop

were left uncompensated, the bandwidth would be 89 kHz and the phase margin –54°. The converter would

oscillate, and therefore is compensated using the error amplifier and a few passive components.

The transfer function of the compensation block (G_EA) can be derived by treating the error amplifier as an

inverting op-amp with input impedance Z_Iand feedback impedance Z_F. The majority of applications require a

Type II, or two-pole one-zero amplifier, shown in Figure 17. The LaPlace domain transfer function for this Type II

network is given by Equation 52.

Z_F

Z_I

1

s ì R1ì C2 + 1

s ì R1ì C1ì C2

C1 + C2

G_EA

=

ì

R_FB2(C1 + C2)

≈

’

s

+1

÷

∆

«

◊

(52)

Many techniques exist for selecting the compensation component values. The following method is based upon

setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero

and pole:

1. Determine the desired control loop bandwidth: The control loop bandwidth (ƒ_0dB) is the point at which the

total control loop gain (H = G_PS× G_EA) is equal to 0 dB. For this example, a low bandwidth of 10 kHz, or

approximately 1/6th of the RHP zero frequency, is chosen because of the wide variation in input voltage.

2. Determine the gain of the power stage at ƒ_0dB: This value, A, can be read graphically from the gain plot of

G_PSor calculated by replacing the ‘s’ terms in G_PSwith ‘2 πf_0dB’. For this example, the gain at 10 kHz is

approximately 16 dB.

3. Calculate the negative of A and convert it to a linear gain: By setting the mid-band gain of the error amplifier

to the negative of the power stage gain at f_0dB, the control loop gain equals 0 dB at that frequency. For this

example, –16 dB = 0.15 V/V.

4. Select the resistance of the top feedback divider resistor R_FB2: This value is arbitrary, however selecting a

resistance between 10 kΩ and 100 kΩ leads to practical values of R1, C1, and C2. For this example, R_FB2

20 kΩ 1%.

=

5. Set Equation 55:

R1 = A × R_FB2

(53)

For this example: R1 = 0.15 × 20000 = 3 kΩ

6. Select a frequency for the compensation zero, ƒ_Z1: The suggested placement for this zero is at the low-

frequency pole of the power stage, ƒ_LFP= ωLFP / 2π. For this example, ƒ_Z1= ƒ_LFP= 423 Hz

7. Set Equation 54.

1

C2 =

:

2p ì R1ì f_Z1

(54)

For this example, C2 = 125 nF

8. Select a frequency for the compensation pole, ƒ_P1: The suggested placement for this pole is at one-fifth of

the switching frequency. For this example, ƒ_P1= 100 kHz

9. Set Equation 55.

C2

C1 =

2Œ×C2×R1×f_P1-1

(55)

For this example, C1 = 530 pF

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10. Plug the closest 1% tolerance values for R_FB2and R1, then the closest 10% values for C1 and C2 into G_EA

and model the error amp: The open-loop gain and bandwidth of the LM5022’s internal error amplifier are 75

dB and 4 MHz, respectively. Their effect on G_EAcan be modeled using Equation 56:

2p ì GBW

OPG =

2p ì GBW

s +

A _DC

(56)

A_DCis a linear gain, the linear equivalent of 75 dB is approximately 5600 V/V. C1 = 560 pF 10%, C2 = 120

nF 10%, R1 = 3.01 kΩ 1%

11. Plot or evaluate the actual error amplifier transfer function:

G_EAì OPG

G_EA-ACTUAL

=

1 + G_EAì OPG

(57)

60

40

20

0

-20

-40

-60

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 20. Overall Loop Gain and Phase

180

120

60

0

-60

-120

-180

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 21. Overall Loop Gain and Phase

12. Plot or evaluate the complete control loop transfer function: The complete control loop transfer function is

obtained by multiplying the power stage and error amplifier functions together. The bandwidth and phase

margin can then be read graphically or evaluated numerically. The bandwidth of this example circuit at V_IN

16 V is 10.5 kHz with a phase margin of 66°.

=

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13. Re-evaluate at the corners of input voltage and output current: Boost converters exhibit significant change in

their loop response when V_INand I_Ochange. With the compensation fixed, the total control loop gain and

phase must be checked to ensure a minimum phase margin of 45° over both line and load.

8.2.2.11 Efficiency Calculations

A reasonable estimation for the efficiency of a boost regulator controlled by the LM5022 can be obtained by

adding together the loss is each current carrying element and using Equation 58.

P_O

P_O+ P_total-loss

h =

(58)

The following shows an efficiency calculation to complement the circuit design. Output power for this circuit is 40

V × 0.5 A = 20 W. Input voltage is assumed to be 13.8 V, and the calculations used assume that the converter

runs in CCM. Duty cycle for V_IN= 13.8 V is 66%, and the average inductor current is 1.5 A.

8.2.2.11.1 Chip Operating Loss

This term accounts for the current drawn at the VIN pin. This current, I_IN, drives the logic circuitry and the power

MOSFETs. The gate driving loss term from MOSFET is included in the chip operating loss. For the LM5022, I_INis

equal to the steady-state operating current, I_CC, plus the MOSFET driving current, I_GC. Power is lost as this

current passes through the internal linear regulator of the LM5022 in Equation 59.

I_GC= Q_G× ƒ_SWI_GC= 27 nC × 500 kHz = 13.5 mA

(59)

I_CCis typically 3.5 mA (taken from Electrical Characteristics). Chip operating loss is then calculated with

Equation 60.

P_Q= V_IN× (I_Q+ I_GC) P_Q= 13.8 × (3.5 m + 13.5m) = 235 mW

(60)

(61)

(62)

8.2.2.11.2 MOSFET Switching Loss

P_SW= 0.5 × V_IN× I_L× (t_R+ t_F) x f_SWP_SW= 0.5 × 13.8 × 1.5 × (10 ns + 12 ns) × 5 × 10⁵= 114 mW

8.2.2.11.3 MOSFET and R_SNSConduction Loss

P_C= D × (I_L²× (R_DSON× 1.3 + R_SNS)) P_C= 0.66 × (1.5²× (0.029 + 0.1)) = 192 mW

8.2.2.11.4 Output Diode Loss

The average output diode current is equal to I_Oor 0.5 A. The estimated forward drop (V_D) is 0.5 V. The output

diode loss is Equation 63.

P_D1= I_O× V_DP_D1= 0.5 × 0.5 = 0.25 W

(63)

8.2.2.11.5 Input Capacitor Loss

This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this

equation ‘n’ is the number of capacitors in parallel. The 4.7-µF input capacitors selected have a combined ESR

of approximately 1.5 mΩ, and Δi_Lfor a 13.8-V input is 0.55 A in Equation 64 and Equation 65.

I_IN-RMS²ì ESR

P_CIN

=

n

(64)

(65)

I_IN-RMS= 0.29 × Δi_L= 0.29 × 0.55 = 0.16 A P_CIN= [0.16²× 0.0015] / 2 = 0.02 mW (negligible)

8.2.2.11.6 Output Capacitor Loss

This term is calculated using the same method as the input capacitor loss, substituting the output capacitor RMS

current for V_IN= 13.8 V. The combined ESR of the output capacitors is also approximately 1.5 mΩ in

Equation 66.

I_O-RMS= 1.13 × 1.5 × (0.66 x 0.34)^0.5= 0.8 A P_CO= [0.8 × 0.0015] / 2 = 0.6 mW

(66)

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8.2.2.11.7 Boost Inductor Loss

The typical DCR of the selected inductor is 40 mΩ in Equation 67.

P_DCR= I_L²× DCR P_DCR= 1.5²× 0.04 = 90 mW

(67)

Core loss in the inductor is estimated to be equal to the DCR loss, adding an additional 90 mW to the total

inductor loss.

8.2.2.11.8 Total Loss

P_LOSS= Sum of All Loss Terms = 972 mW

(68)

(69)

8.2.2.11.9 Efficiency

η = 20 / (20 + 0.972) = 95%

8.2.3 Application Curves

10V/DIV

V_O

SW

10V/DIV

1 és/DIV

V_IN= 9 V, I_O= 0.5 A

Figure 23. Switch Node Voltage

Figure 22. Efficiency

10V/DIV

V_O

50 mV/DIV

SW

10V/DIV

1 és/DIV

V_IN= 9 V, I_O= 0.5 A

V_IN= 16 V, I_O= 0.5 A

Figure 24. Switch Node Voltage

Figure 25. Output Voltage Ripple AC Coupled

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200 mA/DIV

I_O

V_O

2V/DIV

50 mV/DIV

400 és/DIV

1 és/DIV

V_IN= 9 V, I_O= 50 mA to 0.5 A

Figure 27. Load Transient Response

V_IN= 16 V, I_O= 0.5 A

Figure 26. Output Voltage Ripple AC Coupled

200 mA/DIV

I_O

V_O

1V/DIV

1 ms/DIV

V_IN= 16 V, I_O= 50 mA to 0.5 A

Figure 28. Load Transient Response

9 Power Supply Recommendations

LM5022 is a power management device. The power supply for the device can be any DC voltage source within

the specified input range.

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10 Layout

10.1 Layout Guidelines

To produce an optimal power solution with the LM5022, good layout and design of the PCB are as critical as

component selection. The following are the several guidelines to create a good layout of the PCB, as based on

Figure 14:

1. Using a low-ESR ceramic capacitor, place C_INXas close as possible to the VIN and GND pins of the

LM5022.

2. Using a low-ESR ceramic capacitor, place C_OXclose to the load as possible of the LM5022.

3. Using a low-ESR ceramic capacitor, place C_Fclose to the VCC and GND pins of the LM5022.

4. Minimize the loop area formed by the output capacitor connections (C_o1, C_o2) by D1 and R_sns. Make sure

the cathode of D1 and R_snsare positioned next to each other, and place C_o1(+) and C_o1(–) close to D1

cathode and R_sns(–) respectively.

5. R_sns(+) must be connected to the CS pin with a separate trace made as short as possible. This trace

must be routed away from the inductor and the switch node (where D1, Q1, and L1 connect).

6. Minimize the trace length to the FB pin by positioning R_FB1and R_FB2close to the LM5022.

7. Route the VOUT sense path away from noisy node and connect it as close as possible to the positive

side of C_OX

.

10.1.1 Filter Capacitors

The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter

is minimized. Place C_INXas close as possible to the VIN and GND pins of the LM5022. Place C_OXclose to the

load, and C_Fnext to the VCC and GND pins of the LM5022.

10.1.2 Sense Lines

The top of R_SNSmust be connected to the CS pin with a separate trace made as short as possible. Route this

trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep

R_FB1/2close to the LM5022 and run a trace from as close as possible to the positive side of C_OXto R_FB2. As with

the CS line, the FB line must be routed away from the inductor and the switch node. These measures minimize

the length of high impedance lines and reduce noise pickup.

10.1.3 Compact Layout

Parasitic inductance can be reduced by keeping the power path components close together. As described in

Layout Guidelines, keep the high slew-rate current loops as tight as possible. Short, thick traces or copper pours

(shapes) are best.

The switch node must be just large enough to connect all the components together without excessive heating

from the current it carries. The LM5022 (boost converter) operates in two distinct cycles whose high current

paths are shown in Figure 29.

+

-

Figure 29. Boost Converter Current Loops

29

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Layout Guidelines (continued)

The dark grey, inner loops represents the high current paths during the MOSFET on-time. The light grey, outer

loop represents the high current path during the off-time.

10.1.4 Ground Plane and Shape Routing

The diagram of Figure 29 is also useful for analyzing the flow of continuous current versus the flow of pulsating

currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous

current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in

routing must be given to the pulsating current paths, as these are the portions of the circuit most likely to emit

EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as

any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane

with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the

MOSFET and the path between the output capacitor and the load are examples of continuous current paths. In

contrast, the path between the grounded side of the power switch and the negative output capacitor terminal

carries a large pulsating current. This path must be routed with a short, thick shape, preferably on the component

side of the PCB. Multiple vias in parallel must be used right at the negative pads of the input and output

capacitors to connect the component side shapes to the ground plane. Vias must not be placed directly at the

grounded side of the MOSFET (or R_SNS) as they tend to inject noise into the ground plane. A second pulsating

current loop that is often ignored but must be kept small is the gate drive loop formed by the OUT and VCC pins,

Q1, R_SNS, and capacitor C_F.

10.2 Layout Examples

Figure 30. Top Layer and Top Overlay

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Layout Examples (continued)

Figure 31. Bottom Layer

31

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11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.1.2 设计支持

WEBENCH^®软件使用迭代设计流程并可访问组件的综合数据库。有关详细信息，请访问 www.ti.com/webench。

11.2 文档支持

11.2.1 相关文档


型号：	LM5022
厂家：	TEXAS INSTRUMENTS
描述：	6V 至 60V 宽输入电压、电流模式升压、SEPIC 和反激式控制器控制器
文件：	总40页 (文件大小：2157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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