LM3704 [TI]
具有电源故障输入、低电平线路输出和手动复位功能的电压监控器和复位 IC;
| 型号： | LM3704 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源故障输入、低电平线路输出和手动复位功能的电压监控器和复位 IC 监控 |
| 文件： | 总25页 (文件大小：1331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
LM3704 Voltage Supervisor With Power-Fail Input,
Low-Line Output and Manual Reset
1 Features
3 Description
The LM3704 is a feature-rich, easy-to-use voltage
supervisor. It is offered in both push-pull and open-
drain configuration with a tight 2% accuracy over
temperature.
1
•
•
•
•
Available Threshold Voltage of 3.08 V and 2.32 V
No External Components Required
Manual-Reset Input
Available in Both Open-Drain and Push-Pull
Configuration
The LM3704 features include a manual reset, low-line
output, and power-fail input detection. The power-fail
input allows for a configurable second rail to be
monitored helping detect upstream failures. The low-
line output is used as a second interrupt line to
indicate a fall in VCC (1.02 × VRST).
•
•
•
Reset Time-Out Delay of 200 ms
Separate Power-Fail Comparator
±0.5% Reset Threshold Accuracy at Room
Temperature
Device Information(1)
•
•
±2% Reset Threshold Accuracy Over
Temperature
PART NUMBER
LM3704
PACKAGE
BODY SIZE (NOM)
28-µA VCC Supply Current
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Embedded Controllers and Processors
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
VIN1
VCC
VCC
Reset
PFO
Reset
NMI
VIN2
PFI
mP
MR
INT
LLO
GND
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
8.3 System Examples ................................................... 14
Power Supply Recommendations...................... 16
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1 Device Support...................................................... 17
11.2 Community Resources.......................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2012) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
2
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
V
1
2
3
4
5
10
RESET
NC
CC
MR
PFI
9
8
7
PFO
LLO
NC
GND
6
NC
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VCC
I
I
Power supply input.
2
MR
Manual-reset input. When MR is less than VMRT (manual reset threshold) RESET/RESET is engaged.
Power-fail comparator input. When PFI is less than VPFT (power-fail reset threshold), the PFO goes low.
Otherwise, PFO remains high.
3
PFI
I
4
5
6
NC
GND
NC
—
—
—
No connection.
Ground reference for all signals.
No connection.
Low-line logic output. Early power-fail warning output. Low when VCC falls below VLLOT (low-line output
threshold). This output can be used to generate an NMI (non-maskable interrupt) to provide an early
warning of imminent power failure.
7
LLO
O
8
9
PFO
NC
O
Power-fail logic output. When PFI is below VPFT, PFO goes low; otherwise, PFO remains high.
No connection. Test input used at factory only. Leave floating.
—
Reset logic output. Pulses low for tRP (reset time-out period) when triggered, and stays low whenever
VCC is below the reset threshold or when MR is below VMRT. It remains low for tRP after either VCC rises
10
RESET
O
above the reset threshold, or after MR input rises above VMRT
.
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
6
UNIT
V
Supply voltage, VCC
All other inputs
VCC + 0.3
V
Power dissipation
See(2)
Storage temperature, Tstg
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:
TJ(MAX) - TA
P(MAX) =
qJ-A
Where the value of θJ-A for the 10-pin VSSOP package is 195°C/W in a typical printed-circuit board (PCB) mounting and the DSBGA
package is 220°C/W.
6.2 ESD Ratings
VALUE
±1500
±150
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
85
UNIT
TA
Free-air temperature
–40
°C
6.4 Thermal Information
LM3704
THERMAL METRIC(1)
DGS (VSSOP)
UNIT
10 PINS
163.7
58.3
83.5
6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
82.2
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
6.5 Electrical Characteristics
at TJ = 25°C and VCC = 2.2 V to 5.5 V (unless otherwise noted)
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
28
MAX UNIT
VCC
Operating voltage
LM3704, TJ = –40°C to 85°C
1
5.5
50
V
TJ = 25°C
All inputs = VCC
,
ICC
VCC supply current
µA
all outputs floating
TJ = –40°C to 85°C
RESET THRESHOLD
TJ = 25°C
–0.5%
–2%
VRST
0.5%
2%
VRST
Reset threshold
VCC falling
TJ = –40°C to 85°C
TJ = 0°C to 70°C
–1.5%
1.5%
VRSTH
tRP
Reset threshold hysteresis
Reset time-out period
VCC to reset delay
0.0032 × VRST
200
mV
ms
µs
TJ = 25°C
Reset time-out period =
C
TJ = –40°C to 85°C
140
280
tRD
VCC falling at 1 mV/µs
20
RESET
VCC > 1.0 V, ISINK = 50 µA,
TJ = –40°C to 85°C
0.3
0.3
0.3
0.3
0.4
VCC > 1.2 V, ISINK = 100 µA,
TJ = –40°C to 85°C
VCC > 2.25 V, ISINK = 900 µA,
TJ = –40°C to 85°C
VOL
RESET
V
VCC > 2.7 V, ISINK = 1.2 mA,
TJ = –40°C to 85°C
VCC > 4.5 V, ISINK = 3.2 mA,
TJ = –40°C to 85°C
VCC > 2.25 V, ISOURCE = 300 µA,
TJ = –40°C to 85°C
0.8 × VCC
0.8 × VCC
VCC > 2.7 V, ISOURCE = 500 µA,
TJ = –40°C to 85°C
VOH
RESET
V
V
VCC > 4.5 V, ISOURCE = 800 µA,
TJ = –40°C to 85°C
V
CC − 1.5
PFI/MR
TJ = 25°C
1.225
VPFT
PFI input threshold
MR Input threshold
TJ = –40°C to 85°C
1.2
2
1.25
0.8
MR, low
MR, high
VMRT
TJ = –40°C to 85°C
V
VPFTH
VMRTH
/
PFI/MR threshold
hysteresis
PFI/MR falling, VCC = VRST MAX to 5.5 V
0.0032 × VRST
mV
IPFI
Input current (PFI only)
TJ = –40°C to 85°C
TJ = 25°C
–75
35
75 nA
56
12
RMR
MR pullup resistance
kΩ
TJ = –40°C to 85°C
75
tMD
MR to reset delay
MR pulse width
µS
µS
tMR
TJ = –40°C to 85°C
25
PFO, LLO
VCC > 2.25 V, ISINK = 900 µA,
TJ = –40°C to 85°C
0.3
PFO, LLO output low
voltage
VCC > 2.7 V, ISINK = 1.2 mA,
TJ = –40°C to 85°C
VOL
0.3
0.4
V
VCC > 4.5 V, ISINK = 3.2 mA,
TJ = –40°C to 85°C
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
Electrical Characteristics (continued)
at TJ = 25°C and VCC = 2.2 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC > 2.25 V, ISOURCE = 300 µA,
TJ = –40°C to 85°C
0.8 VCC
PFO, LLO output high
voltage
VCC > 2.7 V, ISOURCE = 500 µA,
TJ = –40°C to 85°C
VOH
0.8 VCC
V
VCC > 4.5 V, ISOURCE = 800 µA,
TJ = –40°C to 85°C
VCC − 1.5
LLO OUTPUT
TJ = 25°C
TJ = –40°C to 85°C 1.01 × VRST
1.02 × VRST
VLLOT
LLO output threshold
VLLO − VRST, VCC falling
V
1.03 × VRST
Low-line comparator
hysteresis
VLLOTH
tCD
0.0032 × VRST
20
mV
µs
Low-line comparator delay VCC falling at 1 mV/µs
Figure 1. LM3704 Reset Time With MR
Figure 2. LLO Output
6
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
Figure 3. PFI Comparator Timing Diagram
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
6.6 Typical Characteristics
30
29
30
25
28
20
15
10
27
26
25
5
0
24
23
25
70
85
5
1
3
4
-40
0
2
Temperature (°C)
Supply Voltage (V)
Figure 5. 3.3-V Supply Current vs Temperature
Figure 4. Supply Current vs Supply Voltage
0.5
220
0.4
0.3
215
210
205
0.2
0.1
0
200
195
190
-0.1
-0.2
-0.3
185
180
-0.4
-0.5
5.5
5
6
3.0
4.5
3.5
-40
25
85
4
Temperature (°C)
Supply Voltage (V)
Figure 6. Normalized Reset Threshold Voltage
vs Temperature
Figure 7. Reset Timeout Period vs VCC
215
210
205
200
80
70
60
50
40
30
20
195
190
10
0
10
100
1000
25
-40
85
Temperature (°C)
Reset Comparator Overdrive (mV)
VRST - VCC
VCC = 3.3 V
Figure 9. Maximum Transient Duration
vs Reset Comparator Overdrive
Figure 8. Reset Timeout Period vs Temperature
8
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
Typical Characteristics (continued)
39
37
35
33
31
29
27
25
-40
-20
0
20
40
60
80
Temperature (oC)
Figure 10. Low-Line Comparator Propagation Delay vs Temperature
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
7 Detailed Description
7.1 Overview
The LM3704 microprocessor supervisory circuit monitors power supplies and battery-controlled functions in
systems and does not require external components. There is a standard reset threshold voltage of 3.08 V while
other custom reset threshold voltages are available to provide maximum monitoring flexibility. The RESET pin
pulses low for the reset time-out period when triggered and stays low whenever VCC is below the reset threshold
or when MR is below VMRT. Once the VCC rises above the reset threshold, or after MR input rises above VMRT
,
the RESET pin remains low for the reset timeout period before coming up.
7.2 Functional Block Diagram
VCC
hꢃ9b for 'ò' versions;
/hbb9/Ç for 'ó'
versions
weset ꢂetect
+
w9{9Çꢅw9{9Ç
hÜÇꢃÜÇ
weset [ogic &
hne-{ꢁot
Çimer
-
[[h
/omparator
56 k
+
-
[[h
ꢄanual weset
/omparator
+
-
ꢄw
ꢃCL
ꢃoꢆer Cail
/omparator
+
-
ꢃCh
.andgap weference
1ꢀ225 ë
/opyrigꢁt © 2016, Çexas Lnstruments Lncorporated
7.3 Feature Description
7.3.1 Reset Output
The reset input of a µP initializes the device into a known state. The LM3704 microprocessor supervisory circuit
asserts a forced reset output to prevent code execution errors during power-up, power-down, and brownout
conditions.
RESET is ensured valid for VCC > 1 V. Once VCC exceeds the reset threshold, an internal timer maintains the
output for the reset time-out period. After this interval, reset goes high. The LM3704 offers an active-low RESET.
Any time VCC drops below the reset threshold (such as during a brownout), the reset activates. When VCC again
rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for
longer than the reset time-out period. After this time, reset releases.
10
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
Feature Description (continued)
The Manual Reset input (MR) initiates a forced reset also. See Manual Reset Input (MR).
7.3.2 Reset Threshold
The LM3704 is available with a reset voltage of 3.08 V. Other reset thresholds in the 2.20-V to 5-V range, in
steps of 10 mV, are available; contact Texas Instruments for details.
7.3.3 Manual Reset Input (MR)
Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input
is fully debounced and provides an internal 56-kΩ pullup. When the MR input is pulled below VMRT (1.225 V) for
more than 25 µs, reset is asserted after a typical delay of 12 µs. Reset remains active as long as MR is held low,
and releases after the reset time-out period expires after MR rises above VMRT. Use MR with digital logic to
assert or to daisy chain supervisory circuits. It may be used as another low-line comparator by adding a buffer.
7.3.4 Power-Fail Comparator (PFI/PFO)
The PFI is compared to a 1.225-V internal reference, VPFT. If PFI is less than VPFT, the Power-Fail Output (PFO)
drops low. The power-fail comparator signals a falling power supply, and is driven typically by an external voltage
divider that senses either the unregulated supply or another system supply voltage. The voltage divider generally
is chosen so the voltage at PFI drops below VPFT several milliseconds before the main supply voltage drops
below the reset threshold, providing advanced warning of a brownout.
The voltage threshold is set by R1 and R2 and is calculated with Equation 1.
R1 + R2
)
x 1.225ë
(
VPFT
=
(1)
NOTE
This comparator is completely separate from the rest of the circuitry, and may be
employed for other functions as needed.
7.3.5 Low-Line Output (LLO)
The low-line output comparator is typically used to provide a non-maskable interrupt to a µP when VCC begins
falling. LLO monitors VCC and goes low when VCC falls below VLLOT (typically 1.02 × VRST) with hysteresis of
0.0032 × VRST
.
7.4 Device Functional Modes
7.4.1 RESET Output Low
Anytime VCC drops below the reset threshold, the RESET output drops low and remains low until VCC rises above
the threshold and the reset time-out period has expired. The manual reset input (MR) also causes the reset to be
active. If MR input is pulled below VMRT for more than 25 µs, the RESET output drops low and remains low until
MR rises above the manual reset threshold (VMRT) and the reset time-out period has expired.
7.4.2 RESET Output High
The RESET output remains high as long as VCC is above the reset threshold and MR is above the manual reset
threshold (VMRT).
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3704 is a microprocessor supervisory circuit that provides the maximum flexibility for monitoring power
supplies and battery-controlled functions. The reset threshold is typically 3.08 V but can be customized for
voltages between 2.2 V and 5 V in 10-mV increments by contacting Texas Instruments. The power-fail input,
which is a 1.225-V threshold detector for power-fail warning, can be adjusted using a resistor divider as shown in
Figure 11. This section shows various application circuits to provide different monitoring solutions.
8.2 Typical Application
VIN2
VIN1
VCC
R1
RESE
T
RESET
mP
PFI
MR
INT
LLO
PFO
R2
GND
GND
R1
R2
.
(
(
Power-Fail Reset Threshold, VPFT = 1.225
+ 1
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Monitoring Two Critical Supplies
8.2.1 Design Requirements
The component count is minimal; employing two resistors as part of a voltage-divider circuit is all that is needed
for the typical application of monitoring two critical supplies shown in Figure 11.
8.2.2 Detailed Design Procedure
The voltage-divider circuit that connects to the power-fail reset pin is chosen such that the reset threshold at the
device is 1.225 V as shown in Figure 11.
12
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
Typical Application (continued)
8.2.3 Application Curves
VIN1 = VCC
*Reset Threshold
tRP
RESET
Standard reset threshold is 3.08 V. Custom reset voltages are available between 2.2 V and 5 V in 10-mV increments
by contacting Texas Instruments.
Figure 12. Monitoring VIN1 for Reset Condition
VIN2
Threshold set by R1 and R2 voltage-divider
PFI
=1.225 V
VPFT
PFO
MR
=1.225 V
VMRT
tRP
RESET
See Electrical Characteristics for high and low levels of this specific application.
Figure 13. Monitoring VIN2 for Reset Condition
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
8.3 System Examples
The LM3704 voltage supervisor has various features such as power-fail input detection, low-line output, and
manual reset while requiring few to no additional components making it versatile and easy-to-use. See Figure 14
through Figure 18 for a variety of circuit applications.
spacer
1.8V
1.8V
3.3V
3.3V
107k
107k
VCC
VI/O
VCORE
VI/O
Vcore
VCC
RESET
PFO
RESET
PFI
MR
PFI
MR
RESET
RESET
PFO
332k
332k
GND
GND
3.3k
(Normally
High)
FAULT
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Monitoring Two Supplies Plus Manual
Reset
Figure 15. Monitoring Dual Supplies
Plus External Fault Input
Raw Supply
(Battery)
System
Regulator
3.3V
0.1m ceramic
R1
VCC
INT
PFI
MR
PFO
mP
RESET
RESET
GND
R2
R1
R2
.
(
(
Power-Fail Reset Threshold, VPFT = 1.225
+ 1
Copyright © 2016, Texas Instruments Incorporated
MR input with its 1.225-V nominal threshold, may monitor an additional supply voltage. An internal 56-kΩ
pullup resistor is included on this input.
Figure 16. Microprocessor Supervisor
With Early Warning Detector
14
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
System Examples (continued)
VOUT
IN
VIN
OUT
ADJ
+
LM2941
GND
24.9k
14.7k
2.2mF
SD
7.15k
11.5k
VOUT = 3.3V
VCC
VIN(TRIP) = 5.0V
RESET
MR
OVERRIDE
5V
4V
VIN
3.3V
VOUT
RESET
tRP
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Regulator/Switch With Long-Term Overvoltage Lockout
Prevents Overdissipation in Linear Regulator
3.3V
VCC
RESET
MR
RESET
tRP
tRP
GND
Mechanical
Switch
MR
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Switch Debouncer
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM3704
LM3704
SNVS088F –MAY 2004–REVISED APRIL 2016
www.ti.com
9 Power Supply Recommendations
The input power supply to the VCC pin of the LM3704 must be kept at a voltage lower than the recommended
voltage of 5.5 V. All other input pins must be kept at a voltage lower than VCC + 0.3 V. Do not exceed absolute
maximum ratings found in Absolute Maximum Ratings in any circumstance.
10 Layout
10.1 Layout Guidelines
Keep traces short between IC and external components.
10.2 Layout Example
Figure 19. Layout Example for Application Circuit
16
Submit Documentation Feedback
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LM3704
LM3704
www.ti.com
SNVS088F –MAY 2004–REVISED APRIL 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 1. Table of Functions
OUTPUT
PART NUMBER
LM3704
(X = TOTEM-POLE)
(Y = OPEN-DRAIN)
RESET TIMEOUT PERIOD
X, Y
200 ms
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2016, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM3704
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3704XCMM-308/NOPB
LM3704YCMM-232/NOPB
LM3704YCMM-308/NOPB
LM3704YCMMX-308/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
10
10
10
10
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
3500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
R35B
R76B
R48B
R48B
SN
SN
SN
-40 to 85
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3704XCMM-308/NOPB VSSOP
LM3704YCMM-232/NOPB VSSOP
LM3704YCMM-308/NOPB VSSOP
DGS
DGS
DGS
DGS
10
10
10
10
1000
1000
1000
3500
178.0
178.0
178.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
LM3704YCMMX-308/NOP VSSOP
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3704XCMM-308/NOPB
LM3704YCMM-232/NOPB
LM3704YCMM-308/NOPB
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
10
10
10
10
1000
1000
1000
3500
208.0
208.0
208.0
367.0
191.0
191.0
191.0
367.0
35.0
35.0
35.0
35.0
LM3704YCMMX-308/NOP
B
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
LM3704XABP-308
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XABP-643
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XABPX-308
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XABPX-643
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XAMM-308
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XAMM-643
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XAMMX-308
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XAMMX-643
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
LM3704XBBP-308
Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output and Manual Reset
NSC
©2020 ICPDF网 联系我们和版权申明