LM3703XCBP-308 [TI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA9, PLASTIC, SMD-9;
| 型号： | LM3703XCBP-308 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA9, PLASTIC, SMD-9 |
| 文件： | 总11页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
LM3702, LM3703
www.ti.com
SNVS147C –MAY 2004–REVISED MAY 2004
LM3702/LM3703 Microprocessor Supervisory Circuits with Low Line Output and Manual
Reset
Check for Samples: LM3702, LM3703
1
FEATURES
DESCRIPTION
The LM3702/LM3703 series of microprocessor
supervisory circuits provide the maximum flexibility for
monitoring power supplies and battery controlled
functions in systems without backup batteries. The
LM3702/LM3703 series are available in a 9-bump
DSBGA package.
2
•
Standard Reset Threshold Voltage: 3.08V
•
Custom Reset Threshold Voltages: For Other
Voltages Between 2.2V and 5.0V in 10mV
Increments, Contact Texas Instruments.
•
•
•
•
•
•
No External Components Required
Manual-Reset Input
Built-in features include the following:
RESET (LM3702) or RESET (LM3703) Outputs
Precision Supply Voltage Monitor
Factory Programmable Reset Timeout Delay
Reset: Reset is asserted during power-up, power-
down, and brownout conditions. RESET is ensured
down to VCC of 1.0V.
Available in DSBGA Package for Minimum
Footprint
Manual Reset Input: An input that asserts reset when
pulled low.
•
•
•
•
±0.5% Reset Threshold Accuracy at Room
Temperature
Low Line Output: This early power failure warning
indicator goes low when the supply voltage drops to a
value which is 2% higher than the reset threshold
voltage.
±2% Reset Threshold Accuracy Over
Temperature Extremes
Reset Assertion Down to 1V VCC (RESET
Option Only)
28 µA VCC Supply Current
APPLICATIONS
•
•
•
•
Embedded Controllers and Processors
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
V
IN1
V
CC
V
CC
Reset
Reset
mP
MR
INT
LLO
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
OBSOLETE
LM3702, LM3703
SNVS147C –MAY 2004–REVISED MAY 2004
www.ti.com
Connection Diagram
Figure 1.
1
VCC
Reset
NC
MR
2
3
NC
NC
NC
A
GND
B
LLO
C
Figure 2. Top View
(looking from the coating side)
DSBGA 9 Bump Package
PIN DESCRIPTIONS
Bump No.
Name
MR
Function
A1
B1
C1
Manual-Reset input. When MR is less than VMRT (Manual Reset Threshold) RESET/RESET is engaged.
Power Supply input.
VCC
RESET
Reset Logic Output. Pulses low for tRP (Reset Timeout Period) when triggered, and stays low whenever VCC
is below the reset threshold or when MR is below VMRT. It remains low for tRP after either VCC rises above the
reset threshold, or after MR input rises above VMRT (LM3702 only).
RESET
LLO
Reset Logic Output. RESET is the inverse of RESET (LM3703 only).
C3
Low-Line Logic Output. Early Power-Fail warning output. Low when VCC falls below VLLOT (Low-Line Output
Threshold). This output can be used to generate an NMI (Non-Maskable Interrupt) to provide an early warning
of imminent power-failure.
B3
A2, A3, C2
B2
GND
NC
Ground reference for all signals.
No Connect.
NC
No Connect. Test input used at factory only. Leave floating.
Block Diagram
VCC
OPEN for 'Y'
versions; CONNECT
Reset Comparator
for 'X' versions
RESET/RESET
OUTPUT
+
Reset Logic and
-
One-Shot Timer
Low Line
Comparator
+
56k
LLO
-
1.225V
Reference
Manual Reset
Comparator
MR
+
-
2
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OBSOLETE
LM3702, LM3703
www.ti.com
SNVS147C –MAY 2004–REVISED MAY 2004
Table 1. Table Of Functions
Part Number
Active Low
Reset
Active High Output
Reset Timeout
Manual Reset
Low Line
Output
Reset
(X = totem-pole)
(Y = open-drain)
Period
LM3702
LM3703
x
X, Y(1)
Customized
Customized
x
x
x
x
x
X
(1) = available upon request. Contact TI
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VCC
All Other Inputs
ESD Ratings(3)
)
−0.3V to 6.0V
−0.3V to VCC + 0.3V
1.5kV
Human Body Model
Machine Model
150V
Power Dissipation
See(4)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:
Where the value of θJ-A for the DSBGA package is 220°C/W.
OPERATING RATINGS(1)
Temperature Range
−40°C ≤ TJ ≤ 85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
LM3702/LM3703 SERIES ELECTRICAL CHARACTERISTICS
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
VCC
Operating Voltage Range:
VCC
LM3702
LM3703
1.0
1.2
5.5
5.5
50
V
ICC
VCC Supply Current
All inputs = VCC; all outputs floating
28
µA
RESET THRESHOLD
VRST
Reset Threshold
VCC falling
−0.5
−2
+0.5
+2
VRST
%
VCC falling: TA = 0°C to 70°C
−1.5
+1.5
VRSTH
tRP
Reset Threshold Hysteresis
Reset Timeout Period
0.0032•VRST
mV
Reset Timeout Period = A
Reset Timeout Period = B
Reset Timeout Period = C
Reset Timeout Period = D
1
20
140
1120
1.4
28
200
1600
2
40
280
2240
ms
µs
tRD
VCC to Reset Delay
VCC falling at 1mV/µs
20
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OBSOLETE
LM3702, LM3703
SNVS147C –MAY 2004–REVISED MAY 2004
www.ti.com
LM3702/LM3703 SERIES ELECTRICAL CHARACTERISTICS (continued)
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RESET (LM3703)
VOL
RESET
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 1.2V, ISOURCE = 50µA
VCC > 1.8V, ISOURCE = 150µA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
VRESET = 5.5V
0.3
0.3
0.4
V
VOH
RESET
0.8 VCC
0.8 VCC
0.8 VCC
0.8 VCC
CC − 1.5V
V
V
ILKG
Output Leakage Current
1.0
µA
RESET (LM3702)
VOL
RESET
VCC > 1.0V, ISINK = 50µA
0.3
0.3
0.3
0.3
0.4
VCC > 1.2V, ISINK = 100µA
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
V
VOH
RESET
0.8 VCC
0.8 VCC
CC − 1.5V
V
MR
VMRT
MR Input Threshold
MR, Low
0.8
75
V
MR, High
2.0
35
25
VMRTH
RMR
tMD
MR Threshold Hysteresis
MR Pull-up Resistance
MR to Reset Delay
MR Pulse Width
MR falling: VCC = VRST MAX to 5.5V
0.0032•VRST
mV
kΩ
µS
µS
56
12
tMR
LLO
VOL
LLO Output Voltage
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.3
0.3
0.4
V
VOH
0.8 VCC
0.8 VCC
CC − 1.5V
V
LLO OUTPUT
VLLOT
LLO Output Threshold
(VLLO − VRST, VCC falling)
1.01•VRST
1.02•VRST
0.0032•VRST
20
1.03•VRST
V
VLLOTH
tCD
Low-Line Comparator
Hysteresis
mV
µs
Low-Line Comparator Delay
VCC falling at 1mV/µs
4
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OBSOLETE
LM3702, LM3703
www.ti.com
SNVS147C –MAY 2004–REVISED MAY 2004
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
3.3V Supply Current vs Temperature
30
25
30
29
28
20
15
10
27
26
25
5
0
24
23
25
70
85
-40
0
5
1
3
4
2
Temperature (°C)
Supply Voltage (V)
Figure 3.
Figure 4.
Normalized Reset Threshold Voltage vs Temperature
Reset Timeout Period vs VCC
0.5
220
215
210
0.4
0.3
0.2
205
200
195
190
0.1
0
-0.1
-0.2
-0.3
185
180
-0.4
-0.5
5.5
5
6
3.0
4.5
-40
25
85
3.5
4
Temperature (°C)
Supply Voltage (V)
Figure 5.
Figure 6.
Max. Transient Duration vs Reset Comparator Overdrive
Reset Timeout Period vs Temperature
(VCC = 3.3V)
215
80
70
60
50
40
210
205
200
30
20
195
190
10
0
25
-40
85
10
100
1000
Temperature (°C)
Reset Comparator Overdrive (mV)
VRST - VCC
Figure 7.
Figure 8.
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LM3702, LM3703
SNVS147C –MAY 2004–REVISED MAY 2004
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Low-Line Comparator Propagation Delay vs Temperature
39
37
35
33
31
29
27
25
-40
-20
0
20
40
60
80
Temperature (oC)
Figure 9.
6
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Product Folder Links: LM3702 LM3703
OBSOLETE
LM3702, LM3703
www.ti.com
SNVS147C –MAY 2004–REVISED MAY 2004
CIRCUIT INFORMATION
RESET OUTPUT
The Reset input of a µP initializes the device into a known state. The LM3702/LM3703 microprocessor
supervisory circuits assert a forced reset output to prevent code execution errors during power-up, power-down,
and brownout conditions.
RESET is ensured valid for VCC > 1V. Once VCC exceeds the reset threshold, an internal timer maintains the
output for the reset timeout period. After this interval, reset goes high. The LM3702 offers an active-low RESET;
The LM3703 offers an active-high RESET.
Any time VCC drops below the reset threshold (such as during a brownout), the reset activates. When VCC again
rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for
longer than the reset timeout period. After this time, reset releases.
The Manual Reset input (MR) will initiate a forced reset also. See the MANUAL RESET INPUT (MR) section.
RESET THRESHOLD
The LM3702/LM3703 family is available with a reset voltage of 3.08V. Other reset thresholds in the 2.20V to
5.0V range, in steps of 10 mV, are available; contact TI for details.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input
is fully debounced and provides an internal 56 kΩ pull-up. When the MR input is pulled below VMRT (1.225V) for
more than 25 µs, reset is asserted after a typical delay of 12 µs. Reset remains active as long as MR is held low,
and releases after the reset timeout period expires after MR rises above VMRT. Use MR with digital logic to assert
or to daisy chain supervisory circuits. It may be used as another low-line comparator by adding a buffer.
LOW-LINE OUTPUT (LLO)
The low-line output comparator is typically used to provide a non-maskable interrupt to a µP when VCC begins
falling. LLO monitors VCC and goes low when VCC falls below VLLOT (typically 1.02 • VRST) with hysteresis of
0.0032 • VRST
.
SPECIAL PRECAUTIONS FOR THE DSBGA PACKAGE
As with most integrated circuits, the LM3702 and LM3703 are sensitive to exposure from visible and infrared (IR)
light radiation. Unlike a plastic encapsulated IC, the DSBGA package has very limited shielding from light, and
some sensitivity to light reflected from the surface of the PC board or long wavelength IR entering the die from
the side may be experienced. This light could have an unpredictable affect on the electrical performance of the
IC. Care should be taken to shield the device from direct exposure to bright visible or IR light during operation.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques which are detailed in TI Application Note AN-1112
(SNVA009). Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should
be noted that the pad style which must be used with the 9-pin package is the NSMD (non-solder mask defined)
type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
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SNVS147C –MAY 2004–REVISED MAY 2004
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Timing Diagrams
Figure 10. LM3702 Reset Time with MR
Figure 11. LLO Output
8
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OBSOLETE
LM3702, LM3703
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SNVS147C –MAY 2004–REVISED MAY 2004
Typical Application Circuits
VIN
VOUT
C
VCC
RESET
R
GND
VRSTH
VIN
VOUT
RESET
tRP
Figure 12. LM3703 Power-On Delay
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SNVS147C –MAY 2004–REVISED MAY 2004
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VIN
IN
VOUT
OUT
+
LM2941
24.9k
14.7k
2.2mF
ADJ
SD
GND
7.15k
11.5k
VOUT = 3.3V
VCC
VIN(TRIP) = 5.0V
RESET
MR
OVERRIDE
5V
4V
VIN
3.3V
VOUT
tRP
RESET
Figure 13. Regulator/Switch with Long-Term Overvoltage Lockout Prevents Overdissipation in Linear
Regulator
3.3V
VCC
RESET
MR
RESET
tRP
tRP
GND
Mechanical
Switch
MR
Figure 14. Switch Debouncer
10
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