LM3509SDX/NOPB [TI]
用于白光 LED 和/或 OLED 显示屏的高效升压，具有双路电流阱 | DSC | 10 | -40 to 85;
| 型号： | LM3509SDX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于白光 LED 和/或 OLED 显示屏的高效升压，具有双路电流阱 | DSC | 10 | -40 to 85 驱动 光电二极管 接口集成电路 |
| 文件： | 总31页 (文件大小：2542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3509
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SNVS495D –FEBRUARY 2007–REVISED MAY 2013
LM3509 High Efficiency Boost for White LED's and/or OLED Displays with Dual Current
Sinks and I2C Compatible Brightness Control
Check for Samples: LM3509
1
FEATURES
APPLICATIONS
2
•
Integrated OLED Display Power Supply and
LED Driver
•
Dual Display LCD Backlighting for Portable
Applications
•
•
Drives up to 10 LED’s at 30mA
•
•
Large Format LCD Backlighting
OLED Panel Power Supply
Drives up to 5 LED’s at 20mA and Delivers up
to 21V at 40mA
DESCRIPTION
•
•
•
Over 90% Efficient
The LM3509 current mode boost converter offers two
separate outputs. The first output (MAIN) is a
constant current sink for driving series white LED’s.
The second output (SUB/FB) is configurable as a
constant current sink for series white LED bias, or as
a feedback pin to set a constant output voltage for
powering OLED panels.
32 Exponential Dimming Steps
0.15% Accurate Current Matching Between
Strings
•
•
•
•
•
•
Internal Soft-Start Limits Inrush Current
True Shutdown Isolation for LED’s
Wide 2.7V to 5.5V Input Voltage Range
21V Over-Voltage Protection
1.27MHz Fixed Frequency Operation
Low Profile 10-Pin WSON Package (3mm x
3mm x 0.8mm)
•
•
General Purpose I/O
Active Low Hardware Reset
Typical Application Circuits
10 mH
30 mA per string
OVP
SW
2.7V to 5.5V
IN
C
IN
C
OUT
1 mF
1 mF
LM3509
VIO
10 kW
10 kW
SCL
SDA
MAIN
SUB/FB
RESET/GPIO SET
GND
R
8 kW
SET
Dual White LED Bias Supply
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM3509
SNVS495D –FEBRUARY 2007–REVISED MAY 2013
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DESCRIPTION (CONTINUED)
When configured as a dual output white LED bias supply, the LM3509 adaptively regulates the supply voltage of
the LED strings to maximize efficiency and insure the current sinks remain in regulation. The maximum current
per output is set via a single external low power resistor. An I2C compatible interface allows for independent
adjustment of the LED current in either output from 0 to max current in 32 exponential steps. When configured as
a white LED + OLED bias supply the LM3509 can independently and simultaneously drive a string of up to 5
white LED’s and deliver a constant output voltage of up to 21V for OLED panels.
Output over-voltage protection shuts down the device if VOUT rises above 21V allowing for the use of small sized
low voltage output capacitors. The LM3509 is offered in a small 10-pin thermally- enhanced WSON package and
operates over the -40°C to +85°C temperature range.
2
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SNVS495D –FEBRUARY 2007–REVISED MAY 2013
10 mH
V
= 18V
OLED
SW
2.7V to 5.5V
IN
OVP
C
C
IN
OUT
R1
1 mF
2.2 mF
LM3509
20 mA
40 mA
140 kW
VIO
OLED
Display
10 kW
10 kW
SCL
SDA
MAIN
SUB/FB
R2
10 kW
RESET/GPIO
GND
SET
R
SET
12 kW
OLED Panel Power Supply
Connection Diagram
Top View
BOTTOM VIEW
TOP VIEW
1
10
9
10
9
1
2
2
3
DAP
8
DAP
3
4
8
7
7
4
5
5
6
6
Figure 1. 10-Pin WSON (3mm × 3mm × 0.8mm)
PIN DESCRIPTIONS
Function
Pin
1
Name
MAIN
Main Current Sink Input.
2
SUB/FB
SET
Secondary Current Sink Input or 1.25V Feedback Connection for Constant Voltage Output.
LED Current Setting Connection. Connect a resistor from SET to GND to set the maximum LED
3
current into MAIN or SUB/FB (when in LED mode), where ILED_MAX = 192×1.244V/RSET
.
4
5
6
7
VIO
Logic Voltage Level Input
RESET/GPIO
SW
Active Low Hardware Reset and Programmable General Purpose I/O.
Drain Connection for Internal NMOS Switch
OVP
Over-Voltage Protection Sense Connection. Connect OVP to the positive terminal of the output
capacitor.
8
IN
Input Voltage Connection. Connect IN to the input supply, and bypass to GND with a 1µF ceramic
capacitor.
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PIN DESCRIPTIONS (continued)
Pin
9
Name
SDA
SCL
Function
Serial Data Input/Output
10
Serial Clock Input
Ground
DAP
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
VIN
−0.3V to 6V
−0.3V to 25V
−0.3V to 23V
−0.3V to 6V
Internally Limited
+150ºC
VSW, VOVP
,
VSUB/FB, VMAIN
VSCL, VSDA, VRESET\GPIO, VIO , VSET
Continuous Power Dissipation
Junction Temperature (TJ-MAX
Storage Temperature Range
Maximum Lead Temperature (Soldering, 10s)(4)
)
-65ºC to +150º C
+300°C
ESD Rating(5)
Human Body Model
2.5kV
(1) Absolute maximum ratings are limits beyond which damages to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instrument Sales Office/ Distributors for availability and
specifications.
(3) All voltages are with respect to the potential at the GND pin.
(4) For detailed soldering specifications and information, please refer to Application Note 1187: Leadless Lead frame Package (AN-1187)
(Literature Number SNOA401).
(5) The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7).
Operating Ratings(1)(2)
VIN
2.7V to 5.5V
0V to 23V
VSW, VOVP
,
VSUB/FB, VMAIN
0V to 21V
Junction Temperature Range (TJ)(3)
Ambient Temperature Range (TA)(4)
-40ºC to +110ºC
-40ºC to +85ºC
(1) Absolute maximum ratings are limits beyond which damages to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150ºC (typ.) and
disengages at TJ=140ºC (typ.).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
= +105ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of
the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Thermal Properties
Junction to Ambient Thermal Resistance (θJA
(1)
)
54°C/W
(1) Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 114mm x 76mm x 1.6mm with a 2x1 array of
thermal vias. The ground plane on the board is 113mm x 75mm. Thickness of copper layers are 71.5µm/35µm/35µm/71.5µm
(2oz/1oz/1oz/2oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. The value of θJA of this product in the
WSON package could fall in a range as wide as 50ºC/W to 150ºC/W (if not wider), depending on board material, layout, and
environmental conditions. In applications where high maximum power dissipation exists special care must be paid to thermal dissipation
issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) (Literature
Number SNOA401).
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Electrical Characteristics
Specifications in standard type face are for TA = 25°C and those in boldface type apply over the Operating Temperature
Range of TA = −40°C to +85°C. Unless otherwise specified VIN = 3.6V, VIO = 1.8V, VRESET/GPIO = VIN, VSUB/FB = VMAIN = 0.5V,
(2)
RSET = 12.0kΩ, OLED = ‘0’, ENM = ENS = ‘1’, BSUB = BMAIN = Full Scale.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
21.8
Units
ILED
Output Current Regulation
MAIN or SUB/FB Enabled
18.6
UNI = ‘0’, or ‘1’
20
Maximum Current Per
Current Sink
RSET = 8.0kΩ
30
mA
(3)
ILED-MATCH
IMAIN to ISUB/FB Current
Matching
UNI = ‘1’
0.15
1.244
192
1
%
V
VSET
SET Pin Voltage
3.0V < VIN < 5V
ILED/ISET
ILED Current to ISET Current
Ratio
VREG_CS
VREG_OLED
VHR
Regulated Current Sink
Headroom Voltage
500
1.21
300
mV
V
VSUB/FB Regulation Voltage in 3.0V < VIN < 5.5V, OLED =
OLED Mode
1.172
1.239
‘1’
Current Sink Minimum
Headroom Voltage
ILED = 95% of nominal
mV
RDSON
ICL
NMOS Switch On Resistance ISW = 100mA
0.58
770
22
Ω
NMOS Switch Current Limit
VIN = 3.0V
650
21.2
19.7
1.0
875
22.9
21.2
1.4
mA
VOVP
Output Over-Voltage
Protection
ON Threshold
OFF Threshold
V
20.6
1.27
90
fSW
Switching Frequency
Maximum Duty Cycle
Minimum Duty Cycle
MHz
%
DMAX
DMIN
IQ
10
%
Quiescent Current, Device
Not Switching
VMAIN and VSUB/FB >
VREG_CS, BSUB = BMAIN =
0x00
400
440
µA
VSUB/FB > VREG_OLED
OLED=’1’, ENM=ENS=’0’
,
250
3.6
305
5
ISHDN
Shutdown Current
ENM = ENS = OLED = '0'
µA
V
RESET/GPIO Pin Voltage Specifications
VIL
Input Logic Low
Input Logic High
Output Logic Low
2.7V < VIN <5.5V, MODE bit
= 0
0.5
VIH
VOL
2.7V < VIN < 5.5V, MODE bit
= 0
1.1
V
ILOAD=3mA, MODE bit = 1
400
mV
I2C Compatible Voltage Specifications (SCL, SDA, VIO)
(4)
VIO
VIL
Serial Bus Voltage Level
Input Logic Low
2.7V < VIN < 5.5V
2.7V < VIN < 5.5V
2.7V < VIN < 5.5V
ILOAD = 3mA
1.4
VIN
0.36×VIO
VIO
V
V
VIH
VOL
Input Logic High
0.7×VIO
V
Output Logic Low
400
mV
I2C Compatible Timing Specifications (SCL, SDA, VIO, seeFigure 2)(5)(4)
t1
t2
SCL Clock Period
2.5
µs
ns
Data In Setup Time to SCL
High
100
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but represent the most
likely norm.
(3) The matching specification between MAIN and SUB is calculated as 100 × ((IMAIN or ISUB) - IAVE) / IAVE. This simplifies out to be 100 ×
(IMAIN - ISUB)/(IMAIN + ISUB).
(4) SCL and SDA signals are referenced to VIO and GND for minimum VIO voltage testing.
(5) SCL and SDA must be glitch-free in order for proper brightness control to be realized.
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Electrical Characteristics (continued)
Specifications in standard type face are for TA = 25°C and those in boldface type apply over the Operating Temperature
Range of TA = −40°C to +85°C. Unless otherwise specified VIN = 3.6V, VIO = 1.8V, VRESET/GPIO = VIN, VSUB/FB = VMAIN = 0.5V,
RSET = 12.0kΩ, OLED = ‘0’, ENM = ENS = ‘1’, BSUB = BMAIN = Full Scale.(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t3
Data Out Stable After SCL
Low
0
ns
SDA Low Setup Time to SCL
Low (Start)
4
t
100
100
ns
ns
t5
SDA High Hold Time After
SCL High (Stop)
t
1
t
t
5
4
t
2
t
3
Figure 2. I2C Timing
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SNVS495D –FEBRUARY 2007–REVISED MAY 2013
Typical Performance Characteristics
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
10 LED Efficiency
8 LED Efficiency
vs
ILED
vs
ILED
(2 Strings of 5LEDs)
(2 Strings of 4LEDs)
Figure 3.
Figure 4.
6 LED Efficiency
4 LED Efficiency
vs
ILED
vs
ILED
(2 Strings of 3LEDs)
(2 Strings of 2LEDs)
Figure 5.
Figure 6.
LED Efficiency
LED Efficiency
vs
vs
VIN
VIN
(L = TDK VLF3012AT-100MR49, RL = 0.36Ω, ILED = 40mA)
(L = TDK VLF5014AT-100MR92, RL = 0.2Ω, ILED = 60mA)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
18V OLED Efficiency
12V OLED Efficiency
vs
vs
IOUT
IOUT
Figure 9.
Figure 10.
LED Line Regulation
(UNI = '0')
OLED Line Regulation
IOLED = 60mA
Figure 11.
Figure 12.
OLED Line Regulation
IOLED = 60mA
OLED Load Regulation
VOLED = 18V
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
Peak Current Limit
OLED Load Regulation
VOLED = 12V
vs.
VIN
Figure 15.
Figure 16.
Over Voltage Limit
Switch On-Resistance
vs.
VIN
vs.
VIN
Figure 17.
Figure 18.
Switching Frequency
Maximum Duty Cycle
vs.
VIN
vs.
VIN
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
Shutdown Current
Switching Supply Current
vs.
VIN
vs.
VIN
Figure 21.
Figure 22.
LED Current Matching
LED Current Accuracy
vs.
vs
CODE(1)
CODE
(RSET = 12kΩ±0.05%)
(UNI = '1', RSET = 12kΩ, TA = -40°C to +85°C)
Figure 23.
Figure 24.
LED Current
ILED
vs
vs
CODE
Current Source Headroom Voltage
(VIN = 3V, UNI = '0')
(IMAIN, ISUB, IIDEAL, RSET = 12kΩ±0.05%)
Figure 25.
Figure 26.
(1) The matching specification between MAIN and SUB is calculated as 100 × ((IMAIN or ISUB) - IAVE) / IAVE. This simplifies out to be 100 ×
(IMAIN - ISUB)/(IMAIN + ISUB).
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Typical Performance Characteristics (continued)
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
Start-Up Waveform (LED Mode)
(2 × 5 LEDs, 30mA per string)
Start-Up Waveform (OLED Mode)
(VOUT = 18V, IOUT = 60mA)
Channel 1: SDA (5V/div)
Channel 1: SDA (5V/div)
Channel 2: VOUT (10V/div)
Channel 3: ILED (50mA/div)
Channel 4: IIN (500mA/div)
Time Base: 400µs/div
Channel 2: VOUT (10V/div)
Channel 3: IOUT (50mA/div)
Channel 4: IIN (500mA/div)
Time Base: 400µs/div
Figure 27.
Figure 28.
Load Step (OLED Mode)
(VOUT = 18V, COUT = 2.2µF)
Line Step (LED Mode)
(2 × 5 LEDs, 30mA per String, COUT = 1µF)
Channel 1: VOUT (AC Coupled, 500mV/div)
Channel 1: VOUT (AC Coupled, 500mV/div)
Channel 2: IOUT (20mA/div)
Time Base: 200µs/div
Channel 2: VIN (AC Coupled, 500mV/div)
Time Base: 200µs/div
Figure 29.
Figure 30.
Transition From OLED to OLED + 1 × 4 LED)
(VOUT = 18V, IOUT = 40mA, ILED = 20mA, COUT = 2.2µF)
RESET Functionality
Channel 2: ISUB (20mA/div)
Channel R1: IMAIN (20mA/div)
Channel 1: RESET (2V/div)
Time Base: 200ns/div
Channel 3: SDA (2V/div)
Channel 1: VOUT (AC Coupled, 200mV/div)
Channel 2: IMAIN (20mA/div)
Time Base: 400µs/div
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
VIN = 3.6V, LEDs are OSRAM (LW M67C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK
VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 8.06kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified.
GPIO Functionality
(GPIO Configured as OUTPUT, fSCL = 200kHz)
Ramp Rate Functionality
(RMP1, RMP0 = '00')
Channel 2: GPIO (2V/div)
Channel 3: SDA (2V/div)
Channel 3: SDA (2V/div)
Channel 1:SCL (2V/div)
Time Base: 40µs/div
Channel 1: IMAIN (10mA/div)
Channel 4: ISUB (10mA/div)
Time Base: 40µs/div
Figure 33.
Figure 34.
Ramp Rate Functionality
(RMP1, RMP0 = '01')
Ramp Rate Functionality
(RMP1, RMP0 = '10')
Channel 1:IMAIN (10mA/div)
Channel 3: SDA (2V/div)
Channel 4: ISUB (10mA/div)
Time Base: 200ms/div
Channel 1: IMAIN (10mA/div)
Channel 4: ISUB (10mA/div)
Time Base: 100ms/div
Figure 35.
Figure 36.
Ramp Rate Functionality
(RMP1, RMP0 = '11')
Channel 1:IMAIN (10mA/div)
Channel 4: ISUB (10mA/div)
Time Base: 400ms/div
Figure 37.
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BLOCK DIAGRAM
IN
OVP
SW
S0
S1
500 mV
1.22V
SOFT
START
Thermal
shutdown
Light
Load
OVP
ERROR
AMP
OLED
R
S
R
R
R
R
Z
0.5W
R
Driver
C
C
Osc/
Ramp
Over
Current
Protection
RESET/
GPIO
ƒ
MAIN
S0
S1
MIN
I
MAIN
VIO
OLED
SUB/FB
5 BIT
CONTROL
2
SCL
SDA
I C/
CONTROL
I
SUB/FB
5 BIT
CONTROL
1.244V
RSET
192
ILED_MAX =
1.244V
SET
GND
Figure 38. LM3509 Block Diagram
OPERATION DESCRIPTION
The LM3509 Current Mode PWM boost converter operates from a 2.7V to 5.5V input and provides two regulated
outputs for White LED and OLED display biasing. The first output, MAIN, provides a constant current of up to
30mA to bias up to 5 series white LED’s. The second output, SUB/FB, can be configured as a current source for
up to 5 series white LED’s at at 30mA, or as a feedback voltage pin to regulate a constant output voltage of up to
21V. When both MAIN and SUB/FB are configured for white LED bias the current for each LED string is
controlled independently or in unison via an I2C compatible interface. When MAIN is configured for white LED
bias and SUB/FB is configured as a feedback voltage pin, the current into MAIN is controlled via the I2C
compatible interface and SUB/FB becomes the middle tap of a resistive divider used to regulate the output
voltage of the boost converter.
The core of the LM3509 is a Current Mode Boost converter. Operation is as follows. At the start of each
switching cycle the internal oscillator sets the PWM converter. The converter turns the NMOS switch on, allowing
the inductor current to ramp while the output capacitor supplies power to the white LED’s and/or OLED panel.
The error signal at the output of the error amplifier is compared against the sensed inductor current. When the
sensed inductor current equals the error signal, or when the maximum duty cycle is reached, the NMOS switch
turns off causing the external Schottky diode to pick up the inductor current. This allows the inductor current to
ramp down causing its stored energy to charge the output capacitor and supply power to the load. At the end of
the clock period the PWM controller is again set and the process repeats itself.
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Adaptive Regulation
When biasing dual white led strings (White LED mode) the LM3509 maximizes efficiency by adaptively regulating
the output voltage. In this configuration the 500mV reference is connected to the non-inverting input of the error
amplifier via mux S2 (see Figure 38). The lowest of either VMAIN or VSUB/FB is then applied to the inverting input of
the error amplifier via mux S1. This ensures that VMAIN and VSUB/FB are at least 500mV, thus providing enough
voltage headroom at the input to the current sinks for proper current regulation.
In the instance when there are unequal numbers of LEDs or unequal currents from string to string, the string with
the highest voltage will be the regulation point.
Unison/Non-Unison Mode
Within White LED mode there are two separate modes of operation, Unison and Non-Unison. Non-Unison mode
provides for independent current regulation, while Unison mode gives up independent regulation for more
accurate matching between LED strings. When in Non-Unison mode the LED currents IMAIN and ISUB/FB are
independently controlled via registers BMAIN and BSUB respectively (see Brightness Registers (BMAIN and
BSUB) section). When in Unison mode BSUB is disabled and both IMAIN and ISUB/FB are controlled via BMAIN
only.
Start-Up
The LM3509 features an internal soft-start, preventing large inrush currents during start-up that can cause
excessive voltage ripple on the input. For the typical application circuits when the device is brought out of
shutdown the average input current ramps from zero to 450mA in 1.2ms. See Start Up Plots in the Typical
Performance Characteristics.
OLED Mode
When the LM3509 is configured for a single White LED bias + OLED display bias (OLED mode), the non-
inverting input of the error amplifier is connected to the internal 1.21V reference via MUX S2. MUX S1 switches
SUB/FB to the inverting input of the error amplifier while disconnecting the internal current sink at SUB/FB. The
voltage at MAIN is not regulated in OLED mode so when the application requires white LED + OLED panel
biasing, ensure that at least 300mV of headroom is maintained at MAIN to guarantee proper regulation of IMAIN
.
(see the Typical Performance Characteristics for a plot of ILED vs Current Source Headroom Voltage)
Peak Current Limit
The LM3509’s boost converter has a peak current limit for the internal power switch of 770mA typical (650mA
minimum). When the peak switch current reaches the current limit the duty cycle is terminated resulting in a limit
on the maximum output current and thus the maximum output power the LM3509 can deliver. Calculate the
maximum LED current as a function of VIN, VOUT, L and IPEAK as:
(IPEAK - DIL) ì h ì VIN
IOUT_MAX
where
=
VOUT
VIN ì (VOUT - VIN)
2 ì fSW ì L ì VOUT
DIL =
(1)
ƒSW = 1.27MHz. Typical values for efficiency and IPEAK can be found in the efficiency and IPEAK curves in the
Typical Performance Characteristics.
Over Voltage Protection
The LM3509's output voltage (VOUT) is limited on the high end by the Output Over-Voltage Protection Threshold
(VOVP) of 21.2V. In White LED mode during output open circuit conditions the output voltage will rise to the over
voltage protection threshold (VOVP = 21.2V min). When this happens the controller will stop switching causing
VOUT to droop. When the output voltage drops below 19.7V (min) the device will resume switching. If the device
remains in an over voltage condition the LM3509 will repeat the cycle causing the output to cycle between the
high and low OVP thresholds. See waveform for OVP condition in the Typical Performance Characteristics.
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Output Current Accuracy and Current Matching
The LM3509 provides both precise current accuracy (% error from ideal value) and accurate current matching
between the MAIN and SUB/FB current sinks. Two modes of operation affect the current matching between IMAIN
and ISUB/FB. The first mode (Non-Unison mode) is set by writing a 0 to bit 2 of the General Purpose register (UNI
bit). Non-Unison mode allows for independent programming of IMAIN and ISUB/FB via registers BMAIN and BSUB
respectively. In this mode typical matching between current sinks is 1%.
Writing a 1 to UNI configures the device for Unison mode. In Unison mode, BSUB is disabled and IMAIN and
ISUB/FB are both controlled via register BMAIN. In this mode typical matching is 0.15%.
Light Load Operation
The LM3509 boost converter operates in three modes; continuous conduction, discontinuous conduction, and
skip mode operation. Under heavy loads when the inductor current does not reach zero before the end of the
switching period the device switches at a constant frequency. As the output current decreases and the inductor
current reaches zero before the end of the switching cycle, the device operates in discontinuous conduction. At
very light loads the LM3509 will enter skip mode operation causing the switching period to lengthen and the
device to only switch as required to maintain regulation at the output.
Active Low Reset/General Purpose I/O (RESET\GPIO)
The RESET/GPIO serves as an active low reset input or as a general-purpose logic input/output. Upon power-up
of the device RESET/GPIO defaults to the active low reset mode. The functionality of RESET/GPIO is set via the
GPIO register and is detailed in Table 6. When configured as an active low reset input, (Bit 0 = 0), pulling
RESET/GPIO low automatically programs all registers of the LM3509 with 0x00. Their state cannot be changed
until RESET/GPIO is pulled high. The General Purpose I/O (GPIO) register is used to enable the GPIO function
of the RESET/GPIO pin. The GPIO register is an 8-bit register with only the 3 LSB’s active. The 5 MSB’s are not
used. When configured as an output, RESET/GPIO is open drain and requires an external pull-up resistor.
Thermal Shutdown
The LM3509 offers a thermal shutdown protection. When the die temperature reaches +140°C the device will
shutdown and not turn on again until the die temperature falls below +120°C.
I2C Compatible Interface
The LM3509 is controlled via an I2C compatible interface. START and STOP conditions classify the beginning
and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL
is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C
master always generates START and STOP conditions. The I2C bus is considered busy after a START condition
and free after a STOP condition. During data transmission, the I2C master can generate repeated START
conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA must be
stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed
when SCL is LOW.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 39. Start and Stop Sequences
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I2C Compatible Address
The chip address for the LM3509 is 0110110 (36h). After the START condition, the I2C master sends the 7-bit
chip address followed by a read or write bit (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a READ.
The second byte following the chip address selects the register address to which the data will be written. The
third byte contains the data for the selected register.
MSB
LSB
0
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Figure 40. Chip Address
Transferring Data
Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte
of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is
generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3509 pulls down
SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has
been received. Figure 41 is an example of a write sequence to the General Purpose register of the LM3509.
SCL
SDA
Register Data (06h)
Chip Address (36h)
Register Address (10h)
ACK
ACK
STOP
START
R/W
ACK
Figure 41. Write Sequence to the LM3509
Register Descriptions
There are 4, 8 bit registers within the LM3509 as detailed in Table 1.
Table 1. LM3509 Register Descriptions
Register Name
General Purpose (GP)
Hex Address
Power -On-Value
10
A0
B0
80
0xC0
0xE0
0xE0
0XF8
Brightness Main (BMAIN)
Brightness Sub (BSUB)
General Purpose
I/O (GPIO)
General Purpose Register (GP)
The General Purpose register has four functions. It controls the on/off state of MAIN and SUB/FB, it selects
between Unison or Non-Unison mode, provides for control over the rate of change of the LED current (see
Brightness Rate of Change Description), and selects between White LED and OLED mode. Figure 42 and
Table 2 describes each bit available within the General Purpose Register.
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General Purpose Register
Register Address 0x10
MSB
LSB
1
Bit 7
1
Bit 6
OLED
Bit 5
RMP1
Bit 4
RMP0
Bit 3
UNI
Bit 2
ENS
Bit 1
ENM
Bit 0
Figure 42. General Purpose Register Description
Table 2. General Purpose Register Bit Function
Bit
Name
Function
Power-On-Value
0
ENM
Enable MAIN. Writing a 1 to this bit enables the main current sink (MAIN). Writing a
0 to this bit disables the main current sink and forces MAIN high impedance.
0
1
2
ENS
UNI
Enable SUB/FB. Writing a 1 to this bit enables the secondary current sink (SUB/FB).
Writing a 0 to this bit disables the secondary current sink and forces SUB/FB high
impedance.
0
0
Unison Mode Select. Writing a 1 to this bit disables the BSUB register and causes
the contents of BMAIN to set the current in both the MAIN and SUB/FB current
sinks. Writing a 0 to this bit allows the current into MAIN and SUB/FB to be
independently controlled via the BMAIN and BSUB registers respectively.
3
4
RMP0
RMP1
Brightness Rate of Change. Bits RMP0 and RMP1 set the rate of change of the LED
current into MAIN and SUB/FB in response to changes in the contents of registers
BMAIN and BSUB (see Brightness Rate of Change Description).
0
0
5
OLED
OLED = 0 places the LM3509 in White LED mode. In this mode both the MAIN and
SUB/FB current sinks are active. The boost converter ensures there is at least
500mV at VMAIN and VSUB/FB. OLED = 1 places the LM3509 in OLED mode. In this
mode the boost converter regulates VSUB/FB to 1.25V. VMAIN is unregulated and
must be > 400mV for the MAIN current sink to maintain current regulation.
0
6
7
Don't Care
These are non-functional read only bits. They will always read back as a 1.
1
Table 3. Operational Truth Table
UNI
X
OLED
ENM
ENS
0
Result
0
0
0
1
LM3509 Disabled
1
X
MAIN and SUB/FB current sinks enabled. Current levels set by contents
of BMAIN.
1
0
0
0
0
0
0
0
0
0
1
1
X
1
0
1
MAIN and SUB/FB Disabled
SUB/FB current sink enabled. Current level set by BSUB.
MAIN current sink enabled. Current level set by BMAIN.
MAIN and SUB/FB current sinks enabled. Current levels set by contents
of BMAIN and BSUB respectively.
X
X
1
1
1
0
X
X
SUB/FB current sink disabled (SUB/FB configured as a feedback pin).
MAIN current sink enabled current level set by BMAIN.
SUB/FB current sink disabled (SUB/FB configured as a feedback pin).
MAIN current sink disabled.
* ENM ,ENS, or OLED high enables analog circuitry.
Brightness Registers (BMAIN and BSUB)
With the UNI bit (General Purpose register) set to 0 (Non-Unison mode) both brightness registers (BMAIN and
BSUB) independently control the LED currents IMAIN and ISUB/FB respectively. BMAIN and BSUB are both 8 bit,
but with only the 5 LSB’s controlling the current. The three MSB’s are don’t cares. The LED current control is
designed to approximate an exponentially increasing response of the LED current vs increasing code in either
BMAIN or BSUB (see Figure 45). Program ILED_MAX by connecting a resistor (RSET) from SET to GND, where:
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1.244V
RSET
ILED_MAX = 192 ì
(2)
With the UNI bit (General Purpose register) set to 1 (Unison mode), BSUB is disabled and BMAIN sets both IMAIN
and ISUB/FB. This prevents the independent control of IMAIN and ISUB/FB, however matching between current sinks
goes from typically 1%(with UNI = 0) to typically 0.15% (with UNI = 1). Figure 43 and Figure 44 show the register
descriptions for the Brightness MAIN and Brightness SUB registers. Table 4 and Figure 45 show IMAIN and/or
ISUB/FB vs. brightness data as a percentage of ILED_MAX
.
Brightness Main Register
Register Address 0xA0
MSB
LSB
1
Bit 7
1
Bit 6
1
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
Figure 43. Brightness MAIN Register Description
Brightness Sub Register
Register Address 0xB0
MSB
LSB
1
Bit 7
1
Bit 6
1
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
Figure 44. Brightness SUB Register Description
Table 4. ILED vs. Brightness Register Data
BMAIN or BSUB Brightness Data
% of ILED_MAX
0.000%
0.125%
0.625%
1.000%
1.125%
1.313%
1.688%
2.063%
2.438%
2.813%
3.125%
3.750%
4.375%
5.250%
6.250%
7.500%
BMAIN or BSUB Brightness Data
% of ILED_MAX
8.750%
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
10.000%
12.500%
15.000%
16.875%
18.750%
22.500%
26.250%
31.250%
37.500%
43.750%
52.500%
61.250%
70.000%
87.500%
100.000%
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120%
100%
80%
60%
40%
20%
0%
t
*
STEP
BMAIN or BSUB Code (Decimal)
* t
STEP
is the time between LED current steps
programmed via bits RMP0, RMP1
Figure 45. IMAIN or ISUB vs BMAIN or BSUB Data
Brightness Rate of Change Description
RMP0 and RMP1 control the rate of change of the LED current IMAIN and ISUB/FB in response to changes in
BMAIN and /or BSUB. There are 4 user programmable LED current rates of change settings for the LM3509 (see
Table 5).
Table 5. Rate of Change Bits
RMP0
RMP1
Change Rate (tSTEP
)
0
0
1
1
0
1
0
1
51µs/step
13ms/step
26ms/step
52ms/step
For example, if RSET = 12kΩ then ILED_MAX = 20mA. With the contents of BMAIN set to 0x1F (IMAIN = 20mA),
suppose the contents of BMAIN are changed to 0x00 resulting in (IMAIN = 0mA). With RMP0 =1 and RMP1 = 1
(52ms/step), IMAIN will change from 20mA to 0mA in 31 steps with 52ms elapsing between steps, excluding the
step from 0x1F to 0x1E, resulting in a full scale current change in 1560ms. The total time to transition from one
brightness code to another is:
ttransition = (|InitialCode - FinalCode| - 1) ì tSTEP
(3)
The following 3 additional examples detail possible scenarios when using the brightness register in conjunction
with the rate of change bits and the enable bits.
Example 1:
Step 1: Write to BMAIN a value corresponding to IMAIN = 20mA.
Step 2: Write 1 to ENM (turning on MAIN)
Step 3: IMAIN ramps to 20mA with a rate set by RMP0 and RMP1. (RMP0 and RMP1 bits set the duration spent
at one brightness code before incrementing to the next).
Step 4: ENM is set to 0 before 20mA is reached, thus the LED current fades off at a rate given by RMP0 and
RMP1 without IMAIN going up to 20mA.
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Example 2:
Step 1: ENM is 1, and BMAIN has been programmed with code 0x01. This results in a small current into MAIN.
Step 2: BMAIN is programmed with 0x1F (full scale current). This causes IMAIN to ramp toward full-scale at the
rate selected by RMP0 and RMP1.
Step 3: Before IMAIN reaches full-scale BMAIN is programmed with 0x09. IMAIN will continue to ramp to full scale.
Step 4: When IMAIN has reached full-scale value it will ramp down to the current corresponding to 0x09 at a rate
set by RMP0 and RMP1.
Example 3:
Step 1: Write to BMAIN a value corresponding to IMAIN = 20mA.
Step 2: Write a 1 to both RMP0 and RMP1.
Step 3: Write 1 to ENM (turning on MAIN).
Step 4: IMAIN ramps toward 20mA with a rate set by RMP0 and RMP1. (RMP0 and RMP1 bits set the duration
spent at one brightness code before incrementing to the next).
Step 5: After 1.04s IMAIN has ramped to 16.875% of ILED_MAX (0.16875 × 20mA = 3.375mA). Simultaneously,
RMP0 and RMP1 are both programmed with 0.
Step 6: IMAIN continues ramping from 3.375mA to 20mA, but at a new ramp rate of 51µs/step.
Table 6. GPIO Register Function
Bits 7 – 3
Data (Bit 2)
Mode (Bit 1)
Enable GPIO (Bit 0)
Function
X
X
X
0
RESET/GPIO is configured as an active low reset input.
This is the default power on state.
X
X
Logic Input
0
1
1
1
RESET/GPIO is configured as a logic input. The logic
level applied to RESET/GPIO can be read via bit 2 of the
GPIO register.
Logic Output
RESET/GPIO is configured as a logic output. A 0 in bit 2
forces RESET/GPIO low. A 1 in bit 2 forces
RESET/GPIO high impedance.
GPIO Register
Register Address 0x80
MSB
LSB
Enable
GPIO
Bit 0
1
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
Data
Bit 2
Mode
Bit 1
Figure 46. GPIO Register Description
Shutdown and Output Isolation
The LM3509 provides a true shutdown for either MAIN or SUB/FB when configured as a White LED bias supply.
Write a 0 to ENM (bit 1) of the General Purpose register to turn off the MAIN current sink and force MAIN high
impedance. Write a 0 to ENS (bit 2) of the General Purpose register to turn off the SUB/FB current sink and force
SUB/FB high impedance. Writing a 1 to ENM or ENS turns on the MAIN and SUB/FB current sinks respectively.
When in shutdown the leakage current into MAIN or SUB/FB is typically 3.6µA. See Typical Performance
Characteristics Plots for start-up responses of the LM3509 using the ENM and ENS bits in White LED and OLED
modes.
Application Information
LED Current Setting/Maximum LED Current
Connect a resistor (RSET) from SET to GND to program the maximum LED current (ILED_MAX) into MAIN or
SUB/FB. The RSET to ILED_MAX relationship is:
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1.244V
RSET
ILED_MAX = 192 ì
(4)
where SET provides the constant 1.244V output.
Output Voltage Setting (OLED Mode)
Connect Feedback resistors from the converters output to SUB/FB to GND to set the output voltage in OLED
mode (see R1 and R2 in the Typical Application Circuits (OLED Panel Power Supply). First select R2 < 100kΩ
then calculate R1 such that:
V
≈
∆
«
’
- 1
OUT
R1 = R2
÷
1.21V
◊
(5)
In OLED mode the MAIN current sink continues to regulate the current through MAIN, however, VMAIN is no
longer regulated. To avoid dropout and ensure proper current regulation the application must ensure that VMAIN
0.3V.
>
Input Capacitor Selection
Choosing the correct size and type of input capacitor helps minimize the input voltage ripple caused by the
switching of the LM3509’s boost converter. For continuous inductor current operation the input voltage ripple is
composed of 2 primary components, the capacitor discharge (delta VQ) and the capacitor’s equivalent series
resistance (delta VESR). These ripple components are found by:
DIL x D
2 x fSW x CIN
DVQ
=
and
DVESR = 2 x DIL x RESR
- VIN
V
x (VOUT
)
IN
where DIL =
2 x fSW x L x VOUT
(6)
In the typical application circuit a 1µF ceramic input capacitor works well. Since the ESR in ceramic capacitors is
typically less than 5mΩ and the capacitance value is usually small, the input voltage ripple is primarily due to the
capacitive discharge. With larger value capacitors such as tantalum or aluminum electrolytic the ESR can be
greater than 0.5Ω. In this case the input ripple will primarily be due to the ESR.
Output Capacitor Selection
The LM3509’s output capacitor supplies the LED current during the boost converters on time. When the switch
turns off the inductor energy is discharged through the diode supplying power to the LED’s and restoring charge
to the output capacitor. This causes a sag in the output voltage during the on time and a rise in the output
voltage during the off time. The output capacitor is therefore chosen to limit the output ripple to an acceptable
level depending on LED or OLED panel current requirements and input/output voltage differentials. For proper
operation ceramic output capacitors ranging from 1µF to 2.2µF are required.
As with the input capacitor, the output voltage ripple is composed of two parts, the ripple due to capacitor
discharge (delta VQ) and the ripple due to the capacitors ESR (delta VESR). For continuous conduction mode, the
ripple components are found by:
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ILED ì (VOUT - VIN)
DVQ
=
and
fSW ì VOUT ì COUT
ILED ì VOUT
≈
«
’
◊
DVESR = RESR
ì
+ DI
∆
÷
L
VIN
VIN ì (VOUT - VIN)
where
DIL =
2 ì fSW ì L ì VOUT
(7)
Table 7 lists different manufacturers for various capacitors and their case sizes that are suitable for use with the
LM3509. When configured as a dual output LED driver a 1µF output capacitor is adequate. In OLED mode for
output voltages above 12V a 2.2µF output capacitor is required.
Table 7. Recommended Output Capacitors
Manufacturer
TDK
Part Number
Value
1µF
Case Size
0603
Voltage Rating
C1608X5R1E105M
25V
25V
25V
25V
Murata
TDK
GRM39X5R105K25D539
C2012X5R1E225M
1µF
0603
2.2µF
2.2µF
0805
Murata
GRM219R61E225KA12
0805
Inductor Selection
The LM3509 is designed for use with a 10µH inductor, however 22µH are suitable providing the output capacitor
is increased 2×'s. When selecting the inductor ensure that the saturation current rating (ISAT) for the chosen
inductor is high enough and the inductor is large enough such that at the maximum LED current the peak
inductor current is less than the LM3509’s peak switch current limit. This is done by choosing:
ILED VOUT
ISAT
>
×
+ DIL where
h
VIN
V
- VIN
x (VOUT
)
IN
, and
DIL =
2 x fSW x L x VOUT
(
)
VIN x VOUT - V
IN
L >
ILED_ MAX x VOUT
≈
’
2 x fSW x VOUT x I
-
÷
÷
∆
∆
PEAK
h x VIN
«
◊
(8)
Values for IPEAK can be found in the plot of peak current limit vs. VIN in the Typical Performance Characteristics
graphs. Table 8 shows possible inductors, as well as their corresponding case size and their saturation current
ratings.
Table 8. Recommended Inductors
Manufacturer
Part Number
Value
Dimensions
ISAT
DC Resistance
TDK
VLF3012AT-
100MR49
10µH
2.6mm×2.8mm×1m
m
490mA
0.36Ω
TDK
VLF4012AT-
100MR79
10µH
10µH
3.5mm×3.7mm×1.2
mm
800mA
580mA
0.3Ω
TOKO
A997AS-100M
3.8mm×3.8mm×1.8
mm
0.18Ω
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Diode Selection
The output diode must have a reverse breakdown voltage greater than the maximum output voltage. The diodes
average current rating should be high enough to handle the LM3509’s output current. Additionally, the diodes
peak current rating must be high enough to handle the peak inductor current. Schottky diodes are recommended
due to their lower forward voltage drop (0.3V to 0.5V) compared to (0.6V to 0.8V) for PN junction diodes. If a PN
junction diode is used, ensure it is the ultra-fast type (trr < 50ns) to prevent excessive loss in the rectifier. For
Schottky diodes the B05030WS (or equivalent) work well for most designs. See Table 9 for a list of other
Schottky Diodes with similar performance.
Table 9. Recommended Schottky Diodes
Manufacturer
Diodes Inc.
Part Number
B05030WS
Package
SOD-323
SOD-323
SOD-323
Reverse Breakdown Voltage
Average Current Rating
30V
23V
30V
0.5A
1A
Philips
BAT760
ON Semiconductor
NSR0320MW2T
1A
Output Current Range (OLED Mode)
The maximum output current the LM3509 can deliver in OLED mode is limited by 4 factors (assuming continuous
conduction); the peak current limit of 770mA (typical), the inductor value, the input voltage, and the output
voltage. Calculate the maximum output current (IOUT_MAX) using the following equation:
(IPEAK - DIL) ì h ì VIN
IOUT_MAX
where
=
VOUT
VIN ì (VOUT - VIN)
2 ì fSW ì L ì VOUT
DIL =
(9)
For the typical application circuit with VOUT = 18V and assuming 70% efficiency, the maximum output current at
VIN = 2.7V will be approximately 70mA. At 4.2V due to the shorter on times and lower average input currents the
maximum output current (at 70% efficiency) jumps to approximately 105mA. Figure 47 shows a plot of IOUT_MAX
vs. VIN using the above equation, assuming 80% efficiency. In reality factors such as current limit and efficiency
will vary over VIN, temperature, and component selection. This can cause the actual IOUT_MAX to be higher or
lower.
Figure 47. Typical Maximum Output Current in OLED Mode
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Output Voltage Range (OLED Mode)
The LM3509's output voltage is constrained by 2 factors. On the low end it is limited by the minimum duty cycle
of 10% (assuming continuous conduction) and on the high end it is limited by the over voltage protection
threshold (VOVP) of 22V (typical). In order to maintain stability when operating at different output voltages the
output capacitor and inductor must be changed. Refer to Table 10 for different VOUT, COUT, and L combinations.
Table 10. Component Values for Output Voltage Selection
VOUT
18V
15V
12V
9V
COUT
2.2µF
2.2µF
4.7µF
10µF
10µF
22µF
L
VIN Range
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 4.5V
10µH
10µH
10µH
10µH
4.7µH
4.7µH
7V
5V
Layout Considerations
The WSON is a leadless package with very good thermal properties. This package has an exposed DAP (die
attach pad) at the underside center of the package measuring 1.6mm x 2.0mm. The main advantage of this
exposed DAP is to offer low thermal resistance when soldered to the thermal ground pad on the PCB. For good
PCB layout a 1:1 ratio between the package and the PCB thermal land is recommended. To further enhance
thermal conductivity, the PCB thermal ground pad may include vias to a 2nd layer ground plane. For more
detailed instructions on mounting WSON packages, please refer to Texas Instrument Application Note AN-1187
(Literature Number SNOA401).
The high switching frequencies and large peak currents make the PCB layout a critical part of the design. The
proceeding steps must be followed to ensure stable operation and proper current source regulation.
1. Divide ground into two planes, one for the return terminals of COUT, CIN and the I2C Bus, the other for the
return terminals of RSET and the feedback network. Connect both planes to the exposed PAD, but nowhere
else.
2. Connect the inductor and the anode of D1 as close together as possible and place this connection as close
as possible to the SW pin. This reduces the inductance and resistance of the switching node which
minimizes ringing and excess voltage drops. This will improve efficiency and decrease noise that can get
injected into the current sources.
3. Connect the return terminals of the input capacitor and the output capacitor as close as possible to the
exposed PAD and through low impedance traces.
4. Bypass IN with at least a 1µF ceramic capacitor. Connect the positive terminal of this capacitor as close as
possible to IN.
5. Connect COUT as close as possible to the cathode of D1. This reduces the inductance and resistance of the
output bypass node which minimizes ringing and the excess voltage drops. This will improving efficiency and
decrease noise that can get injected into the current sources.
6. Route the traces for RSET and the feedback divider away from the SW node to minimize noise injection.
7. Do not connect any external capacitance to the SET pin.
24
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LM3509
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SNVS495D –FEBRUARY 2007–REVISED MAY 2013
REVISION HISTORY
Changes from Revision C (May 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3509SD/NOPB
LM3509SDE/NOPB
LM3509SDX/NOPB
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
DSC
DSC
DSC
10
10
10
1000 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
L3509
L3509
L3509
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3509SD/NOPB
LM3509SDE/NOPB
LM3509SDX/NOPB
WSON
WSON
WSON
DSC
DSC
DSC
10
10
10
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3509SD/NOPB
LM3509SDE/NOPB
LM3509SDX/NOPB
WSON
WSON
WSON
DSC
DSC
DSC
10
10
10
1000
250
208.0
208.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
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