LM34926MRX/NOPB [TI]
适用于隔离式直流/直流转换器的 7.5V 至 100V 宽输入电压、300mA 集成二次侧偏置稳压器 | DDA | 8 | -40 to 125;
| 型号： | LM34926MRX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于隔离式直流/直流转换器的 7.5V 至 100V 宽输入电压、300mA 集成二次侧偏置稳压器 | DDA | 8 | -40 to 125 转换器 稳压器 |
| 文件： | 总32页 (文件大小：1855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
LM34926 用于隔离式 DC-DC 转换器的集成二次侧偏置稳压器
1 特性
3 说明
1
•
7.5V 至 100V 宽输入范围
LM34926 稳压器 具有 实现低成本高效率的隔离式偏
置稳压器所需的全部功能。此高压稳压器包含两个
100V N 通道 MOSFET 开关 — 一个高侧降压开关和
一个低侧同步开关。LM34926 所采用的恒定导通时间
(COT) 控制方案无需环路补偿，可提供出色的瞬态响
应。此稳压器的运行通过导通时间控制，该时间与输入
电压成反比。此特性使得工作频率能够保持相对恒定。
使用集成感测电路来执行智能峰值电流限制。其他 特
性 包括一个用于抑制低压条件下运行的可编程输入欠
压比较器。保护 特性 包括热关断和 VCC 欠压锁定
(UVLO)。LM34926 器件采用 WSON-8 和 SO
PowerPAD-8 塑料封装。
•
集成了 300mA 高侧
和低侧开关
•
•
•
•
•
•
•
•
•
•
•
•
•
无需肖特基二极管
恒定导通时间控制
无需环路补偿
超快瞬态响应
接近恒定的运行频率
智能峰值电流限制
可调节输出电压（以 1.225V 为基准电压）
2% 的反馈基准电压精度
频率可调至 1MHz
可调低压闭锁 (UVLO)
远程关断
器件信息(1)
器件型号
LM34926
封装
封装尺寸（标称值）
4.89mm × 3.90mm
4.00mm x 4.00mm
热关断
HSOP (8)
WSON (8)
封装：
–
–
晶圆级小外形无引线 (WSON)-8
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
小外形尺寸 (SO) PowerPAD™-8 封装
使用 LM34926 并借助 WEBENCH® 电源设计器创
•
建定制设计方案
2 应用
•
•
隔离式电信偏压电源
隔离式汽车和工业用电子元件
典型应用
VOUT2
D1
+
C
OUT2
N
S
LM34926
VIN
7
8
7.5V-100V
BST
2
4
+
X1
V
VOUT1
IN
C
+
BST
+
SW
C
IN
RON
N
P
R
UV2
UV1
R
ON
6
5
VCC
FB
R
r
3
R
FB2
UVLO
D2
+
R
RTN
C
VCC
C
OUT1
R
FB1
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVS847
LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Ratings............................ 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持................................................................ 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
Changes from Revision E (December 2014) to Revision F
Page
•
•
•
•
•
向数据表中添加了 WEBENCH 链接 ....................................................................................................................................... 1
Deleted lead temperature from the Absolute Maximum Ratings table .................................................................................. 5
Changed TON vs VIN and RON in Typical Characteristics ....................................................................................................... 7
Changed 14 V to 13 V in VCC Regulator section ................................................................................................................. 11
添加了接收文档更新通知 部分.............................................................................................................................................. 22
Changes from Revision D (December 2013) to Revision E
Page
•
已添加 添加了引脚配置和功能 部分、处理额定值 表、开关特性 表、特性 说明 部分、器件功能模式、应用和实施 部
分、电源建议 部分、布局 部分、器件和文档支持 部分，以及机械、封装和可订购信息 部分 ............................................... 1
CMS 申请编号：C1411181 .................................................................................................................................................... 1
Changed Thermal Information table....................................................................................................................................... 5
Changed Control Overview section...................................................................................................................................... 10
Changed Soft-Start Circuit, Isolated Fly-Buck Converter graphics. ..................................................................................... 14
Deleted Lowest Part Count Isolated Application Schematic ............................................................................................... 20
•
•
•
•
•
Changes from Revision C (December 2013) to Revision D
Page
•
Added Thermal Parameters ................................................................................................................................................... 5
2
版权 © 2012–2017, Texas Instruments Incorporated
LM34926
www.ti.com.cn
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
Changes from Revision B (March 2013) to Revision C
Page
•
•
•
已更改 按照 TI 标准，更改了文档格式 ................................................................................................................................... 1
已更改 将特性、典型应用、引脚说明、建议的额定运行值 中将最低工作输入电压由 9V 更改成了 7.5V............................... 1
Added Absolute Maximum Junction Temperature.................................................................................................................. 5
Changes from Revision A (March 2013) to Revision B
Page
•
Added SW to RTN (100 ns transient) in Absolute Maximum Ratings ................................................................................... 5
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to the TI standards................................................................................................ 21
Copyright © 2012–2017, Texas Instruments Incorporated
3
LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
www.ti.com.cn
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP
Top View
SW
BST
VCC
FB
1
2
3
4
8
RTN
VIN
7
HSOP
Exp Pad
UVLO
RON
6
5
NGU Package
8-Pin WSON
Top View
RTN
VIN
1
2
3
4
8
7
6
5
SW
BST
VCC
FB
WSON-8
UVLO
RON
Exp Pad
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
1
NAME
RTN
VIN
–
I
Ground
Ground connection of the integrated circuit.
Operating input range is 7.5 V to 100 V.
2
Input Voltage
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
enabled when UVLO is above 1.225 V to provide hysteresis.
When UVLO pin is pulled below 0.66 V externally, the parts goes
in shutdown mode.
Input Pin of Undervoltage
Comparator
3
UVLO
I
A resistor between this pin and VIN sets the switch on-time as a
function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
4
5
6
RON
FB
I
I
On-Time Control
Feedback
This pin is connected to the inverting input of the internal
regulation comparator. The regulation level is 1.225 V.
Output from the Internal High
Voltage Series Pass Regulator.
Regulated at 7.6 V.
The internal VCC regulator provides bias supply for the gate
drivers and other internal circuitry. A 1.0-μF decoupling capacitor
is recommended.
VCC
O
An external capacitor is required between the BST and SW pins
(0.01-μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
7
BST
I
Bootstrap Capacitor
Power switching node. Connect to the output inductor and
bootstrap capacitor.
8
–
SW
EP
O
–
Switching Node
Exposed Pad
Exposed pad must be connected to RTN pin. Connect to system
ground plane on application board for reduced thermal resistance.
4
Copyright © 2012–2017, Texas Instruments Incorporated
LM34926
www.ti.com.cn
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN
–0.3
–1.5
–5
MAX
100
UNIT
V
VIN, UVLO to RTN
SW to RTN
VIN + 0.3
VIN + 0.3
100
V
SW to RTN (100-ns transient)
BST to VCC
V
V
BST to SW
13
V
RON to RTN
–0.3
–0.3
–0.3
100
V
VCC to RTN
13
V
FB to RTN
5
V
Maximum junction temperature(3)
150
°C
°C
Storage temperature, Tstg
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The RTN pin is the GND reference electrically connected to the substrate.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
MIN
MAX
100
UNIT
VIN voltage
7.5
V
Operating junction temperature(1)
–40
125
°C
(1) High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM34926
DDA (SO
THERMAL METRICS(1)
NGU (WSON)
UNIT
PowerPAD)
8 PINS
41.1
8 PINS
41.3
3.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(bot)
ΨJB
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal characteristic parameter
Junction-to-board thermal resistance
2.4
19.2
19.1
34.7
0.3
24.4
RθJB
30.6
RθJC(top)
ΨJT
Junction-to-case (top) thermal resistance
Junction-to-top thermal characteristic parameter
37.3
6.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Copyright © 2012–2017, Texas Instruments Incorporated
5
LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
www.ti.com.cn
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless stated otherwise. See(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8.55
4.9
UNIT
VCC SUPPLY
VCC Reg VCC Regulator Output
VCC Current Limit
VIN = 48 V, ICC = 20 mA
VIN = 48 V(2)
6.25
26
7.6
V
mA
V
VCC UVLO Threshold (VCC increasing)
4.15
4.5
300
2.3
VCC UVLO Hysteresis
VCC Drop Out Voltage
mV
V
VIN = 8 V, ICC = 20 mA
Nonswitching, FB = 3 V
UVLO = 0 V
IIN Operating Current
1.75
50
mA
µA
IIN Shutdown Current
225
UNDERVOLTAGE SENSING FUNCTION
UV Threshold
UV Rising
1.19
–10
1.225
–20
1.26
-29
V
µA
V
UV Hysteresis Input Current
Remote Shutdown Threshold
Remote Shutdown Hysteresis
UV = 2.5 V
Voltage at UVLO Falling
0.32
0.66
110
mV
REGULATION AND OVERVOLTAGE COMPARATORS
Internal Reference Trip Point for Switch
ON
FB Regulation Level
1.2
1.225
1.25
V
FB Overvoltage Threshold
FB Bias Current
Trip Point for Switch OFF
1.62
60
V
nA
SWITCH CHARACTERISTICS
Buck Switch RDS(ON)
ITEST = 200 mA, BST-SW = 7 V
ITEST = 200 mA
0.8
0.45
3
1.8
1
Ω
Ω
Synchronous RDS(ON)
Gate Drive UVLO
VBST − VSW Rising
2.4
3.6
V
Gate Drive UVLO Hysteresis
CURRENT LIMIT
260
mV
Current Limit Threshold
Current Limit Response Time
OFF-Time Generator (Test 1)
OFF-Time Generator (Test 2)
THERMAL SHUTDOWN
390
575
150
12
750
mA
ns
Time to Switch Off
FB = 0.1 V, VIN = 48 V
FB = 1.0 V, VIN = 48 V
µs
µs
2.5
Tsd
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
165
20
°C
°C
(1) All limits are specified by design. All electrical characteristics having room temperature limits are tested during production at TA = 25°C.
All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
6.6 Switching Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless otherwise stated.
MIN
TYP
MAX
UNIT
ON-TIME GENERATOR
TON Test 1
VIN = 32 V, RON = 100 kΩ
VIN = 48 V, RON = 100 kΩ
VIN = 75 V, RON = 250 kΩ
VIN = 10 V, RON = 250 kΩ
270
188
350
250
460
336
ns
ns
ns
ns
TON Test 2
TON Test 3
250
370
500
TON Test 4
1880
3200
4425
MINIMUM OFF-TIME
Minimum Off-Timer
FB = 0 V
144
ns
6
Copyright © 2012–2017, Texas Instruments Incorporated
LM34926
www.ti.com.cn
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
6.7 Typical Characteristics
100
90
VIN=36V
VIN=24V
VIN=48V
80
70
60
VOUT2=10V, IOUT1=0
50
50
100
LOAD CURRENT (mA)
Figure 1. Efficiency at 750 kHz, VOUT1 = 10 V
150
200
250
300
Figure 2. VCC vs VIN
Figure 3. VCC vs ICC
Figure 4. ICC vs External VCC
Figure 6. TOFF (ILIM) vs VFB and VIN
Figure 5. TON vs VIN and RON
Copyright © 2012–2017, Texas Instruments Incorporated
7
LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
Figure 7. IIN vs VIN (Operating, Non-Switching)
Figure 8. IIN vs VIN (Shutdown)
8
Copyright © 2012–2017, Texas Instruments Incorporated
LM34926
www.ti.com.cn
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
7 Detailed Description
7.1 Overview
The LM34926 step-down switching regulator features all the functions needed to implement a low-cost, efficient,
isolated bias supply. This high-voltage regulator contains 100-V, N-channel buck and synchronous switches, is
easy to implement, and is provided in thermally enhanced SO PowerPAD-8 and WSON-8 packages. The
regulator operation is based on a constant on-time control scheme using an on-time inversely proportional to VIN.
This control scheme does not require loop compensation. Current limit is implemented with forced off-time
inversely proportional to VOUT. This scheme ensures short circuit protection while providing minimum foldback.
The simplified block diagram of the LM34926 device is shown in Functional Block Diagram.
The LM34926 device can be applied in numerous applications to efficiently regulate down higher voltages. This
regulator is well suited for 48-V telecom and automotive power bus ranges. Protection features include: thermal
shutdown, undervoltage lockout, minimum forced off-time, and an intelligent current limit.
7.2 Functional Block Diagram
LM34926
START-UP
V
CC
V
IN
REGULATOR
V UVLO
4.5V
20 µA
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
V
IN
DISABLE
ON/OFF
TIMERS
R
ON
SW
COT CONTROL
LOGIC
1.225V
FEEDBACK
FB
ILIM
COMPARATOR
OVER-VOLTAGE
1.62V
+
-
CURRENT
LIMIT
ONE-SHOT
VILIM
RTN
Copyright © 2012–2017, Texas Instruments Incorporated
9
LM34926
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 Control Overview
The LM34926 regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is switched on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RT). Following the on-time the switch remains off until the FB voltage falls
below the reference, and the forced minimum off-time has expired. When the FB pin voltage falls below the
reference and the off-time one-shot period expires, the buck switch is then turned on for another on-time one-
shot period. This continues until regulation is achieved and the FB voltage is approximately equal to 1.225 V
(typical).
In a synchronous buck converter, the low-side (sync) FET is on when the high-side (buck) FET is off. The
inductor current ramps up when the high-side switch is on and ramps down when the high-side switch is off.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be determined from Equation 1.
VOUT1
K x RON
fSW
=
where
K = 9 × 10–11
(1)
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is
determined from Equation 2.
RFB2 + RFB1
VOUT = 1.225V x
RFB1
(2)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM34926 device. In cases where the capacitor ESR is too small, additional series resistance
may be required (RC in Figure 9).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 9. However, RC slightly degrades the load regulation.
L1
VOUT
SW
LM34926
R
FB2
R
C
FB
VOUT
(low ripple)
+
C
OUT
R
FB1
Figure 9. Low Ripple Output Configuration
7.3.2 VCC Regulator
The LM34926 device contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input
pin (VIN) can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited
to 30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the UVLO threshold of 4.5 V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when the SW pin is low.
10
Copyright © 2012–2017, Texas Instruments Incorporated
LM34926
www.ti.com.cn
ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
Feature Description (continued)
At high input voltages, the power dissipated in the high-voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source, from 8.55 V to 13 V, the internal regulator is disabled.
This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high-side
switch stays on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the high-
side switch stays off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage is below
1.225 V at the end of each on-time, causing the high-side switch to turn on immediately after the minimum forced
off-time of 144 ns. The high-side switch can be turned off before the on-time is complete if peak current in the
inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62-V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high-side switch will not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM34926 device is determined by the RON resistor, and is inversely proportional to the input
voltage (VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM34926 is determined be Equation 3.
10-10 x RON
TON
=
VIN
(3)
See Figure 5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns, for proper
operation. This requirement limits the maximum frequency for each application.
7.3.6 Current Limit
The LM34926 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds
575 mA, the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-
time is controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, a
maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of
start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of
100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from Equation 4.
0.07ì V
VFB + 0.2 V
IN
TOFF(ILIM)
=
ms
(4)
The current limit protection feature is peak limited, the maximum average output will be less than the peak.
7.3.7 N-Channel Buck Switch and Driver
The LM34926 device integrates an N-channel buck switch and associated floating high voltage gate driver. The
gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage diode. A
0.01-uF ceramic capacitor connected between the BST and SW pins provides the voltage to the driver during the
on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges from VCC
through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to recharge
the bootstrap capacitor.
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LM34926
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Feature Description (continued)
7.3.8 Synchronous Rectifier
The LM34926 device provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a
path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads which would otherwise result in discontinuous operation. This feature
specifically allows the user to design a secondary regulator using a transformer winding off the main inductor to
generate the alternate regulated output voltage.
7.3.9 Undervoltage Detector
The LM34926 device contains a dual-level UVLO circuit. A summary of threshold voltages and operational states
is provided in Device Functional Modes. When the UVLO pin voltage is below 0.66 V, the controller is in a low
current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but less than 1.225 V, the controller
is in standby mode. In standby mode the VCC bias regulator is active while the regulator output is disabled. When
the VCC pin exceeds the VCC undervoltage thresholds and the UVLO pin voltage is greater than 1.225 V, normal
operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum
operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2
.
If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is
satisfied.
VIN
2
V
IN
+
C
IN
R
UV2
UV1
LM34926
3
UVLO
R
Figure 10. UVLO Resistor Setting
7.3.10 Thermal Protection
The LM34926 device should be operated so the junction temperature does not exceed 150°C during normal
operation. An internal Thermal Shutdown circuit is provided to protect the LM34926 device in the event of a
higher than normal junction temperature. When activated, typically at 165°C, the controller is forced into a low-
power reset state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures
from accidental device overheating. When the junction temperature falls below 145°C (typical hysteresis = 20°C),
the VCC regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
LM34926 uses constant on-time (COT) control scheme, in which the on-time is terminated by an on-timer, and
the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for
stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during
the off-time. Furthermore this change in feedback voltage (ΔVFB) during off-time must be large enough to
suppress any noise component present at the feedback node.
12
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Feature Description (continued)
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging and discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during off-time. The resistive ripple must exceed the capacitive ripple at the output node
(VOUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is AC-coupled using Cac to the feedback node (FB). Because this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481
Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs
(SNVA166) for more details for each ripple generation method.
Table 1. Ripple Configuration
TYPE 1
TYPE 2
TYPE 3
LOWEST COST CONFIGURATION
REDUCED RIPPLE CONFIGURATION
MINIMUM RIPPLE CONFIGURATION
VOUT
VOUT
VOUT
L1
L1
L1
C
ac
R
C
r
R
C
r
OUT
FB2
R
R
R
R
C
C
FB2
R
FB2
C
ac
To FB
To FB
GND
C
C
OUT
OUT
To FB
R
FB1
FB1
R
FB1
GND
GND
Cr = 3300 pF
Cac = 100 nF
(VIN(MIN) - VOUT) x TON
25 mV
5
C >
Ö
sw (RFB2||RFB1
)
VOUT
VREF
25 mV
ûIL(MIN)
>
x
RC
<
RrCr
25 mV
ûIL(MIN)
>
RC
7.3.12 Soft Start
A soft-start feature can be implemented with the LM34926 device using an external circuit. As shown in
Figure 11, the soft-start circuit consists of one capacitor C1, two resistors R1 and R2, and a diode D. During the
initial start-up, the VCC voltage is established before the VOUT voltage. Capacitor C1 is discharged and diode D is
thereby forward biased to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and
switching is therefore disabled. As capacitor C1 charges, the voltage at node B gradually decreases and
switching commences. VOUT will gradually rise to maintain the FB voltage at the reference voltage. Once the
voltage at node B is less than a diode drop above the FB voltage, the soft-start sequence is finished and D is
reverse-biased.
During the initial part of the start-up, the FB voltage can be approximated as shown in Equation 5. The effect of
R1 has been ignored to simplify the calculation.
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
VFB = (VCC - VD) x
(5)
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C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 when the input
voltage experiences a momentary drop to initialize the soft-start sequence.
To achieve the desired soft start, the following design guidance is recommended:
1. R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC
.
2. C1 is selected to achieve the desired start-up time which can be determined from .
RFB1 x RFB2
RFB1 + RFB2
)
tS = C1 x (R2 +
3. R1 is used to maintain the node B voltage at zero after the soft start is finished. A value larger than the
feedback resistor divider is preferred. The effect of resistor R1 is ignored.
Using the component values shown in Figure 12, selecting C1 = 1 uF, R2 = 1 kΩ, R1 = 30 kΩ results in a soft-
start time of about 2 ms.
VOUT
VCC
C
1
R
FB2
R
2
To FB
D
D
1
B
R
FB1
R
1
Figure 11. Soft-Start Circuit
7.4 Device Functional Modes
The UVLO pin controls the operating mode of the LM34926 device (see Table 2 for the detailed functional
states).
Table 2. UVLO Mode
UVLO
VCC
MODE
DESCRIPTION
VCC regulator disabled.
Switching disabled.
< 0.66 V
Disabled
Shutdown
VCC regulator enabled.
Switching disabled.
0.66 V — 1.225 V
> 1.225 V
Enabled
Standby
Standby
Operating
VCC regulator enabled.
Switching disabled.
VCC < 4.5 V
VCC > 4.5 V
VCC enabled.
Switching enabled.
14
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ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM34926 device is step-down DC-DC converter. The device is typically used to convert a higher DC voltage
to a lower DC voltage with a maximum available output current of 300 mA. Use the following design procedure to
select component values for the LM34926 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
Application Circuit: 20-V to 95-V Input and 10-V, 250-mA Output Isolated Fly-Buck™ Converter
D1
VOUT2
+
C
OUT2
N2
1 µF
X1
N1 47 µH
LM34926
0.01 µF
+
BST
VOUT1
C
BST
VIN
SW
20V-95V
46.4 kΩ
R
1 nF
C
V
IN
r
r
+
+
+
C
OUT1
C
BYP
0.1 µF
RON
R
UV2
C
IN
C
ac
0.1 µF
D2
1 µF
R
ON
130 kΩ
1 µF
127 kΩ
R
FB2
VCC
FB
UVLO
7.32 kΩ
R
UV1
RTN
+
8.25 kΩ
C
VCC
R
FB1
1 µF
1 kΩ
Figure 12. Isolated Fly-Buck™ Converter Using LM34926
8.2.1 Design Requirements
Selection of external components is illustrated through a design example. Table 3 lists the design example
specifications.
Table 3. Buck Converter Design Specifications
DESIGN PARAMETERS
VALUE
20 V to 95 V
10 V
Input Voltage Range
Primary Output Voltage
Secondary (Isolated) Output Voltage
Maximum Output Current (Primary + Secondary)
Maximum Power Output
9.5 V
250 mA
2.5 W
Nominal Switching Frequency
750 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM34926 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2
8.2.2.3 Total IOUT
The total primary referred load current is calculated by multiplying the isolated output loads by the turns ratio of
the transformer as shown in Equation 6.
N2
IOUT(MAX) = IOUT1 +IOUT2
ì
= 0.25 A
N1
(6)
8.2.2.4 RFB1, RFB2
The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2
.
RFB2
RFB1
1+
VOUT1 = 1.225V x (
)
(7)
(8)
: RFB2 = (1V.225
OUT1
x RFB1 = 7.16 kW
-1
)
8.2.2.5 Frequency Selection
Equation 1 is used to calculate the value of RON required to achieve the desired switching frequency.
VOUT1
K x RON
fSW
=
where
K = 9 × 10–11
(9)
For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is selected
for this design to allow for second-order effects at high switching frequency that are not included in Equation 9.
16
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8.2.2.6 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.39-A minimum) is given by Equation 10.
N2
N1
≈
’
DIL1 = 0.39 A -IOUT1 -IOUT2
ì
ì 2 = 0.28 A
∆
÷
◊
«
(10)
Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 10, the minimum inductor value is
given by Equation 11.
V
- VOUT
VOUT
IN(MAX)
L1=
ì
= 42.6 mH
DIL1 ì ƒSW
V
IN(MAX)
(11)
A higher value of 47 µH is selected to insure the high-side switch current does not exceed the minimum peak
current limit threshold.
8.2.2.7 Primary Output Capacitor
In a conventional buck converter the output ripple voltage is calculated as shown in Equation 12.
DIL1
x f x COUT1
DVOUT
=
(12)
To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capacitor COUT1 of 0.93 µF is
required.
Figure 13 shows the primary winding current waveform (IL1) of a fly-buck converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in Equation 12 should be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by Equation 13.
N2
N1
≈
«
’
◊
I
∆ OUT2 ì
ì TON(MAX)
÷
DVOUT1
=
ö 0.16 V
COUT1
(13)
T
x I
OUT2
x N2/N1
ON(MAX)
IL1
IL2
IOUT2
T
x I
OUT2
ON(MAX)
Figure 13. Current Waveforms for COUT1 Ripple Calculation
A standard 1-µF, 25-V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value should be selected for COUT1 and/or COUT2
.
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8.2.2.8 Secondary Output Capacitor
A simplified waveform for secondary output current (IOUT2) is shown in Figure 14.
I
OUT2
I
L2
T
x I
OUT2
ON(MAX)
Figure 14. Secondary Current Waveforms for COUT2 Ripple Calculation
The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated
using Equation 14.
IOUT2 x TON (MAX)
DVOUT2
=
COUT2
(14)
For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2
.
8.2.2.9 Type III Feedback Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type
II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the
FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents
as shown in Figure 13. In the fly-buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
V
OUT
L1
C
R
r
OUT
C
r
R
FB2
C
ac
GND
To FB
R
FB1
Figure 15. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from Ripple Configuration ensures that the FB pin
ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple
component values are chosen as shown in Equation 15.
C = 1000 pF
r
C
= 0.1 mF
ac
x T
R C Ç (VIN (MIN) - VOUT
)
ON
r
r
50 mV
(15)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
18
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8.2.2.10 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 16.
N2
N1
VD1
=
VIN
(16)
For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected.
8.2.2.11 VCC and Bootstrap Capacitor
A 1-µF capacitor of 16-V or higher rating is recommended for the VCC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01-µF with a 16-V or higher rating.
8.2.2.12 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 17.
IOUT(MAX)
CIN
í
4ì ƒ ì DV
IN
(17)
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.167 μF. A standard value of 0.1 μF is selected for CBYP in this
design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power
source to the converter. A standard value of 1 μF is selected for CIN in this design. The voltage ratings of the two
input capacitors should be greater than the maximum input voltage under all conditions.
8.2.2.13 UVLO Resistors
UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 18
and Equation 19.
VIN (HYS) = IHYS x RUV2
where
IHYS = 20 μA, typical
VIN(UVLO, rising) = 1.225V x (R
(18)
(19)
UV2
+1
)
RUV1
For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 18 and Equation 19 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.
8.2.2.14 VCC Diode
Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a
voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
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8.2.3 Application Curves
VIN = 48 V
IOUT1 = 0 mA
IOUT2 = 100 mA
VIN = 48 V
Step Load on IOUT2 = 80 to 180
mA
IOUT1 = 0
Figure 17. Step Load Response
Figure 16. Steady-State Waveform
100
90
VIN=36V
VIN=24V
VIN=48V
80
70
60
50
VOUT2=10V, IOUT1=0
100 150 200
50
250
300
LOAD CURRENT (mA)
VOUT1 = 10 V
Figure 18. Efficiency at 750 kHz
20
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LM34926
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ZHCSD59F –JUNE 2012–REVISED NOVEMBER 2017
9 Power Supply Recommendations
LM34926 is a power-management device. The power supply for the device is any DC voltage source within the
specified input range.
10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. To ensure proper layout, observe the
following guidelines:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
place the input capacitor close to the IC, directly across VIN and RTN pins, and the connections to these two
pins should be direct to minimize the loop area. In general it is not possible to accommodate all of input
capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the VIN and
RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 19).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low-side gate drivers. Place these two capacitors as close to the IC as possible, and the connecting trace
lengths and loop area should be minimized (see Figure 19).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM34926. Therefore take care while routing the feedback trace to avoid coupling any
noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to any
other switching trace.
4. SW trace: SW node switches rapidly between VIN and GND every cycle and is therefore a possible source of
noise. SW node area should be minimized. In particular SW node should not be inadvertently connected to a
copper plane or pour.
10.2 Layout Example
SW
BST
VCC
FB
1
2
3
4
8
RTN
VIN
C
IN
7
HSOP
UVLO
RON
6
5
C
VCC
Figure 19. Placement of Bypass Capacitors
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 LM34926 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
PowerPAD, Fly-Buck, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
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22
版权 © 2012–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM34926MR/NOPB
LM34926MRX/NOPB
LM34926SD/NOPB
LM34926SDX/NOPB
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
NGU
NGU
8
8
8
8
95
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
S000XB
2500 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
SN
SN
SN
S000XB
L34926
L34926
ACTIVE
ACTIVE
WSON
WSON
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM34926MRX/NOPB
SO
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
PowerPAD
LM34926SD/NOPB
LM34926SDX/NOPB
WSON
WSON
NGU
NGU
8
8
1000
4500
178.0
330.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM34926MRX/NOPB
LM34926SD/NOPB
LM34926SDX/NOPB
SO PowerPAD
WSON
DDA
NGU
NGU
8
8
8
2500
1000
4500
356.0
208.0
367.0
356.0
191.0
367.0
35.0
35.0
35.0
WSON
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DDA HSOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM34926MR/NOPB
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
www.ti.com
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