LM3262 [TI]

具有旁路模式的 6MHz、800mA 微型、可调节、直流/直流降压转换器;


型号：	LM3262
厂家：	TEXAS INSTRUMENTS
描述：	具有旁路模式的 6MHz、800mA 微型、可调节、直流/直流降压转换器转换器
文件：	总32页 (文件大小：2029K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

LM3262 适用于 RF 功率放大器的具有自动旁路功能的

6MHz、800mA 微型可调降压 DC-DC 转换器

1 特性

3 说明

•

由单节锂离子电池供电运行（2.5V 至 5.5V）

LM3262 是一款 DC-DC 转换器，针对由单节锂离子电

池供电的 RF 功率放大器 (PA) 进行了优化。此外，该

器件也可用于其他应用，例如由 USB 供电的便携式

应用。该器件可将介于 2.5V-5.5V 范围内的输入电压

降转换至 0.4V-3.6V 的可调输出电压。输出电压使用

VCON 模拟输入进行设置，可提高 RF 级的 PA 效

率。

6MHz（典型值）脉宽调制 (PWM) 开关频率

可调节输出电压（0.4V 至 3.6V）

800mA 最大负载性能（旁路模式下高达 1A）

高效率（3.8 V_IN，3.4 V_OUT，500mA 时的典型效率

为 93%）

•

自动 ECO/PWM/BP 模式切换

电流过载和热过载保护

LM3262 具有 5 种工作模式。在脉宽调制 (PWM) 模式

下，该器件以 6MHz（典型值）固定频率运行，因此可

在驱动低到中等负载时最大限度地抑制 RF 干扰。轻负

载时，器件自动进入 ECO 模式并以减少的开关频率运

行。在 ECO 模式下，静态电流被减少并延长了电池使

用寿命。该器件在关断模式下处于关闭状态，电池流耗

降至 0.1µA（典型值）。在低电量状态下，旁路模式可

将压降降至 50mV（典型值）以下。此外，该器件还

具备休眠模式。

多功能 VCON 引脚

（无需使用独立 BPEN 控制）

•

软启动功能

小型片式电感，外壳尺寸为 0805 (2012)

休眠模式下的 I_Q为 25µA（典型值）

2V 步长的上升时间和下降时间为

5µs（典型值）

•

9 引脚芯片尺寸球状引脚栅格阵列 (DSBGA) 封装

2 应用

LM3262 采用 9 引脚无引线 DSBGA 封装。高开关频

率 (6MHz) 允许仅使用三个微型表面贴装组件，即一个

电感和两个陶瓷电容。

•

高速上行分组接入 (HSUPA)，采用长期演进 (LTE)

的手机

•

时分同步码分多址 (TD-SCDMA) 和分时长期演进

(TD-LTE)

器件信息⁽¹⁾

器件型号

LM3262

封装

封装尺寸（最大值）

•

手持无线电设备

DSGBA (9)

1.51mm × 1.385mm

RF PC 卡

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

电池供电类 RF 器件

由 USB 供电的便携式应用

典型应用电路

V_IN

2.5 V to 5.5V

VIN

BPEN

V_OUT= 2.5 x VCON

0.4 V to 3.6 V

10 mF

0.5 mH

LM3262

VCON

GPO1

4.7 mF

SGND

PGND

DAC

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVS875

LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

www.ti.com.cn

7.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application ................................................. 16

Power Supply Recommendations...................... 19

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics .......................................... 5

6.6 System Characteristics ............................................ 6

6.7 Timing Requirements................................................ 6

6.8 Typical Characteristics.............................................. 7

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 12

10 Layout................................................................... 20

10.1 Layout Guidelines ................................................. 20

10.2 Layout Examples................................................... 21

10.3 DSBGA Assembly and Use .................................. 25

11 器件和文档支持 ..................................................... 26

11.1 器件支持................................................................ 26

11.2 文档支持................................................................ 26

11.3 社区资源................................................................ 26

11.4 商标....................................................................... 26

11.5 静电放电警告......................................................... 26

11.6 Glossary................................................................ 26

12 机械、封装和可订购信息....................................... 26

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision N (March 2013) to Revision O

Page

•

已添加器件信息和引脚配置和功能部分，ESD 额定值和热性能信息表，特性描述，器件功能模式，应用和实施，电

源相关建议，布局，器件和文档支持以及机械、封装和可订购信息部分 ................................................................................ 1

LM3262

www.ti.com.cn

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

5 Pin Configuration and Functions

YFQ Package

9-Pin DSBGA

Top View

YFQ Package

9-Pin DSBGA

Bottom View

VCON

PGND

SGND

VCON

SGND

VIN

BPEN

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

Voltage control analog input. VCON controls V_OUTin PWM and ECO modes. VCON may also

be used to force the device into sleep mode by setting VCON < 80 mV or into bypass condition

by setting VCON > 1.5 V.

VCON

Analog

SGND

PGND

Ground

Signal ground for analog and control circuitry.

Power ground for the Power MOSFETs and gate drive circuitry

Enable Input. Set this digital input high for normal operation. For shutdown, set low. Do not

leave EN pin floating.

Digital/Input

—

Do not connect to PGND directly — Internally connected to SGND.

Switching node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum switch peak

current limit specification of the LM3262.

Analog

Input

Bypass enable input. Set this digital input high to force bypass operation. For normal operation

with automatic bypass, set low or connect to ground. Do not leave this pin floating.

BPEN

Feedback analog input and bypass FET output. Connect to the output at the output filter

capacitor.

Analog

Input

VIN

Voltage supply input for SMPS converter.

LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

−0.2

MAX

UNIT

VIN to SGND

PGND to SGND

−0.2

0.2

EN, VCON, BPEN

(SGND − 0.2)

(PGND − 0.2)

(V_IN+ 0.2)

FB, SW

Continuous power dissipation⁽³⁾

Junction temperature, T_J-MAX

Maximum lead temperature (soldering, 10 sec)

Storage temperature, T_stg

Internally limited

150

260

150

°C

−65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typical) and

disengages at T_J= 130°C (typical).

6.2 ESD Ratings

VALUE

±2000

±1250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

5.5

UNIT

Input voltage, V_IN

2.5

PWM mode

800

1000

125

°C

Recommended load current

Junction temperature, T_J

Bypass mode

–30

−30

(2)

Ambient temperature, T_A

°C

(1) All voltages are with respect to the potential at the GND pins

(2) In applications where high-power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be de-rated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

6.4 Thermal Information

LM3262

THERMAL METRIC⁽¹⁾

YFQ (DSBGA)

9 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

LM3262

www.ti.com.cn

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

6.5 Electrical Characteristics

Unless otherwise noted, all specifications apply to the 典型应用电路 with: V_IN= EN = 3.6 V and

BPEN = NC = 0 V. All typical (TYP) limits apply for T_A= T_J= 25°C, and all minimum (MIN) and maximum (MAX) apply over

the full operating ambient temperature range (−30°C ≤ T_A= T_J≤ +90°C), unless otherwise specified.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Feedback voltage at minimum

setting

V_{FB, MIN}

PWM mode, VCON = 0.16 V⁽⁴⁾

0.38

0.4

0.42

Feedback voltage at maximum

setting

V_{FB, MAX}

I_SHDN

PWM mode, VCON = 1.44 V, V_IN= 4 V

3.55

3.6

0.1

3.65

Shutdown supply current

EN = SW = VCON = FB = BPEN = NC =0 V⁽⁵⁾

µA

PWM mode, No switching

VCON = 0.13 V, FB = 1 V⁽⁶⁾

I_{Q_PWM}

PWM mode quiescent current

650

795

EN = VIN, BPEN = NC = 0V, SW = tri state

VCON < 0.8 V, FB = 2.05 V⁽⁷⁾

I_{Q_SLEEP}

Low-power sleep mode

µA

ECO mode, No switching

I_{Q_ECO}

I_LIM,P

I_{LIM, BP}

ƒ_OSC

V_IH

ECO mode quiescent current

1450

400

µA

MHz

VCON = 0.8 V, FB = 2.05 V⁽⁶⁾

PFET switch peak current limit See⁽⁸⁾

1300

310

5.7

1600

6.3

BPFET switch peak current

limit

V_FB= V_IN– 1 V

Internal oscillator frequency

EN, BPEN logic high input

threshold

1.2

EN, BPEN logic low input

threshold

V_IL

0.4

Gain

VCON to V_OUTgain

0.16 V ≤ VCON ≤ 1.44 V⁽⁹⁾

2.5

V/V

µA

I_VCON

VCON pin leakage current

VCON = 1 V

–1

Auto bypass detection

negative threshold

VCON = 1.2 V (V_OUT-SET= 3 V)

V_{BP, NEG}

165

200

235

V_IN= 3.2 V, R_L= 6 Ω (I_OUT= 500 mA)⁽¹⁰⁾

Auto bypass detection positive VCON = 1.2 V (V_OUT-SET= 3 V)

threshold

V_IN= 3.25 V, R_L= 6 Ω (I_OUT= 500 mA)⁽¹¹⁾

V_{BP, NEG}

I_{BP, SLEW}

215

250

285

BPEN = High, Forced bypass

1600

(1) All voltages are with respect to the potential at the GND pins.

(2) Minimum and maximum limits are specified by design, test, or statistical analysis.

(3) The parameters in the electrical characteristics table are tested under open loop conditions at V_IN= 3.6 V unless otherwise specified.

For performance over the input voltage range and closed-loop results, refer to Typical Characteristics.

(4) All 0.4-V V_OUTspecifications are at steady-state only.

(5) Shutdown current includes leakage current of PFET.

(6) I_qspecified here is when the device is not switching. For operating input current at no load, refer to Typical Characteristics.

(7) FB has 200 kΩ to SGND.

(8) Current limit is built-in, fixed, and not adjustable.

(9) Care should be taken to keep the VCON pin voltage less than the VIN pin voltage as this can place the device into a manufacturing test

mode.

(10) Entering bypass mode, V_INis compared to the programmed output voltage (2.5 × VCON). When V_IN− (2.5 × VCON) falls below

V_BP,NEGlonger than T_BP,NEG, the bypass FET turns on, and the switching FET turns on.

(11) Bypass mode is exited when V_IN− (2.5 × VCON) exceeds V_BP,POSlonger than T_BP,POS, and PWM mode resumes. The hysteresis for

the bypass detection threshold V_BP,POS− V_BP,NEGis always positive and is approximately 50 mV.

LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

www.ti.com.cn

6.6 System Characteristics

The following parameters are specified by design and verifications providing the component values in the 典型应用电路 are

used. These parameters are not verified by production testing. Minimum (MIN) and maximum (MAX) values are specified

over the ambient temperature range T_A= −30°C ≤ T_A≤ +90°C and over the V_INrange = 2.5 V to 5.5 V, unless otherwise

specified; L = 0.5 μH, DCR = 50 mΩ, C_IN= 10 μF, 6.3 V, 0402 (1005), C_OUT= 4.7 μF, 6.3 V, 0402 (1005). For bench

(1)

evaluation, see

PARAMETER

Maximum duty cycle

TEST CONDITIONS

MODE = LOW

MIN

TYP

MAX

UNIT

100%

2.5 V ≤ V_IN≤ 5.5 V

2.5 × VCON ≤ V_IN– 285 mV

800

Maximum output current

capability

I_OUT

2.5 V ≤ V_IN≤ 5.5 V

2.5 × VCON ≤ V_IN– 165 mV, bypass

mode

1000

–3%

–50

V_OUTlinearity

VCON = 0.16 V to 1.44 V

0 mA ≤ I_OUT≤ 800 mA⁽²⁾

V_IN= 3.8 V, V_OUT= 0.8 V

I_OUT= 10 mA, ECO mode

71%

92%

93%

V_IN= 3.8 V, V_OUT= 2.5 V

I_OUT= 200 mA, PWM mode

Efficiency

V_IN= 3.8 V, V_OUT= 3.4 V

I_OUT= 500 mA, PWM mode

V_IN= 3.6 V to 4.2 V, T_R= T_F= 10 µs,

I_OUT= 100 mA, V_OUT= 0.8 V

LINE_tr

Line transient response

Load transient response

mVpk

V_IN= 3.1/3.6/4.5 V, V_OUT= 0.8 V

I_OUT= 50 mA to 150 mA

T_R= T_F= 10 µs,

LOAD_tr

(1) When the LM3262 device is being evaluated apart from a normal system design or on a PCB other than the TI LM3262 evaluation

module, user should ensure that a 50-µF to 100-μF ceramic input capacitor is added to the PCB to keep input voltage from sagging

during rapid load transitions.

(2) Linearity limits are ±3% or ±50 mV, whichever is larger. V_OUTis monotonic in nature with respect to VCON input.

6.7 Timing Requirements

MIN

NOM

MAX

UNIT

V_OUTrise time VCON change to 90%; V_IN= 3.7 V, V_OUT= 1.4 V to 3.4 V

0.1 µs < VCON_T_R< 1 µs, RL = 12 Ω

µs

T_{VCON_TR}

V_OUTfall time VCON change to 10%; V_IN= 3.7 V, V_OUT= 3.4 V to 1.4 V

µs

0.1 µs < VCON_T_R< 1 µs, RL = 12 Ω

Turnon time (time for output to reach 95% final value after Enable low-to-

high transition)

EN = low-to-high, V_IN= 4.2 V , V_OUT= 3.4 V

T_ON

I_OUT≤ 1 mA, COUT = 4.7 µF

T_{BP, NEG}Auto bypass detect negative threshold delay time⁽¹⁾

T_{BP, POS}Auto bypass detect positive threshold delay time⁽²⁾

µs

0.1

(1) Entering bypass mode, V_INis compared to the programmed output voltage (2.5 × VCON). When V_IN− (2.5 × VCON) falls below V_BP,

_NEGlonger than T_{BP, NEG}, the bypass FET turns on, and the switching FET turns on.

(2) Bypass mode is exited when V_IN− (2.5 × VCON) exceeds V_{BP, POS}longer than T_{BP, POS}, and PWM mode resumes. The hysteresis for

the bypass detection threshold V_{BP, POS}− V_{BP, NEG}is always positive and will be approximately 50 mV.

LM3262

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ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

6.8 Typical Characteristics

V_IN= EN = 3.6 V, L = 0.5 µH, C_IN= 10 µF, C_OUT= 4.7 µF and T_A= 25°C, unless otherwise noted.

VIN = 3.0V

VIN = 3.6V

VIN = 4.2V

-35 -15

85 105

AMBIENT TEMPERATURE (°C)

SW = VCON = EN = BPEN = 0V

VCON < 80 mV

EN = V_IN

BPEN = 0

Figure 1. Shutdown Current vs Temperature

Figure 2. Sleep Mode Current vs Temperature

900

100

800

700

600

VIN = 25°C

VIN = 3.0V

500

VIN = -40°C

VIN = 3.6V

VIN = 95°C

VIN = 4.2V

400

2.5

0.5

3.0

3.5

4.0

4.5

5.0

5.5

1.0

1.5

2.0

2.5

3.0

3.5

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

No Switching

FB = 1 V

VCON = 0.13 V

Closed Loop

Switching

No load

Figure 3. Quiescent Current vs Supply Voltage

Figure 4. ECO Mode Supply Current vs Output Voltage

2.006

2.004

= -30°C

= +25°C

2.002

2.000

1.998

1.996

1.994

= +85°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

SUPPLY VOLTAGE (V)

V_OUT= 2 V

R_LOAD= 10 Ω

V_OUT= 2 V

I_OUT= 200 mA

Figure 6. Output Voltage vs Supply Voltage

Figure 5. Switching Frequency vs Temperature

LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

V_IN= EN = 3.6 V, L = 0.5 µH, C_IN= 10 µF, C_OUT= 4.7 µF and T_A= 25°C, unless otherwise noted.

V_IN= 3.8 V

V_OUT= 0.6 V

V_IN= 3.8 V

V_OUT= 2 V

Figure 7. Output Voltage vs Output Current

Figure 8. Output Voltage vs Output Current

190

VIN = 3.0V

VIN = 3.6V

VIN = 4.5V

170

150

130

110

170

150

130

110

VIN = 3.0V

VIN = 3.6V

VIN = 4.5V

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

OUTPUT VOLTAGE (V)

Figure 9. ECO-PWM Mode Threshold Current

Figure 10. PWM-ECO Mode Threshold Current

vs Output Voltage

3.0

2.5

2.0

1.5

1.0

VIN = 2.5V

VIN = 3.7V

VIN = 5.5V

0.5

0.0

-35 -15

25 45 65 85 105

AMBIENT TEMPERATURE (°C)

Figure 11. Closed-Loop Current Limit vs Temperature

Figure 12. EN High Threshold vs Supply Voltage

LM3262

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ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

Typical Characteristics (continued)

V_IN= EN = 3.6 V, L = 0.5 µH, C_IN= 10 µF, C_OUT= 4.7 µF and T_A= 25°C, unless otherwise noted.

V_IN= 3.6 V

V_OUT= 2 V

I_OUT= 200 mA

V_OUT= 2 V

I_OUT= 50 mA

Figure 13. Output Voltage Ripple in PWM Mode

Figure 14. Output Voltage Ripple in ECO Mode

V_IN= 4 V

V_OUT= 0.4 V to 3.6 V

R_LOAD= 10 Ω

V_IN= 3.6 V to 4.2 V

V_OUT= 0.6 V

I_OUT= 750 mA

Figure 15. VCON Transient Response

Figure 16. Line Transient Response

V_IN= 3.6 V

V_OUT= 0.5 V

I_OUT= 500 mA to 60 mA

V_IN= 4.2 V

V_OUT= 3.1 V

I_OUT= 200 mA to 750 mA

Figure 17. Load Transient Response

Figure 18. Load Transient Response

LM3262

ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

V_IN= EN = 3.6 V, L = 0.5 µH, C_IN= 10 µF, C_OUT= 4.7 µF and T_A= 25°C, unless otherwise noted.

V_IN= 4.2 V

V_OUT= 3.4 V

R_LOAD= 10 Ω

V_IN= 4.2 V

V_OUT= 3.4 V

R_LOAD= 3.6 kΩ

Figure 20. Shutdown

Figure 19. Start-Up

1000

900

800

700

600

500

400

300

200

100

VIN = 3.6V

VIN = 4.2V

VIN = 4.8V

VIN = 5.5V

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

VCON VOLTAGE (V)

V_OUT= 2 V

R_LOAD= 10 Ω→ 0 Ω

R_LOAD= 10 Ω

Figure 21. Timed Current Limit

Figure 22. Low VCON Voltage vs Output Voltage

LM3262

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ZHCSE56O –AUGUST 2012–REVISED DECEMBER 2015

7 Detailed Description

7.1 Overview

The LM3262 is a simple, step-down DC-DC converter optimized for powering RF power amplifiers (PAs) in

mobile phones, portable communicators, and similar battery powered RF devices. It is designed to allow the RF

PA to operate at maximum efficiency over a wide range of power levels from a single li-ion battery cell. The

device is based on a voltage-mode buck architecture, with synchronous rectification for high efficiency. It is

designed for a maximum load capability of 800 mA in PWM mode. Maximum load range may vary from this

depending on input voltage, output voltage, and the inductor chosen.

There are five modes of operation depending on the current required: pulse width modulation (PWM), ECOnomy

(ECO), bypass (BP), sleep, and shutdown. (See Table 1.) The LM3262 operates in PWM mode at higher load

current conditions. Lighter loads cause the device to automatically switch into ECO mode. Shutdown mode turns

the device off and reduces battery consumption to 0.1 µA (typical).

DC PWM mode output voltage precision is ±2% for 3.6 V_OUT. Efficiency is approximately 93% (typical) for a

500-mA load with 3.4-V output, 3.8-V input. The output voltage is dynamically programmable from 0.4 V to 3.6 V

by adjusting the voltage on the control pin (VCON) without the need for external feedback resistors. This ensures

longer battery life by being able to change the PA supply voltage dynamically depending on its transmitting

power.

Additional features include current overload protection and thermal overload shutdown.

The LM3262 is constructed using a chip-scale, 9-pin DSBGA package. This package offers the smallest possible

size for space-critical applications, such as cell phones, where board area is an important design consideration.

Use of a high switching frequency (6 MHz, typical) reduces the size of external components. As shown in the 典

型应用电路, only three external power components are required for implementation. Use of a DSBGA package

requires special design considerations for implementation. (See DSBGA Assembly and Use.) The fine bump-

pitch of the DSBGA package requires careful board design and precision assembly equipment. Use of this

package is best suited for opaque-case applications, where its edges are not subject to high-intensity ambient

red or infrared light. Also, the system controller must set EN low during power-up and other low supply voltage

conditions. (See Shutdown Mode.)

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7.2 Functional Block Diagram

VIN

EN BPEN

VCON

1.5V

ECO COMP

BYPASS

2/5

STANDBY COMP

Ref5

Ref1

OLP

OVER-VOLTAGE

DETECTOR

Ref2

VCON

DELAY

PWM

COMP.

CONTROL LOGIC

DRIVER

ERROR

AMP

RAMP

GENERATOR

NCP

Ref3

OSCILLATOR

Ref4

LIGHT-LOAD

OUTPUT SHORT

PROTECTION

THERMAL

SHUTDOWN

CHECK COMP

SGND

PGND

7.3 Feature Description

7.3.1 Circuit Operation

Referring to the Functional Block Diagram, the LM3262 operates as follows. During the first part of each

switching cycle, the control block in the LM3262 turns on the internal top-side PFET switch. This allows current to

flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of around (V_IN– V_OUT) / L, by storing energy in a magnetic field. During the second part of

each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the

bottom-side NFET synchronous rectifier on. In response, the magnetic field of the inductor collapses, generating

a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load.

As the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a

slope around V_OUT/ L. The output filter capacitor stores charge when the inductor current is high and releases it

when low, smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the

load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and

synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output

voltage is equal to the average voltage at the SW pin.

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Feature Description (continued)

7.3.2 Internal Synchronous Rectification

While in PWM mode, the LM3262 uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

With medium and heavy loads, the NFET synchronous rectifier is turned on during the inductor current down

slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET

is designed to conduct through its intrinsic body diode during transient intervals before it turns on, eliminating the

need for an external diode.

7.3.3 Current Limiting

The current limit feature allows the LM3262 to protect itself and external components during overload conditions.

In PWM mode, the cycle-by-cycle current limit is a 1450 mA (typical). If an excessive load pulls the output

voltage down to less than 0.3 V (typical), the NFET synchronous rectifier is disabled, and the current limit is

reduced to 530 mA (typical). Moreover, when the output voltage becomes less than 0.15 V (typical), the

switching frequency will decrease to 3 MHz, thereby preventing excess current and thermal stress.

7.3.4 Dynamically Adjustable Output Voltage

The LM3262 features dynamically adjustable output voltage to eliminate the need for external feedback resistors

by controlling this voltage using the analog VCON pin. The input impedance of this pin can be approximated by a

series 50-KΩ resistor and 10-pF capacitor. The output can be set from 0.4 V to 3.6 V by changing the voltage on

the analog VCON pin. This feature is useful in PA applications where peak power is needed only when the

handset is far away from the base station or when data is being transmitted. In other instances the transmitting

power can be reduced. Hence the supply voltage to the PA can be reduced, promoting longer battery life. See

Setting The Output Voltage for further details. The LM3262 moves into pulse-skipping mode when duty cycle is

over approximately 92% or less than approximately 15%, and the output voltage ripple increases slightly.

7.3.5 Thermal Overload Protection

The LM3262 has a thermal overload protection function that operates to protect itself from short-term misuse and

overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both

the PFET and the NFET are turned off. When the temperature drops below 125°C, normal operation resumes.

Prolonged operation in thermal overload conditions may damage the device and is considered bad practice.

7.3.6 Soft Start

The LM3262 has a soft-start circuit that limits in-rush current during start-up. During start-up, the switch current

limit is increased in steps. Soft start is activated if EN goes from low to high after V_INreaches 2.5 V.

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7.4 Device Functional Modes

7.4.1 PWM Mode Operation

While in PWM mode operation, the converter operates as a voltage-mode controller with input voltage feed

forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage

is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input

voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency,

then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET

switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the

switch. The current-limit comparator can also turn off the switch if the current limit of the PFET is exceeded — in

this case, the NFET switch is turned on, and the inductor current ramps down. The next cycle is initiated by the

clock turning off the NFET and turning on the PFET.

7.4.2 Bypass Mode Operation

The LM3262 contains an internal BPFET switch for bypassing the PWM DC-DC converter during bypass mode.

In bypass mode, this BPFET is turned on to power the PA directly from the battery for maximum RF output

power. When the device operates in the bypass mode, the output voltage is the input voltage less the voltage

drop across the resistance of the BPFET in parallel with the PFET plus switch inductor. Bypass mode is more

efficient than operating in PWM mode at 100% duty cycle because the combined resistance is significantly less

than the series resistance of the PWM PFET and inductor. This translates into higher voltage available on the

output in bypass mode, for a given battery voltage. The device can be forced into bypass mode by setting the

BPEN pin high or by driving the VCON control pin voltage higher than 1.5 V. This is called forced bypass mode,

and it remains in bypass mode until the BPEN pin goes low or VCON pin drops below 1.5 V. Alternatively, the

device can go into bypass mode automatically. This is called auto-bypass mode or automatic bypass mode. The

bypass switch turns on when the difference between the input voltage and programmed output voltage is less

than 200 mV (typical) for longer than 10 µs (typical). The bypass switch turns off when the input voltage is higher

than the programmed output voltage by 250 mV (typical) for longer than 0.1 µs (typical). This method is very

system resource friendly in that the bypass PFET is turned on automatically when the input voltage gets close to

the output voltage, a typical scenario of a discharging battery. It is also turned off automatically when the input

voltage rises, a typical scenario when connecting a charger. When the device is in SLEEP mode

(VCON < 80 mV), BPEN is don't care.

7.4.3 ECO Mode Operation

At very light loads (50 mA to 100 mA), the LM3262 enters ECO mode operation with reduced switching

frequency and supply current to maintain high efficiency. During ECO mode operation, the LM3262 positions the

output voltage slightly higher (7 mV typical) than the normal output voltage during PWM mode operation, allowing

additional headroom for voltage drop during a load transient from light-to-heavy load.

ECO Mode at Light Load

High ECO Threshold

Load current increases

Target Output Voltage

Low ECO Threshold

PWM Mode at Heavy Load

Figure 23. Operation in ECO Mode and Transfer to PWM Mode

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Device Functional Modes (continued)

7.4.4 Sleep Mode Operation

When VCON is less than 80 mV in 7 µs, the LM3262 goes into sleep mode — the SW pin is in tri-state (floating),

which operates like ECO mode with no switching. The LM3262 device returns to normal operation immediately

when VCON ≥ 130 mV in PWM mode or ECO mode, depending on load detection.

7.4.5 Shutdown Mode

Setting the EN digital pin low (< 0.4 V) places the LM3262 in shutdown mode (0.1 µA typical). During shutdown,

the PFET switch, the NFET synchronous rectifier, reference voltage source, control, and bias circuitry of the

LM3262 are turned off. Setting EN high (> 1.2 V) enables normal operation. EN must be set low to turn off the

LM3262 during power-up and undervoltage conditions when the power supply is less than the 2.5-V minimum

operating voltage. The LM3262 has an undervoltage lockout (UVLO) comparator to turn the power device off in

the case the input voltage or battery voltage is too low. The typical UVLO threshold is approximately 2 V for lock

and 2.1 V for release.

Table 1. Description Of Modes⁽¹⁾

MODE

Shutdown

Sleep

BPEN

VCON

I_OUT(APPROX.)

FB RES

Open

< 80 mV

Open

PWM

> 180 mA

Closed

> 130 mV

< (V_IN− 0.2)/2.5

ECO

< 140 mA

Auto bypass

> (V_IN− 0.2)/2.5

> 130 mV

Forced bypass

> 1.5 V

(1) X = Don't care.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM3262 DC-DC converter steps down an input voltage from 2.5 V to 5.5 V to a dynamically adjustable

output voltage of 0.4 V to 3.6 V.

8.2 Typical Application

V_IN

2.5 V to 5.5V

VIN

BPEN

V_OUT= 2.5 x VCON

0.4 V to 3.6 V

10 mF

0.5 mH

LM3262

VCON

GPO1

DAC

4.7 mF

SGND

PGND

Figure 24. LM3262 Typical Application

8.2.1 Design Requirements

For the typical LM3262 buck regulator, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

2.5 V to 5.5 V

0.4 V to 3.6 V

800 mA

Output voltage

Output current

8.2.2 Detailed Design Procedure

8.2.2.1 Inductor Selection

There are two main considerations when choosing an inductor: the inductor must not saturate, and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Different manufacturers follow

different saturation current rating specifications, so attention must be given to details. Saturation current ratings

are typically specified at 25°C so ratings over the ambient temperature of application should be requested from

manufacturer.

The minimum value of inductance to ensure good performance is 0.3 µH at bias current (I_LIM(typical)) over the

ambient temperature range. Shielded inductors radiate less noise and are preferred. There are two methods to

choose the inductor saturation current rating.

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8.2.2.1.1 Method 1

The saturation current must be greater than the sum of the maximum load current and the worst-case average-

to-peak inductor current. This is shown in Equation 1 :

I_SAT> I_{OUT_MAX}+ I_RIPPLE

where

≈

V_IN- V_OUT

V_OUT

V_IN

≈

I_RIPPLE

2 x L

where

•

I_RIPPLE: average-to-peak inductor current

I_{OUT_MAX}: maximum load current (800 mA)

V_IN: maximum input voltage in application

L: minimum inductor value including worst-case tolerances (30% drop can be considered for Method 1)

F: minimum switching frequency (5.7 MHz)

V_OUT: output voltage

(1)

8.2.2.1.2 Method 2

A more conservative and recommended approach is to choose an inductor than can handle the maximum

current limit of 1600 mA.

The resistance of the inductor must be less than 0.1 Ω for good efficiency. Table 3 lists suggested inductors and

suppliers.

Table 3. Suggested Inductors

MODEL

SIZE (W × L × H) (mm)

2 × 1.25 × 1

VENDOR

Murata

LQM21PNR50XGHL11

MIPSZ2012D0R5

LQM21PNR54MG0

LQM2MPNR47NG0

CIG21LR47M

2 × 1.2 × 1

FDK

2 × 1.25 × 0.9

2 × 1.6 × 0.9

2 × 1.25 × 1

Murata

Samsung

Taiyo Yuden

CKP2012NR47M

2 × 1.25 × 1

8.2.2.2 Capacitor Selection

The LM3262 is designed for use with ceramic capacitors for its input and output filters. Use a 10-µF ceramic

capacitor for input and a sum total of 4.7-µF ceramic capacitance for the output. They should maintain at least

50% capacitance at DC bias and temperature conditions. Ceramic capacitors types such as X5R, X7R, and B

are recommended for both filters. These provide an optimal balance between small size, cost, reliability, and

performance for cell phones and similar applications. Table 4 lists some suggested part numbers and suppliers.

DC-bias characteristics of the capacitors must be considered when selecting the voltage rating and case size of

the capacitor. If it is necessary to choose a 0603 (1608) size capacitor for V_INand 0402 (1005) size capacitor for

V_OUT, the operation of the LM3262 must be carefully evaluated on the system board. Use of a 2.2-µF capacitor in

conjunction with multiple 0.47-µF or 1-µF capacitors in parallel may also be considered when connecting to

power amplifier devices that require local decoupling.

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Table 4. Suggested Capacitors And Their Suppliers

CAPACITANCE

2.2 µF

MODEL

SIZE (W × L) (mm)

1 × 0.5

VENDOR

GRM155R60J225M

C1005X5R0J225M

CL05A225MQ5NSNC

C1608JB0J475M

Murata

TDK

2.2 µF

1 × 0.5

2.2 µF

1 × 0.5

Samsung

TDK

4.7 µF

1.6 × 0.8

1 × 0.5

4.7 µF

C1005X5R0J475M

CL05A475MQ5NRNC

C1608X5R0J106M

GRM155r60J106M

CL05A106MQ5NUNC

TDK

4.7 µF

1 × 0.5

Samsung

TDK

10 µF

1.6 × 0.8

1 × 0.5

10 µF

Murata

Samsung

10 µF

1 × 0.5

The input filter capacitor supplies AC current drawn by the PFET switch of the LM3262 in the first part of each

cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the

AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output

voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform

these functions. The equivalent series resistance (ESR) of the filter capacitors is generally a major factor in

voltage ripple.

8.2.2.3 Setting The Output Voltage

The LM3262 features a pin-controlled adjustable output voltage to eliminate the need for external feedback

resistors. It can be programmed for an output voltage from 0.4 V to 3.6 V by setting the voltage on the VCON

pin, as in Equation 2:

V_OUT= 2.5 × VCON

(2)

When VCON is between 0.16 V and 1.44 V, the output voltage follows proportionally by 2.5 × VCON.

If VCON is less than 0.16 V (V_OUT= 0.4 V), the output voltage may not be well regulated. Refer to Figure 22 for

details. This curve exhibits the characteristics of a typical part, and the performance cannot be ensured as there

may be a part-to-part variation for output voltages less than 0.4 V. For V_OUTlower than 0.4 V, the converter may

suffer from larger output ripple voltage and higher current limit operation.

8.2.2.4 FB

Typically the FB pin is connected to VOUT for regulating the output voltage maximum of 3.6 V. In any application

case, the voltage on FB pin should not exceed 4.5 V.

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8.2.3 Application Curves

100

VIN = 3.0V

VIN = 3.8V

VIN = 4.2V

VIN = 3.8V

VIN = 4.2V

100 200 300 400 500 600 700 800

OUTPUT CURRENT (mA)

100 150 200 250 300

OUTPUT CURRENT (mA)

V_OUT= 2.5 V

V_OUT= 0.8 V

Figure 26. Efficiency vs Output Current

Figure 25. Efficiency vs Output Current

100

VIN = 3.8V

VIN = 3.0V

VIN = 4.2V

VIN = 3.8V

VIN = 5.0V

VIN = 4.2V

100 200 300 400 500 600 700 800

OUTPUT CURRENT (mA)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

OUTPUT VOLTAGE (V)

V_OUT= 3.4 V

R_L=10 Ω

Figure 28. Efficiency vs Output Voltage

Figure 27. Efficiency vs Output Current

9 Power Supply Recommendations

The LM3262 device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. This input

supply should be well-regulated and able to withstand maximum input current and maintain stable voltage

without voltage drop even at load transition condition.

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10 Layout

10.1 Layout Guidelines

PC board layout is critical to successfully designing a DC-DC converter into a product. As much as a 20-dB

improvement in RX noise floor can be achieved by carefully following recommended layout practices. A properly

planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding

circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final

product yield.

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC

converter device, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading

to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or

degraded performance of the converter.

10.1.1 Energy Efficiency

Minimize resistive losses by using wide traces between the power components and doubling up traces on

multiple layers when possible.

10.1.2 EMI

By its very nature, any switching converter generates electrical noise, and the design challenge is to minimize,

contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3262,

switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components

can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained

within tolerable levels.

To minimize radiated noise:

•

Place the LM3262 switcher, input capacitor, output filter inductor, and output filter capacitor close together,

making the interconnecting traces as short as possible.

•

Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3262 and the

inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of

each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3262 by the

inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing

these loops so the current curls in the same direction prevents magnetic field reversal between the two half-

cycles and reduces radiated noise.

•

Make the current loop area(s) as small as possible.

To minimize ground-plane noise:

•

Reduce the amount of switching current that circulates through the ground plane — connect the ground

bumps of the LM3262 and its input filter capacitor together using generous component-side copper fill as a

pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) with multiple

vias. These multiple vias help to minimize ground bounce at the LM3262 by giving it a low-impedance ground

connection.

To minimize coupling to the voltage feedback trace of the DC-DC converter:

•

Route noise sensitive traces, such as the voltage feedback path, as directly as possible from the switcher FB

pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power

components.

To decouple common power supply lines, series impedances may be used to strategically isolate circuits:

•

Take advantage of the inherent inductance of circuit traces to reduce coupling among function blocks, by way

of the power supply traces.

•

Use star connection for separately routing VBATT to PVIN and VBATT_PA.

Inserting a single ferrite bead in-line with a power supply trace may offer a favorable tradeoff in terms of

board area by allowing the use of fewer bypass capacitors.

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Layout Guidelines (continued)

10.1.3 Manufacturing Considerations

The LM3262 package employs a 9-pin, 3-mm × 3-mm array of 250 micron solder balls, with a 0.4-mm pad pitch.

The following simple design rules go a long way to ensuring a good layout:

•

The pad size must be 0.225 ± 0.02 mm, and the solder mask opening must be 0.325 ± 0.02 mm.

As a thermal relief, connect to each pad with 7-mil wide, 7-mil long traces, incrementally increasing each

trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly (refer to AN-1112

DSBGA Wafer Level Chip Scale Package (SNVA009)).

10.2 Layout Examples

Figure 29. Simplified LM3262 RF Evaluation Board Schematic

1. Bulk Input Capacitor C2 must be placed closer to LM3262 than C1.

2. Add a 1-nF (C1) on input of LM3262 for high frequency filtering.

3. Bulk Output Capacitor C3 must be placed closer to LM3262 than C4.

4. Add a 1-nF (C4) on output of LM3262 for high frequency filtering.

5. Connect both GND terminals of C1 and C4 directly to system GND layer of phone board.

6. Connect bumps SGND (A2), NC (B2), BPEN (C1) directly to System GND.

7. Use 0402 caps for both C2 and C3 due to better high frequency filtering characteristics over 0603 capacitors.

8. TI has seen some improvement in high-frequency filtering for small bypass caps (C1 and C4) when they are

connected to System GND instead of same ground as PGND. These capacitors should be 01005 case size

for minimum footprint and best high frequency characteristics.

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Layout Examples (continued)

Figure 30. LM3262 Recommended Parts Placement (Top View)

10.2.1 Component Placement

•

PVIN

1. Use a star connection from PVIN to LM3262 and PVIN to PA VBATT connection (V_CC1). Do not daisy-

chain PVIN connection to LM3262 circuit and then to PA device PVIN connection.

•

TOP LAYER

1. Place a via in LM3262 SGND(A2), BPEN(C1) pads to drop and connect directly to System GND Layer 4.

2. Place two vias at LM3262 SW solder bump to drop VSW trace to Layer 3.

3. Connect C2 and C3 capacitor GND pads to PGND bump on LM3262 using a star connection. Place vias

in C2 and C3 GND pads that connect directly to System GND Layer 4.

4. Add 01005/0201 capacitor footprints (C1, C4) to input/output of LM3262 for improved high frequency

filtering. C1 and C4 GND pads connect directly to System GND Layer 4.

5. Place three vias at L1 inductor pad to bring up VSW trace from Layer 3 to Top Layer.

•

LAYER 2

1. Make FB trace at least 10 mils (0.254 mm) wide.

2. Isolate FB trace away from noisy nodes and connect directly to C3 output capacitor. Place a via in

LM3262 SGND (A2), BPEN (C1) pads to drop and connect directly to System GND Layer 4.

•

LAYER 3

1. Make VSW trace at least 15 mils (0.381 mm) wide.

LAYER 4 (System GND)

1. Connect C2 and C3 PGND vias to this layer.

2. Connect C1 and C4 GND vias to this layer.

3. Connect LM3262 SGND (A2), BPEN (C1), and NC (B2) pad vias to this layer.

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Layout Examples (continued)

Figure 31. Board Layer 1 — PVIN and PGND Routing

Figure 32. Board Layer 2 — FB and PVIN Routing

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Layout Examples (continued)

Figure 33. Board Layer 3 — SW, VCON and EN Routing

Figure 34. Board Layer 4 — System GND Plane

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10.3 DSBGA Assembly and Use

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow

techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section

regarding surface mount technology assembly. For best results in assembly, alignment ordinals on the PC board

must be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD

(non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This

prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of

the board and interfering with mounting. See SNVA009 for specific instructions on how to do this.

The 9-pin package used for the LM3262 has 250 micron solder balls and requires 0.225-mm pads for mounting

on the circuit board. The trace to each pad must enter the pad with a 90° angle to prevent debris from being

caught in deep corners. Initially, as a thermal relief, the trace to each pad must be a width of 7 mil for a section

approximately 7 mil long. Each trace must neck up or down to its optimal width. The important criterion is

symmetry. This ensures the solder bumps on the LM3262 re-flow evenly, and that the device solders level to the

board. In particular, special attention must be paid to the pads for bumps A3 and C3. Because VIN and PGND

are typically connected to large copper planes, inadequate thermal reliefs can result in late or inadequate re-flow

of these bumps.

The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque

cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is

vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed

circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA

devices are sensitive to light, in the red and infrared range, shining on exposed die edges of the package.

TI recommends using a 10-nF capacitor between VCON and ground for non-standard ESD events or

environments and manufacturing processes to prevent unexpected output voltage drift.

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11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 文档支持

11.2.1 相关文档ꢀ

更多信息，请参见以下文档：

AN-1112《DSBGA 晶圆级芯片规模封装》（文献编号：SNVA009）

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM3262TME/NOPB

LM3262TMX/NOPB

ACTIVE

DSBGA

YFQ

250

RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-30 to 90

3000 RoHS & Green

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3262TME/NOPB

LM3262TMX/NOPB

DSBGA

YFQ

250

178.0

8.4

1.57

0.76

4.0

8.0

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3262TME/NOPB

LM3262TMX/NOPB

DSBGA

YFQ

250

208.0

191.0

35.0

3000

Pack Materials-Page 2

MECHANICAL DATA

YFQ0009xxx

0.600±0.075

TMD09XXX (Rev A)

D: Max = 1.51 mm, Min = 1.45 mm

E: Max = 1.385 mm, Min =1.325 mm

4215077/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM3262 [TI]

相关型号：

LM3262TME/NOPB

LM3262TMX/NOPB

LM3263

LM3263TME/NOPB

LM3263TMX/NOPB

LM3263_14

LM3269

LM3269TLE/NOPB

LM3269TLX/NOPB

LM326H

LM326N

LM326N/B+