LM3248TME/NOPB_技术文档

LM3248

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SNVSA01A –JULY 2013–REVISED SEPTEMBER 2013

LM3248 2.7 MHz, 2.5A Adjustable Boost-Buck DC/DC Converter

with Boost and Active Current Assist and Analog Bypass (ACB)

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1

FEATURES

DESCRIPTION

The LM3248 is a PWM/PFM Boost-Buck DC/DC

2

•

Output Voltage V_OUTAdjustable from 0.4V to

4.0V (typ.)

converter that provides efficient utilization of battery

power over a wide voltage range. The device

architecture is suitable for advanced RF front-end

systems that demand dynamic voltage and current to

support converged power amplifier architectures

operating in 2G/3G/4G and 3GPP/LTE modes. For

example, the LM3248 is designed to produce higher

output voltages while maintaining PFM mode as

required by some new reduced-power CMOS PAs.

The extremely fast Boost-Buck function reduces RF

PA overhead power dissipation, extending battery talk

time. The device will operate at input voltage V_IN

range of 2.7V to 5.5V and an adjustable output

voltage V_OUTrange of 0.4V to 4.0V at a maximum

current load of 2.5A.

•

Input Voltage Range V_INfrom 2.7V to 5.5V

Boost-Buck and Buck (Boost-Bypass)

Operating Modes with Seamless Transition

•

2.5A Load Current Capability

High Conversion Efficiency (> 90% typ.)

High-Efficiency PFM/PWM Modes with

Seamless Transition

•

Very Fast Transient Response: 10 µs

ACB Reduces Inductor Size Requirements

Dither to aid RX Band Noise Compliance

APPLICATIONS

The LM3248 is available in a 30-bump, lead-free thin

DSBGA package.

•

Multi-mode 2G/3G/4G and 3GPP/LTE Smart-

phones and Tablets

•

Hand-Held Radios

RF Mobile Devices

Typical Application Diagram

1 ꢀF Low ESL

1.0 ꢀH

10 ꢀF

VBATT

2.7V to 5.5V

SW_

BOOST

OUT_

BOOST

PVIN_

BUCK

VDD1_

BUCK

VDD2_

BUCK

FB_

BUCK

PVIN_

BOOST

ACB

SW_

BUCK

10 ꢀF

1.5 ꢀH

10 ꢀF

ACB

BYPASS

FB

VCC_PA

BUCK

BOOST

VDD_

BOOST

1 nF

VCON

CONTROL

BOOST_

GATE

SGND_

BUCK

SGND_

BOOST

MODE

ENABLE

DGND

1.8V Logic

Apps

Processor

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM3248

SNVSA01A –JULY 2013–REVISED SEPTEMBER 2013

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DESCRIPTION (CONTINUED)

The LM3248 utilizes step-up (Boost) and variable output step-down (Buck) DC/DC converters. Combining a

cascaded Boost and Buck converter in a single package is ideal for powering the latest multimode/multi-standard

RF power amplifiers. The Boost converter provides the RF power subsystem the capability to operate at lower

battery voltages as well as to maintain increased PA linearity and transmit power margins over a wider battery

voltage supply range.

The Buck has a unique Active Current assist and analog Bypass (ACB) feature to minimize inductor size without

any loss of output regulation for the entire battery voltage and RF output power range, until dropout. ACB

provides a parallel current path, when needed, to limit the maximum inductor current while still driving a 2.5A

load. The LM3248 may also be configured as a Buck-only converter with a boost bypass feature to enable

highest efficiency operation with minimal dropout voltage when the Boost is not needed.

The LM3248 automatically and seamlessly transitions between Pulse Width Modulation (PWM) and Pulse

Frequency Modulation (PFM) modes for high-efficiency operation with both full and light load conditions.

Connection Diagram

VDD_

BOOST

PVIN_

BOOST

PVIN_

BOOST

OUT_

BOOST

OUT_

BOOST

A

B

C

SW_

BOOST

SGND_

BOOST

SW_

BOOST

BOOST_

GATE

SW_

BOOST

VDD1_

BUCK

SGND_

BUCK

MODE

PGND

SW_

BUCK

SW_

BUCK

ENABLE

VCON

NC

D

E

F

FB_

BUCK

PVIN_

BUCK

PVIN_

BUCK

ATB1

DGND

VDD2_

BUCK

ATB2

ACB

BGND

ACB

1

2

3

4

5

Figure 1. 30-Bump Thin DSBGA Package (0.4 mm pitch)

(Top View, bumps down)

2

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Pin Descriptions

Pin #

A1

Name

I/O

Description

VDD_BOOST

-

Power supply voltage input for Boost Analog blocks. Connected to V_BATTsupply.

A2

PVIN_BOOST

OUT_BOOST

-

Power supply voltage input for Boost Bypass FET.

A3

A4

Boost converter output. When Boost and Buck are active, OUT_BOOST must be externally

connected to PVIN_BUCK. A 10 µF capacitor must be placed between this node and GND.

Internally connected to BUCK voltage input and feedback to inverting input of Boost error

amplifier.

O

A5

B1

Digital input. A Low-to-High transition wakes up the boost converter and positions it to a high

level in preparation for a possible VCON change.

BOOST_GATE

SGND_BOOST

I

B2

B3

B4

B5

C1

-

Analog Ground for the Boost Analog blocks.

Boost converter switch node. When Boost and Buck are active, SW_BOOST is typically

connected to V_BATTsupply through external power inductor.

SW_BOOST

I/O

I

MODE

Digital input. Low = 3G/4G (PWM/PFM) operation; High = 2G (PWM only) operation.

Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCK

when used with Boost. If Buck-only mode is used then must be directly connected to V_BATT

supply.

C2

VDD1_BUCK

C3

C4

C5

SGND_BUCK

PGND

-

Analog Ground for the Buck Analog Blocks.

Power Ground for output FETs.

Input. Chip enable. Setting ENABLE = High biases up the Buck and initiates VCON regulation

by the Buck.

D1

ENABLE

I

D2

D3

D4

D5

E1

VCON

NC

I

Analog voltage control input which controls Buck output voltage.

No connect; leave this pin floating.

-

SW_BUCK

O

Buck converter switch node for external filter inductor connection.

ATB1

FB_BUCK

DGND

-

Test pin. Connect to SGND or System Ground.

Feedback input to inverting input of error amplifier. Connect Buck output voltage directly to this

node.

E2

E3

E4

E5

F1

Ground for Boost, Buck, and RFFE digital blocks.

Power supply input for Buck PFET and ACB FET. A 10 µF capacitor must be placed between

this node and PGND. Must be externally connected to OUT_BOOST.

PVIN_BUCK

-

ATB2

VDD2_BUCK

BGND

-

Test pin. Connect to SGND or System Ground.

Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCK

when used with Boost.

F2

F3

F4

F5

Ground for ACB bypass circuit.

Active Current assist and Bypass output. Connected to the Buck converter output filter

capacitor.

ACB

-

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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(1) (2)

ABSOLUTE MAXIMUM RATINGS

VBATT pins to GND (PVIN_BOOST, VDD_BOOST, SW_BOOST, PVIN_BUCK,

VDD1_BUCK, VDD2_BUCK, SW_BUCK, ACB, SGND_BOOST, SGND_BUCK, BGND,

PGND)

−0.2V to +6.0V

(GND −0.2V to P_{VIN_BOOST}+0.2V)

+150°C

BOOST_GATE, MODE, ENABLE, OUT_BOOST, FB_BUCK, VCON

Junction Temperature (T_J-MAX

)

Storage Temperature Range

−65°C to +150°C

(3)

Continuous Power Dissipation

Internally Limited

Maximum Lead Temperature

(Soldering, 10 sec)

+260°C

2 kV

(4)

ESD Rating

Human Body Model

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after

power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal

Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds

2.5V.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typ.) and

disengages at T_J< 130°C (typ.).

(4) The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7)

(1)

RECOMMENDED OPERATING CONDITIONS

Input Voltage Range V_BATT

2.7V to 5.5V

Boost Output, Buck Input Range

Recommended Load Current

Junction Temperature (T_J) Range

Ambient Temperature (T_A) Range

0A to 2.5A

−30°C to +125°C

−30°C to +90°C

(1) All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after

power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal

Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds

2.5V.

THERMAL PROPERTIES

(1)

Junction-to-Ambient Thermal Resistance (θ_JA

)

30-bump DSBGA

38°C/W

(1) Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set

forth in the JEDEC standard JESD51-7 and is board dependent.

4

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ELECTRICAL CHARACTERISTICS (BOOST)

Limits in standard typeface are for T_A= 25°C. Limits in boldface type apply over the full operating ambient temperature range

(−30°C ≤ T_A≤ +90°C). Unless otherwise noted, all specifications apply with V_BATT= 3.0V and Buck in IDLE state.

Symbol

Parameter

Condition

Min

Typ

Max

Units

Open Loop ⁽¹⁾, VCON = 1.44V,

V_{OUT_BUCK}= 3.6V

I_{LIM-BOOST,PFET}

PFET valley current limit

4.1

A

Boost internal oscillator

frequency

F_OSC-Boost

2G/3G/4G mode, PWM mode, average

2.7

MHz

(1) Current limit is built-in, fixed, and not adjustable.

SYSTEM CHARACTERISTICS (BOOST)

The following spec table entries are specified by design and verifications providing the component values in the Typical

Application Diagram are used: L = 1.0 µH (TOKO 1276AS-H-1R0N); C_IN= 10 µF (Murata GRM155R61A106M); and C_OUT

=

1µF (Taiyo Yuden LWK107B7105KA-T) + 10 µF (Murata GRM155R61A106M). These parameters are not verified by

production testing.⁽¹⁾(The Boost stage output voltage equation is given in ⁽²⁾.) Min and Max values are specified over the

ambient temperature range T_A= −30°C ≤ T_A≤ 90°C. Unless otherwise noted, typical values are specified at V_BATT= 3.0V,

Buck in IDLE, and T_A= 25°C.

Symbol

Parameter

Condition

Boost Bypass mode

Min

Typ

Max

Units

2.7

5.5

V

VCON = 1.60V , MODE = LOW (3G/4G),

Load = 100 mA

4.45

4.65

(2)

V_{OUT_BOOST}

Boost output voltage

VCON = 1.46V , MODE = HIGH (2G),

(2)

Load = 100 mA

MODE = LOW; BOOST_GATE = HIGH;

SW_BOOST = switching;

VCON = (V_BATT- V_GOTOBOOST)/2.5

mV

–50

25

0

37

V_GOTOBOOST

Boost turn-on threshold voltage

MODE = HIGH; BOOST_GATE = HIGH;

SW_BOOST = switching;

VCON = (V_BATT- V_GOTOBOOST)/2.5

125

Minimum time from ENABLE =

HIGH (and remains steady) to

BOOST_GATE rising edge

T_{ENABLE to}

BOOST_GATE

Initially in Idle State: Boost in 0% duty cycle

(bypass)

µs

T_{BOOST_GATE_Active}Minimum time to assert

BOOST_GATE signal before

BOOST_GATE signal must remain HIGH

during this interval

45

next TTI slot boundary

Max input current averaged

I_IN-BOOST-MAX

V_BATT= 2.7V, V_{OUT_BOOST}= 4.2V

PA active during GSM burst

3.5

A

(2)

across a 2G burst (RMS)

Duty Cycle_MAX-

BOOST

PWM maximum duty cycle

I_OUT-BOOST< 1 mA

70

%

V_BATT= 3.4V to 3.7V, ΔV = ±300 mV,

V_LINE-TR

Line transient response

Load transient response

T_R=T_F= 10 µs, V_{OUT_BUCK}= 3.7V,

R_{LOAD_BUCK}= 4Ω, MODE = 3G/4G

150

(2)

mVpp

V_BATT= 2.7V, I_{OUT_BUCK}= 10 mA to 850

mA,

I_OUT, T_R= T_F= 10 µs

V_{OUT_BUCK}= 3.7V, MODE = 3G/4G

V_LOAD-TR

600

100

(2)

V_BATT= 2.7V, V_BOOST= 3.4V, I_OUT= 2A,

2G mode (Sufficient overhead between

Boost ripple voltage at worst-

case conditions

V_BOOST-RIPPLE

mVpp

V_BOOSTand V_OUT

)

(1) Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing,

but do represent the most likely norm.

(2) V_OUT-BOOST= VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)].

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ELECTRICAL CHARACTERISTICS (BUCK)

Limits in standard typeface are for T_A= T_J= 25°C. Limits in boldface type apply over the full operating ambient temperature

range (−30°C ≤ T_A≤ +90°C). Unless otherwise noted, all specifications apply with V_BATT= 3.8V.

Symbol

V_FB,MIN

Parameter

Condition

Min

Typ

Max

0.45

Units

(1) (2)

Feedback voltage at low setting

VCON = 0.16V, MODE = HIGH

0.35

0.4

V

VCON = 1.6V, MODE = HIGH, V_BATT= 5.0V

V_FB,MAX

Feedback voltage at high setting

3.88

1.34

1.40

4.0

4.12

1.65

2.0

(1) (2)

I_{LIM,PFET,Steady}

State

Positive steady state peak current

limit

(3)

V_OUT= 1.5V

1.45

1.70

Positive Active Current assist

Bypass current limit

VCON = 0.6V, VACB = 2.8V

I_P-ACB,2G

I_LIM,NFET

A

(3)

NFET Switch negative peak

current limit

(3)

VCON = 1.0V

−1.50 −1.31

(4)

I_SHDN

Shutdown supply current I_BATT

DC bias current from V_BATT

Internal oscillator frequency

ENABLE = LOW

0.02

260

4

I_{Q_PFM}

I_{Q_PWM}

F_OSC

ENABLE = HIGH

350

µA

ENABLE = HIGH

1010

2.7

1100

2.916

2G/3G/4G mode, PWM mode, average

2.484

MHz

(1) The parameters in the electrical characteristics table are tested under open loop conditions at V_BATT= 3.8V unless otherwise specified.

For performance over the input voltage range and closed-loop results, refer to the datasheet curves.

(2) V_OUT-BOOST= VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)].

(3) Current limit is built-in, fixed, and not adjustable.

(4) Shutdown current includes leakage current of PFET.

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SYSTEM CHARACTERISTICS (BUCK)

The following spec table entries are specified by design and verification providing the component values in the Typical

Application Diagram are used: L = 1.5 µH (TOKO 1285AS-H-1R5N); C_IN= 10 µF (Murata GRM155R61A106A); and C_OUT

10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These

parameters are not verified by production testing.⁽¹⁾Min and Max values are specified over the ambient temperature

range T_A= −30°C ≤ T_A≤ +90°C. Typical values are specified at V_BATT= 3.8V and T_A= 25°C unless otherwise stated.

=

Symbol

Parameter

Condition

Min

Typ

Max

Units

Time Delay required after

BOOST_GATE = HIGH (before

VCON can change)

T_Warm-Up

ENABLE = High

30

µs

Time for V_OUTto rise from 0V to

3.4V (90% or 3.06V)

V_BATT= 3.8V, R_LOAD= 68Ω,

VCON = 0V to 1.36V

15

10

Time for V_OUTto fall from 3.4V to

0V (10% or 0.34V)

V_BATT= 3.8V, R_LOAD= 68Ω,

VCON = 1.36V to 0V

Time for V_OUTto rise from 0.8V to V_BATT= 3.8V, R_LOAD= 20Ω,

3.3V (90% or 3.05V)

VCON = 0.32V to 1.32V

Time for V_OUTto fall from 3.3V to

0.8V (10% or 1.05V)

V_BATT= 3.8V, R_LOAD= 20Ω,

VCON = 1.32 to 0.32V

Time for V_OUTto rise from 1.4V to V_BATT= 3.8V, R_LOAD= 6.8Ω,

3.4V (90% or 3.2V)

T_RESPONSE

µs

VCON = 0.56V to 1.36V

Time for V_OUTto fall from 3.4V to

1.4V (10% or 1.6V)

V_BATT= 3.8V, R_LOAD= 6.8Ω,

VCON = 1.36V to 0.56V

V_BATT= 3.8V, R_LOAD= 2.2Ω,

VCON = 0.72V to 1.12V

MODE = 2G

Time for V_OUTto rise from 1.8V to

2.8V (93% or 2.73V)

15

V_BATT= 3.8V, R_LOAD= 2.2Ω

VCON = 1.12V to 0.72V

MODE = 2G

Time for V_OUTto fall from 2.8V to

1.8V (7% or 1.87V)

Positive transient peak current

limit

(2)

I_{LIM,PFET,Transient}

V_OUT= 1.5V

1.9

2.1

A

V

_BATT≥ 2.88V, VCON = 1.48V (V_OUT=

3.7V), PWM mode, switcher plus ACB

current

2.0

Maximum load current in PWM

mode

I_{OUT_MAX, PWM}

V_BATT≥ 3.0V, VCON = 1.48V (V_OUT= 3.7V),

PWM mode, switcher plus ACB current

2.3

2.5

VCON = 1.2V (V_OUT= 3.0V), PWM mode,

switcher plus ACB current

Load current to enter into PFM

mode at high duty cycle (D > 0.85

AND Boost in Bypass)

V_BATT/V_OUT= 3.6/3.3V, 4.2/4.0V,

BOOST_GATE = LOW

I_{OUT_PFM}

35

mA

Maximum load current to enter

into PFM mode

I_{OUT_MAX, PFM}

I_OUT,PU

I_{OUT,PD_PWM}

V_{OUT_ACC}

D < 0.85 or SW_BOOST = switching

85

Maximum output transient pullup

current limit

3.0

PWM mode ⁽²⁾, switcher plus ACB current

A

PWM maximum output transient

pulldown current limit

−3.0

V_OUTaccuracy over output voltage

range

(3)

V_OUT= 0.6V to 3.6V

−3

+3

%

(1) Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing,

but do represent the most likely norm.

(2) Current limit is built-in, fixed, and not adjustable.

(3) Accuracy limits are ±3% or ±50 mV, whichever is larger.

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SYSTEM CHARACTERISTICS (BUCK) (continued)

The following spec table entries are specified by design and verification providing the component values in the Typical

Application Diagram are used: L = 1.5 µH (TOKO 1285AS-H-1R5N); C_IN= 10 µF (Murata GRM155R61A106A); and C_OUT

10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These

parameters are not verified by production testing.⁽¹⁾Min and Max values are specified over the ambient temperature

range T_A= −30°C ≤ T_A≤ +90°C. Typical values are specified at V_BATT= 3.8V and T_A= 25°C unless otherwise stated.

=

Symbol

Parameter

Condition

Min

Typ

Max

Units

Ripple voltage at no pulse

skipping condition

V_OUT= 0.4V to 3.6V, R_OUT= 2.2Ω,

2G mode

4

10

(4)

V_BATT= 4.2V to dropout,

Ripple voltage at pulse skipping

condition

V_{OUT_RIPPLE}

V_OUT= 3.6V, R_OUT= 2.2Ω,

14

9

20

15

mVpp

(4)

2G mode

V_OUT= 1.0V,

I_OUT= 40 mA

PFM ripple voltage

(4)

V_BATT= 3.6V to 4.2V,

T_R= T_F= 10 µs,

V_LINE-TR

Line transient response

70

V_OUT= 1.0V, I_OUT= 600 mA

mVpk

kHz

V_OUT= 3.0V,

T_R= T_F= 10 µs, I_OUT= 0A to 1.2A,

2G mode

V_LOAD-TR

Load transient response

Minimum PFM frequency

150

100

V_BATT= 3.2V, V_OUT= 1.0V,

I_OUT= 10 mA

F_{SW_PFM}

(4) Ripple voltage should be measured at C_OUTnode on a well-designed PC board, using suggested inductor and capacitors. Ripple

voltage is defined as the maximum peak-to-peak output voltage variation measured over a 100 µs period.

SYSTEM CHARACTERISTICS (BOOST-BUCK)

See SYSTEM CHARACTERISTICS (BOOST) and SYSTEM CHARACTERISTICS (BUCK) for test conditions.

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_BATT= 4.0V, V_OUT= 3.4V,

I_OUT= 2A (2G, PWM mode)

86

V_BATT= 4.0V, V_OUT= 2.5V,

I_OUT= 800 mA (2G, PWM mode)

89

93

90

94

90

86

92

78

V_BATT= 4.0V, V_OUT= 3.0V,

I_OUT= 400 mA (2G, PWM mode)

V_BATT= 3.4V, V_OUT= 4.0V,

I_OUT= 850 mA (3G/4G, PWM mode)

V_BATT= 3.4V, V_OUT= 3.0V,

I_OUT= 500 mA (3G/4G, PWM mode)

η

Boost-Buck Efficiency

%

V_BATT= 3.4V, V_OUT= 2.5V,

I_OUT= 70 mA (3G/4G, PFM mode)

V_BATT= 3.4V, V_OUT= 0.9V,

I_OUT= 200 mA (3G/4G, PWM mode)

V_BATT= 3.6V, V_OUT= 3.3V,

I_OUT= 20 mA (3G/4G PFM mode)

V_BATT= 3.4V, V_OUT= 0.6V,

I_OUT= 20 mA (3G/4G, PFM mode)

V_BATT= 2.7, 3.2V. R_LOAD= 11.4Ω,

VCON = 0.16V to 1.6V; T_rise= T_fall= 1 µs

MODE = 2G (HIGH)

Time for V_OUTto rise from 0.4V

to 4.0V (93% or 3.75V)

T_RESPONSE

15

µs

V_BATT= 2.7, 3.2V. R_LOAD= 11.4Ω,

VCON = 1.6V to 0.16V; T_rise= T_fall= 1 µs

MODE = 2G (HIGH)

Time for V_OUTto fall from 4.0V

to 0.4V (7% or 0.65V)

8

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ELECTRICAL CHARACTERISTICS (CONTROL INTERFACE)

Limits in standard typeface are for T_A= 25°C. Limits in boldface type apply over the full operating ambient temperature range

(−30°C ≤ T_A≤ +90°C). Unless otherwise noted, all specifications apply with V_BATT= 2.7V to 5.5V.

Symbol

Parameter

Condition

Min

Typ

Max

Units

Input high level threshold

BOOST_GATE, MODE,

ENABLE

V_IH

1.35

V

Input low level threshold

BOOST_GATE, MODE,

ENABLE

V_IL

0.50

VDD_BOOST = VDD2_BUCK = PVIN_BOOST = 3.8V

SW_BOOST = OUT_BOOST = VDD1_BUCK =

PVIN_BUCK = NO CONNECT

1) ENABLE = 1.8V, all remaining pins = GND

2) MODE = 1.8V, all remaining pins = GND

3) BOOST_GATE = 1.8V, all remaining pins = GND

MODE, ENABLE,

BOOST_GATE Pins - HIGH

Input Current

I_IN

–1

0

1

µA

VDD_BOOST = VDD2_BUCK = PVIN_BOOST= 3.8V

SW_BOOST = OUT_BOOST = VDD1_BUCK =

PVIN_BUCK = NO CONNECT

MODE, ENABLE,

BOOST_GATE Pins - LOW

Input Current

1) ENABLE = 0V, all remaining pins = 1.8V

2) MODE = ENABLE = 0V, all remaining pins = 1.8V

3) BOOST_GATE = ENABLE = 0V, all remaining pins =

1.8V

STARTUP TIMING

ENABLE

ENABLE must transition HIGH min. 25 µs

before BOOST_GATE is brought HIGH.

BOOST_GATE

t0

BOOST_GATE must transition HIGH min.

t1 45 µs before slot boundary. LM3248 Auto-

Boost cycle begins.

VCON

OUT_BOOST

V_OUT

VCON signal change must start min. 15 µs

before slot boundary. V_OUTtransition follows

VCON change. OUT_BOOST tracks at V_OUT

450 mV / 950 mV (3G4G/2G).

t2

+

t3 V_OUTsettles to within 90% of final value.

Slot Boundary. LM3248 Boost cycle ends. New

boost output target selected. Start of next TTI

power control.

ts

I_OUT

Note: the BOOST_GATE minimum duration is

shown. To minimize boost circuit current drain,

the BOOST_GATE falling edge should occur as

soon after this minimum time as possible and

before the start of the next Tx slot.

PA RF P_OUT

t0

t1

t2

t3

ts

t = -70 ꢀs

t = -45 ꢀs

t = -15 ꢀs

t = 0 ꢀs

Tx Slot N-1

Tx Slot N

Figure 2. Startup + Optional Boost Timing Sequence

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TYPICAL CHARACTERISTICS

For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.

Switching Frequency

vs

Output Voltage

vs

Input Voltage (V_OUT= 3.0V)

Input Voltage

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

3.0

2.9

2.8

2.7

2.6

2.5

500mA

800mA

1A

1.5A

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

Input Voltage (V)

C008

C007

Figure 3.

Figure 4.

Output Voltage

vs

Input Voltage (V_OUT= 3.2V)

Output Voltage

vs

Input Voltage (V_OUT= 3.4V)

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

500mA

800mA

1A

800mA

1A

1.5A

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

Input Voltage (V)

C006

C005

Figure 5.

Figure 6.

Efficiency vs Load Current

V_BATT=3.4V, MODE=3G4G, T_BOOSTGATE=1ms

Efficiency vs Load Current

V_BATT=3.7V, MODE=3G4G, T_BOOSTGATE=1ms

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

0.8Vout

1.0Vout

0.8Vout

1.5Vout

2.5Vout

3.5Vout

1.0Vout

1.5Vout

2.0Vout

2.5Vout

3.5Vout_Boost

3.0Vout

4.0Vout_Boost

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Load Current (A)

C009

C010

Figure 7.

Figure 8.

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TYPICAL CHARACTERISTICS (continued)

For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.

Efficiency vs Load Current

V_BATT=3.4V, MODE=3G4G, T_BOOSTGATE=10ms

Efficiency vs Load Current

V_BATT=3.7V, MODE=3G4G, T_BOOSTGATE=10ms

100

95

90

85

80

75

70

65

60

100.00

95.00

90.00

85.00

80.00

75.00

70.00

65.00

60.00

0.8Vout

1.5Vout

2.5Vout

3.5Vout_Boost

1.0Vout

2.0Vout

3.0Vout

4.0Vout_Boost

0.8Vout

1.5Vout

2.5Vout

3.5Vout

1.0Vout

2.0Vout

3.0Vout

4.0Vout_Boost

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Load Current (A)

C002

C003

Figure 9.

Figure 10.

Efficiency vs Load Current

V_BATT=3.4V, MODE=3G4G, BOOST_GATE=LOW

Efficiency vs Load Current

V_BATT=3.7V, MODE=3G4G, BOOST_GATE=LOW

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

0.4Vout

0.8Vout

1.5Vout

2.5Vout

3.5Vout

0.6Vout

1.0Vout

2.0Vout

3.0Vout

0.4Vout

0.8Vout

1.5Vout

2.5Vout

0.6Vout

1.0Vout

2.0Vout

3.0Vout

0.01

0.10

1.00

0.01

0.10

1.00

Load Current (A)

Figure 11.

C004

C001

Figure 12.

Efficiency vs Load Current

V_BATT=3.0V, MODE=2G, T_BOOSTGATE=4.62ms

Efficiency vs Load Current

V_BATT=3.4V, MODE=2G, T_BOOSTGATE=4.62ms

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

0.8Vout

1.8Vout

3.0Vout

1.0Vout

2.5Vout

3.4Vout

0.8Vout

1.8Vout

3.0Vout

1.0Vout

2.5Vout

3.4Vout

0.15

1.50

0.15

1.50

Load Current (A)

C012

C013

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.

Efficiency vs Load Current

V_BATT=3.7V, MODE=2G, T_BOOSTGATE=4.62ms

Efficiency vs Load Current

V_BATT=4.0V, MODE=2G, T_BOOSTGATE=4.62ms

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

0.8Vout

1.8Vout

3.0Vout

1.0Vout

2.5Vout

3.4Vout

0.8Vout

1.8Vout

3.0Vout

1.0Vout

2.5Vout

3.4Vout

0.15

1.50

0.15

1.50

Load Current (A)

C014

C015

Figure 15.

Figure 16.

Line Transient

V_BATT=3.6V↔4.2V, T_R=T_F= 10µS, V_OUT=1.0V, Load=600mA

Efficiency vs Load Current

V_BATT=4.0V, MODE=2G, BOOST_GATE=LOW

100

95

90

85

80

75

70

65

60

3.6V to

4.2V

500mV/DIV

V_BATT

V_{BUCK_OUT}(AC)

100mV/DIV

500mA/DIV

I_OUT

0.4Vout

0.8Vout

1.8Vout

3.0Vout

0.6Vout

1.0Vout

2.5Vout

3.4Vout

0.01

0.10

1.00

10.00

Load Current (A)

C011

100µS/DIV

Figure 17.

Figure 18.

Load Transient

V_BATT=3.0V, V_OUT=3.6V, MODE=1.8V, Load=0↔2A,

V_BATT=3.8V, V_OUT=3.0V, MODE=LOW, Load= 0A↔1.2A,

T_R=T_F=10µS

500mV/DIV

V_BATT

500mV/DIV

50mV/DIV

V_{BUCK_OUT}(AC)

500mA/DIV

I_OUT

500mA/DIV

100µS/DIV

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.

Startup in Auto-Boost Mode

V_BATT=2.7V, Load=200 mA, MODE=2G, V_OUT=0.4↔4V,

Timed Output Current Limit into Short Circuit

V_BATT=4.3V, V_OUT=2.5V, Load=6.8Ω/Short to GND

T_R=T_F=10µS

2V/DIV

ENA

V_OUT

2V/DIV

BOOST_GATE

SW_BUCK

2V/DIV

1A/DIV

500mV/DIV

1V/DIV

VCON

V_OUT

I_L(Buck)

20µS/DIV

40µS/DIV

Figure 21.

Figure 22.

VCON Transient Response

VCON Transient with Boost Active

V_BATT=3.2V, MODE=2G, V_OUT= 0.4↔4 V, Load=11.4Ω

V_BATT=3.8V, V_OUT= 0.8V↔3.3V, MODE=LOW

BOOST_GATE=LOW, Load=20Ω, T_R=T_F=10µS

2V/DIV

T_RISE= 7.8µS

ENA

T_FALL= 7.6µS

500mV/DIV

2V/DIV

BOOST_GATE

V_{BUCK_OUT}

500mV/DIV

1V/DIV

VCON

V_OUT

I_OUT

50mA/DIV

1V/DIV

VCON

20µS/DIV

Figure 23.

Figure 24.

VCON Transient Response

V_BATT=3.8V, V_OUT= 1.4V↔3.4V, MODE=LOW

BOOST_GATE=LOW, Load=6.8Ω, T_R=T_F=10µS

VCON Transient Response

V_BATT=3.8V, V_OUT=1.0V, MODE=LOW

BOOST_GATE=LOW, Load=0A↔60mA, T_R=T_F=10µS

T_RISE= 6.8µS

T_FALL= 6.2µS

500mV/DIV

V_{OUT_}AC

10mV/DIV

V_OUT

I_OUT

200mA/DIV

1V/DIV

I_OUT

20mA/DIV

VCON

20µS/DIV

Figure 25.

Figure 26.

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FUNCTIONAL DESCRIPTION

The LM3248 is a high-efficiency boost-buck DC/DC converter used in mobile phones and other battery-powered

RF devices to improve overall system efficiency by tailoring RF PA stage supply rail voltages to RF output power

levels. The LM3248 optimizes efficiency over a wide range of power levels when using Li polymer battery cells

operating as low as 2.7V.

The LM3248 architecture is comprised of a step-up (boost) DC/DC switching converter followed by a step-down

(buck) DC/DC switching converter. This cascaded boost-buck architecture allows the device to support output

voltages that are either above or below the input battery voltage, while simultaneously providing excellent output

transient and noise performance. See Figure 27 for more details. The LM3248 minimizes 3G/4G/4G-LTE

Advanced current consumption in User Equipment (UE) transmit power distribution environments and, in

addition, supports higher power 2G functionality.

1 ꢀF Low ESL

1.0 ꢀH

10 ꢀF

VBATT

2.7V to 5.5V

SW_

BOOST

OUT_

BOOST

PVIN_

BUCK

VDD1_

BUCK

VDD2_

BUCK

FB_

BUCK

PVIN_

BOOST

ACB

SW_

BUCK

10 ꢀF

1.5 ꢀH

10 ꢀF

ACB

BYPASS

FB

VCC_PA

BUCK

BOOST

VDD_

BOOST

1 nF

VCON

CONTROL

BOOST_

GATE

SGND_

BUCK

SGND_

BOOST

MODE

ENABLE

DGND

1.8V Logic

Apps

Processor

Figure 27. Typical Application: Boost-Buck

Boost Converter

The Boost DC/DC converter enables the LM3248 to support output voltages that are either above or below the

input battery voltage. The Boost converter can be operated in either Boost or Boost-Bypass (Buck Only) modes.

Both modes of operation require the device to be enabled (ENABLE) and either 2G or 3G/4G mode (MODE) to

be selected. Boost mode automatically engages the boost circuit when needed and requires an additional digital

control signal, BOOST_GATE. The Buck output settles to new VCON levels approximately 45 µs after

BOOST_GATE transitions from LOW to HIGH (see Figure 2).

The Boost converter output (OUT_BOOST) is externally (and internally) connected to the Buck input

(PVIN_BUCK) supply voltage. The Boost converter enables increased PA efficiency and higher linearity at higher

Tx power settings when the battery voltage is lower than normally required. A unique synchronization scheme

allows the Boost and Buck voltage transitions to occur with minimal time-critical programming. The LM3248

should be operated in Boost-Bypass mode (Buck-Only, BOOST_GATE=LOW) when it is known that the Buck

output voltage will be lower than the battery voltage, such as at low transmit RF power levels. This practice

reduces unnecessary battery drain caused by boost bias circuits and improves efficiency.

When Boost operation is selected (BOOST_GATE=HIGH), the LM3248 monitors the input voltage and compares

it with the VCON output control voltage setting. The Boost circuit is activated on the rising edge of

BOOST_GATE when V_BOOST, the target boost output voltage, is greater than the input or battery voltage (V_BATT

)

to achieve the desired output voltage level, according to the equations:

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V_BOOST= VCON * 2.5 + 0 mV [V_BOOST> V_BATT] (3G or 4G mode)

or

V_BOOST= VCON * 2.5 + 125 mV [V_BOOST> V_BATT] (2G mode)

Once in Boost mode, the Boost voltage automatically adjusts according to the following equations:

V_BOOST= VCON * 2.5 + 450 mV [V_BOOST> V_BATT] (3G or 4G mode)

or

V_BOOST= VCON * 2.5 + 950 mV [V_BOOST> V_BATT] (2G mode)

In Boost mode, internal circuitry will automatically engage the large bypass switch to prevent the Boost output

from ever falling below the battery voltage, V_BATT, by more than a few hundred millivolts (200 mV typ.) when

Boost-Bypass conditions are not met. This functionality is described below.

When operating in Boost mode, the BOOST_GATE signal should be toggled between HIGH and LOW logic

levels at a rate synchronous with the Transmission Time Interval (TTI) frame, per the Startup Timing

requirements given in Figure 2. This provides sufficient setup time for the Boost bias circuits to activate before

the new (possibly higher) Buck output level is updated, ensuring a smooth transition between levels.

Note that V_BOOSTprogrammed output levels are determined by the VCON command voltage; not by the Buck

DC/DC converter output voltage, V_{CC_PA}. This is necessary to minimize Boost output voltage tracking delay

times.

Boost active due to VCON * 2.5

crossing V_BATT-V_BYPthreshold

(V_BOOST§ꢀ9&21ꢀ* 2.5 + V_overhead

)

Boost transitions to

Bypass due to V_BOOST

target (VCON * 2.5)

dropping below

V_overhead§ꢀ0.45V (3G/4G)

§ꢀ0.95V (2G)

V_BATT-V_BYPthreshold.

V_BATT

V_BOOST(in Bypass)

V_BOOSTBYP§ꢀ5_BOOST* Input Current

V_BYP§ꢀ(R_BOOST+ R_BUCK) *

LoadCurrent

V_BATT± 0mV (3G/4G)

V_BATT± 125mV (2G)

VCON * 2.5

Figure 28. Boost Operation showing VCON-V_BATTRelationship

Boost-Bypass Function

The LM3248 provides a bypass function with very low dropout resistance when the Boost stage is not needed to

support the output voltage requirements. The Boost circuit automatically enters Boost-Bypass mode when

BOOST_GATE is high and the VCON voltage is approximately less than VCON(max), as shown below:

[V_BATTí 0 mV]

VCON(max) =

(3G or 4G mode)

(2G mode)

2.5

[V_BATTí 125 mV]

VCON(max) =

2.5

In Boost-Bypass mode, the low resistance (75 mΩ typ.) bypass circuit effectively connects the PVIN_BOOST and

OUT_BOOST pins in parallel with the boost inductor and boost output power transistor. The Boost-Bypass circuit

is active at all times when BOOST_GATE=LOW. When Boost-Bypass is active, the minimum total dropout

resistance of the path between the PVIN_BOOST and OUT_BOOST pins is 60 mΩ (typ.). The Boost-Bypass

mode of operation is valid for 2.7V < V_BATT< 5.5V.

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Buck Converter

The Buck converter output voltage, V_{CC_PA}, is directly proportional to the VCON control voltage, which level is

determined by the applications processor, BBIC or RFIC RF output Power Amplifier control algorithm. The user

can dynamically program the Buck output voltage from 0.4V to 4.0V (typ.) by adjusting the VCON voltage setting,

per the equation: V_{CC_PA}= VCON * 2.5.

The LM3248 has been designed to make rapid, smooth V_{CC_PA}output transitions required by fast 3G/4G and 2G

burst ramp profiles.

The current consumption of RF Power Amplifier modules (RF PAs) typically increases with supply voltage.

Accordingly, DC/DC converter output power requirements increase as the RF PA module V_{CC_PA}voltages

increase. Two operating methods, Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), are

used to optimize system efficiency over a range of PA power levels. When the LM3248 is not needed, the device

can be set to shutdown mode (ENABLE = LOW) to minimize battery current drain. Current overload protection

and thermal overload shutdown are also provided.

2G vs. 3G/4G Modes

The MODE pin enables selection of either constant PWM (2G) or automatic PWM/PFM (3G/4G) operation.

To maintain higher efficiency at light loads, the 3G/4G mode setting is used. When in Boost-Bypass, and average

inductor current drops below 45 to 90 mA (typ.), PFM operation is active. The switching frequency is reduced to

improve efficiency. Conversely, the LM3248 transitions back to PWM operation from PFM when the average

inductor current increases to values above 90 to 160 mA (typ.). Automatic transition into PWM operation also

occurs if the output voltage falls more than 25 mV due to a load current increase.

Active Current and Analog Bypass (ACB)

Fast transient 2G power bursts require high current levels to be sourced or sunk from the LM3248 Buck DC/DC

converter. The Active Current assist and analog Bypass (ACB) feature, built into the Buck DC/DC converter,

enables smooth waveform transitions with load currents as high as 2.5A using smaller footprint inductors and

meets all of the transient requirements when supplying V_{CC_PA}voltages for the latest multi-mode RF Power

Amplifier modules. The ACB circuit provides an additional current path when the load current exceeds 1.4A (typ.)

or as the switcher approaches dropout. Similarly, the ACB circuit enables the LM3248 to respond with faster

output voltage transition times by providing extra output current on rising and falling output edges. The LM3248

handles bypass events by sensing input voltage, output voltage, and load current conditions, and then

automatically and seamlessly transitioning the converter into analog bypass, while maintaining output voltage

regulation and low output voltage ripple. Full bypass (100% duty cycle) will occur if the total dropout resistance in

bypass mode (≈ 50 mΩ) is insufficient to regulate the output voltage.

Shutdown

When the LM3248 ENABLE = LOW, the Buck and Boost DC/DC converters and control circuits are programmed

into an OFF (Shutdown) state and the output power switches are placed in a tri-state condition. The Shutdown

state reduces system current consumption to less than 4 µA.

Output Current Protection

The Buck DC/DC converter and the ACB circuit each have output current protection. The Buck converter

includes a steady-state current limit which monitors load currents and enables the ACB circuit. During transient

over-current conditions the peak current limit detector turns off the PFET switch within the current PWM cycle

and initiates the timed output current limit.

Timed Output Current Limit

If the output load current rises above the I_{LIM,PFET,Transient}threshold continuously for more than 11 μs, and the

output voltage falls below 0.3V (typ.), the LM3248 Buck DC/DC converter switch node (SW_BUCK pin) is put into

a high-impedance state, and the ACB circuit is disabled. The power switch then remains disabled for a period of

35 µs to force the inductor current to ramp down. If the short circuit condition continues, the cycle will repeat.

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Thermal Overload Protection

The LM3248 IC has thermal overload protection that disables the device, protecting it from short-term misuse

and overload conditions. If the junction temperature exceeds 150°C (typ.), all of the power functions will be

turned off. Normal operation resumes after the temperature drops below 130°C (typ.), and the LM3248 will

attempt to return to the operating state before the over-temperature condition occurred. Prolonged operation in

thermal overload condition may damage the device and is therefore not recommended.

Digital Control Signals

The BOOST_GATE, MODE and ENABLE pins are 1.8V logic-level inputs for controlling the LM3248. A logic

LOW level applied to the ENABLE pin puts the LM3248 into a Shutdown state, where minimum current is drawn

from the battery. The MODE pin allows the user to select whether PWM (2G) or PWM/PFM (3G/4G) operation is

allowed. The BOOST_GATE pin enables the Boost DC/DC converter circuitry and related functionality.

Manufacturing Considerations

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow

techniques, as detailed in Texas Instruments Application Note AN-1112 (SNVA009). Please refer to the section

Surface Mount Assembly Considerations. For best results in assembly, local alignment fiducial markers on the

PC board should be used to facilitate placement of the device.

The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that

the solder-mask opening is larger than the pad size. This prevents a lip that would otherwise form if the solder-

mask and pad overlap, which would hold the device off the surface of the board and interfere with mounting. See

Application Note AN-1112 (SNVA009) for specific instructions how to do this.

The 30-bump(5x6) DSBGA package used for the LM3248 has the following Non-Solder Mask Defined (NSMD)

mounting specifications:

•

Solder ball diameter: 0.265 mm

Copper pad size: 0.225 mm ± 0.02 mm

Solder mask opening: 0.325 ± 0.02 mm

The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep

corners. Symmetry is important to ensure the solder bumps re-flow evenly and that the device solders level to

the board. In particular, special attention must be paid to the pads for bumps A1-A5, C4, C5, E4, E5, F4 and F5

since PVIN_BOOST, OUT_BOOST, PGND, PVIN_BUCK and ACB may be connected to large copper planes

and inadequate thermal reliefs can result in inadequate re-flow of these bumps.

Typical Solution Size

FB1

1005

C9

0603

C1

1005

L1

3225

LM3248 IC

2.5 mm x 2.8 mm

L3

Boost + Buck

2016

C7

1005

t7.25mmt

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APPLICATION INFORMATION

Recommended External Components

Inductor Selection

The LM3248 was designed to work with 1.0 µH and 1.5 µH buck inductors. The largest current magnitudes

encountered with the LM3248 are in 2G mode (that is, 2.5A for 2G vs. <1A for 3G/4G). Because of the low duty

cycles encountered with 2G transmission bursts, the maximum RMS current encountered is much less than the

peak.

Suitable inductors are typically rated for maximum current with two different numbers:

1. ΔL/L = 30% (or similar) which means the current level that causes a 30% drop in the inductance value (due

to core saturation), and

2. ΔT = 40°C (or similar) which means the current level that causes a 40°C rise in the inductor's temperature.

Because of the “peaky” nature of 2G current waveforms (low duty cycle, high peak-to-average ratio), the

“ΔL/L=30%” (or similar) current limit will typically be reached long before the “ΔT=40°C” (or similar) current value.

This means that selection of the inductor is saturation-limited.

Another way of saying this is that the inductor core saturation is proportional to the peak current value, while the

temperature rise is due to the RMS current value. As a result, candidate inductors which may appear too small

for the application when looking at the “ΔT=40°C” (or similar) current specification, may be sufficiently sized, as

long as the “ΔL/L = 30%” (or similar) current value is less than the peak current required for the application.

If the “ΔL/L = 30%” (or similar) current value is not specified, or it is not clear whether the max current rating for

the part refers to either one of these rules of measure, this information should be requested from the supplier.

The LM3248 automatically manages the inductor peak and RMS current (or steady-state current peak) through

the SW_BUCK pin. The SW_BUCK pin has two positive current limits. The first is the 1.45A typical (or 1.65A

maximum) overcurrent protection which sets the upper steady-state inductor peak current (as detailed in the

ELECTRICAL CHARACTERISTICS (BUCK) parameter "I_{LIM,PFET,SteadyState}"). It is the dominant factor limiting

currents from surpassing the buck inductor I_SATspecification. The second is an over-limit current protection

"I_{LIM,PFET,Transient}" found in the SYSTEM CHARACTERISTICS (BUCK) table. It limits the maximum peak inductor

current during large signal transients (i.e., < 20 µs) to 1.9A typical (2.1A maximum). When selecting the buck

output inductor, the user should insure that a minimum of 0.3 µH is maintained when peak currents reach the

I_{LIM,PFET,Transient}current limit.

The ACB circuit automatically adjusts its output current to keep the steady-state inductor current below the

I_{LIM,PFET,Steady State}current limit. The inductor RMS current will always be less than this value during the transmit

burst, thus keeping the inductor within its thermal operating limits.

For good efficiency, the inductor's resistance should be less than 0.15Ω. Low DCR inductors (< 0.15Ω) are

recommended. Table 1 suggests some inductors and their suppliers. The slightly larger inductors listed in

Table 1 were observed to enhance efficiency 1 to 2% under some V_IN/V_OUT/Load conditions.

Table 1. Suggested Inductors and Their Suppliers

Boost Inductor 1.0 µH, 3225, 3.0A, 60 mΩ

Model

Vendor

TOKO

Dimensions (mm)

3.2 x 2.5 x 1.0

3.2 x 2.5 x 1.2

I_SAT(–30%) (A)

DCR (mΩ)

1276AS-H-1R0N

CIG32W1R0MNE

1277AS-H-1R0M

3.9

3.0

4.6

48

60

37

Samsung

TOKO

Buck Inductor 1.5 µH, 2016 or 2520, 2.2A, 150 mΩ

Model

Vendor

Dimensions (mm)

2.0 x 1.6 x 1.0

2.5 x 2.0 x 1.2

I_SAT(–30%) (A)

DCR (mΩ)

120

1285AS-H-1R5N

LQM2MPN1R5MG

MAKK2016T1R5M

VLS201610MT-1R5N

1239AS-H-1R5N

TOKO

Murata

2.2

2.0

1.9

1.4

3.3

110

Taiyo-Yuden

TDK

115

151

TOKO

60

18

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Capacitor Selection

The LM3248 is designed to use ceramic capacitors for input and output decoupling. Use a 10 μF capacitor for

the input and approximately 10 μF actual total output capacitance. Capacitor types such as X5R and X7R are

recommended for both filters. These provide an optimal balance between small size, cost, reliability and

performance for cell phones and similar applications. Table 2 lists suggested part numbers and suppliers. DC

bias characteristics of the capacitors must be considered while selecting the voltage rating and case size of the

capacitor. Smaller 0402 (1005) case size capacitors are recommended for filtering. Use of multiple 2.2 μF or 1

μF capacitors can also be considered. For RF Power Amplifier applications, split the output capacitor between

DC-DC converter and RF Power Amplifiers: 10 μF (COUT1) + 4.7 μF (COUT2) + 3 x 1.0 μF (COUT3) is

recommended. The optimum capacitance split is application dependent, and for stability the actual total

capacitance (taking into account effects of capacitor DC bias, temperature de-rating, aging and other capacitor

tolerances) should target 10 μF with 2.5V DC bias (measured at 0.5 VRMS). Place all the output capacitors very

close to the respective device. A high-frequency capacitor (3300 pF) is highly recommended to be placed next to

COUT1.

Table 2. Suggested Capacitors and Their Suppliers

Capacitance

10 µF 6.3V X5R

4.7 µF 10V X5R

1 µF 10V X5R

Model

Dimensions (mm)

1.0 x 0.5

Vendor

Samsung

Murata

Taiyo Yuden

Samsung

TDK

CL05A106MQ5NUNC

GRM155R61A475M

LWK107BJ105MV

1.0 x 0.5

0.8 x 1.6

1 µF 10V X5R

CL03A105MP3NSNC

C0603X5R0J224M

0.61 x 0.3

0.41 x 0.2

0.22 µF 6.3V X5R

0.01 µF 6.3V X5R

1000 pF 25V X7R

100 pF 25V X7R

3300 pF 6.3V X5R

C0603X5R0J103K

TDK

GRM033R71E102KA01D

GRM033R71E101KA01D

C0402X5R0J332K020BC

Murata

TDK

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PCB LAYOUT CONSIDERATIONS

Overview

PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board

layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also

addressing manufacturing issues that can have adverse impacts on board quality and final product yield.

PCB

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC

converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to

poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or

degraded performance of the converter.

Energy Efficiency

Minimize resistive losses by using wide traces between the power components and doubling up traces on

multiple layers when possible.

EMI

By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to

minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the

LM3248, switches Ampere-level currents within nanoseconds, and the traces interconnecting the associated

components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is

maintained within tolerable levels.

To help minimize radiated noise:

•

Place the LM3248 DC-DC converter, its input capacitor, and output filter inductor and capacitor close

together, and make the interconnecting traces as short as possible.

•

Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3248 and the

inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of

each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3248 by the

inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing

these loops so the current curls in the same direction prevents magnetic field reversal between the two half-

cycles and reduces radiated noise.

•

Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return

paths, where possible, to further minimize trace inductances.

To help minimize conducted noise in the ground-plane:

•

Reduce the amount of switching current that circulates through the ground plane by connecting the ground

bumps of the LM3248 and the boost output/buck input filter capacitors together using generous component-

side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane by

multiple vias. The multiple vias help to minimize ground bounce at the LM3248 by giving it a low-impedance

ground connection.

To help minimize coupling to the DC-DC converter's own voltage feedback trace:

•

Route noise sensitive traces, such as the voltage feedback path (FB_BUCK), as directly as possible from the

switcher FB_BUCK pad to the VOUT pad of the output capacitor, but keep them away from noisy traces

between the power components.

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To help minimize noise coupled back into power supplies:

•

Use a star connection to route from the V_BATTpower source to the LM3248 PVIN_BOOST pins and to

the PA device VBATT pins.

•

Include sufficient decoupling capacitance, for both low and high frequency, at the PA V_BATTconnections.

Route traces for minimum inductance (short, wide connections) between supply pins and bypass capacitor(s).

Route traces to minimize inductance between bypass capacitors and the ground plane.

Utilize necessary power supply trace inductance(s) to reduce coupling between function blocks.

Inserting a ferrite bead in series with the V_BATTpower supply trace may offer a favorable tradeoff between

board area and additional shunt bypass capacitors, by attenuating noise that might otherwise propagate

through the supply connections.

4. LM3248 RF Evaluation Board

VBATT_PA

L1

VBATT

C27

C28

10 µF

1.0 µH

1 µF

C34

1 nF

C1

10 nF

Lo ESL

U2

L3

VOUT

PVIN_

SW_BOOST

SW_

C2

10 µF

BOOST

BUCK

1.5 µH

C7

10 µF

C8

3.3 nF

VCC_PA_2G

C3

FB_

BUCK

LM3248

ENABLE

GPO1

C5

3.3 nF

BOOST GATE

GPO2

GPO3

DAC

4.7 µF

ACB

MODE

VCON

BGND

PGND SGND

VCC_PA_3G

BB or

RFIC

PA

C19

330 pF

C20

2.2 µF

PA(s)

VBATT_PA

Figure 29. Simplified LM3248 RF Evaluation Board Schematic

LM3248 PCB Placement Considerations

1. Input Capacitor C2 should be placed closer to LM3248 than C1.

2. Optional to add a 1 nF (C34) capacitor on the input of LM3248 for high frequency filtering.

3. Bulk Output Capacitor C7 should be placed closer to LM3248 than C8.

4. Connect GND terminals of C7, C8 and C34 directly to System RF GND layer of phone board.

5. Connect GND terminals of boost output C27 and buck input C28 capacitors to copper PGND island on the

component side. This island is then tied to the system ground layer through several vias.

6. Connect bumps SGND_BOOST(B2), SGND_BUCK(C3), DGND(E3), and BGND (F3) directly to system

ground layer.

7. Small high-frequency filtering capacitors (e.g., C34) work better when they are connected to system ground

instead of the PGND island. These capacitors should be 0201 (0603 metric) or 01005 (0402 metric) case

size for minimum footprint and best high frequency characteristics.

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RF Evaluation Board Layout Overview

DC-DC

converter

section

3G PA

section

MMMB PA

section

Figure 30. Top View of RF Evaluation Board

The LM3248 RF Evaluation board consists of the LM3248 DC/DC converter and two RF Power Amplifier

stages – a standard 3x3 mm footprint “3G PA” and a Multi-Mode MultiBand (“MMMB PA”) 2G+3G/4G Power

Amplifier. These circuits are outlined in Figure 30.

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Layout Recommendations

Multi-Layer Chip-Capacitors (MLCC), rather than Tantalum, should be used in the LM3248 DC/DC converter, in

order to minimize ESR effects.

One of the most important details is routing the power feed in a way that does not induce noise between the PA

and DC/DC converter circuits that are connected to the common power feed. The “star connection” previously

mentioned is illustrated below in Figure 31. The key is to route the power connections from the V_BATTpower

source to the PA and DC/DC converters separately, so that there is no shared current path – they only join at the

power source. If this is not possible, due to other constraints, it is wise to design in pads for ferrite beads in

series with the V_BATTconnection to the device, at least in prototype layouts, so that additional filtering is available

when performance is validated (see Figure 32).

V_BATT(+) ³VWDU´ꢀ

connection to DC/DC

converter

(power feeds join only at

the power source)

Cuttable jumper

for ferrite bead

(if needed)

Separate V_BATT(+)

connection to PA

sections

PA sections

V_{CC_PA}_2G

routing

(layer 4)

Note: this image shows multiple layers.

Figure 31. LM3248 V_BATTStar Connection and V_{CC_PA}Routing

Critical Boost Output/Buck Input Capacitors

The most critical placement and connections are the boost output/buck input filter capacitors, C27 and C28,

which should be located as close as possible to the U2 LM3248 device OUT_BOOST/PVIN_BUCK and PGND

pads. These two capacitors decouple the fastest (highest di/dt) switching currents in the power supply. By

minimizing the connection length (inductance) between these capacitor and the LM3248 device pads, the user

minimizes the noise that may propagate back into the V_BATTpower bus. The best method to connect these

components to the LM3248 is short, direct connecting traces from the capacitor pads to the device pads on the

same layer (vias are resistive+inductive and impede the fast switching current flow). This is illustrated in

Figure 32, below, with arrows indicating the fast circulating current flows. Note the copper PGND island, which

joins the major current-carrying bypass capacitor GND terminals, C2, C27, and C28.

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C34 HF

decoupling to

system ground

C27, C28 short,

direct conn., all

on comp layer

PGND

Island

System

Ground

ACB

connection

ties directly

to L3/C7

junction

Figure 32. LM3248 Decoupling Cap Placement

(Top View, Component Layer)

The V_BATTsupply currents replenish the main decoupling caps mounted to the PGND island through the system

ground by way of several vias, so that the fast switching currents are confined to the component layer. This

technique reduces ground-plane noise by reducing the amount of switching current that circulates through the

system ground plane. An additional high-frequency decoupling capacitor (C34, 1 nF, 0201 case size) is

recommended between the main power (V_BATT) feed and the system ground (not to PGND) to return any

common mode switching currents that appear on these surfaces.

The Active Current Assist and Bypass (ACB) trace should be kept short and routed directly from ACB pin to the

junction of output inductor L3 and output capacitor C7 (see Figure 32).

Minimizing Switching Noise

Next, the boost and buck inductors, L1 and L3, should be placed so that routing will minimize exposure of the

“noisy” end of each of these components to surrounding circuitry that ties directly to the SW_BUCK and

SW_BOOST pins. Specifically, the FB_BUCK feedback sense connection should be routed away from the

SW_BUCK (or SW_BOOST) nodes. Ideally, make a short, direct connection from the FB_BUCK pin to the

junction of the output capacitor, C7, and buck output inductor, L3. This trace is a voltage sense connection and

does not carry significant current (trace width is not critical). If this connection must be routed under either L1 or

L3 inductors, there should be a ground layer between this trace and the noisy end of the inductor(s) to provide

shielding. Connect output capacitors C7 and C8 directly to the system ground (not to the PGND copper island).

In this example, C7 and C8 are routed to the Layer 3 system ground through multiple vias (see Figure 32 and

Figure 33), which is acceptable, since they do not carry extremely fast (high di/dt) switching currents.

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System

Ground

Noisy end of L3

(SW_BUCK)

FB_BUCK trace

does not run

underneath L3

Figure 33. LM3248 Buck Feedback and Inductor L3 Routing for Low Noise

(Layer 3 shown with Layer 1 Component Overlay)

The SW_BOOST routing to L1 is shown in Figure 34. Note the noisy end of inductor L1 does not cross sensitive

the FB_BUCK trace, but is routed away from it.

Noisy end of L1

(SW_BOOST)

Strap joining

Boost output to

Buck input

Figure 34. LM3248 Inductor L1 Routing for Low Noise

(Layer 2 shown with Layer 1 Component Overlay)

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REVISION HISTORY

Changes from Original (August 2013) to Revision A

Page

•

Changed Product Brief for Full Datasheet; 2 figures: Boost/Buck Output Voltage Timing Diagram and Boost

Operation showing VCON-V_BATTRelationship .................................................................................................................... 25

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PACKAGE MATERIALS INFORMATION

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5-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3248TME/NOPB

LM3248TMX/NOPB

DSBGA

YFQ

30

250

178.0

8.4

2.67

2.95

0.76

4.0

8.0

Q1

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3248TME/NOPB

LM3248TMX/NOPB

DSBGA

YFQ

30

250

210.0

185.0

35.0

3000

Pack Materials-Page 2

MECHANICAL DATA

YFQ0030xxx

D

0.600

±0.075

E

TMD30XXX (Rev B)

D: Max = 2.829 mm, Min =2.769 mm

E: Max = 2.453 mm, Min =2.393 mm

4215085/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

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型号：	LM3248TME/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	LM3248 2.7 MHz, 2.5A Adjustable Boost-Buck DC/DC Converter LM3248 2.7兆赫，可调节2.5A升压 - 降压型DC / DC转换器转换器
文件：	总31页 (文件大小：1334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM3248TME/NOPB [TI]

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