LM2787BPX [TI]
0.01A SWITCHED CAPACITOR REGULATOR, 450kHz SWITCHING FREQ-MAX, PBGA8, SMD-8;
| 型号： | LM2787BPX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.01A SWITCHED CAPACITOR REGULATOR, 450kHz SWITCHING FREQ-MAX, PBGA8, SMD-8 开关 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM2787
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SNVS080F –JULY 2001–REVISED MAY 2013
LM2787 Low Noise Regulated Switched Capacitor Voltage Inverter in DSBGA
Check for Samples: LM2787
1
FEATURES
DESCRIPTION
The LM2787 CMOS Negative Regulated Switched
Capacitor Voltage Inverter delivers a very low noise
adjustable output for an input voltage in the range of
+2.7V to +5.5V. Four low cost capacitors are used in
this circuit to provide up to 10mA of output current.
The regulated output for the LM2787 is adjustable
between −1.5V and −5.2V. The LM2787 operates at
260 kHz (typical) switching frequency to reduce
output resistance and voltage ripple. With an
operating current of only 400 µA (charge pump power
efficiency greater than 90% with most loads) and 0.05
µA typical shutdown current, the LM2787 provides
ideal performance for cellular phone power amplifier
bias and other low current, low noise negative voltage
needs. The device comes in small 8-Bump DSBGA
and thin DSBGA packages.
2
•
Inverts and Regulates the Input Supply
Voltage
•
•
Small 8-Bump DSBGA and Thin DSBGA
Packages
91% Typical Charge Pump Power Efficiency at
10mA
•
•
Low Output Ripple
Shutdown Lowers Quiescent Current to 0.05
µA (Typical)
APPLICATIONS
•
•
•
•
•
Wireless Communication Systems
Cellular Phone Power Amplifier Biasing
Interface Power Supplies
Handheld Instrumentation
Laptop Computers and PDA's
Typical Application Circuit and Connection Diagram
8-Bump DSBGA (Top View)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
LM2787
SNVS080F –JULY 2001–REVISED MAY 2013
www.ti.com
PIN DESCRIPTIONS
Pin No.
A1
Name
Cap+
VIN
Function
Positive terminal for C1.
B1
Positive power supply input.
C1
VOUT
VFB
Regulated negative output voltage.
C2
Feedback input. Connect VFB to an external resistor divider between VOUT and a positive adjust voltage
VADJ (0≤VADJ≤VIN). DO NOT leave unconnected.
C3
B3
A3
A2
SD
Active low, logic-level shutdown input.
Negative unregulated output voltage.
Negative terminal for C1.
Ground.
VNEG
Cap−
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VIN to GND or GND to OUT)
+ 5.8V
(GND − 0.3V) to (VIN + 0.3V)
10mA
SD
VNEG and VOUT Continuous Output Current
VOUT Short-Circuit Duration to GND(3)
Continuous Power Dissipation (TA = 25°C)(4)
1 sec.
600mW
(4)
TJMAX
150°C
(4)
θJA
220°C/W
Operating Input Voltage Range
Operating Output Current Range
Operating Ambient
2.7V to 5.5V
0mA to 10mA
−40°C to 85°C
Temp. Range
Operating Junction Temp. Range
Storage Temperature
−40°C to 110°C
−65°C to 150°C
300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating(5)
2kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when
operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) OUT may be shorted to GND for one second without damage. However, shorting OUT to VIN may damage the device and must be
avoided. Also, for temperatures above TA = 85°C, OUT must not be shorted to GND or VIN or device may be damaged.
(4) The maximum power dissipation must be de-rated at elevated temperatures and is limited by TJMAX (maximum junction temperature), TA
(ambient temperature) and θJA (junction-to-ambient thermal resistance). The maximum power dissipation at any temperature
is:PDissMAX = (TJMAX — TA)/θJA up to the value listed in the Absolute Maximum Ratings.
(5) Rating is for the human body model, a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Electrical Characteristics
Limits with standard typeface apply for TJ = 25°C, and limits in boldface type apply over the full temperature range. Unless
otherwise specified VIN = 3.6V, C1 = C2 = C3 = 1µF.
Symbol
IQ
Parameter
Supply Current
Conditions
Min
Typ
400
0.05
260
Max
950
1
Units
µA
Open Circuit, No Load
ISD
Shutdown Supply Current
Switching Frequency(1)
Power Efficiency at VNEG
µA
FSW
VIN = 3.6V
140
450
kHz
ηPOWER
IL = 3.6mA
IL = 10mA
94
91
%
TSTART
Start Up time
120
600
µs
(1) The output switches operate at one half the oscillator frequency, fOSC = 2fSW
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SNVS080F –JULY 2001–REVISED MAY 2013
Electrical Characteristics (continued)
Limits with standard typeface apply for TJ = 25°C, and limits in boldface type apply over the full temperature range. Unless
otherwise specified VIN = 3.6V, C1 = C2 = C3 = 1µF.
Symbol
RNEG
VR
Parameter
Conditions
Min
Typ
Max
Units
Output Resistance to VNEG
Output Voltage Ripple(3)
See(2)
30
Ω
IL =2.5mA, VOUT = −2.7V
IL = 10mA, VOUT = −3.8V
1
mV
VFB
Feedback Pin Reference
Voltage
IL = 2.5mA(4)
−1.25
−1.20
−1.15
V
V
VOUT
Adjustable Output Voltage
5.5V ≥ VIN ≥ 2.7V, 2.5mA ≥ IL
5.5V ≥ VIN ≥ 3.0V, 10mA ≥ IL
0mA
− (VIN −0.3V)
− (VIN −1.2V)
≥
Load Regulation
Line Regulation
0 to 10mA, VOUT = − 2.4V
5.5V ≥ VIN ≥ 2.7V, IL = 2.5mA
5.5V ≥ VIN ≥ 2.7V
5
1
mV/mA
mV/V
V
VIH
VIL
Shutdown Pin Input Voltage
High
2.4
Shutdown Pin Input Voltage
Low
5.5V ≥ VIN ≥ 2.7V
0.8
V
(2) Current drawn from VNEG pin decreases power efficiency and will increase output voltage ripple.
(3) In the test circuit, capacitors C1, C2, and C3 are 1µF, 0.30Ω maximum ESR capacitors. Capacitors with higher ESR will increase output
resistance, increase output voltage ripple, and reduce efficiency.
(4) The feedback resistors R1 and R2 are 200kΩ resistors.
Figure 1. Standard Application Circuit
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SNVS080F –JULY 2001–REVISED MAY 2013
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Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, VOUT = −2.5V.
Output Voltage
vs.
Output Current
Output Voltage
vs.
Input Voltage
Figure 2.
Figure 3.
Maximum VNEG Current
vs.
No Load Supply Current
vs.
Input Voltage
Input Voltage
Figure 4.
Figure 5.
Switching Frequency
vs.
VFB
vs.
Temperature
Input Voltage
Figure 6.
Figure 7.
4
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SNVS080F –JULY 2001–REVISED MAY 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VOUT = −2.5V.
Start-up Time
vs.
Input Voltage
Start-up from Shutdown (no load)
Figure 8.
Figure 9.
Output Ripple
Output Noise Spectrum
Figure 10.
Figure 11.
Line Transient Response
Load Transient Response
Figure 12.
Figure 13.
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SNVS080F –JULY 2001–REVISED MAY 2013
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FUNCTIONAL BLOCK DIAGRAM
Figure 14. Functional Block Diagram
Device Description
The LM2787 is an inverting, regulated charge-pump power converter. It features low noise, small physical size,
and is simple to use. It is an ideal solution for biasing GaAsFET devices such as power amplifier modules found
in portable devices and cellular phones.
A switched capacitor charge-pump circuit is used to invert the input voltage VIN to its corresponding negative
value which is seen at VNEG. This voltage is regulated by a low dropout linear regulator at VOUT (Figure 14). The
output voltage can be regulated anywhere from −1.5V to −5.2V and is determined by a pair of feedback resistors
(see Setting the Output Voltage). The PSRR of the linear regulator reduces the output voltage ripple produced by
the charge-pump inverter at the output VOUT. The regulator also attenuates noise from the incoming supply due
to its high PSRR.
Shutdown
The LM2787 features a logic-level shutdown feature. The function is active-low and will reduce the supply current
to 0.05µA (typical) when engaged. When shutdown is active VOUT and VNEG are switched to ground.
APPLICATION INFORMATION
Setting the Output Voltage
The output voltage on the LM2787 is set by using a resistor divider between the output, the feedback pin, and an
arbitrary voltage VADJ (Figure 14). VADJ can range from GND to any positive voltage up to VIN. VADJ is usually
chosen to be GND and should not be connected to a different voltage unless it is well regulated so the output will
stay constant. The feedback pin is held at a constant voltage VFB which equals −1.2V. The output voltage can be
selected using the equation:
(1)
The current into the feedback pin IFB is in the range of 10nA to 100nA. Therefore using a value of 500kΩ or
smaller for R1 should make this current of little concern when setting the output voltage. For best accuracy, use
resistors with 1% or better tolerance.
Capacitor Selection
Selecting the right capacitors for your circuit is important. The capacitors affect the output resistance of the
charge-pump, the output voltage ripple, and the overall dropout voltage (VIN-|VOUT|) of the circuit. The output
resistance of the charge-pump inverter is:
6
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SNVS080F –JULY 2001–REVISED MAY 2013
(2)
The switching frequency is fixed at 260kHz and RSW (the combined resistance of the internal switches) is
typically 10Ω. It is clear from this equation that low ESR capacitors are desirable and that larger values of C1 will
further reduce the output resistance. The output resistance of the entire circuit (in dropout) is:
ROUT = RNEG + Rregulator
(3)
Rregulator (the output impedance of the linear regulator) is approximately 10Ω. When the circuit is in regulation, the
overall output resistance is equal to the linear regulator load regulation (5mV/mA). The dropout voltage is
therefore affected by the capacitors used since it is simply defined as IOUT*ROUT
.
A larger value of capacitor and lower ESR for C2 will lower the output voltage ripple of the charge-pump. This
ripple will then be subject to the PSRR of the linear regulator and reduced at VOUT
.
In summation, larger value capacitors with lower ESR will give the lowest output noise and ripple. C1, C2, and C3
should be 1.0µF minimum with less than 0.3Ω ESR. Larger values may be used for any or all capacitors. All
capacitors should be either ceramic, surface-mount chip tantalum, or polymer electrolytic.
Output Noise and Ripple
Low output noise and output voltage ripple are two of the attractive features of the LM2787. Because they are
small, the noise and ripple can be hard to measure accurately. Ground loop error between the circuit and the
oscilloscope caused by the switching of the charge-pump produces ground currents in the probe wires. This
causes sharp voltage spikes on the oscilloscope waveform. To reduce this error, measure the output directly at
the output capacitor (C3) and use the shortest wires possible. Also, do not use the ground lead on the probe.
Take the tip cover off of the probe and touch the grounding ring of the probe directly to the output ground. This
should give the most accurate reading of the actual output waveform.
DSBGA Mounting
The DSBGA package requires specific mounting techniques which are detailed in Application Note AN1112.
Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that
the pad style which must be used with the 8-pin package is the NSMD (non-solder mask defined) type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
DSBGA Light Sensitivity
Exposing the DSBGA device to direct sunlight may cause misoperation of the device. Light sources such as
Halogen lamps can also affect electrical performance if brought near the device.
The wavelengths which have the most detrimental effect are reds and infra-reds. The fluorescent lighting used
inside of most buildings has very little effect on performance.
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SNVS080F –JULY 2001–REVISED MAY 2013
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REVISION HISTORY
Changes from Revision E (May 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
8
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