LM2722M/NOPB [TI]
3.2A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, SO-8;
| 型号： | LM2722M/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.2A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, SO-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总13页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
LM2722 High Speed Synchronous/Asynchronous MOSFET Driver
Check for Samples: LM2722
1
FEATURES
DESCRIPTION
The LM2722, part of the LM2726 family, is designed
2
•
•
•
•
•
Synchronous or Asynchronous Operation
Adaptive Shoot-Through Protection
Input Under-Voltage-Lock-Out
Typical 20ns Internal Delay
to be used with multi-phase controllers. This part
differs from the LM2726 by changing the functionality
of the SYNC_EN pin from a whole chip enable to a
low side MOSFET enable. As a result, the SYNC_EN
pin now provides control between Synchronous and
Asynchronous operations. Having this control can be
Plastic 8-pin SOIC package
advantageous
Asynchronous operations can be more efficient at
very light loads.
in
portable
systems
since
APPLICATIONS
•
Driver for LM2723 Intel Mobile Northwood CPU
Core Power Supply.
The LM2722 drives both top and bottom MOSFETs in
a push-pull structure simultaneously. It takes a logic
level PWM input and splits it into two complimentary
signals with a typical 20ns dead time in between. The
built-in cross-conduction protection circuitry prevents
the top and bottom FETs from turning on
simultaneously. The cross-conduction protection
circuitry detects both the driver outputs and will not
turn on a driver until the other driver output is low.
With a bias voltage of 5V, the peak sourcing and
sinking current for each driver of the LM2722 is
typically 3A. In an SOIC-8 package, each driver is
able to handle 50mA average current. Input UVLO
(Under-Voltage-Lock-Out) forces both driver outputs
low to ensure proper power-up and power-down
operation. The gate drive bias voltage needed by the
high side MOSFET is obtained through an external
bootstrap. Minimum pulse width is as low as 55ns.
•
•
•
High Current DC/DC Power Supplies
High Input Voltage Switching Regulators
Fast Transient Microprocessors
Typical Application
+5
10
Note: for ultra low-frequency operation (such as
skip mode at light load), D1 should be a fast
recovery type diode instead of a Schottky.
D1
VIN (up to 35V)
+
CIN
C2
1mF
LM2722
C1
6
5
4
8
3
2
0.1mF
Q1
VCC CBOOT
SYNC_EN SIGNAL
PWM SIGNAL
L1
HG
VOUT
SYNC_EN
1
7
PWM_IN SW
+
COUT
D2
LG
U1
GND
Q2
NOTE
TI is an Intel Mobile Voltage Positioning (IMVP) licensee.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
NRND
LM2722
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
www.ti.com
Connection Diagram
1
2
3
4
8
GND
SW
HG
7
6
5
LG
CBOOT
VCC
SYNC_EN
PWM_IN
Figure 1. SOIC (D)
(Top View)
Pin Functions
Pin Descriptions
Pin
1
Name
SW
Function
Top driver return. Should be connected to the common node of top and bottom FETs
2
HG
Top gate drive output
3
CBOOT
PWM_IN
SYNC_EN
VCC
Bootstrap. Accepts a bootstrap voltage for powering the high-side driver
4
Accepts a 5V-logic control signal
Low gate Enable
5
6
Connect to +5V supply
Bottom gate drive output
Ground
7
LG
8
GND
Block Diagram
+4V ~ +7V
D1
VIN (up to 35V)
CBOOT
CBYP
CIN
HG
VCC
Q1
Power
On
SW
Reset
VOUT
+
-
COUT
SYNC_EN
PWM_IN
Q2
D2
Logic
LG
Items in bold
are external
to the IC.
Shoot-through
Protection
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: LM2722
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
(1)
Absolute Maximum Ratings
VCC
7.5V
42V
CBOOT
CBOOT to SW
SW to PGND
Junction Temperature
8V
36V
+150°C
Power Dissipation
(2)
720mW
Storage Temperature
ESD Susceptibility
Human Body Model
−65° to 150°C
(3)
1kV
Soldering Time, Temperature
10sec., 300°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
(2) Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PMAX = (TJMAX-TA) / θJA. The junction-to-ambient thermal resistance, θJA, for the LM2722, it is 172°C/W. For a TJMAX of 150°C
and TA of 25°C, the maximum allowable power dissipation is 0.7W.
(3) ESD machine model susceptibility is 100V.
(1)
Operating Ratings
VCC
4V to 7V
Junction Temperature Range
−40° to 125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
Copyright © 2001–2013, Texas Instruments Incorporated
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NRND
LM2722
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
www.ti.com
Electrical Characteristics
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA =
TJ = +25°C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
POWER SUPPLY
Iq_op
Parameter
Condition
Min
Typ
Max
300
Units
Operating Quiescent Current
Peak Pull-Up Current
PWM_IN = 0V
190
µA
TOP DRIVER
Test Circuit 1, Vbias = 5V, R =
0.1Ω
3.0
1.0
A
Ω
A
Pull-Up Rds_on
ICBOOT = IHG = 0.7A
Peak Pull-down Current
Test Circuit 2, Vbias = 5V, R =
0.1Ω
−3.2
Pull-down Rds_on
Rise Time
ISW = IHG = 0.7A
0.5
17
12
23
Ω
t4
t6
t3
t5
Timing Diagram, CLOAD = 3.3nF
ns
ns
ns
Fall Time
Pull-Up Dead Time
Pull-Down Delay
Timing Diagram
Timing Diagram, from PWM_IN
Falling Edge
27
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, Vbias = 5V, R =
0.1Ω
3.2
1.0
3.2
A
Ω
A
Pull-up Rds_on
IVCC = ILG = 0.7A
Peak Pull-down Current
Test Circuit 4, Vbias = 5V, R =
0.1Ω
Pull-down Rds_on
Rise Time
IGND = ILG = 0.7A
0.5
17
14
28
Ω
t8
t2
t7
t1
Timing Diagram, CLOAD = 3.3nF
ns
ns
ns
Fall Time
Pull-up Dead Time
Pull-down Delay
Timing Diagram
Timing Diagram, from PWM_IN
Rising Edge
13
ns
LOGIC
Vuvlo_up
Vuvlo_dn
Power On Threshold
VCC rises from 0V toward 5V
4
3.7
3.0
V
V
Under-Voltage-Lock-Out
Threshold
2.5
Vuvlo_hys
Under-Voltage-Lock-Out
Hysteresis
0.7
V
VIH_EN
VIL_EN
Ileak_EN
SYNC_EN Pin High Input
SYNC_EN Pin Low Input
2.4
V
V
0.8
2
SYNC_EN Pin Leakage
Current
EN = 5V
EN = 0V
−2
−2
µA
2
ton_min
Minimum Positive Input Pulse
Width
55
55
(1)
ns
toff_min
Minimum Negative Input Pulse
Width
(2)
VIH_PWM
VIL_PWM
PWM_IN High Level Input
Voltage
When PWM_IN pin goes high
from 0V
2.4
V
PWM_IN Low Level Input
Voltage
When PWM_IN pin goes low
from 5V
0.8
(1) If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when
the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
(2) If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the
bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
4
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Product Folder Links: LM2722
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
TEST CIRCUIT DIAGRAMS
Timing Diagram
Test Circuits
VX
VX
R
3
5
6
4
2
7
1
8
3
2
7
1
8
CBOOT
SYNC_EN
VCC
HG
LG
HG
LG
CBOOT
5
Vbias
Vbias
SYNC_EN
VCC
R
6
4
SW
SW
PWM_IN
GND
PWM_IN
GND
Vbias
Width = 200ns,One Shot
Width = 200ns, One Shot.
Figure 2. Test Circuit 1
Figure 3. Test Circuit 2
VX
VX
R
3
5
6
4
7
2
1
8
3
5
6
4
7
2
1
8
CBOOT
SYNC_EN
VCC
LG
HG
CBOOT
SYNC_EN
VCC
LG
HG
Vbias
Vbias
R
SW
SW
Vbias
PWM_IN
GND
PWM_IN
GND
Width = 200ns, One Shot
Width = 200ns, One Shot
Figure 4. Test Circuit 3
Figure 5. Test Circuit 4
Vx
R
Ipull_up
=
(1)
(2)
Vbias - Vx
R
Ipull_down
=
Vbias - Vx
. R
Rds_pull_up
=
Vx
(3)
(4)
Vx
. R
Rds_pull_down
=
Vbias - Vx
Copyright © 2001–2013, Texas Instruments Incorporated
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Product Folder Links: LM2722
NRND
LM2722
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
www.ti.com
Typical Waveforms
Figure 6. Switching Waveforms of Test Circuit
Figure 7. When Input Goes High
Figure 8. When Input Goes Low
Figure 9. Minimum Positive Pulse
Application Information
MINIMUM PULSE WIDTH
In order for the shoot-through prevention circuitry in the LM2722 to work properly, the pulses into the PWM_IN
pin must be longer than 55ns. The internal logic waits until the first FET is off plus 20ns before turning on the
opposite FET. If, after a falling edge, a rising edge occurs sooner than the specified time, toff_min, the IC may
intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and
sooner, the driver may start to ignore the pulse and produce no output. This condition results in the PWM_IN pin
in a high state and neither FET turned on. To get out of this state, the PWM_IN pin must see a low signal for
greater than 55ns, before the rising edge.
This will also assure that the gate drive bias voltage has been restored by forcing the top FET source and Cboot
to ground first. Then the internal circuitry is reset and normal operation will resume.
Conversely, if, after a rising edge, a falling edge occurs sooner than the specified miniumum pulse width, ton_min
,
the IC may intermittently fail to turn on the bottom FET. As the falling edge occurs sooner and sooner, the driver
will start to ignore the pulse and produce no output. This will result in the toff inductor current taking a path
through a diode provided for non-synchronous operation. The circuit will resume synchronous operation when the
rising PWM pulses exceed 55ns in duration.
HIGH INPUT VOLTAGES OR HIGH OUTPUT CURRENTS
At input voltages above twice the output voltage and at higher power levels, the designer may find snubber
networks and gate drive limiting useful in reducing EMI and preventing injurious transients. A small resistor, 1Ω
to 5Ω, between the driver outputs and the MOSFET gates will slightly increase the rise time and fall time of the
output stage and reduce switching noise. The trade-off is 1% to 2% in efficiency.
A series R-C snubber across in parallel with the bottom FET can also be used to reduce ringing. Values of 10nF
and 10Ω to 100Ω are a good starting point.
6
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Product Folder Links: LM2722
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 6
Copyright © 2001–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LM2722MX/NOPB
NRND
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
2722
M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM2722MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM2722MX/NOPB
D
8
2500
Pack Materials-Page 2
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