LM25066I_技术文档

LM25066I, LM25066IA

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SNVS824C –JUNE 2012–REVISED MARCH 2013

Intel Node Manager Compliant System Power Management and Protection IC with PMBus

Check for Samples: LM25066I, LM25066IA

1

FEATURES

DESCRIPTION

While the LM25066I/A is functionally similar to the

LM25066/A, the LM25066I/A is fully compliant to Intel

Node Manager 2.0, 2.5 and adds the READ_EIN

energy accumulator feature. The LM25066I/A

combines a high-performance hot-swap controller

with a PMBus 1.2^™compliant SMBus/I²C interface to

accurately measure, control and protect the electrical

operating conditions of critical systems. The

LM25066I/A continuously supplies real-time power,

voltage, current, temperature, and fault data to the

system management host via the SMBus interface.

2

•

Fully Node Manager 2.0 and 2.5 Compliant with

I2C/SMBus interface and PMBus™ compliant

command structure

•

Input voltage range: 2.9V to 17V

Programmable 25mV or 46mV current limit

threshold

•

Read_EIN accurately measures true input

power via simultaneous sampling

Configurable circuit breaker protection for

hard shorts

The LM25066I/A control block includes a unique hot-

swap architecture that provides current and power

limiting to protect sensitive circuitry even during the

most stressful conditions. A fast-acting circuit breaker

prevents damage in the event of a short circuit on the

output. The input under-voltage, over-voltage

hysteresis, insertion delay time and fault detection

time are all configurable. A temperature monitoring

block on the LM25066I/A interfaces with a low-cost

Configurable under- and over-voltage lockouts

with hysteresis

Real time monitoring of V_IN, V_OUT, I_IN, P_IN, V_AUX

with 12-bit resolution and 1 kHz sampling rate

Current measurement accuracy: ±1%

(LM25066IA) and Power measurement

accuracy: ±2.0% (LM25066IA) over temperature

•

Averaging of V_IN, I_IN, P_IN, and V_OUTover

programmable interval ranging from 0.001 to 4

seconds

external

diode

for

continuous

temperature

assessment of the external MOSFET or other thermal

sensitive components. The POWER GOOD output

provides a fast alert when the input and/or output

voltages are outside their programmed range.

Accurate power readings are accomplished by using

•

Programmable WARN and FAULT thresholds

with SMBA notification

Blackbox capture of telemetry measurements

and device status triggered by WARN or

FAULT condition

the

READ_EIN

command.

A

black

box

(Telemetry/Fault Snapshot) function captures and

stores telemetry data and device status in the event

of a warning or a fault.

•

24-lead WQFN package

APPLICATIONS

•

Server backplane systems

Basestation power distribution systems

Solid state circuit breaker (eFuse)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM25066I, LM25066IA

SNVS824C –JUNE 2012–REVISED MARCH 2013

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Typical Application Schematic

Q

2

R

S

V

OUT

IN

1

D

C

LOAD

Z

C

IN

R

1

R

4

VIN

GATE

OUT

SENSE

DIODE

UVLO/EN

FB

R

2

VDD

R

5

OVLO

R

3

R

PG

VDD

ADR2

ADR1

ADR0

PGD

N/C

LM25066I/A

Auxillary ADC Input

(0V - 1.16V)

VAUX

RETRY

CB

SMBA

SDA

SMBus

Interface

SCL

CL

VDD

VREF

TIMER

PWR

GND

R

PWR

C

VDD

C

T

VREF

Connection Diagram

OUT

SCL

SMBA

VREF

PGD

PWR

Exposed

Pad

DIODE

TIMER

RETRY

VAUX

24

5x4 mm WQFN 24L

1

Solder exposed pad to ground.

Top View

WQFN-24

2

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SNVS824C –JUNE 2012–REVISED MARCH 2013

Pin Descriptions

Name

Description

Applications Information

No.

Pad

Exposed

Pad

Exposed pad of WQFN

package

No internal electrical connection. Solder to the ground plane to reduce thermal resistance.

1

2

3

4

ADR2

ADR1

ADR0

VDD

SMBUS address line 2

SMBUS address line 1

SMBUS address line 0

3 - state address line. Should be connected to GND, VDD, or left floating.

Internal sub-regulator

output

Internally sub-regulated 4.5V bias supply. Connect a 1 µF capacitor on this pin to ground

for bypassing.

5

6

CL

CB

Current limit range

Connect this pin to GND to set the nominal over-current threshold at 25mV. Connecting

CL to VDD will set the over-current threshold to be 46mV.

Circuit breaker range

This pin sets the circuit breaker protection point in relation to the over-current trip point.

When connected to GND, this pin will set the circuit breaker point to be 1.8 times the

over-current threshold. Connecting this pin to VDD sets the circuit breaker trip point to be

3.6 times the over-current threshold.

7

8

FB

Power Good feedback

Fault retry input

An external resistor divider from OUT sets the output voltage at which the PGD pin

switches. The threshold at the pin is 1.167V. An internal 24 µA current source provides

hysteresis.

RETRY

This pin configures the power up fault retry behavior. When this pin is grounded, the

device will continually try to engage power during a fault. If the pin is connected to VDD,

the device will latch off during a fault.

9

TIMER

PWR

PGD

Timing capacitor

Power limit set

An external capacitor connected to this pin sets the insertion time delay, fault timeout

period and restart timing.

10

11

An external resistor connected to this pin, in conjunction with the current sense resistor

(R_S), sets the maximum power dissipation allowed in the external series pass MOSFET.

Power Good indicator

An open drain output. This output is high when the voltage at the FB pin is above 1.167V

and the input supply is within its under-voltage and over-voltage thresholds. Connect via a

pullup resistor to the output rail (external MOSFET source) or any other voltage to be

monitored.

12

OUT

Output feedback

Connect to the output rail (external MOSFET source). Internally used to determine the

MOSFET V_DSvoltage for power limiting, and to monitor the output voltage.

13

14

GATE

Gate drive output

Connect to the external MOSFET's gate.

SENSE

Current sense input

The voltage across the current sense resistor (R_S) is measured from VIN to this pin. If the

voltage across R_Sreaches over-current threshold, the load current is limited and the fault

timer activates.

15

16

VIN

Positive supply input

Under-voltage lockout

A small ceramic bypass capacitor close to this pin is recommended to suppress transients

which occur when the load current is switched off.

UVLO/EN

An external resistor divider from the system input voltage sets the under-voltage turn-on

threshold. An internal 23 µA current source provides hysteresis. The enable threshold at

the pin is 1.16V. This pin can also be used for remote shutdown control.

17

OVLO

Over-voltage lockout

An external resistor divider from the system input voltage sets the over-voltage turn-off

threshold. An internal 23 µA current source provides hysteresis. The disable threshold at

the pin is 1.16V.

18

19

20

21

22

GND

SDA

Circuit ground

SMBus data pin

SMBus clock

Data pin for SMBus.

SCL

Clock pin for SMBus.

SMBA

VREF

SMBus alert line

Internal Reference

Alert pin for SMBus, active low.

Internally generated precision 2.73V reference used for analog to digital conversion.

Connect a 1 µF capacitor on this pin to ground for bypassing.

23

24

DIODE

VAUX

External diode

Connect this to a diode-configured NPN transistor for temperature monitoring.

Auxiliary voltage input

Auxiliary pin allows voltage telemetry from an external source. Full scale input of 1.16V.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings⁽¹⁾

(2)

VIN, SENSE to GND

-0.3V to 24V

-0.3V to 20V

-1 to 20V

(2)

GATE, FB, UVLO/EN, OVLO, PGD to GND

Out to GND

SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND

-0.3V to 6V

-0.3V to +0.3V

2kV

VIN to SENSE

ESD Rating, Human Body Model⁽³⁾

Storage Temperature

Junction Temperature

-65°C to +150°C

+150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional.

(2) The GATE pin voltage is typically 7.5V above VIN when the LM25066I/A is enabled. Therefore, the Absolute Maximum Rating of 24V for

VIN and SENSE apply only when the LM25066I/A is disabled or for a momentary surge to that voltage since the Absolute Maximum

Rating for the GATE pin is 20V.

(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Operating Ratings

VIN, SENSE, OUT voltage

2.9V to 17V

2.9V to 5.5V

VDD

Junction Temperature

−40°C to +125°C

Electrical Characteristics

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C

to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless

otherwise stated the following conditions apply: VIN = 12V. See ⁽¹⁾and

Symbol

Input (VIN Pin)

I_IN-EN

Parameter

Conditions

Min

Typ

Max

Unit

Input Current, enabled

UVLO = 2V and OVLO = 0.7V

VIN increasing

5.8

2.6

150

8

mA

V

POR

Power On Reset threshold at VIN

POR_ENHysteresis

2.8

POR_HYS

VIN decreasing

mV

VDD Regulator (VDD pin)

V_DD

I_VDD= 5mA, VIN = 12V

I_VDD= 5mA, VIN = 4.5V

4.3

3.5

25

4.5

3.9

45

4.7

4.3

V

V_DDILIM

VDD Current Limit

mA

UVLO/EN, OVLO Pins

UVLO_TH

UVLO_HYS

UVLO_DEL

UVLO threshold

V_UVLOFalling

1.147

18

1.16

23

8

1.173

28

V

UVLO hysteresis current

UVLO delay

UVLO = 1V

µA

µs

Delay to GATE high

Delay to GATE low

UVLO = 3V

20

UVLO_BIAS

OVLO_TH

UVLO bias current

OVLO threshold

1

µA

V

V_OVLOrising

1.141

-28

1.16

-23

19

1.185

-18

OVLO_HYS

OVLO_DEL

OVLO hysteresis current

OVLO delay

OVLO = 1V

µA

µs

Delay to GATE high

Delay to GATE low

OVLO = 1V

9

OVLO_BIAS

OVLO bias current

1

µA

Power Good (PGD pin)

PGD_VOL

PGD_IOH

Output low voltage

I_SINK= 2 mA

V_PGD= 17V

V_FBto V_PG

25

60

1

mV

µA

ns

Off leakage current

Power Good Delay

PGD_DELAY

115

(1) Current out of a pin is indicated as a negative value.

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C

to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless

otherwise stated the following conditions apply: VIN = 12V. See ⁽¹⁾and

Symbol

FB Pin

Parameter

Conditions

Min

Typ

Max

Unit

FB_TH

FB_HYS

FB_LEAK

FB Threshold

V_FBrising

V_FB= 1V

1.141

-31

1.167

-24

1.19

-18

1

V

FB Hysteresis Current

Off Leakage Current

µA

Power Limit (PWR Pin)

PWR_LIM

I_PWR

Power limit sense voltage (VIN-SENSE) SENSE-OUT = 12V, R_PWR= 25 kΩ

9

12.5

-10

15

mV

µA

Ω

PWR pin current

V_PWR= 2.5V

UVLO = 0.7V

R_SAT(PWR)

PWR pin impedance when disabled

180

Gate Control (GATE Pin)

I_GATE

Source current

Normal operation

UVLO = 1V

-28

1.5

-22

2

-16

2.5

µA

mA

Fault Sink current

POR Circuit Breaker sink current

VIN - SENSE = 150 mV or VIN < R_POR

,

105

190

275

V_GATE= 5V

V_GATE

Gate output voltage in normal operation GATE voltage with respect to ground

17

18.8

20.3

V

OUT Pin

I_OUT-EN

I_OUT-DIS

OUT bias current, enabled

OUT bias current, disabled

OUT = VIN, normal operation

16

µA

(2)

Disabled, OUT = 0V, SENSE = VIN

-12

Current Limit

V_CL

Threshold voltage

CL = GND

22.5

23

25

46

1.2

33

46

45

27.5

27

mV

CL = GND, T_J= 10°C to 85°C

CL = VDD

41

52

t_CL

Response time

VIN-SENSE stepped from 0 mV to 80 mV

Enabled, SENSE = OUT

Disabled, OUT = 0V

µs

I_SENSE

SENSE input current

µA

Enabled, OUT = 0V

Circuit Breaker

V_CB

Threshold voltage x 1.8

CB:CL Ratio

VIN - SENSE, CL = GND, CB = GND

CB = GND

35

1.6

70

45

1.8

90

55

2

mV

µs

V_CB

Threshold voltage x 3.6

CB:CL Ratio

VIN - SENSE, CL = GND, CB = VDD

CB = VDD

110

4

3.1

3.6

0.6

t_CB

Response time

VIN - SENSE stepped from 0 mV to 150

mV, time to GATE low, no load

1.2

Timer (TIMER pin)

V_TMRH

Upper threshold

Lower threshold

1.54

0.85

1.7

1.0

0.3

-5.5

1.9

-90

2.8

0.67

17

1.85

1.07

V

V_TMRL

Restart cycles

End of 8^thcycle

Re-enable threshold

TIMER pin = 2V

V

I_TIMER

Insertion time current

-8

-3

µA

mA

µA

%

Sink current, end of insertion time

Fault detection current

Fault sink current

1.4

2.4

-60

-120

DC_FAULT

Fault Restart Duty Cycle

Fault to GATE low delay

t_{FAULT_DELAY}

TIMER pin reaches the upper threshold

µs

(2) OUT bias current (disabled) due to leakage current through an internal 0.9 MΩ resistance from SENSE to VOUT.

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C

to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless

otherwise stated the following conditions apply: VIN = 12V. See ⁽¹⁾and

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Internal Reference

V_REF

Reference Voltage

2.703

2.73

2.757

V

ADC and MUX

Resolution

12

+/-1

100

Bits

LSB

µs

INL

t_AQUIRE

t_RR

Integral Non-Linearity

ADC only

Acquisition + Conversion Time

Acquisition Round Robin Time

Current input full scale range

Any channel

Cycle all channels

CL = GND

1

ms

mV

µV

V

IIN_FSR

30.2

60.4

7.32

14.64

1.16

283.2

18.7

4.54

CL = VDD

IIN_LSB

Current input LSB

CL = GND

CL = VDD

VAUX_FSR

VAUX_LSB

VIN_FSR

VAUX input full scale range

VAUX input LSB

µV

V

Input voltage full scale range

Input voltage LSB

VIN_LSB

mV

6

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C

to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless

otherwise stated the following conditions apply: VIN = 12V. See ⁽¹⁾and

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Telemetry Accuracy LM25066IA

IIN_ACC

Input Current Accuracy

VIN – SENSE = 25mV, CL = GND

T_J= 10°C to 85°C

-1

+1

%

VIN – SENSE = 25mV, CL = GND

VIN – SENSE = 50mV, CL = VDD

-1.2

-1.8

-5

+1

+1.8

+5

VIN- SENSE= 5mV, CL= GND

T_J= 10°C to 85°C

V_ACC

VAUX, VIN, VOUT Accuracy

Input Power Accuracy

VIN, VOUT = 12V

VAUX = 1V

T_J= 10°C to 85°C

-1

+1

%

VIN, VOUT = 12V

VAUX = 1V

-1

+1.2

+2.0

PIN_ACC

VIN = 12V, VIN – SENSE = 25mV,

CL = GND

-2.0

%

Telemetry Accuracy LM25066I

IIN_ACCInput Current Accuracy

VIN – SENSE = 25mV, CL = GND

-2.7

-2.4

+2.4

VIN – SENSE = 25mV, CL = GND

T_J= 10°C to 85°C

V_ACC

VAUX, VIN, VOUT Accuracy

Input Power Accuracy

VIN, VOUT = 12V

VAUX = 1V

-1.6

-1.4

+1.4

VIN, VOUT = 12V

VAUX = 1V

T_J= 10°C to 85°C

PIN_ACC

VIN = 12V, VIN – SENSE = 25mV,

CL = GND

-3.0

+3.0

10

%

Remote Diode Temperature Sensor

T_ACC

Temperature Accuracy Using Local

T_A= 10°C to 85°C

2

°C

Diode

Remote Diode Resolution

External Diode Current Source

9

bits

µA

I_DIODE

High level

Low level

250

9.4

26

300

Diode Current Ratio

PMBus Pin Thresholds (SMBA, SDA, SCL)

V_IL

V_IH

Data, Clock Input Low Voltage

Data, Clock Input High Voltage

Data Output Low Voltage

Input Leakage Current

0.8

5.5

0.4

1

V

2.1

0

V_OL

I_LEAK

CL

I_PULLUP= 4mA

V

SDA, SMBA, SCL = 5V

SDA, SCL

µA

pF

Pin Capacitance

5

Configuration Pin Thresholds (CB, CL, RETRY)

V_IH

Threshold Voltage

3

V

I_LEAK

Input Leakage Current

CL, CB, RETRY = 5V

1

mA

(3)

Thermal

θ_JA

θ_JC

Junction to Ambient

Junction to Case

42.3

9.5

°C/W

(3) Junction-to-ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the

package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used.

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Typical Performance Characteristics

Unless otherwise specified the following conditions apply: T_J= 25°C, V_IN= 12V. All graphs show junction temperature.

VIN Pin Current

SENSE Pin Current (Enabled)

6.0

5.5

5.0

4.5

4.0

3.5

3.0

54

50

46

42

38

34

30

VIN = 17V

VIN = 12V

VIN = 3V

VIN = 2.9V

-40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 1.

Figure 2.

SENSE Pin Current (Disabled)

OUT Pin Current (Enabled)

52

28

24

20

16

12

8

50

48

46

44

42

40

38

36

34

VIN = 17V

VIN = 12V

VIN = 17V

VIN = 12V

VIN = 2.9V

4

-40 -20

0

20 40 60 80 100 120

-60 -40 -20

0

20 40 60 80 100120140

TEMPERATURE (°C)

Figure 3.

Figure 4.

OUT Pin Current (Disabled)

GATE Pin Voltage

-2

-4

20

18

16

14

12

10

8

VIN = 17V

VIN = 12V

-6

VIN = 9V

-8

VIN = 12V

-10

-12

-14

-16

-18

VIN = 5V

VIN = 2.9V

6

-60 -40 -20

0

20 40 60 80 100120140

-60 -40 -20

0

20 40 60 80 100120140

TEMPERATURE (°C)

Figure 5.

Figure 6.

8

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Typical Performance Characteristics (continued)

Unless otherwise specified the following conditions apply: T_J= 25°C, V_IN= 12V. All graphs show junction temperature.

GATE Pin Source Current

Power Limit Threshold

23

22

21

20

19

18

17

16

15

14

24

20

16

12

8

=50K; CL = VDD

R

PWR

VIN = 5V TO 17V

=25K; CL = GND

PWR

R

VIN = 2.9V

4

0

-40 -20

0

20 40 60 80 100 120 140

-40 -20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

Figure 7.

Figure 8.

PGD Low Voltage

UVLO Threshold

42

38

34

30

26

22

18

1.17

VIN = 2.9 to 12V

VIN = 17V

1.16

1.15

PGD Sink Current = 2mA

-60 -40 -20

0

20 40 60 80 100120140

-60 -40 -20 0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 9.

Figure 10.

UVLO Hysteresis Current

FB Threshold

24.0

23.8

23.6

23.4

23.2

23.0

1.172

1.171

1.170

1.169

1.168

1.167

1.166

1.165

1.164

1.163

1.162

-60 -40 -20 0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 11.

Figure 12.

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Typical Performance Characteristics (continued)

Unless otherwise specified the following conditions apply: T_J= 25°C, V_IN= 12V. All graphs show junction temperature.

OVLO Threshold

OVLO Hysteresis

1.167

1.166

1.165

1.164

1.163

1.162

-16

-18

-20

-22

-24

-26

-28

-30

VIN = 2.9V

VIN = 12V

VIN = 12V to 17V

VIN = 17V

-60 -40 -20

0

20 40 60 80 100120140

-60 -40 -20 0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 13.

Figure 14.

FB Pin Hysteresis

Current Limit Threshold

27.0

26.5

26.0

25.5

25.0

24.5

24.0

23.5

23.0

-23.0

-23.5

-24.0

-24.5

-25.0

-25.5

-26.0

VIN = 5V to 17V

VIN = 2.9V

-60 -40 -20

0 20 40 60 80 100120140

TEMPERATURE (°C)

-60 -40 -20 0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 15.

Figure 16.

Current Limit Threshold

Circuit Breaker Threshold (CL = VDD)

50

200

180

160

140

120

100

80

49

48

CL = VDD, CB = VDD

47

VIN = 5V to 17V

46

45

VIN = 2.9V

44

43

42

41

40

CL = GND, CB = VDD

CL = GND, CB = GND

60

40

-60 -40 -20

0 20 40 60 80 100120140

-60 -40 -20

0 20 40 60 80 100120140

TEMPERATURE (°C)

Figure 17.

Figure 18.

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Typical Performance Characteristics (continued)

Unless otherwise specified the following conditions apply: T_J= 25°C, V_IN= 12V. All graphs show junction temperature.

Reference Voltage

Startup (Insertion Delay)

INSERTION DELAY = 140 ms

2.75

2.74

2.73

2.72

2.71

2.70

1V/DIV

TIMER

10V/DIV

VIN

GATE

VOUT

10V/DIV

100 ms/DIV

-60 -40 -20

0

20 40 60 80 100120140

TEMPERATURE (°C)

Figure 19.

Figure 20.

Startup (Short circuit V_OUT

)

Startup (5A Load)

TIMER

1V/DIV

TIMER

VIN

10V/DIV

GATE

RETRY PERIOD = 1.10s

10V/DIV

GATE

VOUT

10V/DIV

VOUT

2.5A/DIV

ILOAD

1 ms/DIV

400 ms/DIV

Figure 21.

Figure 22.

Startup (UVLO, OVLO)

Startup (PGOOD)

PGOOD

5V/DIV

OVLO = 15.2V

GATE

hyst = 1.2V

VIN

5V/DIV

10.7V

10.25V

VOUT

VIN

UVLO = 2.9V

40 ms/DIV

hyst = 0.2V

40 ms/DIV

Figure 23.

Figure 24.

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Typical Performance Characteristics (continued)

Unless otherwise specified the following conditions apply: T_J= 25°C, V_IN= 12V. All graphs show junction temperature.

Current Limit Event (CL = GND)

Circuit Breaker Event (CL = CB = GND)

1V/DIV

TIMER

1V/DIV

TIMEOUT PERIOD

= 8.3 ms

GATE

10V/DIV

VOUT

ILOAD

>50A

10V/DIV

> 90A Triggers

25A/DIV

Circuit Breaker

50A/DIV

ILOAD

1 ms/DIV

4 ms/DIV

Figure 25.

Figure 26.

Retry Event (Retry = GND)

Latch Off (Retry = VDD)

RETRY PERIOD = 1.1s

TIMER

1V/DIV

TIMER

1V/DIV

GATE

10V/DIV

VOUT

ILOAD

10V/DIV

25A/DIV

10V/DIV

ILOAD

25A/DIV

400 ms/DIV

100 ms/DIV

Figure 27.

Figure 28.

IIN Measurement Accuracy

(VIN - SENSE = 25 mV)

PIN Measurement Accuracy

(VIN - SENSE = 25 mV)

0.5

0.4

1.0

0.8

0.3

0.6

0.2

0.4

0.1

0.2

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.2

-0.4

-0.6

-0.8

-1.0

-15 -5

5

15 25 35 45 55 65 75 85

-15 -5

5

15 25 35 45 55 65 75 85

TEMPERATURE ( °C)

TEMPERATURE (°C)

Figure 29.

Figure 30.

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BLOCK DIAGRAM

24 ꢀA

LM25066I/A

VDD

REG

VDD

1.167V

UV

OV

REF

GEN

Charge

Pump

1/16

25 mV

12bit

ADC

I

VREF

VAUX

D

22 ꢀA

Current Limit

Threshold

GATE

Gate

Control

2 mA

Gain = 2.3V/V

190

mA

18.8V

1 M

V

DS

Power Limit

Threshold

10ꢀA

Diode

Temp

Sense

Current Limit/

Power Limit

Control

DIODE

5.5 ꢀA

Insertion

Timer

90 ꢀA

MEASUREMENT/

AVERAGING

FAULT REGISTERS

23 ꢀA

Fault

Timer

TIMER

TELEMETRY

STATE

MACHINE

SCL

SDA

1.16V

TIMER AND GATE

LOGIC CONTROL

1.9 mA

End

Insertion

Time

2.8 ꢀA

Fault

Discharge

SMBUS

INTERFACE

SMBA

1.72V

1.0V

0.3V

ADDRESS

DECODER

23 ꢀA

2.5V

VDD

ADR0

ADR1

ADR2

POR

2.6V

VIN

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FUNCTIONAL DESCRIPTION

The inline protection functionality of the LM25066I/A is designed to control the in-rush current to the load upon

insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the

backplane’s supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the

system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is

removed can also be implemented using the LM25066I/A.

In addition to a programmable current limit, the LM25066I/A monitors and limits the maximum power dissipation

in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current

limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this

event, the LM25066I/A can latch off or repetitively retry based on the hardware setting of the RETRY pin. Once

started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly

switches off the series pass device upon detection of a severe over-current condition. Programmable under-

voltage lockout (UVLO) and over-voltage lockout (OVLO) circuits shut down the LM25066I/A when the system

input voltage is outside the desired operating range.

The telemetry capability of the LM25066I/A provides intelligent monitoring of the input voltage, output voltage,

input current, input power, temperature, and an auxiliary input. The LM25066I/A also provides a peak capture of

the input power and programmable hardware averaging of the input voltage, current, power, and output voltage.

Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power

and temperature via the PMBus interface. Additionally, the LM25066I/A is capable of detecting damage to the

external MOSFET, Q₁.

Q

2

R

S

V

OUT

V

IN

Q

1

D

C

LOAD

Z

C

IN

R

1

R

4

VIN

GATE

OUT

DIODE

SENSE

UVLO/EN

FB

R

2

VDD

R

5

OVLO

R

3

R

PG

VDD

ADR2

ADR1

ADR0

PGD

N/C

LM25066I/A

Auxillary ADC Input

(0V - 1.16V)

VAUX

RETRY

CB

SMBA

SDA

SMBus

Interface

SCL

CL

VDD

VREF

TIMER

PWR

GND

R

PWR

C

VDD

C

T

VREF

Figure 31. Typical Application Circuit

Power Up Sequence

The VIN operating range of the LM25066I/A is +2.9V to +17V, with transient capability to +24V. Referring to

Figure 31 and Figure 32, as the voltage at VIN initially increases, the external N-channel MOSFET (Q₁) is held

off by an internal 190 mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin

prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the

TIMER pin is initially held at ground. When the V_INvoltage reaches the POR threshold, the insertion time begins.

During the insertion time, the capacitor at the TIMER pin (C_T) is charged by a 5.5 µA current source and Q₁is

held off by a 2 mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay

allows ringing and transients at VIN to settle before Q₁is enabled. The insertion time ends when the TIMER pin

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voltage reaches 1.7V. C_Tis then quickly discharged by an internal 1.9 mA pulldown current. The GATE pin then

switches on Q₁when V_SYS, the input supply voltage, exceeds the UVLO threshold. If V_SYSis above the UVLO

threshold at the end of the insertion time, Q₁switches on at that time. The GATE pin charge pump sources 22

µA to charge the gate capacitance of Q₁. The maximum voltage at the GATE pin with respect to ground is limited

by an internal 18.8V zener diode.

As the voltage at the OUT pin increases, the LM25066I/A monitors the drain current and power dissipation of

MOSFET Q₁. Inrush current limiting and/or power limiting circuits actively control the current delivered to the

load. During the inrush limiting interval (t₂in Figure 32), an internal 90 µA fault timer current source charges C_T.

If Q₁’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER

pin reaches 1.7V, the 90 µA current source is switched off and C_Tis discharged by the internal 2.8 µA current

sink (t₃in Figure 32). The PGD pin switches high when FB exceeds its rising threshold of 1.167V.

If the TIMER pin voltage reaches 1.7V before inrush current limiting or power limiting ceases during t₂, a fault is

declared and Q₁is turned off. See Fault Timer and Restart for a complete description of the fault mode.

The LM25066I/A will pull the SMBA pin low after the input voltage has exceeded its POR threshold to indicate

that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the

STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device

operation and will remain set until a CLEAR_FAULTS command is received.

V

SYS

UVLO

POR

V

IN

1.7V

90mA

2.8 mA

5.5 mA

TIMER

GATE

190 mA

pull-down

2 mA pull-down

22 mA source

I

LIMIT

d

Loa

Current

Output

Voltage

OUTPin

(

)

PGD

t

3

2

1

In rush

Limiting

Insertion Time

Normal Operation

Figure 32. Power Up Sequence (Current Limit Only)

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Gate Control

A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate. During normal

operating conditions (t₃in )Figure 32) the gate of Q₁is held charged by an internal 22 µA current source. The

voltage at the GATE pin (with respect to ground) is limited by an internal 18.8 V zener diode. See the graph

“GATE Pin Voltage” shown previously. Since the gate-to-source voltage applied to Q₁could be as high as 18.8 V

during various conditions, a zener diode with the appropriate voltage rating must be added between the GATE

and OUT pins if the maximum V_GSrating of the selected MOSFET is less than 18.8 V. The external zener diode

must have a forward current rating of at least 190 mA. When the system voltage is initially applied, the GATE pin

is held low by a 190 mA pulldown current. This helps prevent an inadvertent turn-on of the MOSFET through its

drain-gate capacitance as the applied system voltage increases.

During the insertion time (t₁in Figure 32) the GATE pin is held low by a 2 mA pulldown current. This maintains

Q₁in the off-state until the end of t₁, regardless of the voltage at VIN or UVLO. Following the insertion time (t₂in

Figure 32), the gate voltage of Q₁is controlled to keep the current or power dissipation level from exceeding the

programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the

current and power limiting cease before the TIMER pin reaches 1.7V, the TIMER pin capacitor then discharges,

and the circuit begins normal operation. If the inrush limiting condition persists such that the TIMER pin reached

1.7V during t₂, the GATE pin is then pulled low by the 190 mA pulldown current. The GATE pin is then held low

until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin

to GROUND). See Fault Timer and Restart. If the system input voltage falls below the UVLO threshold or rises

above the OVLO threshold, the GATE pin is pulled low by the 2 mA pulldown current to switch off Q₁.

Current Limit

The current limit threshold is reached when the voltage across the sense resistor R_S(VIN to SENSE) exceeds

the internal voltage limit of 25 mV or 46 mV depending on whether the CL pin is connected to GND or VDD,

respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q₁.

While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load

current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25066I/A

resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by

the timer capacitor, C_T, the IIN OC FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the

STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)

register will be toggled high and SMBA pin will be pulled low unless this feature is disabled using the

ALERT_MASK (D8h) register. For proper operation, the R_Sresistor value should be less than 200 mΩ. Higher

values may create instability in the current limit control loop. The current limit threshold pin value may be

overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).

Circuit Breaker

If the load current increases rapidly (e.g. the load is short circuited), the current in the sense resistor (R_S) may

exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds

1.8 or 3.6 times (user settable) the current limit threshold, Q₁is quickly switched off by the 190 mA pulldown

current at the GATE pin, and a Fault Timeout Period begins. When the voltage across R_Sfalls below the

threshold the 190 mA pulldown current at the GATE pin is switched off and the gate voltage of Q₁is then

determined by the current limit or power limit functions. If the TIMER pin reaches 1.7V before the current limiting

or power limiting condition ceases, Q₁is switched off by the 2 mA pulldown current at the GATE pin as described

in Fault Timer and Restart. A circuit breaker event will cause the CIRCUIT BREAKER FAULT bit in the

STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will

be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin

configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register.

Power Limit

An important feature of the LM25066I/A is the MOSFET power limiting. The Power Limit function can be used to

maintain the maximum power dissipation of MOSFET Q₁within the device SOA rating. The LM25066I/A

determines the power dissipation in Q₁by monitoring its drain-source voltage (SENSE to OUT), and the drain

current through R_S(VIN to SENSE). The product of the current and voltage is compared to the power limit

threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the

GATE voltage is controlled to regulate the current in Q₁. While the power limiting circuit is active, the fault timer is

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active as described in Fault Timer and Restart. If the power limit condition persists for longer than the Fault

Timeout Period set by the timer capacitor, C_T, the IIN_OC_FAULT bit in the STATUS_INPUT (7Ch) register, the

INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the

DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be pulled low unless this feature is

disabled using the ALERT_MASK (D8h) register.

Fault Timer and Restart

When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the

gate-to-source voltage of Q₁is controlled to regulate the load current and power dissipation in Q₁. When either

limiting function is active, a 90 µA fault timer current source charges the external capacitor (C_T) at the TIMER pin

as shown in Figure 32 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period

before the TIMER pin reaches 1.7V, the LM25066I/A returns to the normal operating mode and C_Tis discharged

by the 1.9 mA current sink. If the TIMER pin reaches 1.7V during the Fault Timeout Period, Q₁is switched off by

a 2 mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry

configuration.

If the RETRY pin is high, the LM25066I/A latches the GATE pin low at the end of the Fault Timeout Period. C_Tis

then discharged to ground by the 2.8 µA fault current sink. The GATE pin is held low by the 2 mA pulldown

current until a power up sequence is externally initiated by cycling the input voltage (V_SYS), or momentarily pulling

the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 33. The

voltage at the TIMER pin must be <0.3V for the restart procedure to be effective. The TIMER_LATCHED_OFF

bit in the DIAGNOSTIC_WORD (E1h) register will remain high while the latched off condition persists.

V

SYS

VIN

R1

R2

R3

UVLO/EN

Restart

Control

LM25066I/A

OVLO

GND

Figure 33. Latched Fault Restart Control

The LM25066I/A provides an automatic restart sequence which consists of the TIMER pin cycling between 1.7V

and 1V seven times after the Fault Timeout Period, as shown in Figure 34. The period of each cycle is

determined by the 90 µA charging current, and the 2.8 µA discharge current, and the value of the capacitor C_T.

When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 22 µA current source at the GATE pin

turns on Q₁. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The

RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved

through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by

setting the appropriate bits in the DEVICE_SETUP (D9h) register.

Fault

Detection

I

LIMIT

Load

Current

22 mA

Gate Charge

2 mA pulldown

GATE

mA

2.8

1.7V

90 mA

TIMER

1V

1

2

3

7

8

0.3V

t

Fault Timeout

Period

RESTART

Figure 34. Restart Sequence

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Under-Voltage Lockout (UVLO)

The series pass MOSFET (Q₁) is enabled when the input supply voltage (V_SYS) is within the operating range

defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. Typically

the UVLO level at V_SYSis set with a resistor divider (R1-R3) as shown in Figure 35. Refering to the Block

Diagram when V_SYSis below the UVLO level, the internal 23 µA current source at UVLO is enabled, the current

source at OVLO is off, and Q₁is held off by the 2 mA pulldown current at the GATE pin. As V_SYSis increased,

raising the voltage at UVLO above its threshold the 23 µA current source at UVLO is switched off, increasing the

voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q₁is

switched on by the 22 µA current source at the GATE pin if the insertion time delay has expired.

See Applications Section for a procedure to calculate the values of the threshold setting resistors (R1-R3). The

minimum possible UVLO level at V_SYScan be set by connecting the UVLO/EN pin to VIN. In this case, Q₁is

enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power up, an UVLO

condition will toggle high the VIN UV FAULT bit in the STATUS_INPUT (7Ch), the INPUT bit in the

STATUS_WORD register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h)

register, and SMBA pin will be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.

Over-Voltage Lockout (OVLO)

The series pass MOSFET (Q₁) is enabled when the input supply voltage (V_SYS) is within the operating range

defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. If V_SYS

raises the OVLO pin voltage above its threshold, Q₁is switched off by the 2 mA pulldown current at the GATE

pin, denying power to the load. When the OVLO pin is above its threshold, the internal 23 µA current source at

OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V_SYSis reduced below

the OVLO level, Q₁is re-enabled. An OVLO condition will toggle high the VIN OV FAULT bit in the

STATUS_INPUT (7Ch), the INPUT bit in the STATUS_WORD register, and the VIN_OVERVOLTAGE_FAULT bit

in the DIAGNOSTIC_WORD (E1h) register, and the SMBA pin will be pulled low unless this feature is disabled

using the ALERT_MASK (D8h) register.

See Applications Section for a procedure to calculate the threshold setting resistor values.

Shutdown Control

The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open

collector or open drain device, as shown in Figure 35. Upon releasing the UVLO/EN pin, the LM25066I/A

switches on the load current with inrush current and power limiting.

V

SYS

VIN

R1

R2

R3

UVLO/EN

Shutdown

Control

LM25066I/A

OVLO

GND

Figure 35. Shutdown Control

Power Good

The Power Good indicator (PGD) is connected to the drain of an internal N-channel MOSFET capable of

sustaining 17V in the off-state, and transients up to 20V. An external pullup resistor is required at PGD to an

appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be

higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds

the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to

feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as

long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Block Diagram, when the

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voltage at the FB pin is below its threshold, the 24 µA current source at FB is disabled. As the output voltage

increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising

the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is

below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read via the PMBus

interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.

VDD Sub-Regulator

The LM25066I/A contains an internal linear sub-regulator which steps down the input voltage to generate a 4.5V

rail used for powering low voltage circuitry. When the input voltage is below 4.5V, VDD will track VIN. For input

voltages 3.3V and below, VDD should be tied directly to VIN to avoid the dropout of the sub-regulator. The VDD

sub-regulator should be used as the pullup supply for the CL, CB, RETRY, ADR2, ADR1, ADR0 pins if they are

to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, SMBA).

The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated

circuits. The VDD pin is current limited to 45mA in order to protect the LM25066I/A in the event of a short. The

sub-regulator requires a bypass capacitance having a value between 1 µF and 4.7 µF to be placed as close to

the VDD pin as the PCB layout allows.

Remote Temperature Sensing

The LM25066I/A is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base

and collector of the MMBT3904 is connected to the DIODE pin and the emitter is grounded. Place the

MMBT3904 near the device whose temperature is to be monitored. If the temperature of the hot-swap pass

MOSFET, Q₁, is to be measured, the MMBT3904 should be placed as close to Q₁as the layout allows. The

temperature is measured by means of a change in the diode voltage in response to a step in current supplied by

the DIODE pin. The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to

measure the diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between

the DIODE pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000 pF

bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The

temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the

LM25066I/A will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable

the hot-swap pass MOSFET if the temperature exceeds 150°C. These thresholds can be reprogrammed via the

PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature

measurement and protection capability of the LM25066I/A is not used, the DIODE pin should be grounded.

Damaged MOSFET Detection

The LM25066I/A is able to detect whether the external MOSFET, Q₁, is damaged under certain conditions. If the

voltage across the sense resistor exceeds 4mV while the GATE voltage is low or the internal logic indicates that

the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and

DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be pulled low unless this

feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q₁is

shorted because of damage present between the drain and gate and/or drain and source of the external

MOSFET.

Enabling, Disabling, and Resetting

The output can be disabled at any time during normal operation by either pulling the UVLO/EN pin to below its

threshold or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pulldown

strength of 2mA. Toggling the UVLO/EN pin will also reset the LM25066I/A from a latched-off state due to an

over-current or over-power limit condition which has caused the maximum allowed number of retries to be

exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the

volatile memory or address location of the LM25066I/A. User stored values for address, device operation, and

warning and fault levels programmed via the SMBus are preserved while the LM25066I/A is powered regardless

of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to

the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared and the

OPERATION (03h) register should be written to 0h and then 80h.

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The SMBus address of the LM25066I/A is captured based on the states of the ADR0, ADR1, and ADR2 pins

(GND, NC, VDD) during turn-on and is latched into a volatile register once VDD has exceeded its POR threshold

of 2.6V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground.

Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM25066I/A. Once

released, the VREF pin will charge up to its final value and the address will be latched into a volatile register

once the voltage at the VREF exceeds 2.4V.

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APPLICATIONS SECTION

MMBT3904

V

OUT

12V

0.5 mW

PSMN1R2-25YL

330 mF

25 kW

2.1 kW

10 kW

VIN

GATE

OUT

DIODE

SENSE

UVLO/EN

FB

VDD

1.3 kW

OVLO

10 kW

VDD

ADR2

ADR1

ADR0

PGD

N/C

LM25066I/IA

Auxillary ADC Input

(0V - 1.16V)

VAUX

RETRY

CB

SMBA

SDA

SMBus

Interface

SCL

CL

VDD

VREF

TIMER

PWR

GND

6.98 kW

1 mF

0.47 mF

Figure 36. Typical Application Circuit

DESIGN-IN PROCEDURE

(Refer to Figure 36 for Typical Application Circuit) Shown here is the step-by-step procedure for hardware design

of the LM25066I/A. This procedure refers to sections that provide detailed information on the following design

steps. The recommended design-in procedure is as follows:

MOSFET Selection: Determine MOSFET value based on breakdown voltage, current and power ratings.

Current Limit, R_S: Determine the current limit threshold (I_LIM). This threshold must be higher than the normal

maximum load current, allowing for tolerances in the current sense resistor value and the LM25066I/A Current

Limit threshold voltage. Use Equation 1 to determine the value for R_S.

Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q₁)

using the device’s SOA information. Use Equation 2 to determine the value for R_PWR

.

Turn-On Time and TIMER Capacitor, C_T: Determine the value for the timing capacitor at the TIMER pin (C_T)

using Equation 8. The fault timeout period (t_FAULT) MUST be longer than the circuit’s turn-on-time. The turn-on

time can be estimated using the equations in TURN-ON TIME, but should be verified experimentally. Review the

resulting insertion time, and the restart timing if retry is enabled.

UVLO, OVLO: Choose option A, B, C, or D from UVLO, OVLO to set the UVLO and OVLO thresholds and

hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO/EN and

OVLO pins.

Power Good: Choose the appropriate output voltage and calculate the required resistor divider from the output

voltage to the FB pin. Choose either VDD or OUT to connect properly sized pullup resistor for the Power Good

output (PGD).

Refer to Programming Guide section: After all hardware design is complete, refer to the programming guide

for a step by step procedure regarding software.

MOSFET SELECTION

It is recommended that the external MOSFET (Q₁) selection be based on the following criteria:

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•

The BV_DSSrating should be greater than the maximum system voltage (V_SYS), plus ringing and transients

which can occur at V_SYSwhen the circuit card, or adjacent cards, are inserted or removed.

The maximum continuous current rating should be based on the current limit threshold (e.g. 25 mV/R_S), not

the maximum load current, since the circuit can operate near the current limit threshold continuously.

The Pulsed Drain Current spec (I_DM) must be greater than the current threshold for the circuit breaker function

(45 mV/R_Swhen CL = CB = GND).

The SOA (Safe Operating Area) chart of the device and its thermal properties should be used to determine

the maximum power dissipation threshold set by the R_PWRresistor. The programmed maximum power

dissipation should have a reasonable margin from the maximum power defined by the MOSFET’s SOA curve

(if the device is set to infinitely retry, the MOSFET will be repeatedly stressed during fault restart cycles). The

MOSFET manufacturer should be consulted for guidelines.

R_DS(on)should be sufficiently low such that the power dissipation at maximum load current (I_LIMx R_DS(on)

does not raise its junction temperature above the manufacturer’s recommendation.

2

•

)

The gate-to-source voltage provided by the LM25066I/A can be as high as 18.8V at turn-on when the output

voltage is zero. At turn-off, the reverse gate-to-source voltage will be equal to the output voltage at the instant

the GATE pin is pulled low. If the device chosen for Q₁is not rated for these voltages, an external zener

diode must be added from its gate to source, with the zener voltage less than the device maximum V_GS

rating. The zener diode’s working voltage protects the MOSFET during turn-on, and its forward voltage

protects the MOSFET during shutoff. The zener diode’s forward current rating must be at least 190 mA to

conduct the GATE pulldown current when a circuit breaker condition is detected.

CURRENT LIMIT (R_S)

The LM25066I/A monitors the current in the external MOSFET Q₁by measuring the voltage across the sense

resistor (R_S), connected from VIN to SENSE. The required resistor value is calculated from:

V_CL

I_LIM

R_S

=

(1)

where I_LIMis the desired current limit threshold. If the voltage across R_Sreaches V_CL, the current limit circuit

modulates the gate of Q₁to regulate the current at I_LIM. While the current limiting circuit is active, the fault timer is

active as described in Fault Timer and Restart. For proper operation, R_Smust be less than 200 mΩ.

V_CLcan be set to either 25mV or 46mV via hardware and/or software. This setting defaults to use of CL pin

which when grounded is 25mV or high is 46mV. The value when powered can be set via PMBus™ with the

MFR_SPECIFIC_DEVICE_SETUP command, which defaults to the 25mV setting.

Once the desired setting is known, calculate the shunt based on that input voltage and maximum current. While

the maximum load current in normal operation can be used to determine the required power rating for resistor

R_S, basing it on the current limit value provides a more reliable design since the circuit can operate near the

current limit threshold continuously. The resistor’s surge capability must also be considered since the circuit

breaker threshold is 1.8 or 3.6 times the current limit threshold.

Connections from R_Sto the LM25066I/A should be made using Kelvin techniques. In the suggested layout of

Figure 37, the small pads at the lower corners of the sense resistor connect only to the sense resistor terminals

and not to the traces carrying the high current. With this technique, only the voltage across the sense resistor is

applied to VIN and SENSE, eliminating the voltage drop across the high current solder connections.

HIGH CURRENT PATH

TO DRAIN OF

MOSFET Q

FROM SYSTEM

INPUT VOLTAGE

SENSE

RESISTOR

1

R

S

VIN

SENSE

Figure 37. Sense Resistor Connections

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POWER LIMIT THRESHOLD

The LM25066I/A determines the power dissipation in the external MOSFET (Q₁) by monitoring the drain current

(the current in R_S), and the V_DSof Q₁(SENSE to OUT pins). The resistor at the PWR pin (R_PWR) sets the

maximum power dissipation for Q₁and is calculated from Equation 2:

R_PWR= 1.71 x 10⁵x R_Sx P_MOSFET(LIM)

(2)

where P_MOSFET(LIM)is the desired power limit threshold for Q₁and R_Sis the current sense resistor described in

Current Limit. For example, if R_Sis 10 mΩ and the desired power limit threshold is 20W, R_PWRcalculates to 34.2

kΩ. If Q₁’s power dissipation reaches the threshold, Q₁’s gate is controlled to regulate the load current, keeping

Q₁’s power from exceeding the threshold. For proper operation of the power limiting feature, R_PWRmust be ≤150

kΩ. While the power limiting circuit is active, the fault timer is active as described in Fault Timer and Restart.

Typically, power limit is reached during startup, or if the output voltage falls because of a severe overload or

short circuit. The programmed maximum power dissipation should have a reasonable margin from the maximum

power defined by the SOA chart, especially if retry is enabled since the MOSFET will be repeatedly stressed

during fault restart cycles. The MOSFET manufacturer should be consulted for guidelines. If the application does

not require use of the power limit function, the PWR pin can be left open. The accuracy of the power limit

function at turn-on may degrade if a very low value power dissipation limit is set. The reason for this caution is

that the voltage across the sense resistor, which is monitored and regulated by the power limit circuit, is lowest at

turn-on when the regulated current is at a minimum. The voltage across the sense resistor during power limit can

be expressed as follows:

R_PWR

1.71 x 10⁵x V_DS

R_Sx P_FET(LIM)

=

V_SENSE= I_Lx R_S=

V_DS

(3)

where I_Lis the current in R_Sand V_DSis the voltage across Q₁. For example, if the power limit is set at 20W with

R_S= 10 mΩ and V_DS= 15V, the sense resistor voltage calculates to 13.3 mV, which is comfortably regulated by

the LM25066I/A. However, if the power limit is set lower (e.g. 2W), the sense resistor voltage calculates to 1.33

mV. At this low level, noise and offsets within the LM25066I/A may degrade the power limit accuracy. To

maintain accuracy, the sense resistor voltage should not be less than 5 mV.

TURN-ON TIME

The output turn-on time depends on whether the LM25066I/A operates in current limit, or in both power limit and

current limit, during turn-on.

A) Turn-on with current limit only: The current limit threshold (I_LIM) is determined by the current sense resistor

(R_S). If the current limit threshold is less than the current defined by the power limit threshold at maximum V_DS

,

the circuit operates at the current limit threshold only during turn-on. Referring to Figure 39A, as the load current

reaches I_LIM, the gate-to-source voltage is controlled at V_GSLto maintain the current at I_LIM. As the output voltage

reaches its final value (V_DS≊ 0V) the drain current reduces to its normal operating value. The time for the OUT

pin voltage to transition from zero volts to V_SYSis equal to:

V_SYSx C_L

t_ON

=

I_LIM

(4)

where C_Lis the load capacitance. For example, if V_SYS= 12V, C_L= 1000 µF, and I_LIM= 1A, t_ONcalculates to 12

ms. The maximum instantaneous power dissipated in the MOSFET is 12W. This calculation assumes the time

from t₁to t₂in Figure 40(a) is small compared to t_ONand the load does not draw any current until after the output

voltage has reached its final value, and PGD switches high (Figure 39A). The Fault Timeout Period must be set

longer than t_ONto prevent a fault shutdown before the turn-on sequence is complete.

If the load draws current during the turn-on sequence (Figure 39B), the turn-on time is longer than the above

calculation and is approximately equal to:

(I_LIMx R_L) - V_SYS

t_ON= -(R_Lx C_L) x In

(I_LIMx R_L)

(5)

where R_Lis the load resistance. The Fault Timeout Period must be set longer than t_ONto prevent a fault

shutdown before the turn-on sequence is complete.

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R

S

Q1

V

SYS

SENSE

OUT

PGD

VIN

LM25066I/A

R

C

L

GND

Figure 38. A. No Load Current During Turn-On

R

S

Q1

V

SYS

OUT

PGD

SENSE

VIN

C

R

L

LM25066I/A

GND

Load Draws Current During Turn-On

Figure 39. Current During Turn-On

B) Turn-On with Power Limit and Current Limit: The maximum allowed power dissipation in Q₁(P_MOSFET(LIM)

)

is defined by the resistor at the PWR pin, and the current sense resistor R_S. See POWER LIMIT THRESHOLD. If

the current limit threshold (I_LIM) is higher than the current defined by the power limit threshold at maximum V_DS

(P_MOSFET(LIM)/V_SYS), the circuit operates initially in the power limit mode when the V_DSof Q₁is high and then

transitions to current limit mode as the current increases to I_LIMand V_DSdecreases. Assuming the load (R_L) is not

connected during turn-on, the time for the output voltage to reach its final value is approximately equal to:

2

C_Lx P_MOSFET(LIM)

C_Lx V_SYS

t_ON

=

+

2

2 x P_MOSFET(LIM)

2 x I_LIM

(6)

For example, if V_SYS= 12V, C_L= 1000 µF, I_LIM= 1A, and P_MOSFET(LIM)= 10W, t_ONcalculates to ≊12.2 ms, and the

initial current level (I_P) is approximately 0.83A. The Fault Timeout Period must be set longer than t_ON

.

V

SYS

V

SYS

V

DS

V

DS

Drain Current

I

LIM

0

I

P

0

V

GATE

V

GATE

Gate-to-Source Voltage

V

GSL

V

GSL

V

TH

V

TH

t

ON

0

t3

t1 t2

0

a) Current Limit Only

b) Power Limit and Current Limit

Figure 40. MOSFET Power Up Waveforms

TIMER CAPACITOR, C_T

The TIMER pin capacitor (C_T) sets the timing for the insertion time delay, fault timeout period, and the restart

timing of the LM25066I/A.

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A) Insertion Delay -Upon applying the system voltage (V_SYS) to the circuit, the external MOSFET (Q₁) is held off

during the insertion time (t₁in Figure 32) to allow ringing and transients at V_SYSto settle. Since each backplane’s

response to a circuit card plug-in is unique, the worst case settling time must be determined for each application.

The insertion time starts when VIN reaches the POR threshold, at which time the internal 5.5 µA current source

charges C_Tfrom 0V to 1.7V. The required capacitor value is calculated from:

t₁x 5.5 mA

= t₁x 3.2 x 10^-6

C_T=

1.7V

(7)

For example, if the desired insertion delay is 250 ms, C_Tcalculates to 0.8 µF. At the end of the insertion delay,

C_Tis quickly discharged by a 1.9 mA current sink.

B) Fault Timeout Period -During inrush current limiting or upon detection of a fault condition where the current

limit and/or power limit circuits regulate the current through Q₁, the fault timer current source (90 µA) is switched

on to charge C_T. The Fault Timeout Period is the time required for the TIMER pin voltage to reach 1.7V, at which

time Q₁is switched off. The required capacitor value for the desired Fault Timeout Period t_FAULTis calculated

from:

t_FAULTx 90 mA

= t_FAULTx 5.3 x 10^-5

C_T=

1.7V

(8)

For example, if the desired Fault Timeout Period is 15 ms, C_Tcalculates to 0.8 µF. C_Tis discharged by the 2.8

µA current sink at the end of the Fault Timeout Period. After the Fault Timeout Period, if retry is disabled, the

LM25066I/A latches the GATE pin low until a power up sequence is initiated by external circuitry. When the Fault

Timeout Period of the LM25066I/A expires, a restart sequence starts as described below (Restart Timing).

During consecutive cycles of the restart sequence, the fault timeout period is shorter than the initial fault timeout

period described above by approximately 20% since the voltage at the TIMER pin starts ramping up from 0.3V

rather than ground.

Since the LM25066I/A normally operates in power limit and/or current limit during a power up sequence, the

Fault Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See

TURN-ON TIME.

C) Restart Timing - For the LM25066I/A, after the Fault Timeout Period described above, C_Tis discharged by

the 2.8 µA current sink to 1V. The TIMER pin then cycles through seven additional charge/discharge cycles

between 1V and 1.7V as shown in Figure 34. The restart time ends when the TIMER pin voltage reaches 0.3V

during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:

1.4V

7 x 0.7V

t_RESTART= C_Tx

+

2.8 mA

90 mA

2.8 mA

(9)

= C_Tx 2.3 x 10⁶

(10)

For example, if C_T= 0.8 µF, t_RESTART= 2 seconds. At the end of the restart time, Q₁is switched on. If the fault is

still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q₁is approximately 0.67%

in this mode.

UVLO, OVLO

By programming the UVLO and OVLO thresholds the LM25066I/A enables the series pass device (Q₁) when the

input supply voltage (V_SYS) is within the desired operational range. If V_SYSis below the UVLO threshold, or above

the OVLO threshold, Q₁is switched off, denying power to the load. Hysteresis is provided for each threshold.

Option A: The configuration shown in Figure 41 requires three resistors (R1-R3) to set the thresholds.

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V

SYS

VIN

23mA

R1

1.16V

UVLO/EN

OVLO

TIMER AND

GATE

LOGIC CONTROL

R2

R3

23 mA

LM25066I/A

GND

Figure 41. UVLO and OVLO Thresholds Set By R1-R3

The procedure to calculate the resistor values is as follows:

•

Choose the upper UVLO threshold (V_UVH), and the lower UVLO threshold (V_UVL).

Choose the upper OVLO threshold (V_OVH).

The lower OVLO threshold (V_OVL) cannot be chosen in advance in this case, but is determined after the

values for R1-R3 are determined. If V_OVLmust be accurately defined in addition to the other three thresholds,

see Option B below. The resistors are calculated as follows:

V_UV(HYS)

V_UVH- V_UVL

R1 =

R3 =

R2 =

=

23 mA

(11)

(12)

(13)

1.16V x R1 x V_UVL

V_OVHx (V_UVLœ 1.16V)

1.16V x R1

- R3

V_UVL- 1.16V

The lower OVLO threshold is calculated from:

V_OVL= [(R1 + R2) x ((1.16V) - 23 mA)] + 1.16V

R3

(14)

As an example, assume the application requires the following thresholds: V_UVH= 8V, V_UVL= 7V, V_OVH= 15V.

8V - 7V

1V

R1 =

= 43.5 kW

=

23 mA

(15)

(16)

(17)

1.16V x R1 x 7V

R3 =

= 4.03 kW

15V x (7V - 1.16V)

1.16V x R1

R2 =

- R3 = 4.61 kW

(7V œ 1.16V)

The lower OVLO threshold calculates to 12.03V and the OVLO hysteresis is 2.97V. Note that the OVLO

hysteresis is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor

values are known, the threshold voltages and hysteresis are calculated from the following:

1.16V

(R2 + R3)

V_UVH= 1.16V + [R1 x (23 mA +

)]

(18)

1.16V x (R1 + R2 + R3)

V_UVL

=

R2 + R3

(19)

(20)

V_UV(HYS)= R1 x 23µA

1.16V x (R1 + R2 + R3)

R3

V_OVH

=

(21)

V_OVL= [(R1 + R2) x (1.16V) - 23 mA)] + 1.16V

R3

(22)

(23)

V_OV(HYS)= (R1 + R2) x 23µA

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Option B: If all four thresholds must be accurately defined, the configuration in Figure 42 can be used.

V

SYS

VIN

23mA

R1

UVLO/EN

1.16V

TIMER AND

R2

GATE

R3

R4

LOGIC CONTROL

1.16V

OVLO

23 mA

LM25066I/A

GND

Figure 42. Programming the Four Thresholds

The four resistor values are calculated as follows: - Choose the upper and lower UVLO thresholds (V_UVH) and

(V_UVL).

V_UV(HYS)

V_UVH- V_UVL

R1 =

=

23 mA

(24)

(25)

1.16V x R1

R2 =

(V_UVL- 1.16V)

- Choose the upper and lower OVLO threshold (V_OVH) and (V_OVL).

V_OV(HYS)

V_OVH- V_OVL

R3 =

=

23 mA

(26)

(27)

1.16V x R3

(V_OVH- 1.16V)

R4 =

As an example, assume the application requires the following thresholds: V_UVH= 8V, V_UVL= 7V, V_OVH= 15.5V,

and V_OVL= 14V. Therefore V_UV(HYS)= 1V and V_OV(HYS)= 1.5V. The resistor values are:

R1 = 43.5 kΩ, R2 = 8.64 kΩ

R3 = 65.2 kΩ, R4 = 5.27 kΩ

When the R1-R4 resistor values are known, the threshold voltages and hysteresis are calculated from the

following:

V_UVH= 1.16V + [R1 x (1.16V + 23 mA)]

R2

(28)

1.16V x (R1 + R2)

V_UVL

=

R2

(29)

(30)

V_UV(HYS)= R1 x 23 µA

1.16V x (R3 + R4)

V_OVH

=

R4

(31)

V_OVL= 1.16V + [R3 x (1.16V - 23 mA)]

R4

(32)

(33)

V_OV(HYS)= R3 x 23 µA

Option C: The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 43.

Q₁is switched on when the VIN voltage reaches the POR threshold (≊2.6V). The OVLO thresholds are set using

R3, R4. Their values are calculated using the procedure in Option B.

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V

SYS

VIN

23 ꢀA

10k

1.16V

UVLO/EN

TIMER AND

GATE

R3

LOGIC CONTROL

1.16V

OVLO

R4

LM25066I/A

23 ꢀA

GND

Figure 43. UVLO = POR

Option D: The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as

described in Option B or Option C.

POWER GOOD

When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is

disabled allowing PGD to rise to V_PGDthrough the pullup resistor, R_PG, as shown in Figure 45. The pullup voltage

(V_PGD) can be as high as 17V, and can be higher or lower than the voltages at VIN and OUT. VDD is a

convenient choice for V_PGDas it allows interface to low voltage logic and avoids glitching on PGD during power-

up. If a delay is required at PGD, suggested circuits are shown in Figure 46 In Figure 46A, capacitor C_PGadds

delay to the rising edge, but not to the falling edge. In Figure 46B, the rising edge is delayed by R_PG1+ R_PG2and

C_PG, while the falling edge is delayed a lesser amount by R_PG2and C_PG. Adding a diode across R_PG2

(Figure 46C) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the

falling edge.

Setting the output threshold for the PGD pin requires two resistors (R4, R5) as shown in Figure 44. While

monitoring the output voltage is shown in Figure 44. R4 can be connected to any other voltage which requires

monitoring.

The resistor values are calculated as follows:

Choose the upper and lower threshold (V_PGDH) and (V_PGDL) at V_OUT

.

V_PGD(HYS)

V_PGDH- V_PGDL

R4 =

R5 =

=

24 mA

1.167V x R4

(V_PGDH- 1.167V)

(34)

As an example, assume the application requires the following thresholds: V_PGDH= 10.14V, and V_PGDL= 9.9V.

Therefore V_PGD(HYS)= 0.24V. The resistor values are:

R4 = 10 kΩ, R5 = 1.3 kΩ

Where the R4 and R5 resistor values are known, the threshold voltages and hysteresis are calculated from the

following:

1.167V x (R4 + R5)

V_PGDH

=

R5

V_PGDL= 1.167V + [R4 x (1.167V + 24 mA)]

R5

V_PGD(HYS)= R4 x 24 mA

(35)

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Q1

V

OUT

1.167V

GATE

LM25066I/A

R4

FB

R5

24uA

PGD

from UVLO

from OVLO

GND

Figure 44. Programming the PGD Threshold

V

PGD

R

PG

LM25066I/A

Power Good

GND

Figure 45. Power Good Output

V

PGD

V

PGD

R

PG1

LM25066I/A

R

PG1

PGD

Power

Good

Power

Good

Power

Good

R

PG2

R

PG2

C

PG

C

PG

GND

A) Delay at Rising Edge Only

GND

B) Long Delay at Rising Edge,

Short Delay at Falling Edge

C) Short Delay at Rising Edge and

Long Delay at Falling Edge or

Equal Delays

Figure 46. Adding Delay to the Power Good Output Pin

SYSTEM CONSIDERATIONS

A) Continued proper operation of the LM25066I/A hot-swap circuit normally dictates that capacitance be present

on the supply side of the connector into which the hot-swap circuit is plugged in, as depicted in Figure 47. The

capacitor in the “LIVE POWER SOURCE” section is necessary to absorb the transient generated whenever the

hot-swap circuit shuts off the load current. If the capacitance is not present, parasitic inductance of the supply

lines will generate a voltage transient at shut-off which may exceed the absolute maximum rating of the

LM25066I/A, resulting in its destruction. A TVS device with appropriate voltage and power ratings can also be

connected from VIN to GND to clamp the voltage spike (see application note AN-2100 SNVA464).

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B) If the load powered by the LM25066I/A hot-swap circuit has inductive characteristics, a Schottky diode is

required across the LM25066I/A’s output along with some load capacitance. The capacitance and diode are

necessary to limit the negative excursion at the OUT pin when the load current is shut off. If the OUT pin

transitions more than 0.3V negative, the LM25066I/A will internally reset, erasing the volatile setting for retries

and warning thresholds. See Figure 47. To alleviate this, a small gate resistance (e.g. 10Ω) can be used. This

resistor has the added benefit of damping any high frequency gate voltage oscillations, particularly in paralleled

FET arrangements.

R

S

V

SYS

Q

1

V

OUT

+12V

LIVE

POWER

SOURCE

SENSE GATE

OUT

VIN

TVS

D1

C

L

Schottky

D2

Inductive

Load

LM25066I/A

GND

PLUG-IN BOARD

Figure 47. Output Diode Required for Inductive Loads

PC BOARD GUIDELINES

The following guidelines should be followed when designing the PC board for the LM25066I/A:

•

Place the LM25066I/A close to the board’s input connector to minimize trace inductance from the connector

to the MOSFET.

•

Place a small capacitor, C_IN(1nF), directly adjacent to the VIN and GND pins of the LM25066I/A to help

minimize transients which may occur on the input supply line. Transients of several volts can easily occur

when the load current is shut off. ASIDE: note that if the current drawn by such capacitor is deemed

unacceptable, input voltage spike transients can be appropriately miniminzed by proper placement of a TVS

device and operation without this C_INcapacitor becomes feasible.

•

Place a 1 µF capacitor as close as possible to VREF pin.

Place a 1 µF capacitor as close as possible to VDD pin.

The sense resistor (R_S) should be placed close to the LM25066I/A. In particular, the trace to the VIN pin

should be made as low resistance as practical to ensure maximum current and power measurement

accuracy. Connect R_Susing the Kelvin techniques shown in Figure 37.

•

The high current path from the board’s input to the load (via Q₁) and the return path should be parallel and

close to each other to minimize parasitic loop inductance.

The ground connections for the various components around the LM25066I/A should be connected directly to

each other and to the LM25066I/A’s GND pin and then connected to the system ground at one point. Do not

connect the various component grounds to each other through the high current ground line. For more details,

see application note AN-2100 SNVA464.

•

Provide adequate heat sinking for the series pass device (Q₁) to help reduce stresses during turn-on and

turn-off.

•

Keep the gate trace from the LM25066I/A to the pass MOSFET short and direct.

The board’s edge connector can be designed such that the LM25066I/A detects via the UVLO/EN pin that the

board is being removed and responds by turning off the load before the supply voltage is disconnected. For

example, in Figure 48, the voltage at the UVLO/EN pin goes to ground before V_SYSis removed from the

LM25066I/A because of the shorter edge connector pin. When the board is inserted into the edge connector,

the system voltage is applied to the LM25066I/A’s VIN pin before the UVLO voltage is taken high, thereby

allowing the LM25066I/A to turn on the output in a controlled fashion.

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GND

To

Load

V

SYS

R

S

Q1

R1

R2

R3

SCL

OUT

PGD

PWR

TIMER

RETRY

SMBA

VREF

DIODE

VAUX

LM25066I/A

PLUG-IN CARD

CARD EDGE

CONNECTOR

Figure 48. Recommended Board Connector Design

PMBus^™Command Support

The device features an SMBus interface that allows the use of PMBus^™commands to set warn levels, error

masks, and get telemetry on V_IN, V_OUT, I_IN, V_AUX, and P_IN. The supported PMBus^™commands are shown in

Table 1.

Table 1. Supported PMBus^™Commands

Number

Default

Code

Name

Function

R/W

Of Data

Bytes

Value

01h

03h

OPERATION

Retrieves or stores the operation status.

R/W

1

0

80h

CLEAR_FAULTS

Clears the status registers and re-arms the black box registers

for updating.

Send

Byte

19h

43h

4Fh

CAPABILITY

VOUT_UV_WARN_LIMIT

OT_FAULT_LIMIT

Retrieves the device capability.

R

1

2

B0h

Retrieves or stores output under-voltage warn limit threshold.

Retrieves or stores over-temperature fault limit threshold.

R/W

0000h

0FFFh

(256°C)

51h

OT_WARN_LIMIT

Retrieves or stores over-temperature warn limit threshold.

R/W

2

0FFFh

(256°C)

57h

58h

5Dh

VIN_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT

IIN_OC_WARN_LIMIT

Retrieves or stores input over-voltage warn limit threshold.

Retrieves or stores input under-voltage warn limit threshold.

R/W

2

0FFFh

0000h

0FFFh

Retrieves or stores input current warn limit threshold (mirror at

D3h)

78h

79h

7Ah

7Ch

7Dh

7Eh

7Fh

80h

STATUS_BYTE

STATUS_WORD

Retrieves information about the part operating status.

Retrieves information about output voltage status.

Retrieves information about input status.

R

1

2

1

01h

0801h

00h

STATUS_VOUT

STATUS_INPUT

10h

STATUS_TEMPERATURE

STATUS_CML

Retrieves information about temperature status.

Retrieves information about communications status.

Retrieves other status information

00h

STATUS_OTHER

00h

STATUS_MFR_SPECIFIC

Retrieves information about circuit breaker and MOSFET

shorted status.

10h

86h

READ_EIN

Retrieves energy meter measurement.

R

6

00h 00h

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Table 1. Supported PMBus^™Commands (continued)

Number

Of Data

Bytes

Default

Value

Code

Name

Function

R/W

88h

89h

8Bh

8Dh

97h

98h

99h

READ_VIN

READ_IIN

Retrieves input voltage measurement.

Retrieves input current measurement (Mirror at D1h).

Retrieves output voltage measurement.

R

2

1

2

0000h

22h

READ_VOUT

READ_TEMPERATURE_1

READ _PIN

Retrieves temperature measurement.

Retrieves averaged input power measurement (mirror at DFh).

Retrieves PMBus Revision

PMBUS_Revision

MFR_ID

Retrieves manufacturer ID in ASCII characters (TI).

54h

49h

9Ah

MFR_MODEL

Retrieves Part number in ASCII characters. (LM25066I).

R

8

4Ch

4Dh

32h

35h

30h

36h

49h

9Bh

D0h

D1h

D2h

D3h

D4h

D5h

D6h

D7h

D8h

D9h

DAh

MFR_REVISION

Retrieves part revision letter/number in ASCII (e.g. AA).

Retrieves auxiliary voltage measurement.

R

2

41h A

MFR_SPECIFIC_00

READ_VAUX

0000h

0FFFh

0000h

MFR_SPECIFIC_01

MFR_READ_IIN

Retrieves input current measurement. (Mirror at 89h)

Retrieves input power measurement.

R

2

MFR_SPECIFIC_02

MFR_READ_PIN

R

2

MFR_SPECIFIC_03

MFR_IIN_OC_WARN_LIMIT

Retrieves or stores input current limit warn threshold. (Mirror at

5Dh)

R/W

R

2

MFR_SPECIFIC_04

MFR_PIN_OP_WARN_LIMIT

Retrieves or stores input power limit warn threshold.

Retrieves measured maximum input power measurement.

Resets the contents of the peak input power register to zero.

Disables external MOSFET gate control for FAULTs.

Retrieves or stores user user fault mask.

2

MFR_SPECIFIC_05

READ_PIN_PEAK

2

MFR_SPECIFIC_06

CLEAR_PIN_PEAK

Send

Byte

0

MFR_SPECIFIC_07

GATE_MASK

R/W

R

1

0000h

FD04h

0000h

MFR_SPECIFIC_08

ALERT_MASK

2

MFR_SPECIFIC_09

DEVICE_SETUP

Retrieves or stores information about number of retry attempts.

1

MFR_SPECIFIC_10

BLOCK_READ

Retrieves most recent diagnostic and telemetry information in a

single transaction.

12

0460h

0000h

DBh

DCh

DDh

DEh

DFh

MFR_SPECIFIC_11

SAMPLES_FOR_AVG

2^n number of samples to be averaged, range = 00h to 0Ch .

Retrieves averaged input voltage measurement.

R/W

R

1

2

08h

MFR_SPECIFIC_12

READ_AVG_VIN

0000h

MFR_SPECIFIC_13

READ_AVG_VOUT

Retrieves averaged output voltage measurement.

Retrieves averaged input current measurement.

R

MFR_SPECIFIC_14

READ_AVG_IIN

R

MFR_SPECIFIC_15

READ_AVG_PIN

Retrieves averaged input power measurement. (Mirror at 97h)

R

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Table 1. Supported PMBus^™Commands (continued)

Number

Of Data

Bytes

Default

Value

Code

Name

Function

R/W

E0h

MFR_SPECIFIC_16

BLACK_BOX_READ

Captures diagnostic and telemetry information which are

latched when the first SMBA alert occurs after faults have been

cleared.

R

12

0000h

E1h

MFR_SPECIFIC_17

READ_DIAGNOSTIC_WORD

Manufacturer-specific parallel of the STATUS_WORD to convey

all FAULT/WARN data in a single transaction.

R

2

0880h

E2h

MFR_SPECIFIC_18

AVG_BLOCK_READ

Retrieves most recent average telemetry and diagnostic

information in a single transaction.

12

0880h

0000h

Standard PMBus™ Commands

OPERATION (01h)

The OPERATION command is a standard PMBus^™command that controls the MOSFET switch. This command

may be used to switch the MOSFET ON and OFF under host control. It is also used to re-enable the MOSFET

after a fault triggered shutdown. Writing an OFF command followed by an ON command will clear all faults.

Writing only an ON command after a fault triggered shutdown will not clear the fault registers. The OPERATION

command is issued with the write byte protocol.

Table 2. Recognized OPERATION Command Values

Value

80h

Meaning

Default

80h

Switch ON

Switch OFF

00h

n/a

CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is a standard PMBus^™command that resets all stored warning and fault flags

and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued,

the SMBA signal may not clear or will re-assert almost immediately. Issuing a CLEAR_FAULTS command will

not cause the MOSFET to switch back on in the event of a fault turn-off: that must be done by issuing an

OPERATION command after the fault condition is cleared. This command uses the PMBus^™send byte protocol.

CAPABILITY (19h)

The CAPABILITY command is a standard PMBus^™command that returns information about the PMBus^™

functions supported by the LM25066I/A. This command is read with the PMBus^™read byte protocol.

Table 3. CAPABILITY Register

Value

Meaning

Default

B0h

Supports Packet Error Check, 400Kbits/sec, Supports SMBus Alert

B0h

VOUT_UV_WARN_LIMIT (43h)

The VOUT_UV_WARN_LIMIT command is a standard PMBus^™command that allows configuring or reading the

threshold for the VOUT Under-voltage Warning detection. Reading and writing to this register should use the

coefficients shown in Table 44. Accesses to this command should use the PMBus^™read or write word protocol.

If the measured value of VOUT falls below the value in this register, VOUT UV Warn Limit flags are set in the

respective registers, and the SMBA signal is asserted.

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Table 4. VOUT_UV_WARN_LIMIT Register

Value

Meaning

Default

1h – 0FFFh

0000h

VOUT Under-voltage Warning detection threshold

VOUT Under-voltage Warning disabled

0000h (disabled)

n/a

OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT is a standard PMBus^™command that allows configuring or reading the threshold for the

Overtemperature Fault detection. Reading and writing to this register should use the coefficients shown in

Table 44. Accesses to this command should use the PMBus^™read or write word protocol. If the measured

temperature exceeds this value, an overtemperature fault is triggered, the MOSFET is switched off, OT Fault

flags are set in the respective registers, and the SMBA signal is asserted. After the measured temperature falls

below the value in this register, the MOSFET may be switched back on with the OPERATION command. A

single temperature measurement is an average of 16 milliseconds of data. Therefore, the temperature fault

detection time maybe up to 16 ms.

Table 5. OT_FAULT_LIMIT Register

Value

Meaning

Default

0h – 0FFFh

0FFFh

Overtemperature Fault Threshold Value

Overtemperature Fault detection disabled

0FFFh (256°C)

n/a

OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT is a standard PMBus^™command that allows configuring or reading the threshold for the

Overtemperature Warning detection. Reading and writing to this register should use the coefficients shown in

Table 44. Accesses to this command should use the PMBus^™read or write word protocol. If the measured

temperature exceeds this value, an overtemperature warning is triggered, the OT Warn flags are set in the

respective registers, and the SMBA signal is asserted. A single temperature measurement is an average of 16

milliseconds of data. Therefore, the temperature warn detection time maybe up to 16 ms.

Table 6. OT_WARN_LIMIT Register

Value

Meaning

Default

0h – 0FFFh

0FFFh

Overtemperature Warn Threshold Value

Overtemperature Warn detection disabled

0FFFh (256°C)

n/a

VIN_OV_WARN_LIMIT (57h)

The VIN_OV_WARN_LIMIT is a standard PMBus^™command that allows configuring or reading the threshold for

the VIN Over-voltage Warning detection. Reading and writing to this register should use the coefficients shown in

Table 44. Accesses to this command should use the PMBus^™read or write word protocol. If the measured value

of VIN rises above the value in this register, VIN OV Warn flags are set in the respective registers, and the

SMBA signal is asserted.

Table 7. VIN_OV_WARN_LIMIT Register

Value

Meaning

Default

0h – 0FFFh

0FFFh

VIN Over-voltage Warning detection threshold

VIN Over-voltage Warning disabled

0FFFh (disabled)

n/a

VIN_UV_WARN_LIMIT (58h)

The VIN_UV_WARN_LIMIT is a standard PMBus^™command that allows configuring or reading the threshold for

the VIN Under-voltage Warning detection. Reading and writing to this register should use the coefficients shown

in Table 44. Accesses to this command should use the PMBus^™read or write word protocol. If the measured

value of VIN falls below the value in this register, VIN UV Warn flags are set in the respective registers, and the

SMBA signal is asserted.

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Table 8. VIN_UV_WARN_LIMIT Register

Value

Meaning

Default

1h – 0FFFh

VIN Under-voltage Warning detection

threshold

0000h (disabled)

0000h

VIN Under-voltage Warning disabled

n/a

IIN_OC_WARN_LIMIT (5Dh)

The IIN_OC_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the

threshold for the input current, over current warning. For access to this command use the PMBus Read or Write

word protocol. The coefficients show in table 43. To read data use the SMBus Read Word protocol. To write data

use the SMBus Write Word protocol. Sets the input current threshold above which a warning will be generated.

(Mirror at D3h)

STATUS_BYTE (78h)

The STATUS_BYTE command is a standard PMBus^™command that returns the value of a number of flags

indicating the state of the LM25066I/A. Accesses to this command should use the PMBus^™read byte protocol.

To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued.

Table 9. STATUS_BYTE Definitions

Bit

7

NAME

BUSY

Meaning

Not Supported, always 0

Default

0

1

6

OFF

This bit is asserted if the MOSFET is not switched on for any reason.

Not Supported, always 0

5

VOUT OV

IOUT OC

4

OC Fault or OP Fault

3

VIN UV FAULT

TEMPERATURE

CML

A VIN Under-voltage Fault has occurred

A Temperature Fault or Warning has occurred

A Communication Fault has occurred

A fault or warning not listed in bits [7:1] has occurred

2

1

0

None of the Above

STATUS_WORD (79h)

The STATUS_WORD command is a standard PMBus^™command that returns the value of a number of flags

indicating the state of the LM25066I/A. Accesses to this command should use the PMBus™ read word protocol.

To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command issued.

The INPUT and VIN UV FAULT flags will default to 1 on startup. However, they will be cleared to 0 after the first

time the input voltage exceeds the resistor programmed UVLO threshold.

Table 10. STATUS_WORD Definitions

Bit

15

14

13

12

11

10

9

NAME

VOUT

Meaning

An output voltage fault or warning has occurred

Not Supported, always 0

Default

0

1

0

IOUT/POUT

INPUT

An input voltage or current fault has occurred

FET Fail

POWER GOOD

FANS

The Power Good signal has been negated

Not Supported, always 0

CB Fault

Circuit Breaker Fault has occurred

Not Supported, always 0

8

UNKNOWN

BUSY

7

Not Supported, always 0

6

OFF

This bit is asserted if the MOSFET is not switched on for any reason.

Not Supported, always 0

5

VOUT OV

IOUT OC/OP

VIN UV FAULT

TEMPERATURE

4

IIN overcurrent fault or FET dissapation fault

A VIN Under-voltage Fault has occurred

A Temperature Fault or Warning has occurred

3

2

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Table 10. STATUS_WORD Definitions (continued)

Bit

1

NAME

CML

Meaning

Default

A Communication Fault has occurred

A fault or warning not listed in bits [7:1] has occurred

0

1

0

None of the Above

STATUS_VOUT (7Ah)

The STATUS_VOUT command is a standard PMBus^™command that returns the value of the VOUT UV Warning

flag. Accesses to this command should use the PMBus^™read byte protocol. To clear bits in this register, the

underlying fault should be removed and a CLEAR_FAULTS command issued.

Table 11. STATUS_VOUT Definitions

Bit

7

NAME

Meaning

Not Supported, always 0

Default

VOUT OV Fault

VOUT OV Warn

VOUT UV Warn

VOUT UV Fault

VOUT Max

0

6

Not Supported, always 0

5

A VOUT Under-voltage Warning has occurred

Not Supported, always 0

4

3

Not Supported, always 0

2

TON Max Fault

TOFF Max Fault

VOUT Tracking Error

Not Supported, always 0

1

Not Supported, always 0

0

Not Supported, always 0

STATUS_INPUT (7Ch)

The STATUS_INPUT command is a standard PMBus^™command that returns the value of a number of flags

related to input voltage, current, and power. Accesses to this command should use the PMBus^™read byte

protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command

issued. The VIN UV Warn flag will default to 1 on startup. However, it will be cleared to 0 after the first time the

input voltage exceeds the resistor programmed UVLO threshold.

Table 12. STATUS_INPUT Definitions

Bit

7

NAME

VIN OV Fault

VIN OV Warn

VIN UV Warn

VIN UV Fault

Insufficient Voltage

IIN OC Fault

Meaning

Default

A VIN Over-voltage Fault has occurred

A VIN Over-voltage Warning has occurred

A VIN Under-voltage Warning has occurred

A VIN Under-voltage Fault has occurred

Not Supported, always 0

0

1

0

6

5

4

3

2

An IIN Over-current Fault has occurred

An IIN Over-current Warning has occurred

A PIN Over-power Warning has occurred

1

IIN OC Warn

PIN OP Warn

0

STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE is a standard PMBus^™command that returns the value of the of a number of

flags related to the temperature telemetry value. Accesses to this command should use the PMBus^™read byte

protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command

issued.

Table 13. STATUS_TEMPERATURE Definitions

Bit

7

NAME

Meaning

Default

Overtemp Fault

Overtemp Warn

Undertemp Warn

Undertemp Fault

reserved

An Overtemperature Fault has occurred

An Overtemperature Warning has occurred

Not Supported, always 0

0

6

5

4

Not Supported, always 0

3

Not Supported, always 0

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Table 13. STATUS_TEMPERATURE Definitions (continued)

Bit

2

NAME

Meaning

Default

reserved

Not Supported, always 0

0

1

0

STATUS_CML (7Eh)

The STATUS_CML command is a standard PMBus^™command that returns the value of a number of flags

related to communication faults. Accesses to this command should use the PMBus^™read byte protocol. To clear

bits in this register, a CLEAR_FAULTS command should be issued.

Table 14. STATUS_CML Definitions

Bit

7

NAME

Default

Invalid or unsupported command received

Invalid or unsupported data received

0

6

5

Packet Error Check failed

4

Memory Fault Detected Not supported, always 0

Processor Fault Detected Not supported, always 0

Reserved, always 0

3

2

1

Miscellaneous communications fault has occurred

Other memory or logic fault detected Not supported, always 0

0

STATUS_OTHER (7Fh)

Bit

7

NAME

Default

Reserved: always 0

CB Fault

0

6

5

4

Not supported: Always 0

3

2

1

0

STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command is a standard PMBus^™command that contains manufacturer specific

status information. Accesses to this command should use the PMBus^™read byte protocol. To clear bits in this

register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued. The default

loaded status does not create an SMB Alert State.

Table 15. STATUS_MFR_SPECIFIC Definitions

Bit

7

Meaning

Default

Circuit breaker fault

0

1

0

6

Ext. MOSFET shorted fault

Not Supported, Always 0

Defaults loaded⁽¹⁾

5

4

3

Not supported: Always 0

2

1

0

(1) Bit 4, Defaults loaded, does not set an SMBAlert.

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READ_EIN (86h)

The READ_EIN command is a standard PMBus command that returns information the host can use to calculate

average input power consumption. Accesses to this command should use the PMBus Block Read protocol.

Information provided by this command is independent of any device specific averaging period. Six bytes of data

are returned by this command. The first two bytes are the two's complement, signed output of an accumulator

that continuously sums samples of the instantaneous input power. These two data bytes are formatted in the

DIRECT format. The third data byte is a count of the rollover events for the accumulator. This byte is an

unsigned integer indicating the number of times that the accumulator has rolled over from it's maximum positive

value (7FFFh) to zero. The last three data bytes are a 24 bit unsigned integer that counts the number of samples

of the instantaneous input power that have been applied to the accumulator.

The combination of the accumulator and the rollover count may overflow within a few seconds. It is left to the

host software to detect this overflow and handle it appropriately. Similarly, the sample count value will overflow,

but this event only occurs once every few hours.

To convert the data obtained with the READ_EIN command to average power, first convert the accumulator and

rollover count to an unsigned integer:

Accumulator_23 = (rollover_count << 15) + accumulator

overflow detection and handling should be done on the 23 bits of accumulator data and the sample count now.

Data from the previous calculation should be saved and will be used in this calculation to get the unscaled

average power:

Accumulator_23 [n] - Accumulator_23 [n-1]

Sample_count [n] - Sample_count [n-1]

(36)

Where:

accumulator_23 [n] = overflow corrected, 23 bit accumulator data from this read

Sample_count [n] = Sample count data from this read

accumulator_23[n-1]= overflow corrected, 23 bit accumulator data from previous read

Sample_count [n-1] = Sample Count data from previous read

unscaled Average Power is now in the same units as the data from the READ_PIN command. Coefficients from

Table 43 are used to convert the Unscaled Average Power to Watts.

Table 16. READ_EIN

Bit

0

Meaning

Default

Sample Count High byte

Sample Count Mid byte

Sample Count Low byte

Power Accumulator Rollover Count

Power Accumulator High Byte

Power Accumulator Low Byte

Number of Bytes

0

6

1

2

3

4

5

6

READ_VIN (88h)

The READ_VIN command is a standard PMBus^™command that returns the 12-bit measured value of the input

voltage. Reading this register should use the coefficients shown in Table 44. Accesses to this command should

use the PMBus^™read word protocol. This value is also used internally for the VIN Over and Under Voltage

Warning detection.

Table 17. READ_VIN Register

Value

Meaning

Default

0h – 0FFFh

Measured value for VIN

0000h

38

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READ_VOUT (8Bh)

The READ_VOUT command is a standard PMBus^™command that returns the 12-bit measured value of the

output voltage. Reading this register should use the coefficients shown in Table 44. Accesses to this command

should use the PMBus^™read word protocol. This value is also used internally for the VOUT Under Voltage

Warning detection.

Table 18. READ_VOUT Register

Value

Meaning

Default

0h – 0FFFh

Measured value for VOUT

0000h

READ_IIN (89h)

The READ_IIN command is a standard PMBus^™command that returns the 12-bit measured value of the input

current. Returns instantaneous current. Reading this register should use the coefficients shown in Table 44.

Accesses to this command should use the PMBus^™read word protocol. This value is also mirrored at (D1H)

Table 19. READ_IIN Register

Value

Meaning

Default

0h – 0FFFh

Measured value for IIN

0000h

READ_PIN (97h)

The READ_IIN command is a standard PMBus^™command that returns the 12-bit measured value of the input

current. Returns average power Reading this register should use the coefficients shown in Table 44. Accesses to

this command should use the PMBus^™read word protocol. This value is also mirrored at (DFh)

Table 20. READ_PIN Register

Value

Meaning

Default

0h – 0FFFh

Measured value for PIN

0000h

READ_TEMPERATURE_1 (8Dh)

The READ_TEMPERATURE _1 command is a standard PMBus^™command that returns the signed value of the

temperature measured by the external temperature sense diode. Reading this register should use the coefficients

shown in Table 44. Accesses to this command should use the PMBus^™read word protocol. This value is also

used internally for the Over Temperature Fault and Warning detection. This data has a range of -256°C to +

255°C after the coefficients are applied.

Table 21. READ_TEMPERATURE_1 Register

Value

Meaning

Default

0h – 0FFFh

Measured value for TEMPERATURE

0000h

MFR_ID (99h)

The MFR_ID command is a standard PMBus^™command that returns the identification of the manufacturer. To

read the MFR_ID, use the PMBus^™block read protocol.

Table 22. MFR_ID Register

Byte

Name

Number of bytes

MFR ID-1

Value

02h

0

1

2

54h ‘T’

49h ‘I’

MFR ID-2

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MFR_MODEL (9Ah)

The MFR_MODEL command is a standard PMBus^™command that returns the part number of the chip. To read

the MFR_MODEL, use the PMBus^™block read protocol.

Table 23. MFR_MODEL Register

Byte

Name

Number of bytes

MFR ID-1

MFR ID-2

MFR ID-3

MFR ID-4

MFR ID-5

MFR ID-6

MFR ID-7

MFR ID-8

Value

08h

0

1

2

3

4

5

6

7

8

4Ch ‘L’

4Dh ‘M’

32h ‘2’

35h ‘5’

30h ‘0’

36h ‘6’

49h ‘I’

MFR_REVISION (9Bh)

The MFR_REVISION command is a standard PMBus™ command that returns the revision level of the part. To

read the MFR_REVISION, use the PMBus™ block read protocol.

Table 24. MFR_REVISION Register

Byte

Name

Value

02h

0

1

2

Number of bytes

MFR ID-1

MFR ID-2

41h ‘A’

Manufacturer Specific PMBus™ Commands

MFR_SPECIFIC_00: READ_VAUX (D0h)

The READ_VAUX command will report the 12-bit ADC measured auxiliary voltage. Voltages greater than or

equal to 1.16V to ground will be reported at plus full scale (0FFFh). Voltages less than or equal to 0V referenced

to ground will be reported as 0 (0000h). Coefficients for the VAUX value are dependent on the value of the

external divider (if used). To read data from the READ_VAUX command, use the PMBus™ Read Word protocol.

Table 25. READ_VAUX Register

Value

Meaning

Default

0h – 0FFFh

Measured value for VAUX input

0000h

MFR_SPECIFIC_01: MFR_READ_IIN (D1h)

The MFR_READ_IIN command will report the 12-bit ADC measured current sense voltage. To read data from

the MFR_READ_IIN command, use the PMBus™ Read Word protocol. Reading this register should use the

coefficients shown in Table 44. Please see the section on coefficient calculations to calculate the values to use.

Table 26. MFR_READ_IIN Register

Value

Meaning

Default

0h – 0FFFh

Measured value for input current sense voltage

0000h

40

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MFR_SPECIFIC_02: MFR_READ_PIN (D2h)

The MFR_ READ_PIN command will report the upper 12 bits of the VIN x IIN product as measured by the 12-bit

ADC. To read data from the MFR_READ_PIN command, use the PMBus™ Read Word protocol. Reading this

register should use the coefficients shown in Table 44. Please see the section on coefficient calculations to

calculate the values to use.

Table 27. MFR_READ_PIN Register

Value

Meaning

Default

0h – 0FFFh

Value for input current x input voltage

0000h

MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)

The MFR_IIN_OC_ WARN_LIMIT PMBus™ command sets the input over-current warning threshold. In the event

that the input current rises above the value set in this register, the IIN over-current flags are set in the status

registers and the SMBA is asserted. To access the MFR_IIN_ OC_WARN_LIMIT register, use the PMBus™

Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in Table 44.

Table 28. MFR_IIN_OC_WARN_LIMIT Register

Value

Meaning

Default

0FFFh

n/a

0h – 0FFFh

0FFFh

Value for input over-current warn limit

Input over-current warning disabled

MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)

The MFR_PIN_OP_WARN_LIMIT PMBus™ command sets the input over-power warning threshold. In the event

that the input power rises above the value set in this register, the PIN Over-power flags are set in the status

registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus™

Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in Table 44.

Table 29. MFR_PIN_OP_WARN_LIMIT Register

Value

Meaning

Default

0FFFh

n/a

0h – 0FFFh

0FFFh

Value for input over-power warn limit

Input over-power warning disabled

MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)

The READ_PIN_PEAK command will report the maximum input power measured since a Power-On-Reset or the

last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus™ Read Word

protocol. Use the coefficients shown in Table 44.

Table 30. READ_PIN_PEAK Register

Value

Meaning

Default

0h – 0FFFh

Maximum value for input current x input voltage since reset or last clear

0h

MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)

The CLEAR_PIN_PEAK command will clear the PIN_PEAK register. This command uses the PMBus™ Send

Byte protocol.

MFR_SPECIFIC_07: GATE_MASK (D7h)

The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When

the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers will still be

updated (STATUS, DIAGNOSTIC) and an SMBA will still be issued. This register is accessed with the PMBus™

Read / Write Byte protocol.

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WARNING

Inhibiting the MOSFET switch off in response to over-current or circuit breaker

fault conditions will likely result in the destruction of the MOSFET! This

functionality should be used with great care and supervision!

Table 31. GATE_MASK Register

Bit

7

NAME

Not used, always 0

VIN UV FAULT

Default

0

6

5

4

VIN OV FAULT

3

IIN/PFET FAULT

2

OVERTEMP FAULT

Not used, always 0

CIRCUIT BREAKER FAULT

1

0

The IIN/PFET Fault refers to the input current fault and the MOSFET power dissipation fault. There is no input

power fault detection, only input power warning detection.

MFR_SPECIFIC_08: ALERT_MASK (D8h)

The ALERT_MASK is used to mask the SMBA when a specific fault or warning has occurred. Each bit

corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an

SMBA being set. When the corresponding bit is high, that condition will not cause the SMBA to be asserted. If

that condition occurs, the registers where that condition is captured will still be updated (STATUS registers,

DIAGNOSTIC_WORD) and the external MOSFET gate control will still be active (VIN_OV_FAULT,

VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus™ Read

/ Write Word protocol. The VIN UNDERVOLTGE FAULT flag will default to 1 on startup. However, it will be

cleared to 0 after the first time the input voltage exceeds the resistor programmed UVLO threshold.

Table 32. ALERT_MASK Definitions

BIT

15

14

13

12

11

10

9

NAME

DEFAULT

VOUT UNDERVOLTAGE WARN

IIN LIMIT Warn

1

0

1

0

1

0

VIN UNDERVOLTAGE WARN

VIN OVERVOLTAGE WARN

POWER GOOD

OVERTEMP WARN

Not Used, always 0

8

OVERPOWER LIMIT WARN

Not Used, always 0

7

6

EXT_MOSFET_SHORTED

VIN UNDERVOLTAGE FAULT⁽¹⁾

VIN OVERVOLTAGE FAULT

IIN/PFET FAULT

5

4

3

2

OVERTEMPERATURE FAULT

CML FAULT (Communications Fault)

CIRCUIT BREAKER FAULT

1

0

(1) VIN_UV_FAULT initializes after power up as masked. When VIN exceeds the hardware threshold the mask bit is automatically cleared.

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MFR_SPECIFIC_09: DEVICE_SETUP (D9h)

The DEVICE_SETUP command may be used to override pin settings to define operation of the LM25066I/A

under host control. This command is accessed with the PMBus™ read / write byte protocol.

Table 33. DEVICE_SETUP Byte Format

Bit

Name

Meaning

7:5

Retry setting

111 = Unlimited retries

110 = Retry 16 times

101 = Retry 8 times

100 = Retry 4 times

011 = Retry 2 times

010 = Retry 1 time

001 = No retries

000 = Pin configured retries

0 = Low setting (25mV)

1 = High setting (46mV)

0 = Low setting (1.8x)

1 = High setting (3.6x)

0 = Use pin settings

1 = Use SMBus settings

0 = Use pin settings

1 = Use SMBus settings

4

3

2

1

0

Current limit setting

CB/CL Ratio

Current limit Configuration

Circuit Breaker Configuration

Unused

In order to configure the Current Limit Setting via this register, it is necessary to set the Current Limit

Configuration bit (2) to 1 to enable the register to control the current limit function and the Current Limit Setting

bit (4) to select the desired setting. Similarly, in order to control the Circuit Breaker via this register, it is

necessary to set the Circuit Breaker Configuration bit (1) to 1 to enable the register to control the Circuit Breaker

Setting, and the Circuit Breaker / Current Limit Ratio bit (3) to the desired value. If the respective Configuration

bits are not set, the Settings will be ignored and the pin set values used.

The Current Limit Configuration effects the coefficients used for the Current and Power measurements and

warning registers.

MFR_SPECIFIC_10: BLOCK_READ (DAh)

The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry

information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the

LM25066I/A in a single SMBus transaction. The block is 12 bytes long with telemetry information being sent out

in the same manner as if an individual READ_XXX command had been issued (shown below). The contents of

the block read register are updated every clock cycle (85ns) as long as the SMBus interface is idle.

BLOCK_READ also specifies that the VIN, VOUT, IIN and PIN measurements are all time-aligned whereas there

is a chance they may not be if read with individual PMBus™ commands.

The BLOCK_READ command is read via the PMBus™ block read protocol.

Table 34. BLOCK_READ Register Format

Byte Count (always 12)

DIAGNOSTIC_WORD

IIN_BLOCK

(1 byte)

(1 Word)

VOUT_BLOCK

VIN_BLOCK

PIN_BLOCK

TEMP_BLOCK

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MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)

The SAMPLES_FOR_AVERAGE is a manufacturer specific command for setting the number of samples used in

computing the average values for IIN, VIN, VOUT, PIN. The decimal equivalent of the AVGN nibble is the power

of 2 samples (e.g. AVGN=12 equates to 4096 samples used in computing the average). The LM25066I/A

supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096. The SAMPLES_FOR_AVG

number applies to average values of IIN, VIN, VOUT, PIN simultaneously. The LM25066I/A uses simple

averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by

the number of samples. Averaging is calculated according to the following sequence:

Y = (X_(N)+ X_(N-1)+ ... + X₍₀₎) / 2^AVGN

(37)

When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a

whole new sequence begins that will require the same number of samples (in this example, 4096) to be taken

before the new average is ready.

Table 35. SAMPLES_FOR_AVG Register

AVGN

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

N=2^AVGNaverages

Averaging/Register Update Period (ms)

1

2

1

2

4

8

16

32

64

128

256

512

1024

2048

4096

128

256

512

1024

2048

4096

Note that a change in the SAMPLES_FOR_AVG register will not be reflected in the average telemetry

measurements until the present averaging interval has completed. The default setting for AVGN is 0000 and

therefore the average telemetry will mirror the instantaneous telemetry until a value higher than zero is

programmed.

The SAMPLES_FOR_AVG register is accessed via the PMBus™ read / write byte protocol.

Table 36. SAMPLES_FOR_AVG Register

Value

Meaning

Default

0h – 0Ch

Exponent (AVGN) for number of samples to average over

00h

MFR_SPECIFIC_12: READ_AVG_VIN (DCh)

The READ_AVG_VIN command will report the 12-bit ADC measured input average voltage. If the data is not

ready, the returned value will be the previous averaged data. However, if there is no previously averaged data,

the default value (0000h) will be returned. This data is read with the PMBus™ Read Word protocol. This register

should use the coefficients shown in Table 44.

Table 37. READ_AVG_VIN Register

Value

Meaning

Default

0h – 0FFFh

Average of measured values for input voltage

0000h

44

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MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)

The READ_AVG_VOUT command will report the 12-bit ADC measured average output voltage. The returned

value will be the default value (0000h) or previous data when the average data is not ready. This data is read

with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 44.

Table 38. READ_AVG_VOUT Register

Value

Meaning

Default

0h – 0FFFh

Average of measured values for output voltage

0000h

MFR_SPECIFIC_14: READ_AVG_IIN (DEh)

The READ AVG_IIN command will report the 12-bit ADC measured current sense average voltage. The returned

value will be the default value (0000h) or previous data when the average data is not ready. This data is read

with the PMBus™ Read Word protocol. This register should use the coefficients shown in Table 44.

Table 39. READ_AVG_IIN Register

Value

Meaning

Default

0h – 0FFFh

Average of measured values for current sense voltage

0000h

MFR_SPECIFIC_15: READ_AVG_PIN (DFh)

The READ_AVG_PIN command will report the upper 12 bits of the average VIN x IIN product as measured by

the 12-bit ADC. You will read the default value (0000h) or previous data when the average data is not ready.

This data is read with the PMBus™ Read Word protocol. This register should use the coefficients shown in

Table 44.

Table 40. READ_AVG_PIN Register

Value

Meaning

Default

0h – 0FFFh

Average of measured value for input voltage x input current sense voltage

0000h

MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)

The BLACK_BOX_READ command retrieves the BLOCK_READ data which was latched in at the first assertion

of SMBA. It is re-armed with the CLEAR_FAULTS command. It is the same format as the BLOCK_READ

registers, the only difference being that its contents are updated with the SMBA edge rather than the internal

clock edge. This command is read with the PMBus™ Block Read protocol.

MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)

The READ_DIAGNOSTIC_WORD PMBus command will report all of the LM25066I/A faults and warnings in a

single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read

requests to various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD register.

The READ_DIAGNOSTIC_WORD command should be read with the PMBus™ Read Word protocol. The

DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and AVG_BLOCK_READ

operations.

Table 41. READ_DIAGNOSTIC_WORD Format

Bit

15

14

13

12

11

10

Meaning

Default

VOUT_UNDERVOLTAGE_WARN

IIN_OP_WARN

0

1

0

VIN_UNDERVOLTAGE_WARN

VIN_OVERVOLTAGE_WARN

POWER GOOD

OVER_TEMPERATURE_WARN

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Table 41. READ_DIAGNOSTIC_WORD Format (continued)

Bit

9

Meaning

Default

TIMER_LATCHED_OFF

EXT_MOSFET_SHORTED

CONFIG_PRESET

0

1

0

8

7

6

DEVICE_OFF

5

VIN_UNDERVOLTAGE_FAULT

VIN_OVERVOLTAGE_FAULT

IIN_OC/PFET_OP_FAULT

OVER_TEMPERATURE_FAULT

CML_FAULT

4

3

2

1

0

CIRCUIT_BREAKER_FAULT

MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)

The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average

telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating

information of the part in a single PMBus™ transaction. The block is 12 bytes long with telemetry information

being sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown

below). AVG_BLOCK_READ also specifies that the VIN, VOUT, PIN, and IIN measurements are all time-aligned

whereas there is a chance they may not be if read with individual PMBus™ commands. To read data from the

AVG_BLOCK_READ command, use the SMBus Block Read protocol.

Table 42. AVG_BLOCK_READ Register Format

Byte Count (always 12)

DIAGNOSTIC_WORD

AVG_IIN

(1 byte)

(1 word)

AVG_VOUT

AVG_VIN

AVG_PIN

TEMPERATURE

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-

+

Figure 49. Command/Register and Alert Flow Diagram

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Reading and Writing Telemetry Data and Warning Thresholds

All measured telemetry data and user programmed warning thresholds are communicated in 12 bit two’s

compliment binary numbers read/written in 2 byte increments conforming to the Direct format as described in

section 8.3.3 of the PMBus™ Power System Management Protocol Specification 1.1 (Part II). The organization

of the bits in the telemetry or warning word is shown in Table 43, where Bit_11 is the most significant bit (MSB)

and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are

constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value

of the temperature word ranges from 0 to 65535.

Table 43. Telemetry and Warning Word Format

Byte

B7

Bit_7

0

B6

Bit_6

0

B5

Bit_5

0

B4

Bit_4

0

B3

B2

B1

B0

1

2

Bit_3

Bit_11

Bit_2

Bit_10

Bit_1

Bit_9

Bit_0

Bit_8

Conversion from direct format to real world dimensions of current, voltage, power, and temperature is

accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus™ Power

System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts

the values received into a reading of volts, amperes, watts, or other units using the following relationship:

1

(Y x 10^-R- b)

X =

m

(38)

where:

X: the calculated "real world" value (volts, amps, watt, etc.)

m: the slope coefficient

Y: a two byte two's complement integer received from device

b: the offset, a two byte two's complement integer

R: the exponent, a one byte two's complement integer

R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a

register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.

Table 44. Current, Power and Warning Conversion Coefficients (R_Sin mΩ)

Commands

Condition

Format

Number of

Data Bytes

m

b

R

Unit

READ_VIN, READ_AVG_VIN

VIN_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT

DIRECT

2

22070

-1800

-2

V

READ_VOUT, READ_AVG_VOUT

VOUT_UV_WARN_LIMIT

DIRECT

2

22070

3546

-1800

-3

-2

V

READ_VAUX

DIRECT

2

0

V

A

READ_IIN, READ_AVG_IIN

MFR_IIN_OC_WARN_LIMIT

CL = GND

CL = VDD

CL = GND

13661 x R_S-5200

-2

READ_IIN, READ_AVG_IIN

MFR_IIN_OC_WARN_LIMIT

DIRECT

2

6854 x R_S

736 x R_S

-3100

-3300

-2

A

READ_PIN, READ_AVG_PIN,

READ_PIN_PEAK

W

MFR_PIN_OP_WARN_LIMIT

READ_PIN, READ_AVG_PIN,

READ_PIN_PEAK

MFR_PIN_OP_WARN_LIMIT

CL = VDD

DIRECT

2

369 x R_S

16000

-1900

0

-2

-3

-2

W

°C

W

READ_TEMPERATURE_1

OT_WARN_LIMIT

OT_FAULT_LIMIT

READ_PIN, READ_AVG_PIN,

READ_PIN_PEAK

CL = VDD

369 x R_S

-1900

MFR_PIN_OP_WARN_LIMIT

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Table 45. Current, Power and Warning Conversion Coefficients (R_Sin mΩ)

Commands

Condition

CL = GND

CL = VDD

CL = GND

Format

DIRECT

Number of

Data Bytes

m

b

R

-2

Unit

A

*READ_IIN, READ_AVG_IIN

MFR_IIN_OC_WARN_LIMIT

2

13661 x R_S

6854 x R_S

736 x R_S

-5200

-3100

-3300

*READ_IIN, READ_AVG_IIN

MFR_IIN_OC_WARN_LIMIT

A

*READ_PIN, READ_AVG_PIN,

READ_PIN_PEAK

W

MFR_PIN_OP_WARN_LIMIT

Care must be taken to adjust the exponent coefficient, R, such that the value of m remains within the range of -

32768 to +32767. For example, if a 5 mΩ sense resistor is used, the correct coefficients for the READ_IIN

command with CL = VDD would be m = 6830, b = -310, R = -1.

A Note on the "b" Coefficient

Since b coefficients represent offset, for simplification b is set to zero in the following discussions.

Determining Telemetry Coefficients Empirically with Linear Fit

The coefficients for telemetry measurements and warning thresholds presented in Table 44 are adequate for the

majority of applications. Current and power coefficients must be calculated per application as they are dependent

on the value of the sense resistor, R_S, used. Table 45 provides the equations necessary for calculating the

current and power coefficients for the general case. The small signal nature of the current measurement make it

and the power measurement more susceptible to PCB parasitics than other telemetry channels. This may cause

slight variations in the optimum coefficients (m, b, R) for converting from Direct Format digital values to real-world

values (e.g. Amps and Watts). The optimum coefficients can be determined empirically for a specific application

and PCB layout using two or more measurements of the telemetry channel of interest. The current coefficients

can be determined using the following method:

1. While the LM25066I/A is in normal operation, measure the voltage across the sense resistor using kelvin test

points and a high accuracy DVM while controlling the load current. Record the integer value returned by the

READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more

voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should

span nearly the full scale range of the current (for example, voltage across R_Sof 5 mV and 20 mV).

2. Convert the measured voltages to currents by dividing them by the value of R_S. For best accuracy, the value

of R_Sshould be measured. Table 46 assumes a sense resistor value of 5 mΩ.

Table 46. Measurements for linear fit determination of current coefficients

Measured voltage across

R_S(V)

Measured Current (A)

READ_AVG_IIN

(integer value)

0.005

0.01

0.02

1

2

4

648

1331

2698

3. Using the spreadsheet or math program of your choice, determine the slope and the y-intercept values

returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 46:

–

READ_AVG_IIN value = slope x (Measured Current) + (y-intercept)

slope = 683.4

y-intercept = -35.5

4. To determine the ‘m’ coefficient, simply shift the decimal point of the calculated slope to arrive at an integer

with a suitable number of significant digits for accuracy (typically 4) while staying with the range of -32768 to

+32767. This shift in the decimal point equates to the ‘R’ coefficient. For the slope value shown above, the

decimal point would be shifted to the right once hence R = -1.

5. Once the ‘R’ coefficient has been determined, the ‘b’ coefficient is found by multiplying the y-intercept by 10^-

^R. In this case the value of b = -355.

–

Calculated Current Coefficients:

m = 6834

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–

b = -355

R = -1

1

(Y x 10^-R- b)

X =

m

(39)

where:

X: the calculated "real world" value (volts, amps, watts, temperature)

m: the slope coefficient, a the two byte two's complement integer

Y: a two byte, two's complement integer received from device

b: the offset, a two byte two's complement integer

R: the exponent, a one byte two's complement integer

The above procedure can be repeated to determine the coefficients of any telemetry channel simply by

substituting measured current for some other parameter (e.g. power, voltage, etc.).

Writing Telemetry Data

There are several locations that will require writing data if their optional usage is desired. Use the same

coefficients previously calculated for your application and apply them using this method as prescribed by the

PMBus™ revision section 7.2.2 "Sending a Value"

Y = (mX + b) x 10^R

(40)

where:

X: the calculated "real world" value (volts, amps, watts, temperature)

m: the slope coefficient, a two byte two's complement integer

Y: a two byte two's complement integer received from device

b: the offset, a two byte two's complement integer

R: the exponent, a one byte two's complement integer

PMBus™ Address Lines (ADR0, ADR1, ADR2)

The three address lines are to be set high (connect to VDD), low (connect to GND),open (connect to GND) to

select one of 27 addresses for communicating with the LM25066I/A. Table 47 depicts 7-bit addresses (eighth bit

is read/write bit):

Table 47. Device Addressing

ADR2

ADR1

ADR0

Decoded Address

Z

0

Z

0

1

Z

0

Z

0

1

Z

0

1

Z

0

1

Z

0

1

Z

0

1

40h

41h

42h

43h

44h

45h

46h

47h

10h

11h

12h

13h

14h

15h

16h

50

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Table 47. Device Addressing (continued)

ADR2

ADR1

ADR0

Decoded Address

0

1

Z

0

1

Z

0

1

Z

0

1

Z

0

1

Z

0

1

17h

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

SMBus Communications Timing Requirements

t

R

t

F

SCL

t

LOW

V

IH

V

IL

t

SU;STA

HIGH

SU;STO

t

SU;DAT

HD;DAT

HD;STA

SDA

V

IH

V

IL

t

BUF

P

S

P

Figure 50. SMBus Timing Diagram

Table 48. SMBus Timing Definition

Symbol

Parameter

Limits

Unit

Comments

Min

10

Max

F_SMB

T_BUF

SMBus Operating Frequency

Bus free time between Stop and Start Condition

400

kHz

µs

1.3

0.6

T_HD:STA

Hold time after (Repeated) Start Condition. After this

period, the first clock is generated.

µs

T_SU:STA

T_SU:STO

T_HD:DAT

T_SU:DAT

T_TIMEOUT

T_LOW

Repeated Start Condition setup time

Stop Condition setup time

Data hold time

0.6

300

100

25

µs

ns

ms

µs

Data setup time

(1)

(2)

Clock low time-out

35

Clock low period

1.5

0.6

T_HIGH

Clock high period

(1) Devices participating in a transfer will timeout when any clock low exceeds the value of T_TIMEOUT,MINof 25 ms. Devices that have

detected a timeout condition must reset the communication no later than T_TIMEOUT,MAXof 35 ms. The maximum value must be adhered

to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).

(2) T_{HIGH MAX}provides a simple method for devices to detect bus idle conditions.

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Table 48. SMBus Timing Definition (continued)

Symbol

Parameter

Limits

Unit

Comments

Min

Max

25

(3)

(4)

(5)

T_LOW:SEXT

T_LOW:MEXT

T_F

Cumulative clock low extend time (slave device)

Cumulative low extend time (master device)

Clock or Data Fall Time

ms

ns

10

20

300

T_R

Clock or Data Rise Time

ns

(3) T_LOW:SEXTis the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If

a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.

(4) T_LOW:MEXTis the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from

start-to-ack, ack-to-ack, or ack-to-stop.

(5) Rise and fall time is defined as follows:• T_R= ( V_ILMAX– 0.15) to (V_IHMIN+ 0.15)• T_F= 0.9 VDD to (V_ILMAX– 0.15)

SMBA Response

The SMBA effectively has two masks:

1. The Alert Mask Register at D8h, and

2. The ARA Automatic Mask.

The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation

returns the PMBus^™address of the lowest addressed part on the bus that has its SMBA asserted. A successful

ARA read means that THIS part was the one that returned its address. When a part responds to the ARA read, it

releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its

address, the SMBA signal will de-assert.

The way that the LM25066I/A releases the SMBA signal is by setting the ARA Automatic mask bit for all fault

conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not

generate an SMBA on that fault again until the ARA Automatic mask is cleared by the host issuing a Clear Fault

command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the

ARA read is not done. Figure 51 depicts a schematic version of this flow.

From other

fault inputs

SMBA

Fault Condition

Alert Mask D8h

From PMBus

Set

ARA Auto Mask

Clear

ARA Operation Flag Succeeded

CLEAR_FAULT Command Received

Figure 51. Typical Flow Schematic for SMBA Fault

52

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SNVS824C –JUNE 2012–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision B (March 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 52

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MECHANICAL DATA

NHZ0024B

SQA24B (Rev A)

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型号：	LM25066I
厂家：	TEXAS INSTRUMENTS
描述：	具有 I2C 和 PMBus 的 2.9V 至 17V 热插拔控制器，带有 Intel 节点管理器控制器
文件：	总59页 (文件大小：929K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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