LFC789D25CPWG4 [TI]
SPECIALTY ANALOG CIRCUIT, PDSO8, GREEN, PLASTIC, TSSOP-8;型号: | LFC789D25CPWG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | SPECIALTY ANALOG CIRCUIT, PDSO8, GREEN, PLASTIC, TSSOP-8 光电二极管 |
文件: | 总14页 (文件大小:542K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢆꢉꢊ ꢀ ꢀ ꢋꢌꢍ ꢊꢎ ꢁ ꢍꢏ ꢂꢐ ꢌꢏꢎ ꢐ ꢀꢀ ꢍꢎ
SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
D OR PW PACKAGE
(TOP VIEW)
D
D
Two Independent Controllers for
Regulation of:
− Fixed 2.5-V and an Adjustable Output
8
7
6
5
DRV_V
SEN_V
V
V
CC
1
2
3
4
ADJ
ADJ
−
2% (Max) Regulation Across
DRV_V
SEN_V
NC
25
25
Temperature and Load (1 mA to 3 A)
REF
GND
Adjustable Output Can Be Set Via an
External Reference Pin, Allowing for the
Creation of a Tracking Regulator
NC − No internal connection
D
D
Great Design Flexibility With Minimal
External Components
Applications: High-Current, Low-Dropout
Regulators for:
− DDR/RDRAM Memory Termination
− Motherboards
− Chipset I/O
− GTLP Termination
description/ordering information
The LFC789D25 is a dual linear FET controller that simplifies the design of dual power supplies. The device
consists of two independent controllers, each of which drives an external MOSFET to implement a low-dropout
regulator. One controller is programmed to regulate a fixed 2.5-V output, while the second controller can be
programmed to regulate any desired output voltage via a reference input pin, allowing for the creation of a
tracking regulator often needed for termination schemes. And, because heating effects of the external FETs
easily can be isolated from the controllers, the controllers can regulate the output voltages to a maximum
tolerance of 2% across temperature and load.
The LFC789D25 allows designers a great deal of flexibility in selecting external components and topology to
implement their specific power-supply needs. With appropriate heat sinking, the designer can build a regulator
with as much current capability as allowed by the external MOSFET and power supply. And, because the
dropout of the regulator simply is the product of the R
very low dropout can be achieved via proper selection of the power MOSFET.
of the external power MOSFET and the load current,
DS(on)
Packaged in 8-pin SOIC and space-saving TSSOP, the LFC789D25 is characterized for operation from 0°C to
70°C.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 75
Reel of 2500 LFC789D25CDR
Tube of 150 LFC789D25CPW
Reel of 2000 LFC789D25CPWR
LFC789D25CD
SOIC (D)
KADAC
0°C to 70°C
TSSOP (PW)
KADAC
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
functional block diagram
+
_
8
1
V
CC
DRV_V
ADJ
2
3
SEN_V
ADJ
V
REF
Bandgap
Reference
+
_
7
6
DRV_V
SEN_V
25
25
4 kΩ
3.6 kΩ
4
5
GND
NC
PIN DESCRIPTION
PIN FUNCTION
Output of adjustable controller. Drives gate(s) of FET(s) to output user-programmable voltage (V
PIN
1
PIN NAME
DRV_V
).
ADJ
ADJ
2
SEN_V
Sense input of adjustable controller. Senses changes in V
ADJ.
ADJ
3
V
REF
Input pin used to program V , allowing V
ADJ ADJ
to track changes in V
REF
4
GND
NC
Ground
5
No connection
6
SEN_V
Sense Input of 2.5-V controller. Senses changes in 2.5-V supply.
25
7
DRV_V
25
Output of 2.5-V controller. Drives gate(s) of FET(s) to output fixed 2.5 V.
Power supply for device
8
V
CC
2
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
V
CC
(12V)
V
PWR
(3.3V)
LFC789D25
C3
22 µF
1
2
8
7
DRV_V
ADJ
V
CC
V
DRV_V
REF
1.25 V
25
V
DDQ
2.5 V
C4
0.1 µF
C1
100 µF
C2
100 µF
SEN_V
ADJ
6
3
4
SEN_V
V
25
REF
C5
0.1 µF
GND
†
†
R1
R2
†
R1 = R2 = 100 Ω (0.1% matched resistors)
Figure 1. Typical Application Circuit for DDR1 − Memory Voltage (V
) and V
Buffer for DIMMs
REF
DDQ
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
CC
, SEN_V
, SEN_V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V
REF
ADJ
25
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can impact reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
9
MAX
16
UNIT
V
V
CC
Supply voltage
T
A
Operating free-air temperature
0
70
°C
3
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
electrical characteristics, V
= 12 V 5%, T = 25°C (unless otherwise noted)
A
CC
PARAMETER
T
MIN
TYP
MAX
−500
500
UNIT
TEST CONDITIONS
A
−20
ISEN_V
V
ADJ
sense-pin current
nA
ADJ
Full range
Full range
Sense
125
ISEN_V
V
25
sense-pin current
V
= 2.5 V
µA
25
25
V
− 1.5
CC
V
Driver output voltage
Driver output current
I
= 0
V
DRV
DRV
Full range
Full range
Full range
Full range
V
CC
− 3
5
Driver
10
V
V
= 4 V,
= 0.8 V
OUT
DRV
SEN
I
mA
nA
DRV
(nom)
−20
−250
−500
IVREF
Reference
Pin current, V
REF
2.5
2.5
V
output voltage
I
V
= 1 mA to 3 A,
= 3 .3 V 10%
25
regulation
OUT
2.45
2.55
PWR
Output regulation
(see Figure 1)
V
V
V
REF
I
V
V
= 1 mA to 2 A,
= 3.3 V 10%,
OUT
PWR
V
output voltage
ADJ
0.98 ×
1.02 ×
regulation
Full range
Full range
REF
2
= V /2
25
V
REF
V
REF
REF
Supply
I
Supply current
mA
CC
2.5
4
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
A linear voltage regulator can be broken down into four essential building blocks: a pass transistor, a voltage
reference, a feedback network, and a control circuit to drive the pass element, based on the comparison
between the output voltage (as sampled by the feedback network) and the voltage reference. With the exception
of the pass transistor, the -ADJ provides the other three building blocks needed. Thus, with minimal external
components and low overall solution cost, a designer can create two independent, tightly regulated output
voltages capable of delivering high currents in excess of 3 A (as limited by the external pass transistor). One
output is fixed at 2.5 V. The other output can be adjusted to any desired voltage via an externally applied signal
to the V
pin. Because the output of the regulator always tracks any changes to this V
pin, it is relatively
REF
REF
easy to implement a tracking regulator. See the typical application circuit (Figure 1).
internal reference
The fixed 2.5-V output controller uses an internal temperature-compensated bandgap reference centered at
1.2 V. Its tolerance is designed to be < 2% over the specified temperature range, which, when coupled with the
low offset of the driver circuit, allows the 2.5-V output to have a tolerance of 2% over the specified temperature
range and full load.
external reference pin (V
)
REF
For the adjustable output controller, the V
divider tied to an external voltage source and connecting the divider to the V
pin allows great flexibility for the designer. Taking a simple resistor
REF
pin allows the controller to
REF
regulate an output voltage that is some fraction of the external voltage source. And, because any changes in
the external voltage source are sensed by the voltage divider, the regulated output tracks those changes.
If a tracking regulator is not desired, a fixed voltage can be achieved by applying a constant voltage to the V
pin. This signal can be provided by a simple device such as the TL431 adjustable shunt regulator.
REF
The V
pin typically sources a current of 20 nA and, as such, has a minimal loading effect on the resistor
REF
divider or the shunt regulator. The accuracy of the adjustable output depends on the accuracy of the signal
applied to the V
accuracy.
pin. Using high-precision resistors or a TL431A (1% output tolerance) helps achieve good
REF
feedback network (SENSE pins)
The 2.5-V controller senses the output voltage via the SEN_V pin. This pin is tied to an internal resistor divider
25
that essentially halves the sensed output voltage and feeds it back to the controller for comparison to the internal
bandgap reference.
For the adjustable output controller, the SEN_V
controller for comparison to the externally applied V
pin provides direct feedback of the output voltage to the
ADJ
signal.
REF
controller/driver
Both drivers essentially are error amplifiers that can output a worst-case minimum of 9 V (10.5 V at 25°C) when
the LFC789D25 is powered by 12 V. This allows the controllers to regulate a large range of output
voltages, as limited by the threshold voltages of the external NMOS. Both drivers sample the output voltage via
a SEN pin. For the adjustable version, this SEN pin typically sources a current of 20 nA and, thus, has minimal
loading on the output voltage. For the 2.5-V version, this SEN pin sinks a current of approximately 125 µA
(including the currents through the internal resistor divider); this results in minimal loading on the output voltage.
Although not tested, both of these controllers are designed with very low offset (typically less than 4 mV),
resulting in very accurate control of the drive signals.
5
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
MOSFET SELECTION: BENEFITS OF NMOS PASS ELEMENTS REVISITED
A great benefit of having an external pass element is that the control circuitry can be powered by a separate
supply (V ), other than the one used as the input to the pass element (V
). This feature allows the use of
CC
PWR
an NMOS pass element, which requires a positive V
> V for operation. With a separate V
pin to the
easily can
GS
T
CC
GS
controller, the voltage at the gate of the NMOS readily can exceed the voltage at the drain; thus, V
exceed V + V , allowing the NMOS to operate in the triode region (V ≥ V − V ). In the triode region, V
DS
T
DS
GS
T
DS
can be very small, thus achieving very low dropout.
The external NMOS selected for the pass transistor has significant impact on the overall characteristics of the
regulator, as discussed in the following paragraphs.
D
Maximum output current
A benefit of an external pass element is that the designer can size the NMOS to easily sustain the maximum
I
expected. This allows great flexibility, along with cost and space savings, because each regulator has its
OUT
pass element tailored to its individual needs. In addition, using an NMOS pass element allows for smaller size
(and subsequently, lower cost) than a PMOS element for the same current-carrying ability.
D
D
Dropout
Choosing an NMOS with very low R
dropout will be ∼I
in the pass element for a given I
characteristics provides the regulator with very low dropout because
. This lower dropout also results in better efficiency and lower heat dissipation
DS(on)
× R
OUT
DS(on)
.
OUT
Maximum programmable output voltage and NMOS threshold voltage, V
T
The maximum output voltage that can be regulated by the programmable regulator depends on the device’s
power supply (V ) and threshold voltage (V ) of the NMOS. With the drive voltage tied to the gate and V
connected to the source of the NMOS, a minimum V
CC
T
OUT
= V must be maintained in order to maintain the
is calculated as follows:
GS
T
n-channel inversion layer. The maximum V
OUT
V
= V = V − V
S G T
OUT
With V
= 12 V and a corresponding worst-case gate drive voltage of 9 V, the highest achievable
CC
V
= 9 V − V .
OUT
T
D
Stability
A quality of the old npn regulators was their inherent stability under almost any type of load conditions and output
capacitors. An NMOS regulator has the same benefit. Thus, capacitor selection and
equivalent-series-resistance (ESR) values are not needed for stability, but still should be chosen properly for
best transient response (see below).
capacitor selection
: Although a minimum capacitance is not needed for stability with an NMOS pass device, higher capacitance
C
out
values improve transient response. In addition, low-ESR capacitors also help transient response. Tantalum or
aluminum electrolytics can be used for bulk capacitances, while ceramic bypass capacitors can be used to
decouple high-frequency transients due to their low ESL (equivalent series inductance).
C : Input capacitors placed at the drain of the NMOS pass transistor (V
) help improve the overall transient
in
PWR
response by suppressing surges in V
during fast load changes. Low-ESR tantalum or aluminum electrolytic
PWR
capacitors can be used; higher capacitance values improve transient response. A 0.1-µF ceramic capacitor can
be placed at the V
pin of the LFC789D25 to provide bypassing.
CC
6
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SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
layout
Another benefit of a separate controller and pass element is that the heat dissipated in the external NMOS can
be well isolated from the controller, which has very low power dissipation. Both of these factors allow the
bandgap reference and control circuitry to operate over a more stable temperature range, resulting in very good
accuracy over full-load conditions. The LFC789D25 should be placed as close as possible to the external pass
element because short PCB traces allow minimal EMI coupling to both the drive and sense lines.
For best accuracy, connect the SEN pins as close to the load as possible, not to the source of the NMOS. Also,
place the SEN trace in the same direction and plane as the power trace that connects the source of the NMOS
to the load. Also, it is good practice to keep the load current return path as far as possible from the SEN trace.
Place the 0.1-µF bypass capacitor as close as possible to the V
pin and connect it directly to the ground plane.
The GND pin of the LFC789D25 should be connected to the ground plane.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
LFC789D25CD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
D
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
KADAC
LFC789D25CDE4
LFC789D25CDR
ACTIVE
ACTIVE
D
D
75
Green (RoHS
& no Sb/Br)
0 to 70
KADAC
KADAC
2500
Green (RoHS
& no Sb/Br)
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LFC789D25CDR
SOIC
D
8
8
2500
2000
330.0
330.0
12.4
12.4
6.4
7.0
5.2
3.6
2.1
1.6
8.0
8.0
12.0
12.0
Q1
Q1
LFC789D25CPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LFC789D25CDR
SOIC
D
8
8
2500
2000
340.5
367.0
338.1
367.0
20.6
35.0
LFC789D25CPWR
TSSOP
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Pack Materials-Page 2
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