LDC2114 [TI]
适用于低功耗触摸按钮、具有基线跟踪功能的 4 通道电感数字转换器;
| 型号： | LDC2114 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于低功耗触摸按钮、具有基线跟踪功能的 4 通道电感数字转换器 转换器 |
| 文件： | 总53页 (文件大小：2238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
适合低功耗 HMI 按钮应用的 LDC2112/LDC2114 电感应触控解决 方案
1 特性
3 说明
1
•
低功耗：
借助电感式传感技术，设计人员可以测量导电目标的小
幅偏移，从而在金属、玻璃、塑料和木材等各种材料上
实现人机界面 (HMI) 的触控按钮设计。电感应触控系
统的传感器是一款可在小型 PCB 上实现的线圈，该
PCB 位于面板后方，以免受外界环境影响。电感式传
感解决方案不受湿度或油污和灰尘等非导电污染物的干
扰。它能够自动更正导电目标出现的任何变形。
–
–
一个按钮：6µA（速率为 0.625SPS 时）
两个按钮：72µA（速率为 20SPS 时）
•
可配置按钮扫描频率：
0.625SPS 至 80SPS
–
•
•
触摸按钮的应力水平测量
独立通道运算：
–
–
适用于 LDC2112 的双通道
适用于 LDC2114 的四通道
LDC2112/LDC2114 是一款多通道、低噪声电感数字
转换器，采用集成算法，可实现电感应触控 应用。该
器件采用创新型 LC 谐振器，可高度抑制噪音和干扰。
即使材料偏移不足 200nm，LDC2112/LDC2114 也能
够可靠地检测出来。
•
集成算法，可支持：
–
–
–
调节每个按钮的力阈值
环境变化补偿
同步按钮按压检测
LDC2112/LDC2114 还提供了超低功耗模式，专供电
池供电类应用中的开通/关断按钮 使用。
•
•
支持独立运算，无需 MCU
强大的 EMI 性能：
LDC2112/LDC2114 采用 16 引脚 DSBGA 或 TSSOP
封装。DSBGA 封装（间距为 0.4mm）的标称封装尺
寸非常小，仅为 1.6 × 1.6mm，其最大高度为
–
支持 CISPR 22 和 CISPR 24 合规性
•
•
•
工作电压范围：1.8V ± 5%
温度范围：-40°C 至 +85°C
接口：
0.4mm。TSSOP 封装（间距为 0.65mm）的标称封装
尺寸为 5.0 × 4.4mm，其最大高度为 1.2mm。
–
–
I2C
每个通道的专用逻辑输出
器件信息(1)
器件型号
封装
封装尺寸（标称值）
1.6mm x 1.6mm
5.0mm × 4.4mm
2 应用
LDC2112/LDC2114 DSBGA (16)
LDC2112/LDC2114 TSSOP (16)
以下产品的触控按钮及其所用不同材料（包括金
属、塑料和玻璃材料）的应力水平测量：
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
消费类电子产品：
–
–
–
–
–
–
智能手机
简化原理图
智能手表及其他可穿戴设备
智能扬声器
VDD
LDC2114
平板电脑/PC
虚拟现实耳机
条形音箱
OUT0
OUT1
Digital
Algorithm
IN0
OUT2
OUT3
IN1
IN2
•
工业 应用：
Resonant
Circuit
Driver
Inductive
Sensing Core
INTB
–
–
–
–
电视
Logic
I2C
LPWRB
手持设备
家用电器
HMI 面板和键盘
IN3
SCL
SDA
COM
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSD15
LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
目录
7.5 Register Maps......................................................... 15
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 38
Power Supply Recommendations...................... 40
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Digital Interface ......................................................... 7
6.7 I2C Interface.............................................................. 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 15
8
9
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 40
10.3 DSBGA Light Sensitivity ...................................... 41
11 器件和文档支持 ..................................................... 42
11.1 文档支持 ............................................................... 42
11.2 相关链接................................................................ 42
11.3 接收文档更新通知 ................................................. 42
11.4 社区资源................................................................ 42
11.5 商标....................................................................... 42
11.6 静电放电警告......................................................... 42
11.7 出口管制提示 ........................................................ 42
11.8 Glossary................................................................ 42
12 机械、封装和可订购信息....................................... 42
7
4 修订历史记录
Changes from Revision A (January 2017) to Revision B
Page
•
•
•
Changed unit of Data set-up time from µs to ns (typo) ......................................................................................................... 7
已更改 Multi-Channel and Single-Channel Operation .......................................................................................................... 11
已添加 LDC2112 to Register EN – Address 0x0C Table ..................................................................................................... 19
Changes from Original (December 2016) to Revision A
Page
•
已更改 将“高级信息”更改成了“生产数据发布” ......................................................................................................................... 1
2
Copyright © 2016–2017, Texas Instruments Incorporated
LDC2112, LDC2114
www.ti.com.cn
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
5 Pin Configuration and Functions
LDC2112
16-Pin DSBGA
Top View (Bumps Down)
LDC2112
16-Pin TSSOP
Top View
1
2
3
4
COM
GND
LPWRB
VDD
INTB
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
OUT0
SDA
OUT1
NC
IN0
A
B
NC
NC
IN1
GND
NC
ADDR
INTB
LDC2112
ADDR
GND
IN0
LPW
RB
C
D
VDD
GND
SDA
SCL
OUT1
OUT0
NC
IN1
COM
Pin Functions - LDC2112
PIN
DSBGA NO. TSSOP NO.
I/O(1)
DESCRIPTION
NAME
VDD
C1
D1
A4
4
2
P
Power supply
Ground(2)
GND
G
10
Interrupt output
Polarity can be configured in Register 0x11.
INTB
B2
C2
5
3
O
I
Normal / Low Power Mode select
Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode.
LPWRB
Common return current path for all LC resonator sensors
A capacitor should be connected from this pin to GND. Refer to Setting COM
Pin Capacitor.
COM
D2
1
A
IN0
IN1
A3
A2
9
8
A
A
Channel 0 LC sensor input
Channel 1 LC sensor input
Channel 0 logic output
Polarity can be configured in Register 0x1C.
OUT0
OUT1
D4
C4
15
13
O
O
Channel 1 logic output
Polarity can be configured in Register 0x1C.
I2C address
ADDR
B3
11
I
When ADDR = Ground, I2C address = 0x2A. When ADDR = VDD, I2C address =
0x2B.
SCL
SDA
D3
C3
A1
B1
B4
16
14
7
I
I2C clock
I2C data
I/O
No connect
Leave them floating.
NC
6
—
12
(1) I = Input, O = Output, P=Power, G=Ground, A=Analog
(2) Both pins should be connected to the system ground on the PCB.
Copyright © 2016–2017, Texas Instruments Incorporated
3
LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
LDC2114
16-Pin DSBGA
Top View (Bumps Down)
LDC2114
16-Pin TSSOP
Top View
1
2
3
4
COM
GND
LPWRB
VDD
INTB
IN3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
IN0
A
B
IN2
IN3
IN1
GND
OUT0
SDA
OUT3
OUT2
INTB
OUT1
OUT2
OUT3
GND
IN0
LDC2114
LPW
RB
C
D
VDD
GND
SDA
SCL
OUT1
OUT0
IN2
IN1
COM
Pin Functions - LDC2114
PIN
DSBGA NO. TSSOP NO.
I/O(1)
DESCRIPTION
NAME
VDD
C1
D1
A4
4
2
P
Power supply
Ground(2)
GND
G
10
Interrupt output
Polarity can be configured in Register 0x11.
INTB
B2
C2
5
3
O
I
Normal / Low Power Mode select
Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode.
Common return current path for all LC resonator sensors
LPWRB
COM
D2
1
A
A capacitor should be connected from this pin to GND. Refer to Setting COM Pin
Capacitor.
IN0
IN1
IN2
IN3
A3
A2
A1
B1
9
8
7
6
A
A
A
A
Channel 0 LC sensor input
Channel 1 LC sensor input
Channel 2 LC sensor input
Channel 3 LC sensor input
Channel 0 logic output
Polarity can be configured in Register 0x1C.
OUT0
OUT1
OUT2
D4
C4
B4
15
13
12
O
O
O
Channel 1 logic output
Polarity can be configured in Register 0x1C.
Channel 2 logic output
Polarity can be configured in Register 0x1C.
Channel 3 logic output
Polarity can be configured in Register 0x1C.
I2C clock
OUT3
SCL
B3
D3
C3
11
16
14
O
I
I2C data
SDA
I/O
I2C address = 0x2A.
(1) I = Input, O = Output, P=Power, G=Ground, A=Analog
(2) Both pins should be connected to the system ground on the PCB.
4
Copyright © 2016–2017, Texas Instruments Incorporated
LDC2112, LDC2114
www.ti.com.cn
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range unless otherwise noted.(1)
MIN
MAX
2.2
UNIT
V
VDD
VI
Supply voltage
Voltage on SCL, SDA
Voltage on any other pin
Junction temperature
Storage temperature
–0.3
–0.3
–40
–65
3.6
2.2(2)
V
V
TJ
85
℃
°C
TSTG
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum voltage across any two pins (not including SCL or SDA) is VDD + 0.3 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating temperature range unless otherwise noted.
MIN
1.71
–40
NOM
MAX
1.89
85
UNIT
VDD
TJ
Supply voltage
V
Junction temperature
°C
6.4 Thermal Information
LDC2112/LDC2114
THERMAL METRIC(1)
DSBGA
16 PINS
81.8
TSSOP
UNIT
16 PINS
105.1
40.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
0.4
18.2
50.2
ΨJT
0.3
3.6
Junction-to-board characterization
parameter
ΨJB
18
49.6
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
版权 © 2016–2017, Texas Instruments Incorporated
5
LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
6.5 Electrical Characteristics
Over operating temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
VDD
Supply voltage
1.71
1.8
1.89
V
4 channels, 40 SPS per channel,
1 ms sampling window per channel,
LPWRB = VDD
Normal power mode supply current
(4 channels)(1)(2)(3)
IDDNP
IDDNP
IDDLP
0.49
mA
2 channels, 40 SPS per channel,
1 ms sampling window per channel,
LPWRB = VDD
Normal power mode supply current
(2 channels)(1)(2)
0.26
mA
1 channel, 1.25 SPS per channel,
1 ms sampling window per channel,
LPWRB = Ground
Low power mode supply
current(1)(2)
9
5
µA
µA
IDDSB
Standby supply current
No button active (EN = 0x00)
7
SENSOR
Registers SENSORn_CONFIG: RPn = 0
ISENSOR, MAX Sensor maximum current drive
2.5
350
10
mA
(4)
Sensor minimum parallel resonant
impedance
RP, MIN
Ω
Sensor maximum parallel resonant
impedance
RP, MAX
kΩ
fSENSOR
Sensor resonant frequency
1
30
MHz
QSENSOR, MIN Sensor minimum quality factor
QSENSOR, MAX Sensor maximum quality factor
5
30
Sensor oscillation peak-to-peak
Measured on the INn(4) pins with
reference to COM.
VSENSOR, PP
voltage
0.9
17
V
CIN
Sensor input pin capacitance
pF
CONVERTER
Minimum normal power mode scan
rate(5)
SRNP, MIN
SRNP, MAX
SRLP, MIN
LPWRB = VDD
7
56
10
80
13
104
SPS
SPS
SPS
Maximum normal power mode scan
rate(5)
LPWRB = VDD
Minimum low power mode scan
rate(5)
LPWRB = Ground
LPWRB = Ground
0.438
3.5
0.625
0.813
6.5
Maximum low power mode scan
rate(5)
SRLP, MAX
Resolution
5
SPS
Bits
Data code width
12
(1) Sensor configuration: LSENSOR = 0.85 µH, CSENSOR = 58 pF, QSENSOR = 11, RP = 0.7 kΩ.
(2) I2C communication and pull-up resistors current is not included.
(3) Four-channel supply current is applicable to LDC2114 only.
(4) The italic n is the channel index, i.e., n = 0 or 1 for LDC2112; n = 0, 1, 2, or 3 for LDC2114.
(5) For typical distribution of the scan rates, refer to 图 9.
6
版权 © 2016–2017, Texas Instruments Incorporated
LDC2112, LDC2114
www.ti.com.cn
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
6.6 Digital Interface
Over operating temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C. Pins: LPWRB, INTB, OUT0, OUT1,
OUT2, OUT3, and ADDR.
PARAMETER
VOLTAGE LEVELS
TEST CONDITIONS
MIN
0.8 × VDD
0.8 × VDD
–500
TYP
MAX
UNIT
VIH
VIL
VOH
VOL
IL
Input high voltage
V
V
Input low voltage
0.2 × VDD
Output high voltage
Output low voltage
Digital input leakage current
ISOURCE = 400 µA
ISINK = 400 µA
V
0.2 × VDD
500
V
nA
6.7 I2C Interface
MIN
TYP
MAX
UNIT
VOLTAGE LEVELS
VIH
Input high voltage
0.7 × VDD
V
V
V
V
VIL
Input low voltage
Output low voltage
Hysteresis(1)
0.3 × VDD
0.2 × VDD
VOL
HYS
3 mA sink current
0.05 × VDD
I2C TIMING CHARACTERISTICS
fSCL
Clock frequency
Clock low time
Clock high time
400
kHz
µs
tLOW
tHIGH
1.3
0.6
µs
After this period, the first
clock pulse is generated.
tHD;STA
tSU;STA
Hold time repeated START condition
0.6
0.6
µs
µs
Set-up time for a repeated START
condition
tHD;DAT
tSU;DAT
tSU;STO
Data hold time
0
100
0.6
µs
ns
µs
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and
START condition
tBUF
1.3
µs
tVD;DAT
tVD;ACK
Data valid time
0.9
0.9
µs
µs
Data valid acknowledge time
Pulse width of spikes that must be
suppressed by the input filter(1)
tSP
50
ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
SDA
t
BUF
t
t
LOW
t
f
HD;STA
t
r
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
图 1. I2C Timing Diagram
版权 © 2016–2017, Texas Instruments Incorporated
7
LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
6.8 Typical Characteristics
Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C.
One channel enabled with a button sampling window of 1 ms unless specified otherwise.
1600
1400
1200
1000
800
600
400
200
0
800
700
600
500
400
300
200
100
0
10 SPS
20 SPS
40 SPS
80 SPS
10 SPS
20 SPS
40 SPS
80 SPS
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Sensor RP (kW)
Sensor RP (kW)
D001
D011
图 2. Supply Current vs Sensor RP for Normal Power Mode.
图 3. Supply Current vs Sensor RP for Normal Power Mode.
Sensor Frequency = 3.6 MHz. Four Channels Enabled.
Sensor Frequency = 3.6 MHz. Two Channels Enabled.
160
30
VDD = 1.71 V
VDD = 1.8 V
0.625 SPS
1.25 SPS
150
25
VDD = 1.89 V
140
2.5 SPS
5 SPS
20
130
120
110
100
90
15
10
5
0
80
0
1
2
3
4
5
6
7
8
9
10
-40
-20
0
20
40
60
80
100
Sensor RP (kW)
Temperature (èC)
D002
D003
图 4. Supply Current vs Sensor RP for Low Power Mode.
图 5. Supply Current vs Temperature. Sensor RP = 650 Ω,
Sensor Frequency = 3.6 MHz.
Scan Rate = 40 SPS.
160
9
VDD = 1.71 V
VDD = 1.8 V
VDD = 1.89 V
150
140
130
120
110
100
90
8
7
6
5
4
3
-40èC
-25èC
0èC
25èC
85èC
80
1.7
1.75
1.8
VDD (V)
1.85
1.9
-40
-20
0
20
40
60
80
100
Temperature (èC)
D004
D005
图 6. Supply Current vs VDD. Sensor RP = 650 Ω, Scan Rate =
图 7. Standby Current vs Temperature
40 SPS.
8
版权 © 2016–2017, Texas Instruments Incorporated
LDC2112, LDC2114
www.ti.com.cn
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
Typical Characteristics (接下页)
One channel enabled with a button sampling window of 1 ms unless specified otherwise.
450
400
350
300
250
200
150
100
50
9
8
7
6
5
4
3
-40èC
-25èC
0èC
25èC
85°C
0
1.7
1.75
1.8
VDD (V)
1.85
1.9
-12-11-10 -9 -8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
Percentage Offset (%)
D006
D007
图 8. Standby Current vs VDD
图 9. Scan Rate Distribution at 30 °C
版权 © 2016–2017, Texas Instruments Incorporated
9
LDC2112, LDC2114
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LDC2112/LDC2114 is a multi-channel, low-noise, high-resolution inductance to digital converter (LDC)
optimized for inductive touch applications. Button presses form micro-deflections in the conductive targets which
cause frequency shifts in the resonant sensors. The LDC2112/LDC2114 can measure such frequency shifts and
determine when button presses have occurred. With adjustable sensitivity per input channel, the
LDC2112/LDC2114 can reliably operate with a wide range of physical button structures and materials. The high
resolution measurement enables the implementation of force level buttons. The LDC2112/LDC2114 incorporates
customizable post-processing algorithms for enhanced robustness.
The LDC2112/LDC2114 can operate in an ultra-low power mode for optimal battery life, or can be toggled into a
higher scan rate for more responsive button press detection for game play or other low latency applications. The
LDC2112/LDC2114 is operational from –40 °C to +85 °C with a 1.8 V ± 5% power supply voltage.
The LDC2112/LDC2114 is configured through 400 kHz I2C. Button presses can be reported through the I2C
interface or with configurable polarity dedicated push-pull outputs. Besides the LC resonant sensors, the only
external components necessary for operation are supply bypassing capacitors and a COM pin capacitor to
ground.
7.2 Functional Block Diagram
VDD
LDC2112
OUT0
Digital
Algorithm
OUT1
IN0
INTB
Resonant
Circuit
Driver
Inductive
Sensing Core
Logic
I2C
LPWRB
IN1
ADDR
SCL
COM
SDA
GND
Copyright © 2016, Texas Instruments Incorporated
图 10. Block Diagram of LDC2112
10
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Functional Block Diagram (接下页)
VDD
LDC2114
OUT0
OUT1
Digital
IN0
IN1
IN2
Algorithm
OUT2
OUT3
Resonant
Circuit
Driver
Inductive
Sensing Core
INTB
Logic
I2C
LPWRB
IN3
SCL
SDA
COM
GND
Copyright © 2016, Texas Instruments Incorporated
图 11. Block Diagram of LDC2114
7.3 Feature Description
7.3.1 Multi-Channel and Single-Channel Operation
The LDC2112 provides two independent sensing channels; the LDC2114 provides four independent sensing
channels. In the following sections, some parameters, such as DATAn and SENSORn_CONFIG, contain a
channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114.
The LDC2112's two available channels are always enabled in Normal Power Mode. The LDC2112 sequentially
samples both channels at the configured scan rate. Either channel can be independently enabled in Low Power
Mode by setting the LPENn (n = 0 or 1) bit fields in Register EN (Address 0x0C).
Any of the LDC2114’s four available channels can be independently enabled by setting the ENn and LPENn (n =
0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect if the
corresponding ENn bit is also set. If only one channel is set active, the LDC2114 periodically samples the single
active channel at the configured scan rate. When several channels are set active, the LDC2114 operates in
multi-channel mode, and it sequentially samples the active channels at the configured scan rate. Each channel of
the LDC2114 can be independently enabled in Low Power Mode and Normal Power Mode.
7.3.2 Button Output Interfaces
Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2,
or 3), which are push-pull outputs and can be used as interrupts to a micro-controller. The polarities of these pins
are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also
reported by the push-pull interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address
0x11). Any assertion of INTB is cleared upon reading Register STATUS (Address 0x00). Each push-pull output
must be assigned to a dedicated general-purpose input pin on the micro-controller to avoid potential current
fights.
The second method is by use of the LDC2112/LDC2114’s I2C interface. The Register OUT (Address 0x01)
contains the fields OUT0, OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For
more advanced button press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02
through 0x09), which are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a
micro-controller. A valid button push is represented by a positive value. The polarity is configurable in Register
OPOL_DPOL (Address 0x1C). The DATAn values can be used to implement multi-level buttons, where the data
value is correlated to the amount of force applied to the button.
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Feature Description (接下页)
7.3.3 Programmable Button Sensitivity
The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual
buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a 64-level gain factor
for a normalized gain between 1 and 232. Each gain step increases the gain by an average of 9%.
The gain required for an application is primarily determined by the mechanical rigidity of each individual button.
The individual gain steps are listed in the Gain Table.
7.3.4 Baseline Tracking
The LDC2112/LDC2114 incorporates a baseline tracking algorithm to automatically compensate for any slow
change in the sensor output caused by environmental variations, such as temperature drift. The baseline tracking
is configured independently for Normal Power Mode and Low Power Mode. For more information, refer to
Tracking Baseline.
7.3.5 Integrated Button Algorithms
The LDC2112/LDC2114 features several algorithms that can mitigate false button detections due to mechanical
non-idealities. The algorithms look for correlated button responses, for example, similar or opposite responses
between two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more
information, refer to Mitigating False Button Detections.
7.3.6 I2C Interface
The LDC2112/LDC2114 features an I2C Interface that can be used to program the internal registers and read
channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02
through 0x05) registers, the user should always read Register STATUS (Address 0x00) first to lock the data. The
LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.
For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The
sequence of register write is illustrated as follows:
•
•
•
•
Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session
Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1
I2C write to configure registers
Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session
After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above
process is shown in 图 12.
25 ms scan cycle
25 ms scan cycle
Sampling
Sampling
CONFIG_MODE
(Register RESET)
< 1 ms
RDY_TO_WRITE
(Register STATUS)
Program registers only after
confirming RDY_TO_WRITE = 1
图 12. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an
I2C Write Handshake
7.3.6.1 Selectable I2C Address (LDC2112 Only)
The LDC2112 provides an I2C address select pin, ADDR. Connecting this pin to ground will set the LDC2112 I2C
address to 0x2A. Connecting ADDR to VDD will set the LDC2112 I2C address to 0x2B.
The LDC2114 has a fixed I2C address of 0x2A.
12
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Feature Description (接下页)
7.3.6.2 I2C Interface Specifications
The maximum speed of the I2C interface is 400 kHz. This sequence uses the standard I2C 7-bit slave address
followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will auto-
increment as long as the master acknowledges.
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Ack
by
Ack
by
Slave
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
Stop by
Master
Ack
by
Slave
Frame 3
Data Byte
图 13. I2C Sequence of Writing a Single Register
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Ack
by
Ack
by
Slave
Slave
Frame 1
Frame 2
Serial Bus Address Byte
from Master
Slave Register Address (ADDR) from
Master
1
9
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
Ack
by
Slave
Slave
Frame 3
Frame 4
Data Byte to
Register ADDR
Data Byte to
Register ADDR+1
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
Stop by
Master
Slave
Frame N+3
Data Byte to Register
ADDR+N
图 14. I2C Sequence of Writing Consecutive Registers
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Feature Description (接下页)
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Ack
by
Ack
by
Slave
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address from Master
1
9
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
A6
A5
A4
A3
A2
A1
A0
R/W
No Ack
by
Master
Stop
by
Master
Ack
by
Slave
Repeat
Start by
Master
Frame 3
Serial Bus Address Byte
from Master
Frame 4
Data Byte from Slave
图 15. I2C Sequence of Reading a Single Register
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Ack
by
Ack
by
Slave
Slave
Frame 1
Frame 2
Serial Bus Address Byte
from Master
Slave Register Address (ADDR) from
Master
1
9
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
A6
A5
A4
A3
A2
A1
A0
R/W
Repeat
Start by
Master
Ack
by
Master
Ack
by
Slave
Frame 3
Serial Bus Address Byte
from Master
Frame 4
Data Byte from Slave Register ADDR
1
9
1
9
SCL
(continued)
SDA
(continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
No Ack
by
Master
Stop
by
Master
Ack
by
Master
Frame N+4
Data Byte from Slave Register
ADDR+N
Frame 5
Data Byte from Slave Register ADDR+1
图 16. I2C Sequence of Reading Consecutive Registers
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Feature Description (接下页)
7.3.6.3 I2C Bus Control
The LDC2112/LDC2114 cannot drive the I2C clock (SCL), i.e. it does not support clock stretching. In the unlikely
event where the SCL is stuck LOW, power cycle any device that is holding the SCL to activate its internal Power-
On Reset (POR) circuit. If the LDC is connected to the same power supply as that device, there will be about 66
ms set-up time before the LDC becomes active again. For more information, refer to Defining Power-On Timing.
If the data line (SDA) is stuck LOW, the I2C master should send nine clock pulses. The device that is holding the
bus LOW should release it sometime within those nine clocks. If not, then power cycle to clear the bus.
The LDC2112/LDC2114 has built-in monitors to check that the device is currently working. In the unlikely event
of a device fault, the device state will be reset internally, and all the registers will be reset with default settings.
For system robustness, it is recommended to check the value of a modified register periodically to monitor the
device status and reload the register settings if needed.
7.4 Device Functional Modes
The LDC2112/LDC2114 supports two power modes of operation, a Normal Power Mode for active sampling at
10, 20, 40, or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS.
Refer to Configuring Button Scan Rate for details.
7.4.1 Normal Power Mode
When the LPWRB input pin is set to VDD, all enabled channels operate in Normal Power Mode. Each channel
can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal
Power Mode Scan Rate, refer to Electrical Characteristics.
7.4.2 Low Power Mode
When the LPWRB input pin is set to Ground, only the low-power-enabled channels are active. Each channel can
be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel to
operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The
Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive
power-saving state for the majority of the time. Lower scan rates correspond to lower current consumption. In
addition, the individual button sampling window should be set to the lowest effective setting (this is system
dependent, but typically 0.8 to 1 ms). For the electrical specification of the configurable Low Power Mode Scan
Rate, refer to Electrical Characteristics.
If a channel is operational in both Low Power Mode and Normal Power Mode, it is recommended to toggle the
LPWRB pin only after the button associated with that channel is released.
7.4.3 Configuration Mode
Before configuring any register settings, the device must be put into the configuration mode first. Setting
CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device in
configuration mode. Any device configuration changes can then be made. The current consumption in this mode
is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation. Refer to
I2C Interface for more information.
7.5 Register Maps
Registers indicated with Reserved must be written only with indicated values. Improper device operation may
occur otherwise.
表 1. Register List
ADDRESS
0x00
NAME
STATUS
DEFAULT VALUE
DESCRIPTION
0x00
0x00
0x00
0x00
0x00
Device status
0x01
OUT
Channel output logic states
0x02
DATA0_LSB
DATA0_MSB
DATA1_LSB
The lower 8 bits of the Button 0 data (Two’s complement)
The upper 4 bits of the Button 0 data (Two’s complement)
The lower 8 bits of the Button 1 data (Two’s complement)
0x03
0x04
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Register Maps (接下页)
表 1. Register List (接下页)
ADDRESS
0x05
NAME
DEFAULT VALUE
DESCRIPTION
DATA1_MSB
DATA2_LSB
DATA2_MSB
DATA3_LSB
DATA3_MSB
RESET
0x00
0x00
0x00
0x00
0x00
0x00
0x00
The upper 4 bits of the Button 1 data (Two’s complement)
The lower 8 bits of the Button 2 data (Two’s complement)
The upper 4 bits of the Button 2 data (Two’s complement)
The lower 8 bits of the Button 3 data (Two’s complement)
The upper 4 bits of the Button 3 data (Two’s complement)
Reset device and register configurations
0x06
0x07
0x08
0x09
0x0A
0x0B
RESERVED
Reserved. Set to 0x00
0x10 (LDC2112)
0x1F (LDC2114)
0x0C
EN
Enable channels and low power modes
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0xFC
0xFD
NP_SCAN_RATE
GAIN0
0x01
0x28
0x02
0x28
0x01
0x28
0x05
0x28
0x03
0x00
0x03
0x08
0x00
0x00
0x00
0x0F
0x00
0x55
0x00
0x04
0x00
0x04
0x00
0x04
0x02
0x04
0x00
0x50
0x00
0x00
0x01
0x49
0x54
Normal Power Mode scan rate
Gain for Channel 0 sensitivity adjustment
Low Power Mode scan rate
Gain for Channel 1 sensitivity adjustment
Interrupt polarity
LP_SCAN_RATE
GAIN1
INTPOL
GAIN2
Gain for Channel 2 sensitivity adjustment
Low power base increment
Gain for Channel 3 sensitivity adjustment
Normal power base increment
Baseline tracking pause and Max-win
LC oscillation frequency divider
Hysteresis for threshold
LP_BASE_INC
GAIN3
NP_BASE_INC
BTPAUSE_MAXWIN
LC_DIVIDER
HYST
TWIST
Anti-twist
COMMON_DEFORM
RESERVED
Anti-common and anti-deformation
Reserved. Set to 0x00
OPOL_DPOL
RESERVED
Output polarity
Reserved. Set to 0x00
CNTSC
Counter scale
RESERVED
Reserved. Set to 0x00
SENSOR0_CONFIG
RESERVED
Sensor 0 cycle count, frequency, RP range
Reserved. Set to 0x00
SENSOR1_CONFIG
RESERVED
Sensor 1 cycle count, frequency, RP range
Reserved. Set to 0x00
SENSOR2_CONFIG
FTF0
Sensor 2 cycle count, frequency, RP range
Sensor 0 fast tracking factor
Sensor 3 cycle count, frequency, RP range
Reserved. Set to 0x00
SENSOR3_CONFIG
RESERVED
FTF1_2
Sensors 1 and 2 fast tracking factors
Reserved. Set to 0x00
RESERVED
RESERVED
Reserved. Set to 0x00
FTF3
Sensor 3 fast tracking factor
Manufacturer ID lower byte
Manufacturer ID upper byte
MANUFACTURER_ID_LSB
MANUFACTURER_ID_MSB
0x01 (LDC2112)
0x00 (LDC2114)
0xFE
0xFF
DEVICE_ID_LSB
DEVICE_ID_MSB
Device ID lower byte
Device ID upper byte
0x20
16
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7.5.1 Individual Register Listings
Fields indicated with ‘Reserved’ must be written only with indicated values. Improper device operation may occur
otherwise. The R/W column indicates the Read-Write status of the corresponding field. An ‘R/W’ entry indicates
read and write capability, an ‘R’ indicates read-only, and a ‘W’ indicates write-only.
Before reading the OUT (Address 0x01) or channel DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through
0x09), the user should always read the STATUS register (Address 0x00) first to lock the data. The
LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.
表 2. Register STATUS – Address 0x00
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
OUT_STATUS
R
0
Output Status
Logic OR of output bits from Register OUT (Address 0x01). This field
is cleared by reading this register.
6
5
CHIP_READY
R
R
1
0
Chip Ready Status
b0: Chip not ready after internal reset.
b1: Chip ready after internal reset.
RDY_TO_WRITE
Ready to Write
Indicates if registers are ready to be written. See I2C Interface for
more information.
b0: Registers not ready.
b1: Registers ready.
4
3
2
1
0
MAXOUT
R
R
R
R
R
0
0
0
0
0
Maximum Output Code
Indicates if any channel output data reaches the maximum value
(+0x7FF or –0x800). Cleared by a read of the status register.
b0: No maximum output code.
b1: Maximum output code.
FSM_WD
Finite-State Machine Watchdog Error
Reports an error has occurred and conversions have been halted.
Cleared by a read of the status register.
b0: No error in finite-state machine.
b1: Error in finite-state machine.
LC_WD
LC Sensor Watchdog Error
Reports an error when any LC oscillator fails to start. Cleared by a
read of the status register.
b0: No error in LC oscillator initialization.
b1: Error in LC oscillator initialization.
TIMEOUT
Button Timeout
Reports when any button is asserted for more than 50 seconds.
Cleared by a read of the status register.
b0: no timeout error.
b1: timeout error.
REGISTER_FLAG
Register Integrity Flag
Reports if any register's value has an unexpected change. Cleared by
a read of the status register.
b0: No unexpected register change.
b1: Unexpected register change.
表 3. Register OUT – Address 0x01
BIT
7:4
3
FIELD
TYPE
RESET
0000
0
DESCRIPTION
RESERVED
OUT3
R
R
Reserved. Set to b0000.
Output Logic State for Channel 3 (LDC2114 Only)
b0: No button press detected on Channel 3.
b1: Button press detected on Channel 3.
2
1
0
OUT2
OUT1
OUT0
R
R
R
0
0
0
Output Logic State for Channel 2 (LDC2114 Only)
b0: No button press detected on Channel 2.
b1: Button press detected on Channel 2.
Output Logic State for Channel 1
b0: No button press detected on Channel 1.
b1: Button press detected on Channel 1.
Output Logic State for Channel 0
b0: No button press detected on Channel 0.
b1: Button press detected on Channel 0.
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表 4. Register DATA0_LSB – Address 0x02
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
DATA0[7:0]
R
0000 0000 The lower 8 bits of Channel 0 data (Two’s complement).
表 5. Register DATA0_MSB – Address 0x03
BIT
7:4
3:0
FIELD
TYPE
RESET
0000
DESCRIPTION
RESERVED
DATA0[11:8]
R
R
Reserved.
0000
The upper 4 bits of Channel 0 data (Two’s complement).
表 6. Register DATA1_LSB – Address 0x04
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
DATA1[7:0]
R
0000 0000 The lower 8 bits of Channel 1 data (Two’s complement).
表 7. Register DATA1_MSB – Address 0x05
BIT
7:4
3:0
FIELD
TYPE
RESET
0000
DESCRIPTION
RESERVED
DATA1[11:8]
R
R
Reserved.
0000
The upper 4 bits of Channel 1 data (Two’s complement).
表 8. Register DATA2_LSB – Address 0x06
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
DATA2[7:0]
R
0000 0000 The lower 8 bits of Channel 2 data (Two’s complement).
(LDC2114 Only)
表 9. Register DATA2_MSB – Address 0x07
BIT
7:4
3:0
FIELD
TYPE
RESET
0000
DESCRIPTION
RESERVED
DATA2[11:8]
R
R
Reserved.
0000
The upper 4 bits of Channel 2 data (Two’s complement).
(LDC2114 Only)
表 10. Register DATA3_LSB – Address 0x08
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
DATA3[7:0]
R
0000 0000 The lower 8 bits of Channel 3 data (Two’s complement).
(LDC2114 Only)
表 11. Register DATA3_MSB – Address 0x09
BIT
7:4
3:0
FIELD
TYPE
RESET
0000
DESCRIPTION
RESERVED
DATA3[11:8]
R
R
Reserved.
0000
The upper 4 bits of Channel 3 data (Two’s complement).
(LDC2114 Only)
表 12. Register RESET – Address 0x0A
BIT
7:5
4
FIELD
TYPE
R/W
RESET
000
DESCRIPTION
RESERVED
FULL_RESET
Reserved. Set to b000.
R/W
0
Device Reset
b0: Normal operation.
b1: Resets the device and register configurations. All registers will be
returned to default values. Normal operation will not resume until
STATUS:CHIP_READY = 1.
3:1
0
RESERVED
R/W
R/W
000
0
Reserved. Set to b000.
CONFIG_MODE
Configuration Mode
b0: Normal operation.
b1: Holds the device in configuration mode (no data conversion), but
maintains current register configurations. Any device configuration
changes should be made with this bit set to 1. After all configuration
changes have been written, set this bit to 0 for normal operation.
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表 13. Register EN – Address 0x0C
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
LPEN3
R/W
0
Channel 3 Low-Power-Enable (LDC2114 Only)
b0: Disable Channel 3 in Low Power Mode.
b1: Enable Channel 3 in Low Power Mode. EN3 must also be set
to 1.
6
5
4
3
LPEN2
R/W
R/W
R/W
R/W
0
0
1
1
Channel 2 Low-Power-Enable (LDC2114 Only)
b0: Disable Channel 2 in Low Power Mode.
b1: Enable Channel 2 in Low Power Mode. EN2 must also be set
to 1.
LPEN1
Channel 1 Low-Power-Enable
b0: Disable Channel 1 in Low Power Mode.
b1: Enable Channel 1 in Low Power Mode. EN1 must also be set
to 1.
LPEN0
Channel 0 Low-Power-Enable
b0: Disable Channel 0 in Low Power Mode.
b1: Enable Channel 0 in Low Power Mode. EN0 must also be set
to 1.
EN3 (LDC2114)
Channel 3 Enable (LDC2114 Only)
b0: Disable Channel 3.
b1: Enable Channel 3.
RESERVED (LDC2112)
EN2 (LDC2114)
R
0
1
Reserved. Set to b0. (LDC2112 Only)
2
1
R/W
Channel 2 Enable (LDC2114 Only)
b0: Disable Channel 2.
b1: Enable Channel 2.
RESERVED (LDC2112)
EN1 (LDC2114)
R
0
1
Reserved. Set to b0. (LDC2112 Only)
R/W
Channel 1 Enable (LDC2114 Only)
b0: Disable Channel 1.
b1: Enable Channel 1.
RESERVED (LDC2112)
EN0 (LDC2114)
R
0
1
Reserved. Set to b0. (LDC2112 Only)
For LDC2112, Channel 1 is always enabled.
0
R/W
Channel 0 Enable (LDC2114 Only)
b0: Disable Channel 0.
b1: Enable Channel 0.
RESERVED (LDC2112)
R
0
Reserved. Set to b0. (LDC2112 Only)
For LDC2112, Channel 0 is always enabled.
表 14. Register NP_SCAN_RATE – Address 0x0D
BIT
7:2
1:0
FIELD
TYPE
R/W
RESET
b00 0000
01
DESCRIPTION
RESERVED
NPSR
Reserved. Set to b00 0000.
R/W
Normal Power Mode Scan Rate
Refer to Configuring Button Scan Rate for more information.
b00: 80 SPS
b01: 40 SPS (Default)
b10: 20 SPS
b11: 10 SPS
表 15. Register GAIN0 – Address 0x0E
BIT
7:6
5:0
FIELD
TYPE
R/W
RESET
00
DESCRIPTION
RESERVED
GAIN0
Reserved. Set to b00.
R/W
b10 1000
Gain for Channel 0
Refer to the Gain Table for detailed configuration.
表 16. Register LP_SCAN_RATE – Address 0x0F
BIT
7:2
1:0
FIELD
TYPE
R/W
RESET
b00 0000
10
DESCRIPTION
RESERVED
LPSR
Reserved. Set to b00 0000.
R/W
Low Power Mode Scan Rate
Refer to Configuring Button Scan Rate for more information.
b00: 5 SPS
b01: 2.5 SPS
b10: 1.25 SPS (Default)
b11: 0.625 SPS
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表 17. Register GAIN1 – Address 0x10
BIT
7:6
5:0
FIELD
TYPE
R/W
RESET
00
DESCRIPTION
RESERVED
GAIN1
Reserved. Set to b00.
R/W
b10 1000
Gain for Channel 1
Refer to the Gain Table for detailed configuration.
表 18. Register INTPOL – Address 0x11
BIT
7:3
2
FIELD
TYPE
R/W
RESET
b0 0000
0
DESCRIPTION
RESERVED
INTPOL
Reserved. Set to b0 0000.
R/W
Interrupt Polarity
b0: Set INTB pin polarity to active low.
b1: Set INTB pin polarity to active high.
1:0
RESERVED
R/W
01
Reserved. Set to b01.
表 19. Register GAIN2 – Address 0x12
BIT
7:6
5:0
FIELD
TYPE
R/W
RESET
00
DESCRIPTION
RESERVED
GAIN2
Reserved. Set to b00.
R/W
b10 1000
Gain for Channel 2 (LDC2114 Only)
Refer to the Gain Table for detailed configuration.
表 20. Register LP_BASE_INC – Address 0x13
BIT
7:3
2:0
FIELD
TYPE
R/W
RESET
b0 0000
b101
DESCRIPTION
RESERVED
LPBI
Reserved. Set to b0 0000.
R/W
Baseline Tracking Increment in Low Power Mode
Refer to Tracking Baseline for more information. Valid values:
[b000:b111].
b101: LPBI = 5 (Default)
表 21. Register GAIN3 – Address 0x14
BIT
7:6
5:0
FIELD
TYPE
R/W
RESET
00
DESCRIPTION
RESERVED
GAIN3
Reserved. Set to b00.
R/W
b10 1000
Gain for Channel 3 (LDC2114 Only)
Refer to the Gain Table for detailed configuration.
表 22. Register NP_BASE_INC – Address 0x15
BIT
7:3
2:0
FIELD
TYPE
R/W
RESET
b0 0000
b011
DESCRIPTION
RESERVED
NPBI
Reserved. Set to b0 0000.
R/W
Baseline Tracking Increment in Normal Power Mode
Refer to Tracking Baseline for more information. Valid values:
[b000:b111].
b011: NPBI = 3 (Default)
表 23. Register BTPAUSE_MAXWIN – Address 0x16
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
BTPAUSE3
R/W
0
Baseline Tracking Pause for Channel 3 (LDC2114 Only)
Pauses baseline tracking for Channel 3 when OUT3 is asserted.
Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 3 regardless of OUT3
status. (Default)
b1: Pauses baseline tracking for Channel 3 when OUT3 is
asserted.
6
BTPAUSE2
R/W
0
Baseline Tracking Pause for Channel 2 (LDC2114 Only)
Pauses baseline tracking for Channel 2 when OUT2 is asserted.
Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 2 regardless of OUT2
status. (Default)
b1: Pauses baseline tracking for Channel 2 when OUT2 is
asserted.
20
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ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
表 23. Register BTPAUSE_MAXWIN – Address 0x16 (接下页)
BIT
FIELD
TYPE
RESET
DESCRIPTION
5
BTPAUSE1
R/W
0
Baseline Tracking Pause for Channel 1
Pauses baseline tracking for Channel 1 when OUT1 is asserted.
Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 1 regardless of OUT1
status. (Default)
b1: Pauses baseline tracking for Channel 1 when OUT1 is
asserted.
4
BTPAUSE0
R/W
0
Baseline Tracking Pause for Channel 0
Pauses baseline tracking for Channel 0 when OUT0 is asserted.
Refer to Tracking Baseline for more information.
b0: Normal baseline tracking for Channel 0 regardless of OUT0
status. (Default)
b1: Pauses baseline tracking for Channel 0 when OUT0 is
asserted.
3
2
1
0
MAXWIN3
MAXWIN2
MAXWIN1
MAXWIN0
R/W
R/W
R/W
R/W
0
0
0
0
Max-Win Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Resolving Simultaneous Button Presses (Max-Win) for
more information.
b0: Exclude Channel 3 from the max-win group. (Default)
b1: Include Channel 3 in the max-win group.
Max-Win Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Resolving Simultaneous Button Presses (Max-Win) for
more information.
b0: Exclude Channel 2 from the max-win group. (Default)
b1: Include Channel 2 in the max-win group.
Max-Win Algorithm Setting for Channel 1
Refer to Resolving Simultaneous Button Presses (Max-Win) for
more information.
b0: Exclude Channel 1 from the max-win group. (Default)
b1: Include Channel 1 in the max-win group.
Max-Win Algorithm Setting for Channel 0
Refer to Resolving Simultaneous Button Presses (Max-Win) for
more information.
b0: Exclude Channel 0 from the max-win group. (Default)
b1: Include Channel 0 in the max-win group.
表 24. Register LC_DIVIDER – Address 0x17
BIT
7:3
2:0
FIELD
TYPE
R/W
RESET
b0 0000
b011
DESCRIPTION
RESERVED
LCDIV
Reserved. Set to b0 0000.
R/W
LC Oscillation Frequency Divider
The frequency divider sets the button sampling window in
conjunction with SENCYCn. Valid values: [b000:b111].
Refer to Programming Button Sampling Window for more
information.
b011: LCDIV = 3 (Default)
表 25. Register HYST – Address 0x18
BIT
7:4
3:0
FIELD
TYPE
R/W
RESET
b0000
b1000
DESCRIPTION
RESERVED
HYST
Reserved. Set to b0000.
R/W
Hysteresis
Defines the hysteresis for button triggering threshold. Valid values:
[b0000:b1111].
Hysteresis = HYST × 4
b1000: HYST = 8, Hysteresis = 32 (Default)
Refer to Setting Button Triggering Threshold for more information.
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表 26. Register TWIST – Address 0x19
BIT
7:3
2:0
FIELD
TYPE
R/W
RESET
b0 0000
b000
DESCRIPTION
RESERVED
ANTITWIST
Reserved. Set to b0 0000.
R/W
Anti-Twist
When set to 0, the anti-twist algorithm is not enabled.
When greater than 0, all buttons are enabled for the anti-twist
algorithm. The validation of all buttons is void if any button’s DATA
is negative by a threshold.
Anti-twist Threshold = ANTITWIST × 4.
Refer to Overcoming Case Twisting (Anti-Twist) for more
information.
表 27. Register COMMON_DEFORM – Address 0x1A
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
ANTICOM3
R/W
0
Anti-Common Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Eliminating Common-Mode Change (Anti-Common) for
more information.
b0: Exclude Channel 3 from the anti-common group. (Default)
b1: Include Channel 3 in the anti-common group.
6
5
4
3
2
1
0
ANTICOM2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Anti-Common Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Eliminating Common-Mode Change (Anti-Common) for
more information.
b0: Exclude Channel 2 from the anti-common group. (Default)
b1: Include Channel 2 in the anti-common group.
ANTICOM1
Anti-Common Algorithm Setting for Channel 1
Refer to Eliminating Common-Mode Change (Anti-Common) for
more information.
b0: Exclude Channel 1 from the anti-common group. (Default)
b1: Include Channel 1 in the anti-common group.
ANTICOM0
Anti-Common Algorithm Setting for Channel 0
Refer to Eliminating Common-Mode Change (Anti-Common) for
more information.
b0: Exclude Channel 0 from the anti-common group. (Default)
b1: Include Channel 0 in the anti-common group.
ANTIDFORM3
ANTIDFORM2
ANTIDFORM1
ANTIDFORM0
Anti-Deform Algorithm Setting for Channel 3 (LDC2114 Only)
Refer to Mitigating Metal Deformation (Anti-Deform) for more
information.
b0: Exclude Channel 3 from the anti-deform group. (Default)
b1: Include Channel 3 in the anti-deform group.
Anti-Deform Algorithm Setting for Channel 2 (LDC2114 Only)
Refer to Mitigating Metal Deformation (Anti-Deform) for more
information.
b0: Exclude Channel 2 from the anti-deform group. (Default)
b1: Include Channel 2 in the anti-deform group.
Anti-Deform Algorithm Setting for Channel 1
Refer to Mitigating Metal Deformation (Anti-Deform) for more
information.
b0: Exclude Channel 1 from the anti-deform group. (Default)
b1: Include Channel 1 in the anti-deform group.
Anti-Deform Algorithm Setting for Channel 0
Refer to Mitigating Metal Deformation (Anti-Deform) for more
information.
b0: Exclude Channel 0 from the anti-deform group. (Default)
b1: Include Channel 0 in the anti-deform group.
表 28. Register OPOL_DPOL – Address 0x1C
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
OPOL3
R/W
0
Output Polarity for OUT3 Pin (LDC2114 Only)
b0: Active low (Default)
b1: Active high
6
OPOL2
R/W
0
Output Polarity for OUT2 Pin (LDC2114 Only)
b0: Active low (Default)
b1: Active high
22
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ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
表 28. Register OPOL_DPOL – Address 0x1C (接下页)
BIT
FIELD
TYPE
RESET
DESCRIPTION
5
OPOL1
OPOL0
DPOL3
DPOL2
DPOL1
DPOL0
R/W
0
Output Polarity for OUT1 Pin
b0: Active low (Default)
b1: Active high
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
Output Polarity for OUT0 Pin
b0: Active low (Default)
b1: Active high
Data Polarity for Channel 3 (LDC2114 Only)
b0: DATA3 decreases as fSENSOR3 increases.
b1: DATA3 increases as fSENSOR3 increases. (Default)
Data Polarity for Channel 2 (LDC2114 Only)
b0: DATA2 decreases as fSENSOR2 increases.
b1: DATA2 increases as fSENSOR2 increases. (Default)
Data Polarity for Channel 1
b0: DATA1 decreases as fSENSOR1 increases.
b1: DATA1 increases as fSENSOR1 increases. (Default)
Data Polarity for Channel 0
b0: DATA0 decreases as fSENSOR0 increases.
b1: DATA0 increases as fSENSOR0 increases. (Default)
表 29. Register CNTSC – Address 0x1E(1)
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:6
CNTSC3
R/W
01
Counter Scale for Channel 3 (LDC2114 Only)
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC3 = 0
b01: CNTSC3 = 1 (Default)
b10: CNTSC3 = 2
b11: CNTSC3 = 3
5:4
3:2
1:0
CNTSC2
CNTSC1
CNTSC0
R/W
R/W
R/W
01
01
01
Counter Scale for Channel 2 (LDC2114 Only)
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC2 = 0
b01: CNTSC2 = 1 (Default)
b10: CNTSC2 = 2
b11: CNTSC2 = 3
Counter Scale for Channel 1
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC1 = 0
b01: CNTSC1 = 1 (Default)
b10: CNTSC1 = 2
b11: CNTSC1 = 3
Counter Scale for Channel 0
Refer to Scaling Frequency Counter Output for more information.
b00: CNTSC0 = 0
b01: CNTSC0 = 1 (Default)
b10: CNTSC0 = 2
b11: CNTSC0 = 3
(1) The Counter Scale sets a scaling factor for the internal frequency counter to avoid data overflow. The formula for calculating counter
scale is CNTSCn = LCDIV + ceiling(log2 (0.0861×(SENCYCn+1)/fSENSORn)), n = 0, 1, 2, or 3, where LCDIV and SENCYCn are the
exponential and linear scalers that set the number of sensor oscillation cycles, fSENSORn is the sensor frequency in MHz.
表 30. Register SENSOR0_CONFIG – Address 0x20
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
RP0
R/W
0
Channel 0 Sensor RP Range Select
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the
inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350Ω ≤ RP ≤ 4kΩ (Default)
b1: 800Ω ≤ RP ≤ 10kΩ
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表 30. Register SENSOR0_CONFIG – Address 0x20 (接下页)
BIT
FIELD
TYPE
RESET
DESCRIPTION
6:5
FREQ0
R/W
00
Channel 0 Sensor Frequency Range Select
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
4:0
SENCYC0
R/W
b0 0100
Channel 0 Sensor Cycle Count
SENCYC0 sets the Channel 0 button sampling window in
conjunction with LCDIV.
Refer to Programming Button Sampling Window for more
information.
表 31. Register SENSOR1_CONFIG – Address 0x22
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
RP1
R/W
0
Channel 1 Sensor RP Range Select
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the
inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5
4:0
FREQ1
R/W
R/W
00
Channel 1 Sensor Frequency Range Select
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
SENCYC1
b0 0100
Channel 1 Sensor Cycle Count
SENCYC1 sets the Channel 1 button sampling window in
conjunction with LCDIV.
Refer to Programming Button Sampling Window for more
information.
表 32. Register SENSOR2_CONFIG – Address 0x24
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
RP2
R/W
0
Channel 2 Sensor RP Range Select (LDC2114 Only)
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the
inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5
4:0
FREQ2
R/W
R/W
00
Channel 2 Sensor Frequency Range Select (LDC2114 Only)
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
SENCYC2
b0 0100
Channel 2 Sensor Cycle Count (LDC2114 Only)
SENCYC2 sets the Channel 2 button sampling window in
conjunction with LCDIV.
Refer to Programming Button Sampling Window for more
information.
24
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ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
表 33. Register FTF0 – Address 0x25
BIT
7:3
2:1
FIELD
TYPE
R/W
RESET
b0 0000
01
DESCRIPTION
RESERVED
FTF0
Reserved. Set to b0 0000.
R/W
Fast Tracking Factor for Channel 0
Defines baseline tracking speed for negative values of DATA0.
Refer to Tracking Baseline for more information.
b00: FTF0 = 0
b01: FTF0 = 1 (Default)
b10: FTF0 = 2
b11: FTF0 = 3
0
RESERVED
R/W
0
Reserved. Set to b0.
表 34. Register SENSOR3_CONFIG – Address 0x26
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
RP3
R/W
0
Channel 3 Sensor RP Range Select (LDC2114 Only)
Set based on the actual sensor RP physical parameter.
RP = 1/RS × L/C
where RS is the AC series resistance in the LC resonator, L is the
inductance, and C is the capacitance.
Refer to Designing Sensor Parameters for more information.
b0: 350 Ω ≤ RP ≤ 4 kΩ (Default)
b1: 800 Ω ≤ RP ≤ 10 kΩ
6:5
4:0
FREQ3
R/W
R/W
00
Channel 3 Sensor Frequency Range Select (LDC2114 Only)
Refer to Designing Sensor Parameters for more information.
b00: 1 MHz to 3.3 MHz (Default)
b01: 3.3 MHz to 10 MHz
b10: 10 MHz to 30 MHz
b11: Reserved
SENCYC3
b0 0100
Channel 3 Sensor Cycle Count (LDC2114 Only)
SENCYC3 sets the Channel 3 button sampling window in
conjunction with LCDIV.
Refer to Programming Button Sampling Window for more
information.
表 35. Register FTF1_2 – Address 0x28
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:6
FTF2
R/W
01
Fast Tracking Factor for Channel 2 (LDC2114 Only)
Defines baseline tracking speed for negative values of DATA2.
Refer to Tracking Baseline for more information.
b00: FTF2 = 0
b01: FTF2 = 1 (Default)
b10: FTF2 = 2
b11: FTF2 = 3
5:4
FTF1
R/W
01
Fast Tracking Factor for Channel 1
Defines baseline tracking speed for negative values of DATA1.
Refer to Tracking Baseline for more information.
b00: FTF1 = 0
b01: FTF1 = 1 (Default)
b10: FTF1 = 2
b11: FTF1 = 3
3:0
RESERVED
R/W
b0000
Reserved. Set to b0000.
表 36. Register FTF3 – Address 0x2B
BIT
7:2
1:0
FIELD
TYPE
R/W
RESET
b00 0000
01
DESCRIPTION
RESERVED
FTF3
Reserved. Set to b00 0000.
R/W
Fast Tracking Factor for Channel 3 (LDC2114 Only)
Defines baseline tracking speed for negative values of DATA3.
Refer to Tracking Baseline for more information.
b00: FTF3 = 0
b01: FTF3 = 1 (Default)
b10: FTF3 = 2
b11: FTF3 = 3
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表 37. Register MANUFACTURER_ID_LSB – Address 0xFC
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
MANUFACTURER_ID [7:0]
R
0x49
Manufacturer ID [7:0]
表 38. Register MANUFACTURER_ID_MSB – Address 0xFD
BIT
FIELD
TYPE
RESET
DESCRIPTION
7:0
MANUFACTURER_ID [15:8]
R
0x54
Manufacturer ID [15:8]
表 39. Register DEVICE_ID_LSB – Address 0xFE
BIT
FIELD
TYPE
RESET
DESCRIPTION
Device ID [7:0]
7:0
DEVICE_ID [7:0]
R
0x01
(LDC2112)
0x00
(LDC2114)
表 40. Register DEVICE_ID_MSB – Address 0xFF
BIT
FIELD
TYPE
RESET
DESCRIPTION
Device ID [15:8]
7:0
DEVICE_ID [15:8]
R
0x20
26
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www.ti.com.cn
ZHCSGN4B –DECEMBER 2016–REVISED APRIL 2017
7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3
表 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors
BIT VALUE IN DECIMAL
NORMALIZED GAIN FACTOR
BIT VALUE IN DECIMAL
NORMALIZED GAIN FACTOR
0
1.0
1.0625
1.1875
1.3125
1.4375
1.5625
1.6875
1.8125
2.0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
16
17
1
2
19
3
21
4
23
5
25
6
27
7
29
8
32
9
2.125
2.375
2.625
2.875
3.125
3.375
3.625
4.0
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
38
42
46
50
54
58
64
4.25
68
4.75
76
5.25
84
5.75
92
6.25
100
108
116
128
136
152
168
184
200
216
232
6.75
7.25
8.0
8.5
9.5
10.5
11.5
12.5
13.5
14.5
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LDC2112/LDC2114 supports multiple buttons. Each button can be configured in various ways for optimal
operation.
8.1.1 Theory of Operation
An AC current flowing through an inductor will generate an AC magnetic field. If a conductive material, such as a
metal object, is in close proximity to the inductor, the magnetic field will induce circulating eddy currents on the
surface of the conductor. The eddy currents are a function of the distance, size, and composition of the
conductor. If the conductor is deflected toward the inductor as shown in 图 17, more eddy currents will be
generated.
图 17. Metal Deflection
The eddy currents create their own magnetic field, which opposes the original field generated by the inductor.
This effect reduces the effective inductance of the system, resulting in an increase in sensor frequency. 图 18
shows the inductance and frequency response of an example sensor with a diameter of 14 mm. As the sensitivity
of an inductive sensor increases with closer targets, the conductive plate should be placed quite close to the
sensor—typically 10% of the sensor diameter for circular coils. For rectangular or race-track-shaped coils, the
target to sensor distance should typically be less than 10% of the shorter side of the coil.
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Application Information (接下页)
7
6.5
6
5
4.75
4.5
4.25
5.5
5
Sensor Inductance (μH)
Sensor Frequency (MHz)
4
4.5
4
3.75
3.5
3.25
3
3.5
3
0
1
2
3
4
5
6
7
Distance between Sensor and Target (mm)
8
9
10
D010
图 18. Sensor Inductance and Frequency vs Target Distance. Sensor Diameter = 14 mm
The output DATAn registers (Addresses 0x02 through 0x09) of the LDC2112/LDC2114 contain the processed
values of the changes in sensor frequencies.
8.1.2 Designing Sensor Parameters
Each inductive touch button uses an LC resonator sensor, as illustrated in 图 19, where L is the inductor, C is the
capacitor, and RS is the AC series resistance of the sensor at the frequency of operation. The key parameters of
the LC sensor include frequency, effective parallel resistance RP, and quality factor Q. These parameters must
be within the ranges as specified in the Sensor section of the Electrical Characteristics table. Note that the
effective RP and Q changes when the conductive target is in place.
L
C
RS
图 19. LC Resonator
The LC sensor frequency, as defined by the equation below, must be between 1 MHz and 30 MHz.
1
fSENSOR
=
2p LC
The sensor quality factor, as defined by the equation below, must be between 5 and 30.
(1)
(2)
1
L
QSENSOR
=
RS
C
The series resistance can be represented as an equivalent parallel resistance, RP, which is given by
L
RP =
RSC
(3)
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Application Information (接下页)
C
RP
L
图 20. Equivalent Parallel Circuit
RP can be viewed as the load on the sensor driver. This load corresponds to the current drive needed to maintain
the oscillation amplitude. RP must be between 350 Ω and 10 kΩ.
In summary, the LDC2112/LDC2114 requires that the sensor parameters are within the following ranges when
the conductive target is present:
•
•
•
1 MHz ≤ fSENSOR ≤ 30 MHz
5 ≤ Q ≤ 30
350 Ω ≤ RP ≤ 10 kΩ
8.1.3 Setting COM Pin Capacitor
The COM pin requires a bypass capacitor to ground. The capacitor should be a low ESL, low ESR type. CCOM
must be sized so that the following relationship is valid for all channels.
100 × CSENSORn / QSENSORn < CCOM < 1250 × CSENSORn / QSENSORn
(4)
The value of QSENSORn when the sensor is at the minimum target distance should be used. The maximum
acceptable value for CCOM is 20 nF. The CCOM range for a particular sensor configuration can be obtained with
the Spiral_Inductor_Designer tab of the LDC Calculations Tool.
8.1.4 Defining Power-On Timing
The low power architecture of the LDC2112/LDC2114 makes it possible for the device to be active all the time.
When not being used, the LDC2112/LDC2114 can operate in Low Power Mode with a single standby power
button, which typically consumes less than 10 µA. If additional power-saving is desired, or in the rare event
where a power-on reset becomes necessary (see I2C Interface), the output data will become ready after 50 ms
startup time, about 1 ms optional register loading time, and two sampling windows for all active channels. The
power-on timing of the LDC2112/LDC2114 is illustrated in 图 21 below.
Only Channels 0 and 1 are enabled. Scan rate: 40 SPS.
25 ms scan cycle
25 ms scan cycle
66 ms startup time
Sampling
Sampling
VDD
IN0
IN1
DATA is ready
after all active channels
finish two conversions.
66 ms startup time is
independent of scan rate.
Events
Power up
图 21. Power-On Timing
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Application Information (接下页)
8.1.5 Configuring Button Scan Rate
The LDC2112/LDC2114 periodically samples all active channels at the selected scan rate. The device can
operate at eight different scan rates to meet various power consumption requirements, where a lower scan rate
achieves lower power consumption. In Normal Power Mode, the scan rate can be programmed to 80, 40, 20, or
10 SPS through Register NP_SCAN_RATE (Address 0x0D). In Low Power Mode, the scan rate can be
programmed to 5, 2.5, 1.25, or 0.625 SPS through Register LP_SCAN_RATE (Address 0x0F). The mode is
selected by setting the LPWRB pin to VDD (Normal Power) or ground (Low Power). In either mode, each button
can be independently enabled through a bit in Register EN (Address 0x0C). For typical distribution of the scan
rates, refer to 图 9.
表 42. Button Scan Rates
SCAN RATE (SPS)
LPSR (0x0F) SETTING
b11
NPSR (0x0D) SETTING
Not Applicable
Not Applicable
Not Applicable
Not Applicable
b11
LPWRB PIN SETTING
0.625
1.25
2.5
5
Ground
Ground
Ground
Ground
VDD
b10
b01
b00
10
Not Applicable
Not Applicable
Not Applicable
Not Applicable
20
b10
VDD
40
b01
VDD
80
b00
VDD
8.1.6 Programming Button Sampling Window
The button sampling window is the actual duration per scan cycle for active data sampling of the sensor
frequency. It is programmed with the exponential parameter, LCDIV, in Register LC_DIVIDER (Address 0x17),
and the individual linear sensor cycle counter SENCYCn (n = 0, 1, 2, or 3) in Registers SENSORn_CONFIG (n =
0, 1, 2, or 3, Addresses 0x20, 0x22, 0x24, 0x26). For most touch button applications, the button sampling
window should be set to between 1 ms and 8 ms. The recommended minimum sensor conversion time is 1 ms.
Longer conversion time can be used to achieve better signal-to-noise ratio if needed. If multiple channels are
enabled, the active channels will sample sequentially, as illustrated in 图 22.
Button Sampling Window: set by
LCDIV, SENCYCn, and fSENSORn
IN0
IN1
IN2
IN3
Scan Rate: set by NPSR,
LPSR, and LPWRB pin
图 22. Configurable Scan Rate and Button Sampling Window
The LDC2112/LDC2114 is designed to work with LC resonator sensors with oscillation frequencies ranging from
1 MHz to 30 MHz. The exact definition of the button sampling window is given by the equation below.
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Number of Sensor Oscillation Cycles
Button Sampling Window =
Sensor Frequency
128ì SENCYCn +1 ì 2LCDIV
(
)
tSAMPLE
=
,n = 0,1, 2, or 3
fSENSORn
where:
•
•
•
tSAMPLE is the button sampling window in µs,
SENCYCn and LCDIV are the linear and exponential scalers that set the number of sensor oscillation cycles, and
fSENSORn is the sensor frequency in MHz.
(5)
In the equation above, LCDIV (0 to 7, default 3) is the exponential LC divider that sets the approximate ranges
for all channels, and SENCYCn (0 to 31, default 4) is the linear sensor cycle scaler that fine-tunes each
individual channel. Together they set the number of sensor oscillation cycles used to determine the button
sampling window.
For example, if the LC sensor frequency is 9.2 MHz, and it is desirable to get 1 ms button sampling window, then
this can be achieved by setting SENCYCn = 17 and LCDIV = 2.
Alternatively, from the button sampling window and sensor frequency, the LCDIV can be read off from 图 23. For
example, 1 ms button sampling window and 9.2 MHz sensor frequency intersect at the region where LCDIV = 2.
Then SENCYCn can be calculated accordingly.
30
LCDIV=7
25
LCDIV=6
20
LCDIV=5
15
LCDIV=4
10
LCDIV=3
LCDIV=2
5
LCDIV=1
LCDIV=0
0
0
1
2
3
4
5
6
Button Sampling Window (ms)
7
8
9
D008
图 23. LCDIV as a Function of Sensor Frequency and Button Sampling Window
8.1.7 Scaling Frequency Counter Output
The LDC2112/LDC2114 requires this internal frequency counter scaler to be set based on the button sampling
window to avoid data overflow. The scaler in Register CNTSC (Address 0x1E) must be set by the following
formula:
≈
’
0.0861ì SENCYCn +1
(
)
CNTSCn = LCDIV + ceiling log
, n = 0,1, 2, or 3
(
)
∆
÷
÷
2
∆
fSENSORn
«
◊
where:
•
•
•
CNTSCn is the internal frequency counter scaler,
SENCYCn and LCDIV are the linear and exponential scalers that set the number of sensor oscillation cycles, and
fSENSORn is the sensor frequency in MHz.
(6)
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8.1.8 Setting Button Triggering Threshold
Every material shows some hysteresis when it deforms then returns to the original state. The amount of
hysteresis is a function of material properties and physical parameters, such as size and thickness. This feature
modifies the hysteresis of the button signal threshold according to different materials and various button shapes
and sizes. Hysteresis can be programmed in Register HYST (Address 0x18). By default, the button triggering
hysteresis is set to 32. The nominal button triggering threshold is 128. With hysteresis, the effective on-threshold
is 128 + 32 = 160. This means if the DATAn (n = 0, 1, 2, or 3) reaches 160, the LDC considers that as a button
press. When the DATAn decreases to 128 – 32 = 96, the LDC considers the button to be released.
ThresholdON = 128 +Hysteresis
ThresholdOFF = 128 -Hysteresis
(7)
(8)
OUTn
High=Button
Press Detected
Low=No Button
Press Detected
DATAn
ThresholdOFF
128
ThresholdON
图 24. Button Triggering Threshold with Hysteresis. Output Polarity: Active High
8.1.9 Tracking Baseline
The LDC2112/LDC2114 automatically tracks slow changes in the baseline signal and compensates for
environmental drifts and variations. In Normal Power Mode, the effective baseline increment per scan cycle
(BINCNP) can be determined by 公式 9:
2NPBI
BINCNP
=
72
where:
•
NPBI is the Normal Power Baseline Increment index that can be configured in Register NP_BASE_INC (Address
0x15).
(9)
In Low Power Mode, the effective baseline increment per scan cycle (BINCLP) can be determined by 公式 10:
2LPBI
BINCLP
=
9
where:
•
LPBI the Low Power Baseline Increment index that can be configured in Register LP_BASE_INC (Address 0x13).
(10)
As a result of baseline tracking, a button press with a constant force only lasts for a finite amount of time. The
duration of a button press is defined by 公式 11 (DATAn > ThresholdON).
DATAn - ThresholdOFF
Duration of Button Press =
BINC
where:
•
•
•
Duration of Button Press is the number of scan cycles that the channel is asserted,
DATAn is the button signal at the beginning of a press, and
BINC is the baseline increment per scan cycle.
(11)
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Button Released
Button Pressed
Baseline
DATAn
Baseline Increment
Fast tracking if DATAn is
negative
图 25. Baseline Tracking in the Presence of a Button Press
The baseline tracking for a particular channel can be paused when the channel output is asserted. This is
achieved by setting the corresponding BTPAUSE bit in Register BTPAUSE_MAXWIN (Address 0x16) to b1.
If DATAn is negative, the tracking speed will be scaled by the fast tracking factor as specified in Registers FTF0
(Address 0x25), FTF1_2 (Address 0x28), or FTF3 (Address 0x2B). The scaling factors for various FTFn settings
are shown in 表 43.
BINC (DATAn < 0) = Fast_Tracking_Factor_n × BINC (DATAn > 0)
(12)
表 43. Fast Tracking Factor Settings
FTFn Setting
Fast Tracking Factor
b00
b01
b10
b11
1
4
8
16
8.1.10 Mitigating False Button Detections
The LDC2112/LDC2114 offers several algorithms that can mitigate false button detections due to mechanical
non-idealities associated with groups of buttons. These are listed below.
8.1.10.1 Eliminating Common-Mode Change (Anti-Common)
This algorithm eliminates false detection when a user presses the middle of two or more buttons, which could
lead to a common-mode response on multiple buttons. All the buttons can be individually enabled to have this
feature by programming Register COMMON_DEFORM (Address 0x1A).
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Button 0
Button 1
Intentional Press
of Button 1
Common-mode change
to both Buttons 0 and 1.
DATA
Threshold = 128+Hysteresis
Time
Button 0
OUTPUT without
Anti-common
(High = Button
Press Detected)
Button 1
Time
Button 0
OUTPUT with
Anti-common
(High = Button
Press Detected)
Button 1
Time
图 26. Illustration of the Anti-Common Feature
8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)
This algorithm enables the system to select the button pressed with maximum force when multiple buttons are
pressed at the same time. This could happen when two buttons are physically very close to each other, and
pressing one causes a residual reaction on the other. Buttons can be individually enabled to join the “max-win”
group by configuring Register BTPAUSE_MAXWIN (Address 0x16).
Intentional Press of Button 0
with coupled response of
Button 1
Intentional Press of
Button 0
Button 1
Button 1
DATA
Threshold = 128+Hysteresis
Time
Button 0
OUTPUT
without Max-Win
(High = Button
Press Detected)
Button 1
Time
Button 0
OUTPUT with
Max-Win
(High = Button
Press Detected)
Button 1
Time
图 27. Illustration of the Max-Win Feature
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8.1.10.3 Overcoming Case Twisting (Anti-Twist)
The anti-twist algorithm reduces the likelihood of false detection when the case is twisted, which could cause
unintended mechanical activation of the buttons, or an opposite reaction in two adjacent buttons. When this
algorithm is enabled, detection of button presses is suppressed if any button’s output data is negative by a
configurable threshold. The anti-twist algorithm can be enabled by configuring Register TWIST (Address 0x19).
Button 0
Button 1
Intentional Press of
Button 1.
Twisting effect of
Buttons 0 and 1.
DATA
Threshold = 128+Hysteresis
Time
Button 0
OUTPUT without
Anti-twist
(High = Button
Press Detected)
Button 1
Time
Button 0
OUTPUT with
Anti-twist
(High = Button
Press Detected)
Button 1
Time
图 28. Illustration of the Anti-Twist Feature
8.1.10.4 Mitigating Metal Deformation (Anti-Deform)
This function filters changes due to metal deformation in the vicinity of one or more buttons. Such metal
deformation can be accidentally caused by pressing a neighboring button that does not have sufficient
mechanical isolation. The user can specify which buttons to join the anti-deform group by configuring Register
COMMON_DEFORM (Address 0x1A).
8.1.11 Reporting Interrupts for Button Presses and Error Conditions
INTB, the LDC2112/LDC2114 interrupt pin, is asserted when a button press or an error condition occurs. The
default polarity is active low and can be configured through Register INTPOL (Address 0x11).
图 29 shows the LDC2112/LDC2114 response to a single button press on Channel 0. At the end of the button
sampling window following a press of Button 0, the OUT0 pin and INTB pin are asserted. The OUT_STATUS bit
changes from 0 to 1, and remains so until a read of the STATUS register clears it. The OUTn (n = 0, 1, 2, or 3)
and INTB pins are asserted until the end of the button sampling window following the release of the button.
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OUTn and INTB are programmed to —Active Low“. Scan Rate: 40 SPS.
25 ms scan cycle
25 ms scan cycle
25 ms scan cycle
Sampling
Sampling
Sampling
OUT0
Pin
INTB
Pin
STATUS
Register
OUT0 and
Reading the Status
Register clears the
OUT_STATUS bit.
INTB asserted,
OUT_STATUS
bit asserted
Button 0
pressed
Button 0
Events
OUT0 de-asserted
released
图 29. Timing Diagram of a Single Button Press
图 30 shows the LDC2112/LDC2114 response to multiple button presses. In this example, after Button 0 is
pressed, the OUT0 pin is asserted. After that, Button 1 is also pressed, following which Button 0 is released. The
OUT0 pin is de-asserted and OUT1 pin asserted at the end of the next button sampling window. The INTB pin
remains continuously asserted as long as at least one of the buttons is pressed. The OUT_STATUS bit only
changes from 0 to 1 after the first button assertion.
OUTn and INTB are programmed to —Active Low“. Scan Rate: 40 SPS.
25 ms scan cycle
25 ms scan cycle
25 ms scan cycle
Sampling
Sampling
Sampling
OUT0
Pin
OUT1
Pin
INTB
Pin
STATUS
Register
Button 1 Button 0
pressed released
OUT0 de-asserted
OUT1 asserted
Button 1
released
OUT1 and INTB
de-asserted
Button 0
pressed
OUT0 and
INTB asserted
Events
Reading the Status Register
clears the OUT_STATUS bit.
图 30. Timing Diagram of Multiple Button Presses
The INTB pin also reports any error event. If an error occurs, the INTB pin is asserted and the error is reported in
the STATUS register (Address 0x00). Refer to Register STATUS (Address 0x00) for possible error events.
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8.1.12 Estimating Supply Current
When the LDC2112/LDC2114 is active (in either Normal Power Mode or Low Power Mode), its current can be
characterized by 公式 13:
12
IACTIVEn = 1.6 +
1.21 + 0.011ìfSENSORn
1+16ìRPn
where
•
•
•
•
IACTIVEn is the supply current in mA during active sampling,
RPn is the sensor parallel resonant impedance in kΩ,
fSENSORn is the sensor frequency in MHz, and
n is the channel index, i.e. n = 0 or 1 for LDC2112; n = 0, 1, 2, or 3 for LDC2114.
(13)
The LDC2112/LDC2114 is only actively sampling the enabled channels during a fraction of the scan window. So
the average supply current is:
≈
’
1
IDD
=
ì∆ IACTIVEn ì tSAMPLEn ÷ + 0.005
∆ƒ
÷
tSCAN
« n
◊
where
•
•
•
•
IDD is the average supply current in mA,
tSCAN is the scan window (set by the scan rate) in ms,
IACTIVEn is the supply current when the device is active as defined by 公式 13, and
tSAMPLE is the button sampling window in ms.
(14)
8.2 Typical Application
8.2.1 Touch Button Design
The low power architecture of LDC2112/LDC2114 makes them suitable for driving button sensors in consumer
electronics, such as mobile phones. Most mobile phones today have three buttons along the edges, namely the
power button, volume up, and volume down. The LDC2112 can support two buttons, and LDC2114 can support
four.
On a typical smartphone, the two volume buttons are next to each other, so they may be susceptible to false
detections such as simultaneous button presses. To prevent such mis-triggers, they can be grouped together to
take advantage of the various features that mitigate false detections as explained in Mitigating False Button
Detections. For example, if Max-win is applied to the two volume buttons, only the one with the greater force will
be triggered.
The inductive touch solution does not require any mechanical cutouts at the button locations. This can support
reduced manufacturing cost for the phone case and enhance the case’s resistance to moisture, dust, and dirt.
This is a great advantage compared to mechanical buttons in the market today.
8.2.1.1 Design Requirements
The sensor parameters, including frequency, RP, and Q factor have to be within the design space of the
LDC2112/LDC2114 as specified in Electrical Characteristics.
8.2.1.2 Detailed Design Procedure
The LDC2112/LDC2114 is a multi-channel device. The italic n in the parameters below refers to the channel
index, i.e., n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114.
1. Select system-based options:
•
Select Normal or Low Power Mode of operation by setting the LPWRB pin to VDD or Ground, respectively.
Configure the enable bits for all channels in Register EN (Address 0x0C).
•
Select the polarities of OUTn and INTB pins by configuring Register OPOL_DPOL (Address 0x1C) and
Register INTPOL (Address 0x11).
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Typical Application (接下页)
•
Configure the sensor frequency setting in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24,
0x26).
2. Choose the sampling rate (80, 40, 20, 10, 5, 2.5, 1.25, or 0.625 SPS) based on system power consumption
requirement, and configure Register NP_SCAN_RATE (Address 0x0D) or Register LP_SCAN_RATE (Address
0x0F).
3. Choose the button sampling window based on power consumption and noise requirements (recommended: 1
ms to 8 ms). While a longer button sampling window provides better noise performance, 1 ms is typically
sufficient for most applications. Set SENCYCn and LCDIV in Registers SENSORn_CONFIG (Addresses 0x20,
0x22, 0x24, 0x26) and Register LC_DIVIDER (Address 0x17) in the following steps:
•
Calculate LCDIV = ceiling (log2 (fSENSORn × tSAMPLEn) – 12), where fSENSORn is the sensor frequency in MHz,
tSAMPLEn is the button sampling window in µs
•
•
If LCDIV < 0, set it to 0
Adjust SENCYCn to get desired tSAMPLEn according to tSAMPLEn = 128 × (SENCYCn + 1) × 2LCDIV / fSENSORn
4. Calibrate gain in the appropriate Registers GAINn (Addresses 0x0E, 0x10, 0x12, 0x14). The gain setting can
be used to tune the sensitivity of the touch button. GAINn is a 6-bit field with 64 different gain levels
corresponding to normalized gains between 1 and 232. A good mechanical and sensor design typically requires
a gain level of around 32 to 50, corresponding to relative gains of 16 to 76 (normalized to gain level of 0). Use
the following sequence to determine the appropriate gain for each button:
•
•
•
•
Apply minimum desired force to the button.
Read initial DATAn value after the button press. Note that the baseline tracking will affect this value.
Calculate gain factor needed to increase DATAn to the programmed threshold (default is 160).
Look up the Gain Table to find the required gain setting.
5. Enable special features to mitigate button interference if there is any. Registers BTPAUSE_MAXWIN, TWIST,
COMMON_DEFORM (Addresses 0x16, 0x19, 0x1A).
For more information on inductive touch system design, including mechanical design and sensor electrical
design, refer to Inductive Touch System Design Guide.
8.2.1.3 Application Curves
图 31 shows a sequence of button presses of 150 grams force, two presses to Channel 0, then two presses to
Channel 1. Each button press response is greater than the threshold.
400
Channel 0
Channel 1
Threshold
350
300
250
200
150
100
50
0
-50
0
2
4
6
8
Time (s)
D009
图 31. Conversion DATA vs Time for Channels 0 and 1
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9 Power Supply Recommendations
The LDC2112/LDC2114 power supply should be bypassed with a 1 µF and a 0.1 µF pair of capacitors in parallel
to ground. The capacitors should be placed as close to the LDC as possible. The smaller value 0.1 µF capacitor
should be placed closer to the VDD pin than the 1 µF capacitor. The capacitors should be a low ESL, low ESR
type. To enable close positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is
recommended for the DSBGA package.
Refer to Recommended Operating Conditions for more details.
10 Layout
10.1 Layout Guidelines
The COM pin must be bypassed to ground with an appropriate value capacitor. For details of how to choose the
capacitor value, refer to Setting COM Pin Capacitor. CCOM should be placed as close as possible to the COM
pin. The COM signal should be tied to a small copper fill placed underneath the INn signals. The INn signals
should stay clear of other high frequency traces.
Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor
capacitor should be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in 图 32)
should be placed at the appropriate location next to (but not touching) the metal target. The INn traces should be
at least 6 mil (0.15 mm) wide to minimize parasitic inductances.
For the DSBGA package, the inner four device pads (INTB, OUT3, LPWRB, and SDA) should be routed out on
an inner layer through vias, with the traces offset to reduce coupling with other signals. These four vias may
need to use blind vias or microvias to bring the signals out. The PCB layer stack should use a thinner (4 mil or
0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used.
10.2 Layout Example
图 32. Layout of LDC2114 (DSBGA-16) With Decoupling Capacitors and Sensor Capacitors
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Layout Example (接下页)
图 33. Layout of LDC2114 (TSSOP-16) With Decoupling Capacitors and Sensor Capacitors
10.3 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as
halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with
wavelengths in the red and infrared part of the spectrum have the most detrimental effect.
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
LDC 计算工具
《电感应触控系统设计指南》
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 44. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
LDC2112
LDC2114
11.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过本协议的披露方获得的任何产品或技术数据（其中包括软
件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制产品或此项技术的任
何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政府机构授权的情况下，接收
方不得在知情的情况下，以直接或间接的方式将其出口。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
42
版权 © 2016–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LDC2112PWR
LDC2112PWT
LDC2112YFDR
LDC2112YFDT
LDC2114PWR
LDC2114PWT
LDC2114YFDR
LDC2114YFDT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
DSBGA
DSBGA
TSSOP
TSSOP
DSBGA
DSBGA
PW
PW
16
16
16
16
16
16
16
16
2000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LDC2112
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
LDC2112
17M
YFD
YFD
PW
17M
LDC2114
LDC2114
14G
PW
YFD
YFD
14G
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LDC2112PWR
LDC2112YFDR
LDC2112YFDT
LDC2114PWR
LDC2114YFDR
LDC2114YFDT
TSSOP
DSBGA
DSBGA
TSSOP
DSBGA
DSBGA
PW
YFD
YFD
PW
16
16
16
16
16
16
2000
3000
250
330.0
180.0
180.0
330.0
180.0
180.0
12.4
8.4
6.9
1.69
1.69
6.9
5.6
1.69
1.69
5.6
1.6
0.46
0.46
1.6
8.0
4.0
4.0
8.0
4.0
4.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
2000
3000
250
12.4
8.4
12.0
8.0
YFD
YFD
1.69
1.69
1.69
1.69
0.46
0.46
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LDC2112PWR
LDC2112YFDR
LDC2112YFDT
LDC2114PWR
LDC2114YFDR
LDC2114YFDT
TSSOP
DSBGA
DSBGA
TSSOP
DSBGA
DSBGA
PW
YFD
YFD
PW
16
16
16
16
16
16
2000
3000
250
350.0
182.0
182.0
350.0
182.0
182.0
350.0
182.0
182.0
350.0
182.0
182.0
43.0
20.0
20.0
43.0
20.0
20.0
2000
3000
250
YFD
YFD
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YFD0016
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.4 MAX
C
SEATING PLANE
0.05 C
0.175
0.125
BALL TYP
1.2
TYP
SYMM
D
C
B
A
1.2
TYP
SYMM
D: Max = 1.625 mm, Min =1.565 mm
E: Max = 1.625 mm, Min =1.565 mm
0.4
TYP
1
2
3
4
0.285
16X
C A
0.185
0.015
B
0.4
TYP
4222547/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFD0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
16X ( 0.225)
A
(0.4) TYP
B
C
SYMM
D
2
3
4
1
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MAX
0.05 MIN
(
0.225)
METAL
METAL UNDER
SOLDER MASK
(
0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222547/A 12/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFD0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
16X ( 0.25)
A
B
(0.4)
TYP
SYMM
METAL
TYP
C
D
1
2
3
4
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4222547/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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