LDC1314-Q1 [TI]
4 通道、12 位、通用汽车类电感数字转换器;
| 型号： | LDC1314-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4 通道、12 位、通用汽车类电感数字转换器 转换器 |
| 文件： | 总58页 (文件大小：1360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
LDC1312-Q1/LDC1314-Q1 适用于电感感测的多通道 12 位电感数字转换
器 (LDC)
1 特性
2 应用
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
•
•
•
•
•
汽车按钮和旋钮
线性和旋转编码器
滑块按钮
–
–
–
器件温度 1 级：-40°C 至 +125°C 的环境运行温
度范围
工业与汽车中的金属探测
流量计
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
3 说明
器件组件充电模式 (CDM) ESD 分类等级 C5
•
•
•
•
•
易于使用 – 配置要求极低
LDC1312-Q1 和 LDC1314-Q1 分别是用于电感感测解
决方案的 2 通道和 4 通道 12 位电感数字转换器
(LDC)。由于具备多通道且支持远程感测，LDC1312-
Q1 和 LDC1314-Q1 能以最低的成本和功耗实现高性
能且可靠的电感感测。此类产品使用简便，仅需要传感
器频率处于 1kHz 至 10MHz 的范围内即可开始工作。
由于支持的传感器频率范围 1kHz 至 10MHz 较宽，因
此还支持使用非常小的 PCB 线圈，从而进一步降低感
测解决方案的成本和尺寸。
单个 IC 最多可测量四个传感器
具备多条通道，支持对环境和老化条件进行补偿
多通道远程感测，可将系统成本降至最低
与中等分辨率和高分辨率选项引脚兼容
–
LDC1312-Q1/LDC1314-Q1：2/4 通道 12 位
LDC
–
LDC1612-Q1/LDC1614-Q1：2/4 通道 28 位
LDC
•
•
支持 1kHz 至 10MHz 的宽传感器频率范围
器件信息(1)
功耗：
器件型号
LDC1312-Q1
LDC1314-Q1
封装
WSON (12)
WQFN (16)
封装尺寸（标称值）
4.00mm x 4.00mm
4.00mm x 4.00mm
–
–
35µA（低功耗休眠模式）
200nA（关断模式）
•
•
•
由 3.3V 电压供电运行
支持内部或外部基准时钟
抗直流磁场和磁铁干扰
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
测量精度与目标距离间的关系
简化电路原理图
3.3 V
2.5
2.25
2
3.3 V
LDC1312
MCU
VDD
CLKIN
VDD
SD
40 MHz
GPIO
GPIO
INTB
1.75
1.5
1.25
1
IN0A
IN0B
Target
Target
Sensor 0
Sensor 1
Core
GND
IN1A
IN1B
SDA
SCL
I2
C
I2
C
Peripheral
3.3 V
0.75
0.5
0.25
0
ADDR
GND
Copyright © 2016, Texas Instruments Incorporated
0
10%
20%
30%
40%
50%
60%
70%
Sensing Range (Target Distance / •SENSOR
)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSCZ6
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 20
8.5 Programming........................................................... 20
8.6 Register Maps......................................................... 22
Application and Implementation ........................ 39
9.1 Application Information............................................ 39
9.2 Typical Application ................................................. 42
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics .......................................... 6
7.6 Timing Characteristics ............................................. 7
7.7 Switching Characteristics - I2C................................. 7
7.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
9
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 46
11.1 Layout Guidelines ................................................. 46
11.2 Layout Example .................................................... 46
12 器件和文档支持 ..................................................... 51
12.1 器件支持................................................................ 51
12.2 文档支持................................................................ 51
12.3 社区资源................................................................ 51
12.4 相关链接................................................................ 51
12.5 商标....................................................................... 51
12.6 静电放电警告......................................................... 51
12.7 Glossary................................................................ 51
13 机械、封装和可订购信息....................................... 51
8
4 修订历史记录
日期
修订版本
注释
2016 年 4 月
*
最初发布。
2
版权 © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
5 说明 （续）
LDC1312-Q1 和 LDC1314-Q1 提供匹配良好的通道，可实现差分测量与比率测量。因此，设计人员能够利用一个
通道来补偿感测过程中的环境条件和老化条件，例如温度、湿度和机械漂移。得益于易用、低能耗、低系统成本等
特性，这些产品有助于设计人员大幅改进现有传感解决方案，从而为所有市场（尤其是消费品和工业应用）中的产
品引入全新的感测 功能。相比同类感测技术，电感感测具有更高的性能、可靠性和灵活性，而且系统成本与功耗更
低。
LDC1312-Q1 和 LDC1314-Q1 能够通过 I2C 接口轻松进行配置。双通道 LDC1312-Q1 采用 WSON-12 封装，四
通道 LDC1314-Q1 采用 WQFN-16 封装。
Copyright © 2016, Texas Instruments Incorporated
3
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
6 Pin Configuration and Functions
LDC1314-Q1 RGH
16 pin WQFN
Top View
LDC1312-Q1 DNT
12 pin WSON
Top View
SCL
SDA
IN1B
IN1A
IN0B
IN0A
GND
VDD
1
2
3
4
5
6
12
11
10
9
SCL
SDA
1
2
3
4
12 IN1B
CLKIN
ADDR
INTB
SD
DAP
11 IN1A
10 IN0B
DAP
CLKIN
ADDR
8
9
IN0A
7
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
1
NAME
SCL
I
I/O
I
I2C Clock input
I2C Data input/output
Master Clock input. Tie this pin to GND if internal oscillator is selected
2
SDA
3
CLKIN
ADDR
I2C Address selection pin: when ADDR=L, I2C address = 0x2A, when ADDR=H, I2C address =
0x2B.
4
I
5
INTB
SD
O
I
Configurable Interrupt output pin
Shutdown input
6
7
VDD
GND
IN0A
IN0B
IN1A
IN1B
IN2A
IN2B
IN3A
IN3B
DAP(2)
P
Power Supply
8
G
A
Ground
9
External LC sensor 0 connection
External LC sensor 0 connection
External LC sensor 1 connection
External LC sensor 1 connection
External LC sensor 2 connection (LDC1314 only)
External LC sensor 2 connection (LDC1314 only)
External LC sensor 3 connection (LDC1314 only)
External LC sensor 3 connection (LDC1314 only)
Connect to Ground
10
11
12
13
14
15
16
DAP
A
A
A
A
A
A
A
N/A
(1) I = Input, O = Output, P=Power, G=Ground, A=Analog
(2) There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP
can be left floating, for best performance the DAP should be connected to the same potential as the device's GND pin. Do not use the
DAP as the primary ground for the device. The device GND pin must always be connected to ground.
4
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
7 Specifications
7.1 Absolute Maximum Ratings
MIN
MAX
UNIT
V
VDD
Vi
Supply Voltage
5
Voltage on any pin
–0.3
–8
VDD+0.3
V
IA
Input current on any INx pin
Input current on any Digital pin
Junction Temperature
Storage temperature range
8
mA
mA
°C
ID
–5
5
Tj
–55
–65
150
150
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
MIN
2.7
NOM
MAX
3.6
UNIT
VDD
TA
Supply Voltage
V
Operating Temperature
–40
125
°C
7.4 Thermal Information
LDC1312
DNT (WSON)
12 PINS
36.7
LDC1314
THERMAL METRIC(1)
RGH (WQFN)
16 PINS
35.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
36.2
36.2
14
13.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
0.4
ψJB
14.2
13.4
RθJC(bot)
3.5
3.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2016, Texas Instruments Incorporated
5
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
(1)
7.5 Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
PARAMETER
TEST CONDITIONS(2)
MIN(3)
TYP(4)
MAX(3)
UNIT
POWER
VDD
Supply Voltage
TA = –40°C to +125°C
2.7
3.6
V
(6)
IDD
Supply Current (not including
sensor current)(5)
CLKIN = 10MHz
2.1
35
mA
µA
µA
IDDSL
ISD
Sleep Mode Supply Current(5)
60
1
Shutdown Mode Supply
Current(5)
0.2
SENSOR
ISENSORMAX
RP
Sensor Maximum Current drive
Sensor RP
HIGH_CURRENT_DRV = b0
DRIVE_CURRENT_CHx = 0xF800
1.5
mA
1
100
10
kΩ
IHDSENSORMAX
High current sensor drive mode: HIGH_CURRENT_DRV = b1
Sensor Maximum Current
6
mA
DRIVE_CURRENT_CH0 = 0xF800
Channel 0 only
RP_HD_MIN
fSENSOR
Minimum sensor RP
250
Ω
Sensor Resonance Frequency
TA = –40°C to +125°C
0.001
MHz
VSENSORMAX
Maximum oscillation amplitude
(peak)
1.8
V
NBITS
Number of bits
RESET_DEV.OUTPUT_GAIN=b00
12
bits
RCOUNT ≥ 0x0400
fCS
Maximum Channel Sample Rate single active channel continuous
conversion, SCL=400kHz
13.3
kSPS
pF
CIN
Sensor Pin input capacitance
4
MASTER CLOCK
fCLKIN
External Master Clock Input
Frequency (CLKIN)
TA = –40°C to +125°C
2
40
MHz
CLKINDUTY_MIN
CLKINDUTY_MAX
External Master Clock minimum
acceptable duty cycle (CLKIN)
40%
60%
External Master Clock maximum
acceptable duty cycle (CLKIN)
VCLKIN_LO
VCLKIN_HI
CLKIN low voltage threshold
CLKIN high voltage threshold
0.3ˣVDD
V
V
0.7ˣVD
D
fINTCLK
Internal Master Clock Frequency
range
35
43.4
–13
55
MHz
TCf_int_μ
Internal Master Clock
Temperature Coefficient mean
ppm/°C
(1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. Absolute Maximum Ratings indicate junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Register values are represented as either binary (b is the prefix to the digits), or hexadecimal (0x is the prefix to the digits). Decimal
values have no prefix.
(3) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through
correlations using statistical quality control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(5) I2C read/write communication and pullup resistors current through SCL, SDA not included.
(6) Sensor inductor: 2 layer, 32 turns/layer, 14mm diameter, PCB inductor with L=19.4 µH, RP=5.7 kΩ at 2MHz Sensor capacitor: 330 pF
1% COG/NP0 Target: Aluminum, 1.5mm thickness Channel = Channel 0 (continuous mode) CLKIN = 40 MHz, CHx_FIN_DIVIDER =
b0000, CHx_FREF_DIVIDER = b00 0000 0001 CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100 RP_OVERRIDE = b1,
AUTO_AMP_DIS = b1, DRIVE_CURRENT_CH0 = 0x9800
6
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
7.6 Timing Characteristics
MIN
NOM
MAX
UNIT
ms
tWAKEUP
Wake-up Time from SD high-low transition to I2C readback
2
tWD-TIMEOUT Sensor recovery time (after watchdog timeout)
5.2
ms
7.7 Switching Characteristics - I2C
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE LEVELS
VIH
VIL
Input High Voltage
Input Low Voltage
0.7ˣVDD
V
V
0.3ˣVDD
VOL
Output Low Voltage (3mA sink
current)
0.4
V
V
HYS
Hysteresis
0.1ˣVDD
I2C TIMING CHARACTERISTICS
fSCL
Clock Frequency
Clock Low Time
Clock High Time
10
1.3
0.6
400
kHz
μs
tLOW
tHIGH
tHD;STA
μs
Hold Time (repeated) START
condition
After this period, the first clock
pulse is generated
0.6
0.6
μs
μs
tSU;STA
Set-up time for a repeated START
condition
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Data hold time
0
100
0.6
μs
ns
μs
Data setup time
Set-up time for STOP condition
Bus free time between a STOP
and START condition
1.3
μs
tVD;DAT
tVD;ACK
tSP
Data valid time
0.9
0.9
μs
μs
Data valid acknowledge time
Pulse width of spikes that must be
suppressed by the input filter(1)
50
ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
SDA
t
BUF
t
t
f
LOW
t
HD;STA
t
r
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 1. I2C Timing
Copyright © 2016, Texas Instruments Incorporated
7
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
7.8 Typical Characteristics
Common test conditions (unless specified otherwise): Sensor inductor: 2 layer, 32 turns/layer, 14 mm diameter, PCB inductor
with L=19.4 µH, RP=5.7 kΩ at 2 MHz; Sensor capacitor: 330 pF 1% COG/NP0; Target: Aluminum, 1.5mm thickness; Channel
= Channel 0 (continuous mode); CLKIN = 40 MHz, CHx_FIN_DIVIDER = 0x1, CHx_FREF_DIVIDER = 0x001, CH0_RCOUNT
= 0xFFFF, SETTLECOUNT_CH0 = 0x0100, RP_OVERRIDE = 1, AUTO_AMP_DIS = 1, DRIVE_CURRENT_CH0 = 0x9800
3.25
3.225
3.2
3.25
VDD = 2.7 V
VDD = 3 V
VDD = 3.3 V
VDD = 3.6 V
3.2
3.175
3.15
3.125
3.1
3.15
3.1
-40°C
-20°C
0°C
50°C
85°C
100°C
125°C
3.075
3.05
25°C
3.05
-40
-20
0
20
40
60
80
100
120
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (°C)
VDD (V)
D003
D004
Includes 1.57 mA sensor coil current
–40°C to +125°C
Includes 1.57 mA sensor coil current
Figure 2. Active Mode IDD vs. Temperature
Figure 3. Active Mode IDD vs. VDD
60
55
50
45
40
35
30
25
65
60
55
50
45
40
35
30
25
VDD = 2.7 V
VDD = 3 V
VDD = 3.3 V
VDD = 3.6 V
-40°C
-20°C
0°C
25°C
50°C
85°C
100°C
125°C
-40
-20
0
20
40
60
80
100
120
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (°C)
VDD (V)
D005
D006
–40°C to +125°C
Figure 4. Sleep Mode IDD vs. Temperature
Figure 5. Sleep Mode IDD vs. VDD
1.4
1.2
1
1.6
1.4
1.2
1
VDD = 2.7 V
VDD = 3 V
VDD = 3.3 V
VDD = 3.6 V
-40°C
-20°C
0°C
25°C
50°C
85°C
100°C
125°C
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
120
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (°C)
VDD (V)
D007
D008
–40°C to +125°C
Figure 6. Shutdown Mode IDD vs. Temperature
Figure 7. Shutdown Mode IDD vs. VDD
8
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Typical Characteristics (continued)
Common test conditions (unless specified otherwise): Sensor inductor: 2 layer, 32 turns/layer, 14 mm diameter, PCB inductor
with L=19.4 µH, RP=5.7 kΩ at 2 MHz; Sensor capacitor: 330 pF 1% COG/NP0; Target: Aluminum, 1.5mm thickness; Channel
= Channel 0 (continuous mode); CLKIN = 40 MHz, CHx_FIN_DIVIDER = 0x1, CHx_FREF_DIVIDER = 0x001, CH0_RCOUNT
= 0xFFFF, SETTLECOUNT_CH0 = 0x0100, RP_OVERRIDE = 1, AUTO_AMP_DIS = 1, DRIVE_CURRENT_CH0 = 0x9800
43.4
43.39
43.38
43.37
43.36
43.35
43.34
43.33
43.32
43.41
VDD = 2.7 V
VDD = 3 V
VDD = 3.3 V
VDD = 3.6 V
-40°C
-20°C
0°C
25°C
50°C
85°C
100°C
125°C
43.4
43.39
43.38
43.37
43.36
43.35
43.34
43.33
43.32
-40
-20
0
20
40
60
80
100
120
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (°C)
VDD (V)
D009
D010
–40°C to +125°C
Data based on 1 unit
Figure 8. Internal Oscillator Frequency vs. Temperature
Figure 9. Internal Oscillator Frequency vs. VDD
Copyright © 2016, Texas Instruments Incorporated
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LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
8 Detailed Description
8.1 Overview
Conductive objects brought in contact with an AC electromagnetic (EM) field will induce field changes that can be
detected using a sensor such as an inductor. Conveniently, an inductor, along with a capacitor, can be used to
construct an L-C resonator, also known as an L-C tank, which can be used to produce an EM field. In the case of
an L-C tank, the effect of the field disturbance is an apparent shift in the inductance of the sensor, which can be
observed as a shift in the resonant frequency. Using this principle, the LDC1312/1314 is an inductance-to-digital
converter (LDC) that measures the oscillation frequency of an LC resonator. The device outputs a digital value
that is proportional to frequency. This frequency measurement can be converted to an equivalent inductance.
8.2 Functional Block Diagram
40 MHz
40 MHz
CLKIN
CLKIN
VDD
SD
VDD
SD
fREF
fREF
INTB
INTB
IN0A
IN0B
IN0A
IN0B
Resonant
Circuit
Driver
Resonant
Circuit
Driver
Core
I2C
Core
I2C
fIN
fIN
IN3A
IN3B
IN1A
IN1B
Resonant
Circuit
Driver
Resonant
Circuit
Driver
SDA
SCL
SDA
SCL
ADDR
ADDR
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Block Diagrams for the LDC1312 (Left) and LDC1314 (Right)
The LDC1312/LDC1314 is composed of front-end resonant circuit drivers, followed by a multiplexer that
sequences through the active channels, connecting them to the core that measures and digitizes the sensor
frequency (fSENSOR). The core uses a reference frequency (fREF) to measure the sensor frequency. fREF is derived
from either an internal reference clock (oscillator), or an externally supplied clock. The digitized output for each
channel is proportional to the ratio of fSENSOR/fREF. The I2C interface is used to support device configuration and
to transmit the digitized frequency values to a host processor. The LDC can be placed in shutdown mode, saving
current, using the SD pin. The INTB pin may be configured to notify the host of changes in system status.
8.3 Feature Description
8.3.1 Clocking Architecture
Figure 11 shows the clock dividers and multiplexers of the LDC.
10
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Feature Description (continued)
IN0A
fSENSOR0
Sensor 0
Sensor 1
÷ m
fIN0
IN0B
IN1A
CH0_FIN_DIVIDER (0x14)
fSENSOR1
÷ m
fIN1
IN1B
tfINt
CH1_FIN_DIVIDER (0x15)
IN2A(1)
Sensor 2(1)
Sensor 3(1)
÷ m
fIN2
(1)
(1)
(1)
fSENSOR2
IN2B(1)
IN3A(1)
CH2_FIN_DIVIDER (0x16)(1)
(1)
fSENSOR3
÷ m
fIN3
IN3B(1)
CONFIG (0x1A)
MUX_CONFIG
(0x1B)
CH3_FIN_DIVIDER (0x17)(1)
Core
Data
Output
÷ n
fREF0
CH0_FREF_DIVIDER (0x14)
REF_CLK_SRC
(0x1A)
÷ n
fREF1
CLKIN
tfCLKIN
t
tfREF
t
tfCLK
t
CH1_FREF_DIVIDER (0x15)
tfINT
t
(1)
÷ n
fREF2
Int. Osc.
CH2_FREF_DIVIDER (0x16)(1)
(1)
÷ n
fREF3
CONFIG (0x1A)
MUX_CONFIG
(0x1B)
CH3_FREF_DIVIDER (0x17)(1)
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Clocking Diagram
(1) LDC1314 only
In Figure 11, the key clocks are fIN, fREF, and fCLK. fCLK is selected from either the internal clock source or external
clock source (CLKIN). The frequency measurement reference clock, fREF, is derived from the fCLK source. TI
recommends that precision applications use an external master clock that offers the stability and accuracy
requirements needed for the application. The internal oscillator may be used in applications that require low cost
and do not require high precision. The fINx clock is derived from sensor frequency for a channel x, fSENSORx. fREFx
and fINx must meet the requirements listed in Table 1, depending on whether fCLK (master clock) is the internal or
external clock.
Table 1. Clock Configuration Requirements
SET
SET
VALID fREFx
RANGE (MHz)
VALID fINx
RANGE
SET
MODE(1)
CLKIN SOURCE
CHx_FIN_DIVIDE CHx_SETTLECO
CHx_RCOUNT to
R to
UNT to
Multi-Channel
Internal
External
fREFx < 55
fREFx < 40
fREFx < 35
(2)
< fREFx /4
≥ b0001
> 3
> 8
Single-Channel
Either external or
internal
(1) Channels 2 and 3 are only available for LDC1314
(2) If fSENSOR ≥ 8.75 MHz, then CHx_FIN_DIVIDER must be ≥ 2
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Table 2 shows the clock configuration registers for all channels.
Table 2. Clock Configuration Registers
CHANNEL(1)
CLOCK
REGISTER
FIELD [ BIT(S) ]
REF_CLK_SRC [9]
VALUE
fCLK = Master
Clock Source
CONFIG, addr
0x1A
b0 = internal oscillator is used as the
master clock
b1 = external clock source is used as the
master clock
All
fREF0
fREF1
fREF2
fREF3
fIN0
CLOCK_DIVIDER CH0_FREF_DIVIDER [9:0]
S_CH0, addr 0x14
fREF0 = fCLK / CH0_FREF_DIVIDER
fREF1 = fCLK / CH1_FREF_DIVIDER
fREF2 = fCLK / CH2_FREF_DIVIDER
fREF3 = fCLK / CH3_FREF_DIVIDER
fIN0 = fSENSOR0 / CH0_FIN_DIVIDER
fIN1 = fSENSOR1 / CH1_FIN_DIVIDER
fIN2 = fSENSOR2 / CH2_FIN_DIVIDER
fIN3 = fSENSOR3 / CH3_FIN_DIVIDER
0
1
2
3
0
1
2
3
CLOCK_DIVIDER CH1_FREF_DIVIDER [9:0]
S_CH1, addr 0x15
CLOCK_DIVIDER CH2_FREF_DIVIDER [9:0]
S_CH2, addr 0x16
CLOCK_DIVIDER CH3_FREF_DIVIDER [9:0]
S_CH3, addr 0x17
CLOCK_DIVIDER CH0_FIN_DIVIDER [15:12]
S_CH0, addr 0x14
fIN1
CLOCK_DIVIDER CH1_FIN_DIVIDER [15:12]
S_CH1, addr 0x15
fIN2
CLOCK_DIVIDER CH2_FIN_DIVIDER [15:12]
S_CH2, addr 0x16
fIN3
CLOCK_DIVIDER CH3_FIN_DIVIDER [15:12]
S_CH3, addr 0x17
(1) Channels 2 and 3 are only available for LDC1314
8.3.2 Multi-Channel and Single Channel Operation
The multi-channel package of the LDC enables the user to save board space and support flexible system design.
For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant
frequency of the sensor. Using a 2nd sensor as a reference provides the capability to cancel out a temperature
shift. When operated in multi-channel mode, the LDC sequentially samples the active channels. In single channel
mode, the LDC samples a single channel, which is selectable. Table 3 shows the registers and values that are
used to configure either multi-channel or single channel modes.
Table 3. Single and Multi-Channel Configuration Registers
MODE
REGISTER
FIELD [ BIT(S) ]
VALUE(1)
00 = chan 0
01 = chan 1
10 = chan 2
11 = chan 3
CONFIG, addr 0x1A
ACTIVE_CHAN [15:14]
Single channel
0 = continuous conversion on a
single channel (default)
MUX_CONFIG addr 0x1B
MUX_CONFIG addr 0x1B
AUTOSCAN_EN [15]
AUTOSCAN_EN [15]
1 = continuous conversion on
multiple channels
00 = Ch0, Ch 1
Multi-channel
MUX_CONFIG addr 0x1B
RR_SEQUENCE [14:13]
01 = Ch0, Ch 1, Ch 2
10 = Ch0, CH1, Ch2, Ch3
(1) Channels 2 and 3 are only available for LDC1314
The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the
reference frequency. The data outputs represent the 12 MSBs of a 16-bit result:
DATAx/ 212 = fSENSORx/fREFx
(1)
The sensor frequency can be calculated from:
DATAx * ƒREFx
ƒsensorx
=
212
(2)
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Table 4 shows the registers that contain the fixed point sample values for each channel.
Table 4. LDC1314/1312 Sample Data Registers
CHANNEL(1)
REGISTER
FIELD NAME [BITS(S) ]
VALUE
0
DATA_MSB_CH0, addr 0x00
DATA0 [11:0]
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
1
2
3
DATA_MSB_CH1, addr 0x02
DATA_MSB_CH2, addr 0x04
DATA_MSB_CH3, addr 0x06
DATA1 [11:0]
DATA2 [11:0]
DATA3 [11:0]
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
(1) Channels 2 and 3 available for LDC1314 only.
When the LDC sequences through the channels in multi-channel mode, the dwell time interval for each channel
is the sum of 3 parts: sensor activation time + conversion time + channel switch delay.
The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown
in Figure 12. The settling wait time is programmable and should be set to a value that is long enough to allow
stable oscillation. The settling wait time for channel x is given by:
tSx = (CHX_SETTLECOUNTˣ16)/fREFx
(3)
Table 5 shows the registers and values for configuring the settling time for each channel.
Channel 0
Sensor
Activation
Channel 0
Conversion
Channel
switch delay Sensor
Activation
Channel 1
Channel 1
Conversion
Channel
switch delay Sensor
Activation
Channel 0
Channel 0
Channel 1
Figure 12. Multi-channel Mode Sequencing
Active Channel
Sensor Signal
Sensor
Activation
Conversion
Conversion
Conversion
Amplitude
Correction
Amplitude
Correction
Amplitude
Correction
Figure 13. Single-channel Mode Sequencing
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Table 5. Settling Time Register Configuration
CHANNEL(1)
REGISTER
SETTLECOUNT_CH0, addr 0x10
FIELD
CONVERSION TIME(2)
0
1
2
3
CH0_SETTLECOUNT (15:0)
CH1_SETTLECOUNT (15:0)
CH2_SETTLECOUNT (15:0)
CH3_SETTLECOUNT (15:0)
(CH0_SETTLECOUNT*16)/fREF0
(CH1_SETTLECOUNT*16)/fREF1
(CH2_SETTLECOUNT*16)/fREF2
(CH3_SETTLECOUNT*16)/fREF3
SETTLECOUNT_CH1, addr 0x11
SETTLECOUNT_CH2, addr 0x12
SETTLECOUNT_CH3, addr 0x13
(1) Channels 2 and 3 are available only in the LDC1314.
(2) fREFx is the reference frequency configured for the channel.
The SETTLECOUNT for any channel x must satisfy:
CHx_SETTLECOUNT ≥ QSENSORx × fREFx / (16 × fSENSORx
)
where
•
•
•
fSENSORx = Frequency of the Sensor on Channel x
fREFx = Reference frequency for Channel x
QSENSORx = Quality factor of the sensor on Channel x, where Q can be calculated by:
(4)
(5)
C
L
Q = RP
Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08,
program the register to 7 or higher).
L, RP and C values can be obtained by using Texas Instrument’s WEBENCH® for the coil design.
The conversion time represents the number of reference clock cycles used to measure the sensor frequency. It is
set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:
tCx = (CHx_RCOUNT ˣ 16 + 4) /fREFx
(6)
The reference count value must be chosen to support the required number of effective bits (ENOB). For details,
refer to the application note Optimizing L Measurement Resolution for the LDC161x and LDC1101.
Table 6. Conversion Time Configuration Registers, Channels 0 - 3(1)
CHANNEL
REGISTER
RCOUNT_CH0, addr 0x08
RCOUNT_CH1, addr 0x09
RCOUNT_CH2, addr 0x0A
RCOUNT_CH3, addr 0x0B
FIELD [ BIT(S) ]
CH0_RCOUNT (15:0)
CONVERSION TIME
(CH0_RCOUNT*16)/fREF0
0
1
2
3
CH1_RCOUNT (15:0)
CH2_RCOUNT (15:0)
CH3_RCOUNT (15:0)
(CH1_RCOUNT*16)/fREF1
(CH2_RCOUNT*16)/fREF2
(CH3_RCOUNT*16)/fREF3
(1) Channels 2 and 3 are available only for LDC1314.
The typical channel switch delay time between the end of conversion and the beginning of sensor activation of
the subsequent channel is:
Channel Switch Delay = 692 ns + 5 / fref
(7)
The deterministic conversion time of the LDC allows data polling at a fixed interval. A data ready flag (DRDY) is
also available for interrupt driven system designs (see the STATUS register description in Register Maps).
An offset value may be subtracted from each DATA value to compensate for a frequency offset or maximize the
dynamic range of the sample data. The offset values should be < fSENSORx_MIN / fREFx. Otherwise, the offset might
be so large that it masks the LSBs which are changing.
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Table 7. Frequency Offset Registers
CHANNEL
REGISTER
FIELD [ BIT(S) ]
VALUE
(1)
0
1
2
3
OFFSET_CH0, addr 0x0C
OFFSET_CH1, addr 0x0D
OFFSET_CH2, addr 0x0E
OFFSET_CH3, addr 0x0F
CH0_OFFSET [ 15:0 ]
CH1_OFFSET [ 15:0 ]
CH2_OFFSET [ 15:0 ]
CH3_OFFSET [ 15:0 ]
fOFFSET0 = CH0_OFFSET * (fREF0/216
fOFFSET1 = CH1_OFFSET * (fREF1/216
fOFFSET2 = CH2_OFFSET * (fREF2/216
fOFFSET3 = CH3_OFFSET * (fREF3/216
)
)
)
)
(1) Channels 2 and 3 are only available for LDC1314
Internally, the LDC measures with 16bits of resolution, while the conversion output word width is only 12bits. For
systems in which the sensor signal variation is less than 25% of the full scale range, the LDC can report
conversion results with higher resolution by setting the output gain. The output gain is applied to all device
channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels,
allowing access to the 4LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is
applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel
will be lost when gain is applied.
Table 8. Output Gain Register
CHANNEL
EFFECTIVE
RESOLUTION (BITS)
REGISTER
FIELD [ BIT(S) ]
VALUES
OUTPUT RANGE
(1)
All
RESET_DEV, addr
0x1C
OUTPUT_GAIN [ 10:9 ] 00 (default): Gain =1 (0
bits shift)
12
100% full scale
01: Gain = 4 (2 bits left
shift)
14
15
16
25% full scale
12.5% full scale
6.25% full scale
10: Gain = 8 (3 bits left
shift)
11 : Gain = 16 (4 bits left
shift)
(1) Channels 2 and 3 are available for LDC1314 only.
Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN=0x0, the reported output code is
0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The
original 4 MSBs (0x0) are no longer accessible. Figure 14 shows the segments of the 16-bit sample that is
reported for each possible gain setting.
MSB
LSB
Conversion result
Output_gain = 0x3
Output_gain = 0x2
Output_gain = 0x1
15
12
11
11
8
7
4
3
0
0
11
0
11
0
Output_gain = 0x0
(default)
11
0
11
0
Data available in DATA_MSB_CHx.DATA_CHx [11:0]
Figure 14. Conversion Data Output Gain
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The sensor frequency can be determined by:
DATAx
« 2(12+OUTPUT_GAIN)
CHx_OFFSET
216
≈
∆
’
ƒSENSORx = CHx_FIN_DIVIDER* ƒREFx
+
÷
◊
where
•
•
•
DATAx = Conversion result from the DATA_CHx register
CHx_OFFSET = Offset value set in the OFFSET_CHx register
OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register
(8)
8.3.3 Current Drive Control Registers
The registers listed in Table 9 are used to control the sensor drive current. The recommendations listed in the
last column of Table 9 should be followed.
Auto-calibration mode is used to determine the optimal sensor drive current for a fixed sensor design. This mode
should only be used during system prototyping.
The auto-amplitude correction attempts to maintain the sensor oscillation amplitude between 1.2V and 1.8V by
adjusting the sensor drive current between conversions. When auto-amplitude correction is enabled, the output
data may show non-monotonic behavior due to an adjustment in drive current. Auto-amplitude correction is only
recommended for low-precision applications.
A high sensor current drive mode can be enabled to drive sensor coils with > 1.5mA on channel 0, only in single
channel mode. This feature can be used when the sensor RP is lower than 1kΩ. Set the HIGH_CURRENT_DRV
register bit to b1 to enable this mode.
Table 9. Current Drive Control Registers
CHANNEL(1)
REGISTER
CONFIG, addr 0x1A
FIELD [ BIT(S) ]
VALUE
SENSOR_ACTIVATE_SEL [11]
Sets current drive for sensor activation.
Recommended value is b0 (Full Current
mode).
All
RP_OVERRIDE_EN [12]
AUTO_AMP_DIS [10]
Set to b1 for normal operation (RP over
ride enabled)
Disables Automatic amplitude correction.
Set to b1 for normal operation (disabled)
CONFIG, addr 0x1A
HIGH_CURRENT_DRV [6]
b0 = normal current drive (1.5 mA)
b1 = Increased current drive (> 1.5 mA)
for Ch 0 in single channel mode only.
Cannot be used in multi-channel mode.
0
0
DRIVE_CURRENT_CH0, addr 0x1E CH0_IDRIVE [15:11]
Drive current used during the settling and
conversion time for Ch. 0 (auto-amplitude
correction must be disabled and RP over
ride=1 )
CH0_INIT_IDRIVE [10:6]
Initial drive current stored during auto-
calibration. Not used for normal operation.
DRIVE_CURRENT_CH1, addr 0x1F CH1_IDRIVE [15:11]
Drive current used during the settling and
conversion time for Ch. 1 (auto-amplitude
correction must be disabled and RP over
ride=1 )
1
2
CH1_INIT_IDRIVE [10:6]
Initial drive current stored during auto-
calibration. Not used for normal operation.
DRIVE_CURRENT_CH2, addr 0x20 CH2_IDRIVE [15:11]
Drive current used during the settling and
conversion time for Ch. 2 (auto-amplitude
correction must be disabled and RP over
ride=1 )
CH2_INIT_IDRIVE [10:6]
Initial drive current stored during auto-
calibration. Not used for normal operation.
(1) Channels 2 and 3 are available for LDC1314 only.
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CHANNEL(1)
3
ZHCSF01 –APRIL 2016
Table 9. Current Drive Control Registers (continued)
REGISTER
FIELD [ BIT(S) ]
VALUE
DRIVE_CURRENT_CH3, addr 0x21 CH3_IDRIVE [15:11]
Drive current used during the settling and
conversion time for Ch. 3 (auto-amplitude
correction must be disabled and RP over
ride=1 )
CH3_INIT_IDRIVE [10:6]
Initial drive current stored during auto-
calibration. Not used for normal operation.
If the RP value of the sensor attached to channel x is known, Table 10 can be used to select the 5-bit value to be
programmed into the CHx_IDRIVE field for the channel. If the measured RP (at maximum spacing between the
sensor and the target) falls between two of the table values, use the current drive value associated with the lower
RP from Table 10. All channels that use an identical sensor/target configuration should use the same IDRIVE
value.
Table 10. CHx_IDRIVE Values for Maximum Measured RP.
MEASURED RP (kΩ)
CHx_IDRIVE REGISTER FIELD VALUE,
BINARY (BITS [15:11] )
NOMINAL CURRENT (μA)
90.0
77.6
66.9
57.6
49.7
42.8
36.9
31.8
27.4
23.3
20.4
17.6
15.1
13.0
11.2
9.7
b00000
b00001
b00010
b00011
b00100
b00101
b00110
b00111
b01000
b01001
b01010
b01011
b01100
b01101
b01110
b01111
b10000
b10001
b10010
b10011
b10100
b10101
b10110
b10111
b11000
b11001
b11010
b11011
b11100
b11101
b11110
b11111
16
18
20
23
28
32
40
46
52
59
72
82
95
110
127
146
169
195
212
244
297
342
424
489
551
635
763
880
1017
1173
1355
1563
8.4
7.2
6.2
5.4
4.6
4.0
3.4
3.0
2.5
2.2
1.9
1.6
1.4
1.2
1.0
0.9
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If the RP is not known, the following steps for auto-calibration can be used to configure the needed drive current,
either during system prototyping, or during normal startup if feasible:
1. Set target at the maximum planned operating distance from the sensor.
2. Place the device into SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b0.
3. Program the desired values of SETTLECOUNT and RCOUNT values for the channel.
4. Enable auto-calibration by setting RP_OVERDRIVE_EN to b0.
5. Take the device out of SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b1.
6. Allow the device to perform at least one measurement, with the target stable (fixed) at the maximum
operating range.
7. Read the channel current drive value from the appropriate DRIVE_CURRENT_CHx register (addresses
0x1e, 0x1f, 0x20, or 0x21), in the CHx_INIT_DRIVE field (bits 10:6). Save this value.
8. During startup for normal operating mode, write the value saved from the CHx_INIT_DRIVE bit field into the
Chx_IDRIVE bit field (bits 15:11).
9. During normal operating mode, the RP_OVERRIDE_EN must set to b1 to force the fixed current drive.
If the current drive results in the oscillation amplitude greater than 1.8V, the internal ESD clamping circuit will
become active. This may cause the sensor frequency to shift so that the output values no longer represent a
valid system state. If the current drive is set at a lower value, the SNR performance of the system will decrease,
and at near zero target range, oscillations may completely stop, and the output sample values will be all zeroes.
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8.3.4 Device Status Registers
The registers listed in Table 11 may be used to read device status.
Table 11. Status Registers
CHANNEL(1)
REGISTER
FIELDS [ BIT(S) ]
VALUES
Refer to Register Maps section
for a description of the individual
status bits.
12 fields are available that
contain various status bits [ 15:0 ]
All
STATUS, addr 0x18
12 fields are available that are
Refer to Register Maps section
All
ERROR_CONFIG, addr 0x19
used to configure error reporting [ for a description of the individual
15:0 ] error configuration bits.
(1) Channels 2 and 3 are available for LDC1314 only.
See the STATUS and ERROR_CONFIG register description in the Register Map section. These registers can be
configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:
1. The error or status register must be unmasked by enabling the appropriate register bit in the
ERROR_CONFIG register
2. The INTB function must be enabled by setting CONFIG.INTB_DIS to 0
When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the
DATA_CHx register is read. Reading also de-asserts INTB.
Interrupts are cleared by one of the following events:
1. Entering Sleep Mode
2. Power-on reset (POR)
3. Device enters Shutdown Mode (SD is asserted)
4. S/W reset
5. I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS
along with the ERR_CHAN field and de-assert INTB
Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.
8.3.5 Input Deglitch Filter
The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the
conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input
deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 12. For optimal
performance, TI recommends to select the lowest setting that exceeds the sensor oscillation frequency. For
example, if the maximum sensor frequency is 2.0 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).
Table 12. Input deglitch filter register
CHANNEL(1)
ALL
MUX_CONFIG.DEGLITCH REGISTER VALUE
DEGLITCH FREQEUNCY
001
100
101
011
1 MHz
3.3 MHz
10 MHz
33 MHz
ALL
ALL
ALL
(1) Channels 2 and 3 are available for LDC1314 only.
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8.4 Device Functional Modes
8.4.1 Startup Mode
When the LDC powers up, it enters into Sleep Mode and will wait for configuration. Once the device is
configured, exit Sleep Mode by setting CONFIG.SLEEP_MODE_EN to b0.
TI recommends to configure the LDC while in Sleep Mode. If a setting on the LDC needs to be changed, return
the device to Sleep Mode, change the appropriate register, and then exit Sleep Mode.
8.4.2 Normal (Conversion) Mode
When operating in the normal (conversion) mode, the LDC is periodically sampling the frequency of the sensor(s)
and generating sample outputs for the active channel(s).
8.4.3 Sleep Mode
Sleep Mode is entered by setting the CONFIG.SLEEP_MODE_EN register field to 1. While in this mode, the
device configuration is maintained. To exit Sleep Mode, set the CONFIG.SLEEP_MODE_EN register field to 0.
After setting CONFIG.SLEEP_MODE_EN to b0, sensor activation for the first conversion will begin after 16,384
fINT clock cycles. While in Sleep Mode the I2C interface is functional so that register reads and writes can be
performed. While in Sleep Mode, no conversions are performed. In addition, entering Sleep Mode will clear
conversion results, any error condition and de-assert the INTB pin.
8.4.4 Shutdown Mode
When the SD pin is set to high, the LDC will enter Shutdown Mode. Shutdown Mode is the lowest power state.
To exit Shutdown Mode, set the SD pin to low. Entering Shutdown Mode will return all registers to their default
state.
While in Shutdown Mode, no conversions are performed. In addition, entering Shutdown Mode will clear any
error condition and de-assert the INTB pin. While the device is in Shutdown Mode, is not possible to read to or
write from the device via the I2C interface.
8.4.4.1 Reset
The LDC can be reset by writing to RESET_DEV.RESET_DEV. Any active conversion will stop and all register
values will return to their default value. This register bit will always return 0b when read.
8.5 Programming
The LDC device uses an I2C interface to access control and data registers.
8.5.1 I2C Interface Specifications
The LDC uses an extended start sequence with I2C for register access. The maximum speed of the I2C interface
is 400kbit/s. This sequence follows the standard I2C 7bit slave address followed by an 8bit pointer register byte
to set the register address. When the ADDR pin is set low, the LDC I2C address is 0x2A; when the ADDR pin is
set high, the LDC I2C address is 0x2B. The ADDR pin must not change state after the LDC exits Shutdown
Mode.
20
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Programming (continued)
1
9
1
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
R7 R6 R5 R4 R3 R2 R1 R0
Start by
Master
Ack by
Slave
Ack by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register
Address
1
9
1
9
SCL
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SDA
Ack by
Slave
Ack by Stop by
Slave Master
Frame 3
Data MSB from
Master
Frame 4
Data LSB from
Master
Figure 15. I2C Write Register Sequence
1
9
1
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
R7 R6 R5 R4 R3 R2 R1 R0
Start by
Master
Ack by
Slave
Ack by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register
Address
1
9
1
9
1
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
Ack by
Slave
Ack by
Master
Nack by Stop by
Master Master
Frame 3
Serial Bus Address Byte
from Master
Frame 4
Data MSB from
Slave
Frame 5
Data LSB from
Slave
Figure 16. I2C Read Register Sequence
Copyright © 2016, Texas Instruments Incorporated
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8.6 Register Maps
8.6.1 Register List
Fields indicated with Reserved must be written only with indicated values, otherwise improper device operation
may occur. The R/W column indicates the Read-Write status of the corresponding field. A ‘R/W’ entry indicates
read and write capability, a ‘R’ indicates read-only, and a ‘W’ indicates write-only.
Figure 17. Register List
ADDRESS
0x00
0x02
0x04
0x06
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
NAME
DATA_CH0
DEFAULT VALUE
0x0000
DESCRIPTION
Channel 0 Conversion Result and Error Status
Channel 1 Conversion Result and Error Status
Channel 2 Conversion Result and Error Status (LDC1314 only)
Channel 3 Conversion Result and Error Status (LDC1314 only)
Reference Count setting for Channel 0
DATA_CH1
0x0000
0x0000
0x0000
0x0080
0x0080
0x0080
0x0080
0x0000
0x0000
0x0000
0x0000
DATA_CH2
DATA_CH3
RCOUNT_CH0
RCOUNT_CH1
RCOUNT_CH2
RCOUNT_CH3
OFFSET_CH0
OFFSET_CH1
OFFSET_CH2
OFFSET_CH3
Reference Count setting for Channel 1
Reference Count setting for Channel 2. (LDC1314 only)
Reference Count setting for Channel 3.(LDC1314 only)
Offset value for Channel 0
Offset value for Channel 1
Offset value for Channel 2 (LDC1314 only)
Offset value for Channel 3 (LDC1314 only)
Channel 0 Settling Reference Count
SETTLECOUNT_CH0 0x0000
SETTLECOUNT_CH1 0x0000
SETTLECOUNT_CH2 0x0000
SETTLECOUNT_CH3 0x0000
Channel 1 Settling Reference Count
Channel 2 Settling Reference Count (LDC1314 only)
Channel 3 Settling Reference Count (LDC1314 only)
Reference and Sensor Divider settings for Channel 0
CLOCK_DIVIDERS_C 0x0000
H0
0x15
0x16
0x17
CLOCK_DIVIDERS_C 0x0000
H1
Reference and Sensor Divider settings for Channel 1
CLOCK_DIVIDERS_C 0x0000
H2
Reference and Sensor Divider settings for Channel 2 (LDC1314 only)
Reference and Sensor Divider settings for Channel 3 (LDC1314 only)
CLOCK_DIVIDERS_C 0x0000
H3
0x18
0x19
0x1A
0x1B
0x1C
0x1E
STATUS
0x0000
0x0000
0x2801
0x020F
0x0000
Device Status Report
ERROR_CONFIG
CONFIG
Error Reporting Configuration
Conversion Configuration
MUX_CONFIG
RESET_DEV
Channel Multiplexing Configuration
Reset Device
DRIVE_CURRENT_CH 0x0000
0
Channel 0 sensor current drive configuration
0x1F
0x20
0x21
DRIVE_CURRENT_CH 0x0000
1
Channel 1 sensor current drive configuration
DRIVE_CURRENT_CH 0x0000
2
Channel 2 sensor current drive configuration (LDC1314 only)
Channel 3 sensor current drive configuration (LDC1314 only)
DRIVE_CURRENT_CH 0x0000
3
0x7E
0x7F
MANUFACTURER_ID 0x5449
Manufacturer ID
Device ID
DEVICE_ID
0x3054
22
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ZHCSF01 –APRIL 2016
8.6.2 Address 0x00, DATA_CH0
Figure 18. Address 0x00, DATA_CH0
15
14
13
12
11
10
2
9
1
8
0
CH0_ERR_UR CH0_ERR_OR CH0_ERR_WD CH0_ERR_AE
DATA0[11:0]
7
6
5
4
3
DATA0[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Address 0x00, DATA_CH0 Field Descriptions
Bit
Field
Type
Reset
Description
15
CH0_ERR_UR
R
0
Channel 0 Conversion Under-range Error Flag. Cleared by
reading the bit.
14
13
CH0_ERR_OR
CH0_ERR_WD
CH0_ERR_AE
DATA0[11:0]
R
R
R
R
0
0
0
Channel 0 Conversion Over-range Error Flag. Cleared by
reading the bit.
Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
12
Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
11:0
0000 0000 Channel 0 Conversion Result
0000
8.6.3 Address 0x02, DATA_CH1
Figure 19. Address 0x02, DATA_CH1
15
14
13
12
11
10
2
9
1
8
0
CH1_ERR_UR CH1_ERR_OR CH1_ERR_WD CH1_ERR_AE
DATA1[11:0]
7
6
5
4
3
DATA1[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Address 0x02, DATA_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
15
CH1_ERR_UR
R
0
Channel 1 Conversion Under-range Error Flag. Cleared by
reading the bit.
14
13
CH1_ERR_OR
CH1_ERR_WD
CH1_ERR_AE
DATA1[11:0]
R
R
R
R
0
0
0
Channel 1 Conversion Over-range Error Flag. Cleared by
reading the bit.
Channel 1 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
12
Channel 1 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
11:0
0000 0000 Channel 1 Conversion Result
0000
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8.6.4 Address 0x04, DATA_CH2 (LDC1314 only)
Figure 20. Address 0x04, DATA_CH2
15
14
13
12
11
10
2
9
1
8
0
CH2_ERR_UR CH2_ERR_OR CH2_ERR_WD CH2_ERR_AE
DATA2[11:0]
7
6
5
4
3
DATA2[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Address 0x04, DATA_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15
CH2_ERR_UR
R
0
Channel 2 Conversion Under-range Error Flag. Cleared by
reading the bit.
14
13
CH2_ERR_OR
CH2_ERR_WD
CH2_ERR_AE
DATA2[11:0]
R
R
R
R
0
0
0
Channel 2 Conversion Over-range Error Flag. Cleared by
reading the bit.
Channel 2 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
12
Channel 2 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
11:0
0000 0000 Channel 2 Conversion Result
0000
8.6.5 Address 0x06, DATA_CH3 (LDC1314 only)
Figure 21. Address 0x06, DATA_CH3
15
14
13
12
11
10
2
9
1
8
0
CH3_ERR_UR CH3_ERR_OR CH3_ERR_WD CH3_ERR_AE
DATA3[11:0]
7
6
5
4
3
DATA3[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Address 0x06, DATA_CH3 Field Descriptions
Bit
Field
Type
Reset
Description
15
CH3_ERR_UR
R
0
Channel 3 Conversion Under-range Error Flag. Cleared by
reading the bit.
14
13
CH3_ERR_OR
CH3_ERR_WD
CH3_ERR_AE
DATA3[11:0]
R
R
R
R
0
0
0
Channel 3 Conversion Over-range Error Flag. Cleared by
reading the bit.
Channel 3 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
12
Channel 3 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
11:0
0000 0000 Channel 3 Conversion Result
0000
24
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ZHCSF01 –APRIL 2016
8.6.6 Address 0x08, RCOUNT_CH0
Figure 22. Address 0x08, RCOUNT_CH0
15
7
14
6
13
12
11
10
9
1
8
0
CH0_RCOUNT
CH0_RCOUNT
5
4
3
2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Address 0x08, RCOUNT_CH0 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH0_RCOUNT
R/W
0000 0000
1000 0000
Channel 0 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC0) =
(CH0_RCOUNTˣ16)/fREF0
8.6.7 Address 0x09, RCOUNT_CH1
Figure 23. Address 0x09, RCOUNT_CH1
15
14
13
12
11
10
9
1
8
0
CH1_RCOUNT
7
6
5
4
3
2
CH1_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Address 0x09, RCOUNT_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH1_RCOUNT
R/W
0000 0000
1000 0000
Channel 1 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC1)=
(CH1_RCOUNTˣ16)/fREF1
8.6.8 Address 0x0A, RCOUNT_CH2 (LDC1314 only)
Figure 24. Address 0x0A, RCOUNT_CH2
15
14
13
12
11
10
9
1
8
0
CH2_RCOUNT
7
6
5
4
3
2
CH2_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Address 0x0A, RCOUNT_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH2_RCOUNT
R/W
0000 0000
1000 0000
Channel 2 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC2)=
(CH2_RCOUNTˣ16)/fREF2
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8.6.9 Address 0x0B, RCOUNT_CH3 (LDC1314 only)
Figure 25. Address 0x0B, RCOUNT_CH3
15
7
14
6
13
12
11
10
9
1
8
0
CH3_RCOUNT
CH3_RCOUNT
5
4
3
2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Address 0x0B, RCOUNT_CH3 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH3_RCOUNT
R/W
0000 0000
1000 0000
Channel 3 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC3)=
(CH3_RCOUNTˣ16)/fREF3
8.6.10 Address 0x0C, OFFSET_CH0
Figure 26. Address 0x0C, CH0_OFFSET
15
14
13
12
11
10
9
1
8
0
CH0_OFFSET
7
6
5
4
3
2
CH0_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. CH0_OFFSET Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH0_OFFSET
R/W
0000 0000
0000 0000
Channel 0 Conversion Offset. fOFFSET_0
(CH0_OFFSET/216)*fREF0
=
8.6.11 Address 0x0D, OFFSET_CH1
Figure 27. Address 0x0D, OFFSET_CH1
15
14
13
12
11
10
9
1
8
0
CH1_OFFSET
7
6
5
4
3
2
CH1_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Address 0x0D, OFFSET_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH1_OFFSET
R/W
0000 0000
0000 0000
Channel 1 Conversion Offset. fOFFSET_1
(CH1_OFFSET/216)*fREF1
=
26
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ZHCSF01 –APRIL 2016
8.6.12 Address 0x0E, OFFSET_CH2 (LDC1314 only)
Figure 28. Address 0x0E, OFFSET_CH2
15
7
14
6
13
12
11
10
9
1
8
0
CH2_OFFSET
CH2_OFFSET
5
4
3
2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Address 0x0E, OFFSET_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH2_OFFSET
R/W
0000 0000
0000 0000
Channel 2 Conversion Offset. fOFFSET_2
(CH2_OFFSET/216)*fREF2
=
8.6.13 Address 0x0F, OFFSET_CH3 (LDC1314 only)
Figure 29. Address 0x0F, OFFSET_CH3
15
14
13
12
11
10
9
1
8
0
CH3_OFFSET
7
6
5
4
3
2
CH3_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Address 0x0F, OFFSET_CH3 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH3_OFFSET
R/W
0000 0000 Channel 3 Conversion Offset. fOFFSET_3
0000 0000 (CH3_OFFSET/216)*fREF3
=
8.6.14 Address 0x10, SETTLECOUNT_CH0
Figure 30. Address 0x10, SETTLECOUNT_CH0
15
14
13
12
11
10
9
1
8
0
CH0_SETTLECOUNT
7
6
5
4
3
2
CH0_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Address 0x11, SETTLECOUNT_CH0 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH0_SETTLECOUNT
R/W
0000 0000 Channel 0 Conversion Settling
0000 0000 The LDC will use this settling time to allow the LC sensor to
stabilize before initiation of a conversion on Channel 0.
If the amplitude has not settled prior to the conversion start, an
Amplitude error will be generated if reporting of this type of error
is enabled.
0x0000: Settle Time (tS0)= 32 ÷ fREF0
0x0001: Settle Time (tS0)= 32 ÷ fREF0
0x0002- 0xFFFF: Settle Time (tS0)= (CH0_SETTLECOUNTˣ16)
÷ fREF0
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8.6.15 Address 0x11, SETTLECOUNT_CH1
Figure 31. Address 0x11, SETTLECOUNT_CH1
15
7
14
6
13
12
11
10
9
1
8
0
CH1_SETTLECOUNT
5
4
3
2
CH1_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. Address 0x12, SETTLECOUNT_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH1_SETTLECOUNT
R/W
0000 0000 Channel 1 Conversion Settling
0000 0000 The LDC will use this settling time to allow the LC sensor to
stabilize before initiation of a conversion on a Channel 1.
If the amplitude has not settled prior to the conversion start, an
Amplitude error will be generated if reporting of this type of error
is enabled.
0x0000: Settle Time (tS1)= 32 ÷ fREF1
0x0001: Settle Time (tS1)= 32 ÷ fREF1
0x0002- 0xFFFF: Settle Time (tS1)= (CH1_SETTLECOUNTˣ16)
÷ fREF1
8.6.16 Address 0x12, SETTLECOUNT_CH2 (LDC1314 only)
Figure 32. Address 0x12, SETTLECOUNT_CH2
15
14
13
12
11
10
9
1
8
0
CH2_SETTLECOUNT
7
6
5
4
3
2
CH2_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. Address 0x12, SETTLECOUNT_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH2_SETTLECOUNT
R/W
0000 0000 Channel 2 Conversion Settling
0000 0000 The LDC will use this settling time to allow the LC sensor to
stabilize before initiation of a conversion on Channel 2.
If the amplitude has not settled prior to the conversion start, an
Amplitude error will be generated if reporting of this type of error
is enabled.
0x0000: Settle Time (tS2)= 32 ÷ fREF2
0x0001: Settle Time (tS2)= 32 ÷ fREF2
0x0002- 0xFFFF: Settle Time (tS2)= (CH2_SETTLECOUNTˣ16)
÷ fREF2
28
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ZHCSF01 –APRIL 2016
8.6.17 Address 0x13, SETTLECOUNT_CH3 (LDC1314 only)
Figure 33. Address 0x13, SETTLECOUNT_CH3
15
7
14
6
13
12
11
10
9
1
8
0
CH3_SETTLECOUNT
5
4
3
2
CH3_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. Address 0x13, SETTLECOUNT_CH3 Field Descriptions
Bit
Field
Type
Reset
Description
15:0
CH3_SETTLECOUNT
R/W
0000 0000 Channel 3 Conversion Settling
0000 0000 The LDC will use this settling time to allow the LC sensor to
stabilize before initiation of a conversion on Channel 3.
If the amplitude has not settled prior to the conversion start, an
Amplitude error will be generated if reporting of this type of error
is enabled
0x0000: Settle Time (tS3)= 32 ÷ fREF3
0x0001: Settle Time (tS3)= 32 ÷ fREF3
0x0002- 0xFFFF: Settle Time (tS3)= (CH3_SETTLECOUNTˣ16)
÷ fREF3
8.6.18 Address 0x14, CLOCK_DIVIDERS_CH0
Figure 34. Address 0x14, CLOCK_DIVIDERS_CH0
15
14
13
12
11
10
9
8
CH0_FIN_DIVIDER
RESERVED
CH0_FREF_DIVIDER
7
6
5
4
3
2
1
0
CH0_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. Address 0x14, CLOCK_DIVIDERS_CH0 Field Descriptions
Bit
15:12
11:10
9:0
Field
Type
R/W
R/W
R/W
Reset
Description
0000
Channel 0 Input Divider Sets the divider for Channel 0 input.
Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz
b0000: Reserved. Do not use.
CH0_FIN_DIVIDER≥b0001:
fin0 = fSENSOR0/CH0_FIN_DIVIDER
CH0_FIN_DIVIDER
RESERVED
00
Reserved. Set to b00.
00 0000
0000
Channel 0 Reference Divider Sets the divider for Channel 0
reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH0_FREF_DIVIDER
CH0_FREF_DIVIDER≥b00’0000’0001:
fREF0 = fCLK/CH0_FREF_DIVIDER
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8.6.19 Address 0x15, CLOCK_DIVIDERS_CH1
Figure 35. Address 0x15, CLOCK_DIVIDERS_CH1
15
7
14
13
12
11
10
9
8
CH1_FIN_DIVIDER
RESERVED
CH1_FREF_DIVIDER
6
5
4
3
2
1
0
CH1_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. Address 0x15, CLOCK_DIVIDERS_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
0000
Channel 1 Input Divider. Sets the divider for Channel 1 input.
Used when the Sensor frequency is greater than the maximum
FIN
.
15:12
CH1_FIN_DIVIDER
R/W
b0000: Reserved. Do not use.
CH1_FIN_DIVIDER≥b0001:
fin1 = fSENSOR1/CH1_FIN_DIVIDER
11:10
9:0
RESERVED
R/W
R/W
00
Reserved. Set to b00.
00 0000
0000
Channel 1 Reference Divider. Sets the divider for Channel 1
reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH1_FREF_DIVIDER
CH1_FREF_DIVIDER≥ b00’0000’0001:
fREF1 = fCLK/CH1_FREF_DIVIDER
8.6.20 Address 0x16, CLOCK_DIVIDERS_CH2 (LDC1314 only)
Figure 36. Address 0x16, CLOCK_DIVIDERS_CH2
15
14
13
12
11
10
9
8
CH2_FIN_DIVIDER
RESERVED
CH2_FREF_DIVIDER
7
6
5
4
3
2
1
0
CH2_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Address 0x16, CLOCK_DIVIDERS_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15:12
CH2_FIN_DIVIDER
R/W
0000
Channel 2 Input Divider. Sets the divider for Channel 2 input.
Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz.
b0000: Reserved. Do not use.
CH2_FIN_DIVIDER≥b0001:
fIN2 = fSENSOR2/CH2_FIN_DIVIDER
11:10
9:0
RESERVED
R/W
R/W
00
Reserved. Set to b00
CH2_FREF_DIVIDER
00 0000
0000
Channel 2 Reference Divider. Sets the divider for Channel 2
reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH2_FREF_DIVIDER ≥ b00’0000’0001: fREF2
=
fCLK/CH2_FREF_DIVIDER
30
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www.ti.com.cn
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8.6.21 Address 0x17, CLOCK_DIVIDERS_CH3 (LDC1314 only)
Figure 37. Address 0x17, CLOCK_DIVIDERS_CH3
15
7
14
13
12
11
10
9
8
CH3_FIN_DIVIDER
RESERVED
CH3_FREF_DIVIDER
6
5
4
3
2
1
0
CH3_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. Address 0x17, CLOCK_DIVIDERS_CH3
Bit
Field
Type
Reset
Description
15:12
CH3_FIN_DIVIDER
R/W
0000
Channel 3 Input Divider. Sets the divider for Channel 3 input.
Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz.
b0000: Reserved. Do not use.
CH3_FIN_DIVIDER≥b0001:
fIN3 = fSENSOR3/CH3_FIN_DIVIDER
11:10
9:0
RESERVED
R/W
R/W
00
Reserved. Set to b00
CH3_FREF_DIVIDER
00 0000
0000
Channel 3 Reference Divider. Sets the divider for Channel 3
reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: reserved
CH3_FREF_DIVIDER ≥ b00’0000’0001: fREF3
=
fCLK/CH3_FREF_DIVIDER
8.6.22 Address 0x18, STATUS
Figure 38. Address 0x18, STATUS
15
7
14
13
12
11
10
9
8
ERR_CHAN
ERR_UR
ERR_OR
ERR_WD
ERR_AHE
ERR_ALE
ERR_ZC
6
5
4
3
2
1
0
RESERVED
DRDY
RESERVED
CH0_UNREA
DCONV
CH1_
CH2_
CH3_
UNREADCONV UNREADCONV UNREADCONV
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. Address 0x18, STATUS Field Descriptions
Bit
Field
Type
Reset
Description
15:14
ERR_CHAN
R
00
Error Channel
Indicates which channel has generated a Flag or Error. Once
flagged, any reported error is latched and maintained until either
the STATUS register or the DATA_CHx register corresponding
to the Error Channel is read.
b00: Channel 0 is source of flag or error.
b01: Channel 1 is source of flag or error.
b10: Channel 2 is source of flag or error (LDC1314 only).
b11: Channel 3 is source of flag or error (LDC1314 only).
13
12
ERR_UR
ERR_OR
R
R
0
0
Conversion Under-range Error
b0: No Conversion Under-range error was recorded since the
last read of the STATUS register.
b1: An active channel has generated a Conversion Under-range
error. Refer to STATUS.ERR_CHAN field to determine which
channel is the source of this error.
Conversion Over-range Error.
b0: No Conversion Over-range error was recorded since the last
read of the STATUS register.
b1: An active channel has generated a Conversion Over-range
error. Refer to STATUS.ERR_CHAN field to determine which
channel is the source of this error.
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Table 33. Address 0x18, STATUS Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11
ERR_WD
R
0
Watchdog Timeout Error
b0: No Watchdog Timeout error was recorded since the last
read of the STATUS register.
b1: An active channel has generated a Watchdog Timeout error.
Refer to STATUS.ERR_CHAN field to determine which channel
is the source of this error.
10
ERR_AHE
ERR_ALE
ERR_ZC
DRDY
R
R
R
R
0
0
0
0
Amplitude High Error
b0: No Amplitude High error was recorded since the last read of
the STATUS register.
b1: An active channel has generated an Amplitude High error.
Refer to STATUS.ERR_CHAN field to determine which channel
is the source of this error.
9
Amplitude Low Error
b0: No Amplitude Low error was recorded since the last read of
the STATUS register.
b1: An active channel has generated an Amplitude Low error.
Refer to STATUS.ERR_CHAN field to determine which channel
is the source of this error.
8
Zero Count Error
b0: No Zero Count error was recorded since the last read of the
STATUS register.
b1: An active channel has generated a Zero Count error. Refer
to STATUS.ERR_CHAN field to determine which channel is the
source of this error.
6
Data Ready Flag.
b0: No new conversion result was recorded in the STATUS
register.
b1: A new conversion result is ready. When in Single Channel
Conversion, this indicates a single conversion is available. When
in sequential mode, this indicates that a new conversion result
for all active channels is now available.
3
2
1
CH0_UNREADCONV
CH1_ UNREADCONV
CH2_ UNREADCONV
R
R
R
0
0
0
Channel 0 Unread Conversion b0: No unread conversion is
present for Channel 0.
b1: An unread conversion is present for Channel 0.
Read Register DATA_CH0 to retrieve conversion results.
Channel 1 Unread Conversion b0: No unread conversion is
present for Channel 1.
b1: An unread conversion is present for Channel 1.
Read Register DATA_CH1 to retrieve conversion results.
Channel 2 Unread Conversion b0: No unread conversion is
present for Channel 2.
b1: An unread conversion is present for Channel 2.
Read Register DATA_CH2 to retrieve conversion results
(LDC1314 only)
0
CH3_ UNREADCONV
R
0
Channel 3 Unread Conversion
b0: No unread conversion is present for Channel 3.
b1: An unread conversion is present for Channel 3.
Read Register DATA_CH3 to retrieve conversion results
(LDC1314 only)
8.6.23 Address 0x19, ERROR_CONFIG
Figure 39. Address 0x19, ERROR_CONFIG
15
14
13
12
11
10
9
8
UR_ERR2OUT OR_ERR2OUT
WD_
AH_ERR2OUT AL_ERR2OUT
RESERVED
ERR2OUT
7
6
5
4
3
2
1
0
UR_ERR2INT
OR_ERR2INT WD_ERR2INT
AH_ERR2INT
AL_ERR2INT
ZC_ERR2INT
Reserved
DRDY_2INT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
32
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www.ti.com.cn
ZHCSF01 –APRIL 2016
Table 34. Address 0x19, ERROR_CONFIG
Bit
Field
Type
Reset
Description
15
UR_ERR2OUT
R/W
0
Under-range Error to Output Register
b0: Do not report Under-range errors in the DATA_CHx
registers.
b1: Report Under-range errors in the DATA_CHx.CHx_ERR_UR
register field corresponding to the channel that generated the
error.
14
13
OR_ERR2OUT
WD_ ERR2OUT
R/W
R/W
0
0
Over-range Error to Output Register
b0: Do not report Over-range errors in the DATA_CHx registers.
b1: Report Over-range errors in the DATA_CHx.CHx_ERR_OR
register field corresponding to the channel that generated the
error.
Watchdog Timeout Error to Output Register
b0: Do not report Watchdog Timeout errors in the DATA_CHx
registers.
b1: Report Watchdog Timeout errors in the
DATA_CHx.CHx_ERR_WD register field corresponding to the
channel that generated the error.
12
11
AH_ERR2OUT
AL_ERR2OUT
R/W
R/W
0
0
Amplitude High Error to Output Register
b0:Do not report Amplitude High errors in the DATA_CHx
registers.
b1: Report Amplitude High errors in the
DATA_CHx.CHx_ERR_AE register field corresponding to the
channel that generated the error.
Amplitude Low Error to Output Register
b0: Do not report Amplitude High errors in the DATA_CHx
registers.
b1: Report Amplitude High errors in the
DATA_CHx.CHx_ERR_AE register field corresponding to the
channel that generated the error.
7
6
UR_ERR2INT
OR_ERR2INT
R/W
R/W
0
0
Under-range Error to INTB
b0: Do not report Under-range errors by asserting INTB pin and
STATUS register.
b1: Report Under-range errors by asserting INTB pin and
updating STATUS.ERR_UR register field.
Over-range Error to INTB
b0: Do not report Over-range errors by asserting INTB pin and
STATUS register.
b1: Report Over-range errors by asserting INTB pin and
updating STATUS.ERR_OR register field.
5
4
3
2
WD_ERR2INT
AH_ERR2INT
AL_ERR2INT
ZC_ERR2INT
R/W
R/W
R/W
R/W
0
0
0
0
Watchdog Timeout Error to INTB b0: Do not report Under-range
errors by asserting INTB pin and STATUS register.
b1: Report Watchdog Timeout errors by asserting INTB pin and
updating STATUS.ERR_WD register field.
Amplitude High Error to INTB b0: Do not report Amplitude High
errors by asserting INTB pin and STATUS register.
b1: Report Amplitude High errors by asserting INTB pin and
updating STATUS.ERR_AHE register field.
Amplitude Low Error to INTB b0: Do not report Amplitude Low
errors by asserting INTB pin and STATUS register.
b1: Report Amplitude Low errors by asserting INTB pin and
updating STATUS.ERR_ALE register field.
Zero Count Error to INTB b0: Do not report Zero Count errors by
asserting INTB pin and STATUS register.
b1: Report Zero Count errors by asserting INTB pin and
updating STATUS. ERR_ZC register field.
1
0
Reserved
R/W
R/W
0
0
Reserved (set to b0)
DRDY_2INT
Data Ready Flag to INTB b0: Do not report Data Ready Flag by
asserting INTB pin and STATUS register.
b1: Report Data Ready Flag by asserting INTB pin and updating
STATUS. DRDY register field.
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8.6.24 Address 0x1A, CONFIG
Figure 40. Address 0x1A, CONFIG
15
14
6
13
12
11
10
9
8
ACTIVE_CHAN
SLEEP_MODE RP_OVERRID SENSOR_ACTI AUTO_AMP_DI REF_CLK_SR
RESERVED
_EN
5
E_EN
4
VATE_SEL
3
S
2
C
1
7
0
INTB_DIS
HIGH_CURRE
NT_DRV
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. Address 0x1A, CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15:14
ACTIVE_CHAN
R/W
00
Active Channel Selection
Selects channel for continuous conversions when
MUX_CONFIG.SEQUENTIAL is 0.
b00: Perform continuous conversions on Channel 0
b01: Perform continuous conversions on Channel 1
b10: Perform continuous conversions on Channel 2 (LDC1314
only)
b11: Perform continuous conversions on Channel 3 (LDC1314
only)
13
12
SLEEP_MODE_EN
RP_OVERRIDE_EN
R/W
R/W
1
0
Sleep Mode Enable
Enter or exit low power Sleep Mode.
b0: Device is active.
b1: Device is in Sleep Mode.
Sensor RP Override Enable
Provides control over Sensor current drive used during the
conversion time for Ch. x, based on the programmed value in
the CHx_IDRIVE field.
b0: Override off
b1: RP Override on
11
SENSOR_ACTIVATE_SEL
R/W
1
Sensor Activation Mode Selection.
Set the mode for sensor initialization.
b0: Full Current Activation Mode – the LDC will drive maximum
sensor current for a shorter sensor activation time.
b1: Low Power Activation Mode – the LDC uses the value
programmed in DRIVE_CURRENT_CHx during sensor
activation to minimize power consumption.
10
AUTO_AMP_DIS
REF_CLK_SRC
R/W
R/W
0
0
Automatic Sensor Amplitude Correction Disable
Setting this bit will disable the automatic Amplitude correction
algorithm and stop the updating of the CHx_INIT_IDRIVE field.
b0: Automatic Amplitude correction enabled
b1: Automatic Amplitude correction is disabled. Recommended
for precision applications.
9
Select Reference Frequency Source b0:
Use Internal oscillator as reference frequency
b1: Reference frequency is provided from CLKIN pin.
8
7
RESERVED
INTB_DIS
R/W
R/W
0
0
Reserved. Set to b0.
INTB Disable
b0: INTB pin will be asserted when status register updates.
b1: INTB pin will not be asserted when status register updates
6
HIGH_CURRENT_DRV
R/W
0
High Current Sensor Drive
b0: The LDC will drive all channels with normal sensor current
(1.5mA max).
b1: The LDC will drive channel 0 with current >1.5mA.
This mode is not supported if AUTOSCAN_EN = b1 (multi-
channel mode)
5:0
RESERVED
R/W
00 0001
Reserved Set to b00’0001
34
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ZHCSF01 –APRIL 2016
8.6.25 Address 0x1B, MUX_CONFIG
Figure 41. Address 0x1B, MUX_CONFIG
15
14
13
12
11
10
9
8
0
AUTOSCAN_E
N
RR_SEQUENCE
RESERVED
7
6
5
4
3
2
1
RESERVED
DEGLITCH
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. Address 0x1B, MUX_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15
AUTOSCAN_EN
R/W
0
Auto-Scan Mode Enable
b0: Continuous conversion on the single channel selected by
CONFIG.ACTIVE_CHAN register field.
b1: Auto-Scan conversions as selected by
MUX_CONFIG.RR_SEQUENCE register field.
14:13
RR_SEQUENCE
R/W
00
Auto-Scan Sequence Configuration
Configure multiplexing channel sequence. The LDC will perform
a single conversion on each channel in the sequence selected,
and then restart the sequence continuously.
b00: Ch0, Ch1
b01: Ch0, Ch1, Ch2 (LDC1314 only)
b10: Ch0, Ch1, Ch2, Ch3 (LDC1314 only)
b11: Ch0, Ch1
12:3
2:0
RESERVED
DEGLITCH
R/W
R/W
00 0100
0001
Reserved. Must be set to 00 0100 0001
111
Input deglitch filter bandwidth.
Select the lowest setting that exceeds the oscillation tank
oscillation frequency.
b001: 1MHz
b100: 3.3MHz
b101: 10MHz
b111: 33MHz
8.6.26 Address 0x1C, RESET_DEV
Figure 42. Address 0x1C, RESET_DEV
15
14
13
12
11
10
OUTPUT_GAIN
9
1
8
RESET_DEV
RESERVED
RESERVED
7
6
5
4
3
2
0
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. Address 0x1C, RESET_DEV Field Descriptions
Bit
Field
Type
Reset
Description
15
RESET_DEV
R/W
0
Device Reset
Write b1 to reset the device. Will always readback 0.
14:11
10:9
RESERVED
R/W
R/W
0000
00
Reserved. Set to b0000
OUTPUT_GAIN
Output gain control
00: Gain = 1 (0 bits shift)
01: Gain = 4 (2 bits shift)
10: Gain = 8 (3 bits shift)
11: Gain = 16 (4 bits shift)
8:0
RESERVED
R/W
0 0000
0000
Reserved, Set to b0 0000 0000
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8.6.27 Address 0x1E, DRIVE_CURRENT_CH0
Figure 43. Address 0x1E, DRIVE_CURRENT_CH0
15
7
14
6
13
12
11
10
9
8
0
CH0_IDRIVE
CH0_INIT_IDRIVE
5
4
3
2
1
CH0_INIT_IDRIVE
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. Address 0x1E, DRIVE_CURRENT_CH0 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
CH0_IDRIVE
R/W
0 0000
Channel 0 L-C Sensor drive current
This field defines the Drive Current used during the settling +
conversion time of Channel 0 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6
CH0_INIT_IDRIVE
R
0 0000
Channel 0 Sensor Current Drive
This field stores the Initial Drive Current calculated during the
initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the
sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0
RESERVED
–
00 0000
Reserved
8.6.28 Address 0x1F, DRIVE_CURRENT_CH1
Figure 44. Address 0x1F, DRIVE_CURRENT_CH1
15
14
13
12
11
10
9
8
0
CH1_IDRIVE
CH1_INIT_IDRIVE
7
6
5
4
3
2
1
CH1_INIT_IDRIVE
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 39. Address 0x1F, DRIVE_CURRENT_CH1 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
CH1_IDRIVE
R/W
0 0000
Channel 1 L-C Sensor drive current
This field defines the Drive Current used during the settling +
conversion time of Channel 1 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6
5:0
CH1_INIT_IDRIVE
RESERVED
R
-
0 0000
Channel 1 Sensor Current Drive
This field stores the Initial Drive Current calculated during the
initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the
sensor clock if the AUTO_AMP_DIS field is NOT set.
00 0000
Reserved
36
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LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
8.6.29 Address 0x20, DRIVE_CURRENT_CH2 (LDC1314 only)
Figure 45. Address 0x20, DRIVE_CURRENT_CH2
15
7
14
6
13
12
11
10
9
8
0
CH2_IDRIVE
CH2_INIT_IDRIVE
5
4
3
2
1
CH2_INIT_IDRIVE
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. Address 0x20, DRIVE_CURRENT_CH2 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
CH2_IDRIVE
R/W
0 0000
Channel 2 L-C Sensor drive current
This field defines the Drive Current to be used during the settling
+ conversion time of Channel 2 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6
CH2_INIT_IDRIVE
R
0 0000
Channel 2 Sensor Current Drive
This field stores the Initial Drive Current calculated during the
initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the
sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0
RESERVED
–
00 0000
Reserved
8.6.30 Address 0x21, DRIVE_CURRENT_CH3 (LDC1314 only)
Figure 46. Address 0x21, DRIVE_CURRENT_CH3
15
14
13
12
11
10
9
8
0
CH3_IDRIVE
CH3_INIT_IDRIVE
7
6
5
4
3
2
1
CH3_INIT_IDRIVE
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 41. DRIVE_CURRENT_CH3 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
CH3_IDRIVE
R/W
0 0000
Channel 3 L-C Sensor drive current
This field defines the Drive Current to be used during the settling
+ conversion time of Channel 3 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6
5:0
CH3_INIT_IDRIVE
RESERVED
R
–
0 0000
Channel 3 Sensor Current Drive
This field stores the Initial Drive Current calculated during the
initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the
sensor clock if the AUTO_AMP_DIS field is NOT set.
00 0000
Reserved
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LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
8.6.31 Address 0x7E, MANUFACTURER_ID
Figure 47. Address 0x7E, MANUFACTURER_ID
15
7
14
6
13
12
11
10
9
1
8
0
MANUFACTURER_ID
5
4
3
2
MANUFACTURER_ID
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 42. Address 0x7E, MANUFACTURER_ID Field Descriptions
Bit
Field
Type
Reset
Description
15:0
MANUFACTURER_ID
R
0101 0100 Manufacturer ID = 0x5449
0100 1001
8.6.32 Address 0x7F, DEVICE_ID
Figure 48. Address 0x7F, DEVICE_ID
7
6
5
4
3
2
1
0
DEVICE_ID
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 43. Address 0x7F, DEVICE_ID Field Descriptions
Bit
Field
Type
Reset
Description
7:0
DEVICE_ID
R
0011 0000 Device ID = 0x3054
0101 0100
38
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www.ti.com.cn
ZHCSF01 –APRIL 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Theory of Operation
9.1.1.1 Conductive Objects in an EM Field
An AC current flowing through an inductor will generate an AC magnetic field. If a conductive material, such as a
metal object, is brought into the vicinity of the inductor, the magnetic field will induce a circulating current (eddy
current) on the surface of the conductor.
Conductive
Target
Eddy
d
Current
Figure 49. Conductor in AC Magnetic Field
The eddy current is a function of the distance, size, and composition of the conductor. The eddy current
generates its own magnetic field, which opposes the original field generated by the sensor inductor. This effect is
equivalent to a set of coupled inductors, where the sensor inductor is the primary winding and the eddy current in
the target object represents the secondary inductor. The coupling between the inductors is a function of the
sensor inductor, and the resistivity, distance, size, and shape of the conductive target. The resistance and
inductance of the secondary winding caused by the eddy current can be modeled as a distance dependent
resistive and inductive component on the primary side (coil). Figure 49 shows a simplified circuit model of the
sensor and the target as coupled coils.
9.1.1.2 L-C Resonators
An EM field can be generated using an L-C resonator, or L-C tank. One topology for an L-C tank is a parallel R-
L-C construction, as shown in Figure 50.
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LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
Application Information (continued)
5istance-dependent coupling
a(d)
9ddy
/urrent
CPAR
5istꢀnce (d)
Çarget wesistance
/oil {eries
wesistance (ws)
I
RP(d)
L(d)
CPAR + CTANK
ꢀarallel 9lectrical
ꢁodel, [-/ Çank
Copyright © 2016, Texas Instruments Incorporated
Figure 50. Electrical Model of the L-C Tank Sensor
An oscillator can be constructed by combining a frequency selective circuit (resonator) with a gain block in a
closed loop. The criteria for oscillation are: (1) loop gain > 1, and (2) closed loop phase shift of 2π radians. The
R-L-C resonator provides the frequency selectivity and contributes to the phase shift. At resonance, the
impedance of the reactive components (L and C) cancels, leaving only RP, the lossy (resistive) element in the
circuit. The voltage amplitude is maximized. The RP can be used to determine the sensor drive current. A lower
RP requires a larger sensor current to maintain a constant oscillation amplitude. The sensor oscillation frequency
is given by:
1
1
Q2
5 *10-9
1
ƒSENSOR
=
* 1-
-
ö
2p LC
Q LC
2p LC
where
•
•
•
C is the sensor capacitance (CTANK + CPAR
)
L is the inductance
Q is the quality factor of the resonator. Q can be approximated by:
(9)
C
L
Q = RP
where
•
RS is the AC series resistance of the inductor
(10)
40
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ZHCSF01 –APRIL 2016
Application Information (continued)
Texas Instruments' WEBENCH design tool can be used for coil design, in which the parameter values for RP, L
and C are calculated. See http://www.ti.com/webench.
RP is a function of target distance, target material, and sensor characteristics. Figure 51 shows that RP is directly
proportional to the distance between the sensor and the target. The graph represents a 14-mm diameter PCB
coil (23 turns, 4-mil trace width, 4-mil spacing between traces, 1-oz copper thickness, FR4).
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Distance (mm)
Figure 51. Example RP vs. Distance with a 14-mm PCB Coil and 2mm Thick Stainless Steel Target
It is important to configure the LDC current drive so that the sensor will still oscillate at the minimum RP value.
For example, if the closest target distance in a system with the response shown in Figure 51 is 1mm, then the
LDC RP value is 5 kΩ. The objective is to maintain a sufficient sensor oscillation voltage so that the sensor
frequency can be measured even at the minimum operating distance. See section Current Drive Control
Registers for details on setting the current drive.
The inductance that is measured by the LDC is
1
L(d) = Linf -M(d) =
(2p* ƒSENSOR )2 *C
where
•
•
•
•
•
L(d) is the measured sensor inductance, for a distance d between the sensor coil and target
Linf is the inductance of the sensing coil without a conductive target (target at infinite distance)
M(d) is the mutual inductance
fSENSOR = sensor oscillation frequency for a distance d between the sensor coil and target
C = CTANK + CPAR
(11)
Figure 52 shows an example of variation in sensor frequency and inductance as a function of distance for a 14-
mm diameter PCB coil (23 turns, 4-mil trace width, 4-mil spacing between traces, 1-oz copper thickness, FR4).
Copyright © 2016, Texas Instruments Incorporated
41
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
Application Information (continued)
4
24
21
18
15
12
9
Target D = 0.5 x coil •
Target D = 1 x coil •
3.5
3
2.5
2
1.5
1
Sensor Frequency (MHz)
Inductance (µH)
6
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Target Distance D (mm)
D011
Figure 52. Example Sensor Frequency, Inductance vs. Target Distance
with 14-mm PCB Coil and 1.5 mm Thick Aluminum Target
In the absence of magnetic materials, such as ferrous metals and ferrites, the inductance shift, and therefore the
measured frequency shift, depends only on current flow geometries. Temperature drift is dominated by physical
expansion of the inductor and other mechanical system components over temperature which alter current flow
geometries. Note that the additional temperature drift of the sensor capacitor must also be taken into account.
For additional information on temperature effects and temperature compensation, see LDC1000 Temperature
Compensation (SNAA212)
9.2 Typical Application
Example of a multi-channel implementation using the LDC1312. This example is representative of an axial
displacement application, in which the target movement is perpendicular to the plane of the coil. The second
channel can be used to sense proximity of a second target, or it can be used for temperature compensation by
connecting a reference coil.
3.3 V
3.3 V
LDC1312
MCU
VDD
CLKIN
VDD
40 MHz
SD
GPIO
INTB
GPIO
IN0A
IN0B
Target
Sensor 0
Core
GND
IN1A
SDA
I2C
Peripheral
Target
I2C
IN1B
SCL
3.3 V
ADDR
Sensor 1
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 53. Example Multi-Channel Application - LDC1312
42
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LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Typical Application (continued)
9.2.1 Design Requirements
•
Design example in which Sensor 0 is used for proximity measurement and Sensor 1 is used for temperature
compensation:
•
•
•
•
•
•
•
Using WEBENCH for coil design
Target distance = 0.1 cm
Distance resolution = 0.2 µm
Target diameter = 1 cm
Target material = stainless steel (SS416)
Number of PCB layers for the coil = 2
The application requires 500SPS ( TSAMPLE = 2000 µs)
9.2.2 Detailed Design Procedure
The target distance, resolution and diameter are used as inputs to WEBENCH to design the sensor coil, The
resulting coil design is a 2 layer coil, with an area of 2.5 cm2, diameter of 1.77 cm, and 39 turns. The values
for RP, L and C are: RP = 6.6 kΩ, L = 43.9 µH, C = 100 pF.
Using L and C, fSENSOR = 1/2π√(LC) = 1/2π√(43.9*10-6 * 100*10-12) = 2.4 MHz
Using a system master clock of 40 MHz applied to the CLKIN pin allows flexibility for setting the internal
clock frequencies. The sensor coil is connected to channel 0 (IN0A and IN0B pins).
After powering on the LDC, it will be in Sleep Mode. Program the registers as follows (example sets registers
for channel 0 only; channel 1 registers can use equivalent configuration):
1. Set the dividers for channel 0.
(a) Because the sensor freqeuncy is less than 8.75 MHz, the sensor divider can be set to 1, which means
setting field CH0_FIN_DIVIDER to 0x1. By default, fIN0 = fSENSOR = 2.4MHz.
(b) The design constraint for fREF0 is > 4 × fSENSOR. A 20 MHz reference frequency satisfies this constraint,
so the reference divider should be set to 2. This is done by setting the CH0_FREF_DIVIDER field to
0x02.
(c) The combined value for Chan. 0 divider register (0x14) is 0x1002.
2. Program the settling time for Channel 0. The calculated Q of the coil is 10 (see Multi-Channel and Single
Channel Operation).
(a) CH0_SETTLECOUNT ≥ Q × fREF0 / (16 × fSENSOR0) → 5.2, rounded up to 6. To provide margin to account
for system tolerances, a higher value of 10 is chosen.
(b) Register 0x10 should be programmed to a minimum of 10.
(c) The settle time is: (10 x 16)/20,000,000 = 8 µs
(d) The value for Chan. 0 SETTLECOUNT register (0x10) is 0x000A.
3. The channel switching delay is ~1μs for fREF = 20 MHz (see Multi-Channel and Single Channel Operation)
4. Set the conversion time by the programming the reference count for Channel 0. The budget for the
conversion time is : TSAMPLE – settling time – channel switching delay = 1000 – 8 – 1 = 991 µs
(a) To determine the conversion time register value, use the following equation and solve for
CH0_RCOUNT: Conversion Time (tC0)= (CH0_RCOUNTˣ16)/fREF0
.
(b) This results in CH0_RCOUNT having a value of 1238 decimal (rounded down)
(c) Set the CH0_RCOUNT register (0x08) to 0x04D6.
5. Use the default values for the ERROR_CONFIG register (address 0x19). By default, no interrupts are
enabled
6. Sensor drive current: to set the CH0_IDRIVE field value, read the value from Table 10 using RP = 6.6 kΩ. In
this case the IDRIVE value should be set to 18 (decimal). The INIT_DRIVE current field should be set to
0x00. The combined value for the DRIVE_CURRENT_CH0 register (addr 0x1E) is 0x9000.
7. Program the MUX_CONFIG register
(a) Set the AUTOSCAN_EN to b1 bit to enable sequential mode
(b) Set RR_SEQUENCE to b00 to enable data conversion on two channels (channel 0, channel 1)
(c) Set DEGLITCH to b100 to set the input deglitch filter bandwidth to 3.3MHz, the lowest setting that
exceeds the oscillation tank frequency.
(d) The combined value for the MUX_CONFIG register (address 0x1B) is 0x820C
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LDC1312-Q1, LDC1314-Q1
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www.ti.com.cn
Typical Application (continued)
8. Finally, program the CONFIG register as follows:
(a) Set the ACTIVE_CHAN field to b00 to select channel 0.
(b) Set SLEEP_MODE_EN field to b0 to enable conversion.
(c) Set RP_OVERRIDE_EN to b1 to disable auto-calibration.
(d) Set SENSOR_ACTIVATE_SEL = b0, for full current drive during sensor activation
(e) Set the AUTO_AMP_DIS field to b1 to disable auto-amplitude correction
(f) Set the REF_CLK_SRC field to b1 to use the external clock source.
(g) Set the other fields to their default values.
(h) The combined value for the CONFIG register (address 0x1A) is 0x1601.
We then read the conversion results for channel 0 and channel 1 every 1000 µs from register addresses
0x00 and 0x02.
9.2.2.1 Recommended Initial Register Configuration Values
Based on the example configuration in section Detailed Design Procedure, the following register write sequence
is recommended:
Table 44. Recommended Initial Register Configuration Values (Single-channel Operation)
Address
Value
Register Name
Comments
0x08
0x04D6
RCOUNT_CH0
Reference count calculated from timing requirements (1 kSPS) and resolution
requirements
0x10
0x14
0x000A
0x1002
SETTLECOUNT_ Minimum settling time for chosen sensor
CH0
CLOCK_DIVIDER CH0_FIN_DIVIDER = 1, CH0_FREF_DIVIDER = 2
S_CH0
0x19
0x1B
0x1E
0x0000
0x020C
0x9000
ERROR_CONFIG Can be changed from default to report status and error conditions
MUX_CONFIG
Enable Ch 0 (continuous mode), set Input deglitch bandwidth to 3.3MHz
DRIVE_CURREN Sets sensor drive current on ch 0
T_CH0
0x1A
0x1601
CONFIG
Select active channel = ch 0, disable auto-amplitude correction and auto-
calibration, enable full current drive during sensor activation, select external
clock source, wake up device to start conversion. This register write must
occur last because device configuration is not permitted while the LDC is in
active mode.
Table 45. Recommended Initial Register Configuration Values (Multi-channel Operation)
Address
Value
Register Name
Comments
0x08
0x04D6
RCOUNT_CH0
Reference count calculated from timing requirements (1 kSPS) and resolution
requirements
0x09
0x10
0x11
0x14
0x15
0x04D6
0x000A
0x000A
0x1002
0x1002
RCOUNT_CH1
Reference count calculated from timing requirements (1 kSPS) and resolution
requirements
SETTLECOUNT_ Minimum settling time for chosen sensor
CH0
SETTLECOUNT_ Minimum settling time for chosen sensor
CH1
CLOCK_DIVIDER CH0_FIN_DIVIDER = 1, CH0_FREF_DIVIDER = 2
S_CH0
CLOCK_DIVIDER CH1_FIN_DIVIDER = 1, CH1_FREF_DIVIDER = 2
S_CH1
0x19
0x1B
0x0000
0x820C
ERROR_CONFIG Can be changed from default to report status and error conditions
MUX_CONFIG
Enable Ch 0 and Ch 1 (sequential mode), set Input deglitch bandwidth to
3.3MHz
0x1E
0x1F
0x9000
0x9000
DRIVE_CURREN Sets sensor drive current on ch 0
T_CH0
DRIVE_CURREN Sets sensor drive current on ch 1
T_CH1
44
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Table 45. Recommended Initial Register Configuration Values (Multi-channel Operation) (continued)
Address
Value
Register Name
Comments
0x1A
0x1601
CONFIG
disable auto-amplitude correction and auto-calibration, enable full current
drive during sensor activation, select external clock source, wake up device
to start conversion. This register write must occur last because device
configuration is not permitted while the LDC is in active mode.
9.2.2.2 Inductor Self-Resonant Frequency
Every inductor has a distributed parasitic capacitance, which is dependent on construction and geometry. At the
Self-Resonant Frequency (SRF), the reactance of the inductor cancels the reactance of the parasitic
capacitance. Above the SRF, the inductor will electrically appear to be a capacitor. Because the parasitic
capacitance is not well-controlled or stable, TI recommends that: fSENSOR < 0.8 × fSR
.
175.0
150.0
125.0
100.0
75.0
50.0
25.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (MHz)
Figure 54. Example Coil Inductance vs. Frequency
In Figure 54, the inductor has a SRF at 6.38 MHz; therefore the inductor should not be operated above 0.8×6.38
MHz, or 5.1 MHz.
9.2.3 Application Curves
Common test conditions (unless specified otherwise):
•
•
•
•
•
•
•
Sensor inductor: 2 layer, 32 turns/layer, 14mm diameter, PCB inductor with L=19.4 µH, RP=5.7 kΩ at 2 MHz
Sensor capacitor: 330pF 1% COG/NP0
Target: Aluminum, 1.5 mm thickness
Channel = Channel 0 (continuous mode)
CLKIN = 40MHz, CHx_FIN_DIVIDER = 0x01, CHx_FREF_DIVIDER = 0x001
CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100
RP_OVERRIDE = 1, AUTO_AMP_DIS = 1, DRIVE_CURRENT_CH0 = 0x9800
Copyright © 2016, Texas Instruments Incorporated
45
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
3500
3000
2.5
2.25
2
Average Code (DEC)
1.75
1.5
1.25
1
2500
Target Distance =
0.5 x coil diameter
Target Distance =
1 x coil diameter
2000
0.75
0.5
0.25
0
1500
1000
0
20%
40%
60%
80%
100%
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Target Distance / •SENSOR
Target Distance / •SENSOR
D012
D013
Figure 55. Typical Output Code vs. Target Distance (0 to
14mm)
Figure 56. Measurement precision in Distance vs. Target
Distance (0 to 10mm)
10 Power Supply Recommendations
•
The LDC requires a voltage supply within 2.7 V and 3.6 V. A multilayer ceramic bypass X7R capacitor of 1μF
between the VDD and GND pins is recommended. If the supply is located more than a few inches from the
LDC, additional bulk capacitance may be required in addition to the ceramic bypass capacitor. An electrolytic
capacitor with a value of 10μF is a typical choice.
•
The optimum placement is closest to the VDD and GND terminals of the device. Care should be taken to
minimize the loop area formed by the bypass capacitor connection, the VDD terminal, and the GND terminal
of the IC. See Figure 57 and Figure 58 for a layout example.
11 Layout
11.1 Layout Guidelines
Avoid long traces to connect the sensor to the LDC. Short traces reduce parasitic capacitances between sensor
inductor and offer higher system performance.
11.2 Layout Example
Figure 57 to Figure 60 show the LDC1312 evaluation module (EVM) layout.
46
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Layout Example (continued)
Figure 57. Example PCB Layout: Top Layer (Signal)
Copyright © 2016, Texas Instruments Incorporated
47
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
Layout Example (continued)
Figure 58. Example PCB Layout: Mid-layer 1 (GND)
48
Copyright © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
Layout Example (continued)
Figure 59. Example PCB Layout: Mid-layer 2 (Power)
Copyright © 2016, Texas Instruments Incorporated
49
LDC1312-Q1, LDC1314-Q1
ZHCSF01 –APRIL 2016
www.ti.com.cn
Layout Example (continued)
Figure 60. Example PCB Layout: Bottom Layer (Signal)
50
版权 © 2016, Texas Instruments Incorporated
LDC1312-Q1, LDC1314-Q1
www.ti.com.cn
ZHCSF01 –APRIL 2016
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
相关链接如下：
•
德州仪器 (TI) 的 WEBENCH 工具：http://www.ti.com.cn/webench
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档如下：
•
《LDC1000 温度补偿》（文献编号：SNAA212）
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 相关链接
表 46 下面的表格中列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问
样片或购买链接。
表 46. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
LDC1312-Q1
LDC1314-Q1
12.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
51
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LDC1312QDNTRQ1
LDC1312QDNTTQ1
ACTIVE
WSON
WSON
DNT
12
12
4500 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LC1312Q
Q1
ACTIVE
DNT
SN
LDC1312
Q1
LDC1314QRGHRQ1
LDC1314QRGHTQ1
ACTIVE
ACTIVE
WQFN
WQFN
RGH
RGH
16
16
SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LC1314Q
LC1314Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DNT0012B
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.1) TYP
2.6 0.1
6
7
2X
2.5
3
0.1
10X 0.5
12
1
0.3
0.2
12X
0.1
C A B
C
0.5
0.3
PIN 1 ID
(45 X 0.25)
12X
0.05
4214928/C 10/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DNT0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
SYMM
12X (0.6)
1
12
12X (0.25)
(1.25)
SYMM
(3)
10X (0.5)
7
6
(R0.05) TYP
(
0.2) VIA
TYP
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214928/C 10/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DNT0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
(0.68)
12X (0.6)
1
12
12X (0.25)
(0.76)
SYMM
10X (0.5)
4X
(1.31)
(R0.05) TYP
6
7
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4214928/C 10/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号：
LDC1350
Electric Fuse, Time Delay Blow, 1350A, 600VAC, 600VDC, 200000A (IR), Inline/holder,
LITTELFUSE
LDC1400
Electric Fuse, Time Delay Blow, 1400A, 600VAC, 600VDC, 200000A (IR), Inline/holder,
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LDC1500
Electric Fuse, Time Delay Blow, 1500A, 600VAC, 600VDC, 200000A (IR), Inline/holder,
LITTELFUSE
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