JM38510/33001B2A [TI]
QUADRUPLE 2-INPUT POSITIVE-NAND GATES; 四路2输入正与非门型号: | JM38510/33001B2A |
厂家: | TEXAS INSTRUMENTS |
描述: | QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
文件: | 总13页 (文件大小:468K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
SN54F00 . . . J PACKAGE
SN74F00 . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = A • B or Y = A + B in positive logic.
2Y
GND
8
The SN54F00 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F00 is characterized for
operation from 0°C to 70°C.
SN54F00 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each gate)
3
2
1
20 19
18
INPUTS
OUTPUT
Y
1Y
NC
2A
4
5
6
7
8
4A
NC
4Y
NC
3B
A
B
H
X
L
17
16
15
14
H
L
L
H
H
NC
2B
X
9 10 11 12 13
†
logic symbol
1
1A
2
&
3
6
NC – No internal connection
1Y
2Y
3Y
4Y
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
8
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
1
2
1A
1B
3
1Y
2Y
3Y
4Y
4
5
2A
2B
6
8
9
3A
3B
10
12
13
4A
4B
11
Pin numbers shown are for the D, J, and N packages.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range: SN54F00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74F00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F00
SN74F00
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
– 1
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F00
SN74F00
PARAMETER
TEST CONDITIONS
UNIT
V
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
I
–1.2
–1.2
IK
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
3.4
0.3
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
0.5
0.1
V
I
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
20
IH
IL
V = 0.5 V
I
– 0.6
–150
2.8
– 0.6
–150
2.8
mA
mA
mA
mA
§
V
O
= 0
–60
–60
OS
V = 0
I
1.9
6.8
1.9
6.8
CCH
CCL
V = 4.5 V
I
10.2
10.2
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
switching characteristics (see Note 2)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
= 500Ω,
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
T
A
T
A
= MIN to MAX
′F00
TYP
3.3
SN54F00
SN74F00
MIN
1.6
1
MAX
5
MIN
2
MAX
MIN
1.6
1
MAX
t
t
7
6
PLH
A or B
Y
ns
2.8
4.3
1.5
6.5
5.3
PHL
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9757701Q2A
5962-9757701QCA
5962-9757701QDA
JM38510/33001B2A
JM38510/33001BCA
JM38510/33001BDA
JM38510/33301B2A
SN54F00J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
20
14
14
20
14
14
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
FK
J
LCCC
CDIP
CFP
W
FK
J
LCCC
CDIP
SOIC
SN74F00D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F00DE4
SN74F00DR
SN74F00DRE4
SN74F00N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
N
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74F00N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
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Call TI
SN74F00NE4
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74F00NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F00NSRE4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54F00FK
SNJ54F00J
SNJ54F00W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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