IWR6843ABGABLR [TI]
IWR6843, IWR6443 Single-Chip 60- to 64-GHz mmWave Sensor;型号: | IWR6843ABGABLR |
厂家: | TEXAS INSTRUMENTS |
描述: | IWR6843, IWR6443 Single-Chip 60- to 64-GHz mmWave Sensor |
文件: | 总80页 (文件大小:2635K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IWR6843,IWR6443
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
IWR6843, IWR6443 Single-Chip 60- to 64-GHz mmWave Sensor
•
Other interfaces available to user application
– Up to 6 ADC channels (low sample rate
monitoring)
1 Features
•
FMCW transceiver
– Integrated PLL, transmitter, receiver, Baseband,
and A2D
– Up to 2 SPI ports
– Up to 2 UARTs
– 60- to 64-GHz coverage with 4-GHz continuous
bandwidth
– 1 CAN-FD interface
– I2C
– Four receive channels
– Three transmit channels
– Supports 6-bit phase shifter for TX Beam
forming
– Ultra-accurate chirp engine based on fractional-
N PLL
– GPIOs
– 2 lane LVDS interface for raw ADC data and
debug instrumentation
•
Functional Safety-Compliant targeted
– Developed for functional safety applications
– Documentation will be available to aid IEC
61508 functional safety system design
– Hardware integrity up to SIL-2 targeted
– Safety-related certification
– TX power: 12 dBm
– RX noise figure:
•
12 dB
– Phase noise at 1 MHz:
–93 dBc/Hz
•
IEC 61508 certification by TUV Sud planned
•
•
•
Non-Functional safety variants
Power management
– Built-in LDO network for enhanced PSRR
– I/Os support dual voltage 3.3 V/1.8 V
Clock source
– 40.0 MHz crystal with internal oscillator
– Supports external oscillator at 40 MHz
– Supports externally driven clock (square/sine)
at 40 MHz
•
Built-in calibration and self-test
– ARM® Cortex®-R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across frequency and
temperature
– Embedded self-monitoring with no host
processor involvement on Functional Safety-
Compliant targeted devices
C674x DSP for advanced signal processing
(IWR6843 only)
Hardware accelerator for FFT, filtering, and CFAR
processing
Memory compression
•
•
•
•
•
Easy hardware design
– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip
chip BGA package for easy assembly and low-
cost PCB design
– Small solution size
Operating conditions:
•
•
ARM-R4F microcontroller for object detection, and
interface control
– Supports autonomous mode (loading user
application from QSPI flash memory)
Internal memory with ECC
– Junction temperature range of –40°C to 105°C
•
– IWR6843: 1.75 MB, divided into MSS program
RAM (512 KB), MSS data RAM (192 KB), DSP
L1 RAM (64KB) and L2 RAM (256 KB), and L3
radar data cube RAM (768 KB)
– IWR6443: 1.4 MB, divided into MSS program
RAM (512 KB), MSS data RAM (192 KB), and
L3 radar data cube RAM (768 KB)
– Technical reference manual includes allowed
size modifications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
IWR6843, IWR6443
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
www.ti.com
•
•
•
•
•
•
•
Traffic monitoring
2 Applications
Proximity and position sensing
Security and surveillance
Factory automation safety guards
People counting
Motion detection
Occupancy detection
•
Industrial sensor for measuring range, velocity, and
angle
•
•
•
•
Building automation
Displacement sensing
Gesture recognition
Robotics
3 Description
The IWR device is an integrated single chip mmWave sensor based on FMCW radar technology capable of
operation in the 60-GHz to 64-GHz band. It is built with TI’s low power 45-nm RFCMOS process and enables
unprecedented levels of integration in an extremely small form factor. This device is an ideal solution for low
power, self-monitored, ultra-accurate radar systems in the industrial space. Multiple variants are currently
available including Functional Safety-Compliant targeted devices and non-functional safety devices.
Device Information
BODY SIZE
PART NUMBER
IWR6843AQGABL
IWR6843AQGABLR
IWR6843ABGABLR
IWR6843ABGABL
IWR6443AQGABL
IWR6443AQGABLR
PACKAGE(1)
FCBGA (161)
FCBGA (161)
FCBGA (161)
FCBGA (161)
FCBGA (161)
FCBGA (161)
TRAY / TAPE AND REEL
10.4 mm × 10.4 mm Tray (Non-Functional Safety)
10.4 mm × 10.4 mm Tape and Reel (Non-Functional Safety)
10.4 mm × 10.4 mm Tape and Reel (Functional Safety-Compliant targeted, SIL2)
10.4 mm × 10.4 mm Tray (Functional Safety-Compliant targeted, SIL2)
10.4 mm × 10.4 mm Tray (Non-Functional Safety)
10.4 mm × 10.4 mm Tape and Reel (Non-Functional Safety)
(1) For more information, see Section 13, Mechanical, Packaging, and Orderable Information.
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4 Functional Block Diagram
Figure 4-1 shows the functional block diagram of the device.
Serial Flash interface
QSPI
Cortex R4F
@ 200MHz
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
External MCU
interface
SPI
(User programmable)
PMIC control
SPI / I2C
Digital
Front-end
Data
RAM
Prog RAM
DMA
Boot
ROM
CAN-FD Communication
CAN-FD
(Decimation
filter chain)
Debug
UARTs
For debug
Master sub-system
(Customer programmed)
Test/
Debug
JTAG for debug/
development
Phase
Shift
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Phase
Shift
Synth
(20 GHz)
Ramp
Generator
PA
x3
C674x DSP
@600 MHz
High-speed input for
hardware-in-loop verification
Phase
Shift
ADC
Buffer
PA
GPADC
Osc.
(IWR6843 only)
6
HW
Accel
L1P
(32kB)
L1D
(32kB)
L2
(256kB)
Temp
DMA
CRC
Radar Data Memory
(L3)
DSP sub-system
(Customer programmed)
RF/Analog sub-system
Figure 4-1. Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagram................................................................ 8
7.2 Pin Attributes.............................................................13
7.3 Signal Descriptions................................................... 21
8 Specifications................................................................ 26
8.1 Absolute Maximum Ratings...................................... 26
8.2 ESD Ratings............................................................. 26
8.3 Power-On Hours (POH)............................................26
8.4 Recommended Operating Conditions.......................27
8.5 Power Supply Specifications.....................................28
8.6 Power Consumption Summary................................. 29
8.7 RF Specification........................................................30
8.8 CPU Specifications................................................... 30
8.9 Thermal Resistance Characteristics for FCBGA
9 Detailed Description......................................................55
9.1 Overview...................................................................55
9.2 Functional Block Diagram.........................................55
9.3 Subsystems.............................................................. 56
9.4 Other Subsystems.................................................... 60
10 Monitoring and Diagnostics....................................... 62
10.1 Monitoring and Diagnostic Mechanisms................. 62
11 Applications, Implementation, and Layout............... 67
11.1 Application Information............................................67
11.2 Reference Schematic..............................................67
12 Device and Documentation Support..........................68
12.1 Device Nomenclature..............................................68
12.2 Tools and Software................................................. 69
12.3 Documentation Support.......................................... 69
12.4 Support Resources................................................. 69
12.5 Trademarks.............................................................70
12.6 Electrostatic Discharge Caution..............................70
12.7 Glossary..................................................................70
13 Mechanical, Packaging, and Orderable
Information.................................................................... 71
13.1 Packaging Information............................................ 71
13.2 Tray Information for ABL, 10.4 × 10.4 mm..............75
Package [ABL0161].....................................................31
8.10 Timing and Switching Characteristics..................... 32
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5 Revision History
Changes from May 31, 2020 to September 30, 2020 (from Revision C (May 2020) to Revision D
(Sept 2020))
Page
•
•
•
Global: Updated/Changed the numbering format for tables, figures, and cross-references throughout the
document............................................................................................................................................................1
Section 1 Added "Embedded self-monitoring with no host processor involvement on Functional Safety-
compliant devices" and "Non-functional safety variants" ...................................................................................1
Description: Added Functional Safety-Compliant targeted production parts IWR6843ABGABLR and
IWR6843ABGABL. Changed/Updated paragraph..............................................................................................2
Table 6-1 Added row showing "Functional Safety-Compliant (SIL-2)" and "Non-Functional safety variant".......6
Section 8.5: Added " Ripple Specifications" table and the preceeding paragraph. Added table note for Power
Supply Rails Characteristics.............................................................................................................................28
Table 8-3 (Maximum Current Ratings at Power Terminals): Updated/Changed the associated footnote table
references.........................................................................................................................................................29
Section 8.7 (RF Specification): Updated/Changed the "1-db Compression Point …" footnote........................ 30
Section 8.9 (Thermal Resistance Characteristics for FCBGA Package [ABL0161]): Removed "A junction
temperature of 105C is assumed" from footnote.............................................................................................. 31
Section 9.3.2 Updated/Added paragraph about the IWR6443 device features supported/not supported........59
Section 10.1 Added Monitoring and Diagnostic chapter...................................................................................62
Applications, Implementation, and Layout: Updated/Changed section............................................................ 67
Applications, Implementation, and Layout: Removed Layout section ............................................................. 67
Deleted "Related Links" section........................................................................................................................68
Section 13.2 (Tray Information for ABL, 10.4 × 10.4 mm): Added new section with tray information...............75
•
•
•
•
•
•
•
•
•
•
•
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6 Device Comparison
Unless otherwise noted, the device-specific information, in this document, relates to both the IWR6843 and
IWR6443 devices. The device differences are highlighted in Table 6-1, Device Features Comparison.
Table 6-1. Device Features Comparison
FUNCTION
IWR6843AOP
IWR6843
IWR6443
IWR1843
IWR1642
IWR1443
Antenna on Package (AOP)
Number of receivers
Number of transmitters
RF frequency range
On-chip memory
Yes
—
—
—
—
—
4
4
3(1)
4
4
4
4
3(1)
3(1)
3(1)
2
3
76 to 81 GHz
576KB
15
60 to 64 GHz
60 to 64 GHz
1.75MB
10
60 to 64 GHz
76 to 81 GHz
76 to 81 GHz
1.75MB
10
1.4MB
10
2MB
10
1.5MB
5
Max I/F (Intermediate Frequency) (MHz)
Max real sampling rate (Msps)
Max complex sampling rate (Msps)
SIL
25
25
25
25
12.5
6.25
—
37.5
12.5
—
12.5
12.5
—
12.5
—
18.75
—
2-Targeted
Yes
Non-Functional safety variant
Processors
Yes
Yes
Yes
Yes
Yes
MCU (R4F)
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
—
DSP (C674x)
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
Controller Area Network (CAN-FD) interface
Trace
2
2
2
2
2
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
—
—
PWM
—
Hardware In Loop (HIL/DMM)
GPADC
—
Yes
Yes
Yes
Yes
Yes
Yes
2
LVDS/Debug
CSI2
Hardware accelerator
1-V bypass mode
Yes
Yes
Yes
3
Yes
Yes
Yes
3
Yes
Yes
Yes
3
Yes
Yes
Yes
—
Yes
Yes
2
JTAG
Number of Tx that can be simultaneously
used
3
Product Preview (PP),
Product
Advance Information (AI),
status
AI(2)
PD(3)
PD(3)
PD(3)
PD(3)
PD(3)
or Production Data (PD)
(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to
be fed on the VOUT PA pin.
(2) ADVANCE INFORMATION for pre-production products; subject to change without notice.
(3) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty.
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6.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less
power using the smallest footprint mmWave sensor portfolio for industrial applications.
mmWave IWR
The Texas Instruments IWRxxxx family of mmWave Sensors are highly integrated and built
on RFCMOS technology operating in 76- to 81-GHz or 60- to 64-GHz frequency band. The
devices have a closed-loop PLL for precise and linear chirp synthesis, includes a built-in
radio processor (BIST) for RF calibration and safety monitoring. The devices have a very
small-form factor, low power consumption, and are highly accurate. Industrial applications
from long range to ultra short range can be realized using these devices.
Companion
products for
IWR6843
Review products that are frequently purchased or used in conjunction with this product.
Reference
designs for
IWR6843
The IWR6843 TI Designs Reference Design Library is a robust reference design library
spanning analog, embedded processor and connectivity. Created by TI experts to help you
jump-start your system design, all TI Designs include schematic or block diagrams, BOMs,
and design files to speed your time to market. Search and download designs at ti.com/
tidesigns.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
Figure 7-1 shows the pin locations for the 161-pin FCBGA package. Figure 7-2, Figure 7-3, Figure 7-4, and
Figure 7-5 show the same pins, but split into four quadrants.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOUT
_14APLL
OSC
_CLKOUT
VSSA
VSSA
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
VSSA
VOUT_
14SYNTH
VIN
_18CLK
VIN
_18VCO
VSSA
VSSA
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VSSA
VSSA
VBGAP
VSSA
VSSA
CLKP
CLKM
VIN
_13RF2
VSSA
VSSA
VSSA
GPADC5
VIOIN_
18DIFF
VIN
_13RF2
SPIA_MOSI
GPADC6
VSSA
VSSA
VSSA
VSSA
VSSA
RX4
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPIA_CLK
SPIA_MISO
SPIB_CLK
SPIB_MISO
SPIA_CS_N
SPIB_MOSI
VIN_18BB
VSS
VSS
VSS
VIOIN
VIN
_13RF1
G
H
J
VSSA
RX3
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
SYNC_OUT
GPIO_0
GPIO_1
GPIO_2
VPP
VIN_SRAM
VIN
_13RF1
VSSA
VSS
SPIB_CS_N
VDDIN
VIN
_13RF1
VSSA
RX2
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
LVDS_TXP[0] LVDS_TXM[0]
LVDS_TXP[1] LVDS_TXM[1]
LVDS_CLKP LVDS_CLKM
K
L
VSSA
VIN_18BB
VSS
VSSA
RX1
VSSA
VSS
LVDS
_FRCLKP
LVDS
_FRCLKM
M
N
P
R
VSSA
NERROR
_OUT
MCU
_CLKOUT
WARM
_RESET
VSSA
GPADC1
VSSA
VSSA
GPADC2
GPADC4
VSSA
RS232_RX
RS232_TX
GPIO_32
GPIO_33
NERROR_IN
GPIO_36
TMS
TCK
VDDIN
QSPI_CS_N
TDI
QSPI[1]
QSPI[3]
TDO
DMM_SYNC
GPIO_47
VDDIN
PMIC
_CLKOUT
SPI_HOST
_INTR
GPIO_34
VDDIN
GPADC3
NRESET
SYNC_IN
GPIO_31
GPIO_38
GPIO_37
VNWA
GPIO_35
VIOIN_18
VIOIN
QSPI_CLK
QSPI[0]
QSPI[2]
VSS
Not to scale
Figure 7-1. Pin Diagram
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1
2
3
4
5
6
7
8
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
VSSA
VSSA
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VIN
_13RF2
VSSA
VSSA
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
RX4
VIN_18BB
VIN
_13RF1
G
VSSA
VSSA
VSS
VSS
VSS
Not to scale
1
3
2
4
Figure 7-2. Top Left Quadrant
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9
10
11
12
13
14
15
VOUT
OSC
A
B
C
D
E
F
VSSA
VSSA
VSSA
_14APLL
_CLKOUT
VIN
_18CLK
VIN
VOUT
VSSA
VSSA
VBGAP
VSSA
VSSA
CLKP
CLKM
_18VCO
_14SYNTH
GPADC5
SPIA_MOSI
SPIA_CLK
SPIB_MOSI
SYNC_OUT
VIOIN
_18DIFF
GPADC6
SPIA_MISO
SPIB_CLK
SPIB_MISO
SPIA_CS_N
VSS
VSS
VSS
VSS
VIOIN
VSS
VIN_SRAM
G
Not to scale
1
3
2
4
Figure 7-3. Top Right Quadrant
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1
2
3
4
5
6
7
8
VIN
_13RF1
H
RX3
VSSA
VSS
VIN
_13RF1
J
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
K
L
RX2
VIN_18BB
VSSA
VSSA
VSSA
VSS
VSS
M
N
P
R
RX1
VSSA
NERROR
_OUT
MCU
_CLKOUT
VSSA
GPADC1
VSSA
VSSA
VSSA
RS232_RX
SYNC_IN
GPIO_31
RS232_TX
GPIO_32
GPIO_33
NERROR_IN
GPADC2
GPADC4
GPADC3
NRESET
GPIO_34
GPIO_36
GPIO_38
VDDIN
GPIO_35
GPIO_37
Not to scale
1
3
2
4
Figure 7-4. Bottom Left Quadrant
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9
10
11
12
13
14
15
H
J
VSS
VSS
GPIO_0
SPIB_CS_N
VDDIN
VSS
VSS
VSS
GPIO_1
GPIO_2
VPP
LVDS_TXP[0] LVDS_TXM[0]
LVDS_TXP[1] LVDS_TXM[1]
LVDS_CLKP LVDS_CLKM
K
L
VSS
VSS
LVDS
_FRCLKP
LVDS
_FRCLKM
M
N
P
R
WARM
_RESET
GPIO_47
VDDIN
TMS
TCK
VDDIN
QSPI_CS_N
TDI
QSPI[1]
QSPI[3]
QSPI_clk
TDO
DMM_SYNC
PMIC
_CLKOUT
SPI_HOST_
INTR_1
VNWA
VIOIN_18
VIOIN
QSPI[0]
QSPI[2]
VSS
Not to scale
1
3
2
4
Figure 7-5. Bottom Right Quadrant
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7.2 Pin Attributes
Table 7-1. Pin Attributes (ABL0161 Package)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS[4]
H13
GPIO_0
GPIO_13
0xFFFFEA04
0
IO
IO
O
O
O
O
IO
IO
O
O
I
Output Disabled
Pull Down
GPIO_0
1
PMIC_CLKOUT
ADC_VALID
EPWM1B
2
9
10
11
0
ePWM2A
J13
GPIO_1
GPIO_16
0xFFFFEA08
Output Disabled
Pull Down
GPIO_1
1
SYNC_OUT
ADC_VALID
DMM_MUX_IN
SPIB_CS_N_1
SPIB_CS_N_2
EPWM1SYNCI
GPIO_26
2
7
12
13
14
15
0
IO
IO
I
K13
GPIO_2
0xFFFFEA64
IO
IO
O
O
O
O
O
O
O
O
O
IO
I
Output Disabled
Pull Down
GPIO_2
1
OSC_CLKOUT
MSS_UARTB_TX
BSS_UART_TX
SYNC_OUT
PMIC_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
TRACE_DATA_0
GPIO_31
2
7
8
9
10
11
12
13
0
R4
GPIO_31
0xFFFFEA7C
Output Disabled
Pull Down
1
DMM0
2
MSS_UARTA_TX
TRACE_DATA_1
GPIO_32
4
IO
O
IO
I
P5
R5
P6
GPIO_32
GPIO_33
GPIO_34
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
1
DMM1
2
TRACE_DATA_2
GPIO_33
0
O
IO
I
1
DMM2
2
TRACE_DATA_3
GPIO_34
0
O
IO
1
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Table 7-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS[4]
DMM3
2
I
EPWM3SYNCO
TRACE_DATA_4
GPIO_35
4
O
O
IO
I
R7
P7
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_47
0xFFFFEA8C
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
Pull Down
Pull Down
1
DMM4
2
EPWM2SYNCO
TRACE_DATA_5
GPIO_36
4
O
O
IO
I
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEABC
0
1
DMM5
2
MSS_UARTB_TX
TRACE_DATA_6
GPIO_37
5
O
O
IO
I
R8
P8
0
1
DMM6
2
BSS_UART_TX
TRACE_DATA_7
GPIO_38
5
O
O
IO
I
0
1
DMM7
2
DSS_UART_TX
TRACE_CLK
GPIO_47
5
O
O
IO
I
N15
0
1
DMM_CLK
2
N14
N8
DMM_SYNC
TRACE_CTL
DMM_SYNC
GPIO_25
0xFFFFEAC0
0xFFFFEA60
0
O
I
Output Disabled
Output Disabled
Pull Down
Pull Down
2
MCU_CLKOUT
0
IO
O
O
O
O
O
I
MCU_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
EPWM1A
1
2
6
7
12
N7
N6
P9
NERROR_IN
NERROR_IN
NERROR_OUT
SOP[2]
0xFFFFEA44
0xFFFFEA4C
0xFFFFEA68
0
Input
NERROR_OUT
PMIC_CLKOUT
0
O
I
Hi-Z (Open Drain)
Output Disabled
During Power Up
Pull Down
GPIO_27
0
IO
O
O
O
O
O
O
PMIC_CLKOUT
CHIRP_START
CHIRP_END
FRAME_START
EPWM1B
1
6
7
8
11
12
EPWM2A
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Table 7-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS[4]
R13
N12
QSPI[0]
QSPI[1]
GPIO_8
0xFFFFEA2C
0
IO
IO
IO
IO
I
Output Disabled
Pull Down
QSPI[0]
1
SPIB_MISO
GPIO_9
2
0xFFFFEA30
0
Output Disabled
Pull Down
QSPI[1]
1
SPIB_MOSI
SPIB_CS_N_2
GPIO_10
2
IO
IO
IO
I
8
R14
P12
R12
QSPI[2]
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
0
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
QSPI[2]
1
CAN_FD_TX
GPIO_11
8
O
IO
I
QSPI[3]
0
QSPI[3]
1
CAN_FD_RX
GPIO_7
8
I
QSPI_CLK
0
IO
O
IO
O
IO
O
IO
IO
I
QSPI_CLK
SPIB_CLK
DSS_UART_TX
GPIO_6
1
2
6
P11
N4
QSPI_CS_N
RS232_RX
0xFFFFEA40
0xFFFFEA74
0
Output Disabled
Input Enabled
Pull Up
Pull Up
QSPI_CS_N
SPIB_CS_N
GPIO_15
1
2
0
RS232_RX
MSS_UARTA_RX
BSS_UART_TX
MSS_UARTB_RX
CAN_FD_RX
I2C_SCL
1
2
I
6
IO
IO
I
7
8
9
IO
O
O
O
IO
O
IO
IO
IO
O
IO
O
EPWM2A
10
11
12
0
EPWM2B
EPWM3A
N5
RS232_TX
GPIO_14
0xFFFFEA78
Output Enabled
RS232_TX
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
CAN_FD_TX
I2C_SDA
1
5
6
7
10
11
12
EPWM1A
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Table 7-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS[4]
EPWM1B
13
14
15
0
1
7
0
1
0
1
2
0
1
2
8
0
1
2
6
7
8
0
1
2
6
7
8
9
0
1
2
6
0
1
2
0
1
2
6
O
NDMM_EN
I
EPWM2A
O
E13
SPIA_CLK
GPIO_3
0xFFFFEA14
IO
IO
O
Output Disabled
Pull Up
SPIA_CLK
DSS_UART_TX
GPIO_30
E15
E14
SPIA_CS_N
SPIA_MISO
0xFFFFEA18
0xFFFFEA10
IO
IO
IO
IO
O
Output Disabled
Output Disabled
Pull Up
Pull Up
SPIA_CS_N
GPIO_20
SPIA_MISO
CAN_FD_TX
GPIO_19
D13
F14
SPIA_MOSI
SPIB_CLK
0xFFFFEA0C
0xFFFFEA24
IO
IO
I
Output Disabled
Output Disabled
Pull Up
Pull Up
SPIA_MOSI
CAN_FD_RX
DSS_UART_TX
GPIO_5
O
IO
IO
I
SPIB_CLK
MSS_UARTA_RX
MSS_UARTB_TX
BSS_UART_TX
CAN_FD_RX
GPIO_4
O
O
I
H14
SPIB_CS_N
0xFFFFEA28
IO
IO
O
Output Disabled
Pull Up
SPIB_CS_N
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
QSPI_CLK_EXT
CAN_FD_TX
GPIO_22
O
IO
I
O
G14
SPIB_MISO
0xFFFFEA20
IO
IO
IO
O
Output Disabled
Pull Up
SPIB_MISO
I2C_SCL
DSS_UART_TX
GPIO_21
F13
P13
SPIB_MOSI
0xFFFFEA1C
0xFFFFEA00
IO
IO
IO
IO
O
Output Disabled
Output Disabled
Pull Up
SPIB_MOSI
I2C_SDA
SPI_HOST_INTR
GPIO_12
Pull Down
SPI_HOST_INTR
ADC_VALID
SPIB_CS_N_1
O
IO
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Table 7-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
MODE [5] [9]
TYPE [6]
ADDRESS[4]
P4
SYNC_IN
GPIO_28
0xFFFFEA6C
0
IO
I
Output Disabled
Pull Down
SYNC_IN
1
MSS_UARTB_RX
DMM_MUX_IN
SYNC_OUT
SOP[1]
6
IO
I
7
9
O
I
G13
SYNC_OUT
0xFFFFEA70
During Power Up
Output Disabled
Pull Down
GPIO_29
0
IO
O
I
SYNC_OUT
DMM_MUX_IN
SPIB_CS_N_1
SPIB_CS_N_2
GPIO_17
1
9
10
IO
IO
IO
I
11
P10
TCK
0xFFFFEA50
0
Input Enabled
Pull Down
Pull Up
TCK
1
MSS_UARTB_TX
CAN_FD_TX
GPIO_23
2
O
O
IO
I
8
R11
N13
TDI
0xFFFFEA58
0xFFFFEA5C
0
Input Enabled
TDI
1
MSS_UARTA_RX
SOP[0]
2
I
TDO
During Power Up
I
Output Enabled
GPIO_24
0
1
2
6
7
9
0
1
2
6
0
IO
O
O
O
O
I
TDO
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
NDMM_EN
GPIO_18
N10
N9
TMS
0xFFFFEA54
0xFFFFEA48
IO
I
Input Enabled
Pull Down
TMS
BSS_UART_TX
CAN_FD_RX
WARM_RESET
O
I
WARM_RESET
IO
Hi-Z Input (Open
Drain)
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
4. PINCNTL ADDRESS: MSS Address for PinMux Control
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5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit
range value.
6. TYPE: Signal type and direction:
•
•
•
I = Input
O = Output
IO = Input or Output
7. BALL RESET STATE: The state of the terminal at power-on reset
8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
•
•
•
Pull Up: Internal pullup
Pull Down: Internal pulldown
An empty box means No pull.
9. Pin Mux Control Value maps to lower 4 bits of register.
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IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Table 7-2. PAD IO Control Registers
Default Pin/Ball Name
SPI_HOST_INTR
GPIO_0
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA00
0xFFFFEA04
0xFFFFEA08
0xFFFFEA0C
0xFFFFEA10
0xFFFFEA14
0xFFFFEA18
0xFFFFEA1C
0xFFFFEA20
0xFFFFEA24
0xFFFFEA28
0xFFFFEA2C
0xFFFFEA30
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
0xFFFFEA40
0xFFFFEA44
0xFFFFEA48
0xFFFFEA4C
0xFFFFEA50
0xFFFFEA54
0xFFFFEA58
0xFFFFEA5C
0xFFFFEA60
0xFFFFEA64
0xFFFFEA68
0xFFFFEA6C
0xFFFFEA70
0xFFFFEA74
0xFFFFEA78
P13
H13
J13
D13
E14
E13
E15
F13
G14
F14
H14
R13
N12
R14
P12
R12
P11
N7
GPIO_1
SPIA_MOSI
SPIA_MISO
SPIA_CLK
SPIA_CS_N
SPIB_MOSI
SPIB_MISO
SPIB_CLK
SPIB_CS_N
QSPI[0]
QSPI[1]
QSPI[2]
QSPI[3]
QSPI_CLK
QSPI_CS_N
NERROR_IN
WARM_RESET
NERROR_OUT
TCK
N9
N6
P10
N10
R11
N13
N8
TMS
TDI
TDO
MCU_CLKOUT
GPIO_2
K13
P9
PMIC_CLKOUT
SYNC_IN
P4
SYNC_OUT
RS232_RX
RS232_TX
G13
N4
N5
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Table 7-2. PAD IO Control Registers (continued)
Default Pin/Ball Name
GPIO_31
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA7C
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0xFFFFEA8C
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEABC
0xFFFFEAC0
R4
P5
GPIO_32
GPIO_33
R5
P6
GPIO_34
GPIO_35
R7
P7
GPIO_36
GPIO_37
R8
P8
GPIO_38
GPIO_47
N15
N14
DMM_SYNC
The register layout is as follows:
Table 7-3. PAD IO Register Bit Descriptions
RESET (POWER
ON DEFAULT)
BIT
FIELD
TYPE
DESCRIPTION
31-11 NU
RW
RW
0
0
Reserved
10
9
SC
IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
PUPDSEL
PI
RW
RW
0
0
Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8
Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7
6
OE_OVERRIDE
RW
RW
1
1
Output Override
OE_OVERRIDE_CTRL
Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is
associated with for example a SPI Chip select)
5
4
IE_OVERRIDE
RW
RW
0
0
Input Override
IE_OVERRIDE_CTRL
Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0
FUNC_SEL
RW
1
Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)
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7.3 Signal Descriptions
Note
All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-
failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being
present to the device.
Note
The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the
application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should
be used to isolate the GPIO output from the radar device and a pull resister used to define the
required state in the application. The NRESET signal to the radar device could be used to control the
output enable (OE) of the tri-state buffer.
7.3.1 Signal Descriptions - Digital
SIGNAL NAME
BSS_UART_TX
PIN TYPE
DESCRIPTION
Debug UART Transmit [Radar Block]
BALL NO.
F14, H14, K13, N10, N13,
N4, N5, R8
O
CAN_FD_RX
CAN_FD_TX
DMM0
I
O
I
CAN FD (MCAN) Receive Signal
D13, F14, N10, N4, P12
CAN FD (MCAN) Transmit Signal
E14, H14, N5, P10, R14
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Clock
R4
P5
DMM1
I
DMM2
I
R5
P6
DMM3
I
DMM4
I
R7
P7
DMM5
I
DMM6
I
R8
P8
DMM7
I
DMM_CLK
I
N15
Debug Interface (Hardware In Loop) Mux Select between DMM1 and
DMM2 (Two Instances)
DMM_MUX_IN
I
G13, J13, P4
DMM_SYNC
DSS_UART_TX
EPWM1A
EPWM1B
EPWM1SYNCI
EPWM2A
EPWM2B
EPWM2SYNCO
EPWM3A
EPWM3SYNCO
GPIO_0
I
Debug Interface (Hardware In Loop) - Sync
Debug UART Transmit [DSP]
PWM Module 1 - Output A
PWM Module 1 - Output B
PWM Module 1 - Sync Input
PWM Module 2- Output A
PWM Module 2 - Output B
PWM Module 2 - Sync Output
PWM Module 3 - Output A
PWM Module 3 - Sync Output
General-purpose I/O
N14
O
D13, E13, G14, P8, R12
O
N5, N8
O
H13, N5, P9
I
J13
O
H13, N4, N5, P9
O
N4
R7
O
O
N4
O
P6
IO
IO
IO
IO
IO
IO
IO
H13
J13
K13
E13
H14
F14
P11
GPIO_1
General-purpose I/O
GPIO_2
General-purpose I/O
GPIO_3
General-purpose I/O
GPIO_4
General-purpose I/O
GPIO_5
General-purpose I/O
GPIO_6
General-purpose I/O
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BALL NO.
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
SIGNAL NAME
GPIO_7
PIN TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
DESCRIPTION
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
I2C Clock
R12
R13
N12
R14
P12
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
P13
GPIO_13
H13
N5
GPIO_14
GPIO_15
N4
GPIO_16
J13
GPIO_17
P10
GPIO_18
N10
D13
E14
GPIO_19
GPIO_20
GPIO_21
F13
GPIO_22
G14
R11
GPIO_23
GPIO_24
N13
N8
GPIO_25
GPIO_26
K13
GPIO_27
P9
GPIO_28
P4
GPIO_29
G13
C13
R4
GPIO_30
GPIO_31
GPIO_32
P5
GPIO_33
R5
GPIO_34
P6
GPIO_35
R7
GPIO_36
P7
GPIO_37
R8
GPIO_38
P8
GPIO_47
N15
G14, N4
F13, N5
J14
I2C_SCL
I2C_SDA
I2C Data
LVDS_TXP[0]
LVDS_TXM[0]
LVDS_TXP[1]
LVDS_TXM[1]
LVDS_CLKP
LVDS_CLKM
LVDS_FRCLKP
LVDS_FRCLKM
MCU_CLKOUT
MSS_UARTA_RX
MSS_UARTA_TX
Differential data Out – Lane 0
Differential data Out – Lane 1
Differential clock Out
O
J15
O
K14
O
K15
O
L14
O
L15
O
M14
M15
N8
Differential Frame Clock
O
O
Programmable clock given out to external MCU or the processor
Master Subsystem - UART A Receive
I
F14, N4, R11
H14, N13, N5, R4
O
Master Subsystem - UART A Transmit
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SIGNAL NAME
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
PIN TYPE
DESCRIPTION
Master Subsystem - UART B Receive
BALL NO.
MSS_UARTB_RX
MSS_UARTB_TX
NDMM_EN
IO
N4, P4
F14, H14, K13, N13, N5,
P10, P7
O
I
Master Subsystem - UART B Transmit
Debug Interface (Hardware In Loop) Enable - Active Low Signal
N13, N5
Failsafe input to the device. Nerror output from any other device can
be concentrated in the error signaling monitor module inside the
device and appropriate action can be taken by Firmware
NERROR_IN
I
N7
Open drain fail safe output signal. Connected to PMIC/
Processor/MCU to indicate that some severe criticality fault has
happened. Recovery would be through reset.
NERROR_OUT
O
N6
PMIC_CLKOUT
QSPI[0]
O
IO
I
Output Clock from IWR6843 device for PMIC
QSPI Data Line #0 (Used with Serial Data Flash)
QSPI Data Line #1 (Used with Serial Data Flash)
QSPI Data Line #2 (Used with Serial Data Flash)
QSPI Data Line #3 (Used with Serial Data Flash)
QSPI Clock (Used with Serial Data Flash)
QSPI Clock (Used with Serial Data Flash)
QSPI Chip Select (Used with Serial Data Flash)
Debug UART (Operates as Bus Master) - Receive Signal
Debug UART (Operates as Bus Master) - Transmit Signal
Sense On Power - Line#0
H13, K13, P9
R13
QSPI[1]
N12
QSPI[2]
I
R14
QSPI[3]
I
P12
QSPI_CLK
QSPI_CLK_EXT
QSPI_CS_N
RS232_RX
RS232_TX
SOP[0]
O
I
R12
H14
O
I
P11
N4
O
I
N5
N13
SOP[1]
I
Sense On Power - Line#1
G13
SOP[2]
I
Sense On Power - Line#2
P9
SPIA_CLK
SPIA_CS_N
SPIA_MISO
SPIA_MOSI
SPIB_CLK
SPIB_CS_N
SPIB_CS_N_1
SPIB_CS_N_2
SPIB_MISO
SPIB_MOSI
SPI_HOST_INTR
SYNC_IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
I
SPI Channel A - Clock
E13
SPI Channel A - Chip Select
E15
SPI Channel A - Master In Slave Out
SPI Channel A - Master Out Slave In
SPI Channel B - Clock
E14
D13
F14, R12
SPI Channel B Chip Select (Instance ID 0)
SPI Channel B Chip Select (Instance ID 1)
SPI Channel B Chip Select (Instance ID 2)
SPI Channel B - Master In Slave Out
SPI Channel B - Master Out Slave In
Out of Band Interrupt to an external host communicating over SPI
Low frequency Synchronization signal input
Low Frequency Synchronization Signal output
JTAG Test Clock
H14, P11
G13, J13, P13
G13, J13, N12
G14, R13
F13, N12
P13
P4
SYNC_OUT
TCK
O
I
G13, J13, K13, P4
P10
R11
N13
N10
N15
N14
R4
TDI
I
JTAG Test Data Input
TDO
O
I
JTAG Test Data Output
TMS
JTAG Test Mode Signal
TRACE_CLK
TRACE_CTL
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
TRACE_DATA_4
O
O
O
O
O
O
O
Debug Trace Output - Clock
Debug Trace Output - Control
Debug Trace Output - Data Line
Debug Trace Output - Data Line
P5
Debug Trace Output - Data Line
R5
Debug Trace Output - Data Line
P6
Debug Trace Output - Data Line
R7
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BALL NO.
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
SIGNAL NAME
TRACE_DATA_5
PIN TYPE
DESCRIPTION
Debug Trace Output - Data Line
O
O
O
O
O
O
O
P7
TRACE_DATA_6
TRACE_DATA_7
FRAME_START
CHIRP_START
CHIRP_END
Debug Trace Output - Data Line
R8
Debug Trace Output - Data Line
P8
Pulse signal indicating the start of each frame
Pulse signal indicating the start of each chirp
Pulse signal indicating the end of each chirp
When high, indicating valid ADC samples
N8, K13, P9
N8, K13, P9
N8, K13, P9
P13, H13
ADC_VALID
Open drain fail safe warm reset signal. Can be driven from PMIC for
diagnostic or can be used as status signal that the device is going
through reset.
WARM_RESET
IO
N9
7.3.2 Signal Descriptions - Analog
PIN
TYPE
INTERFACE
SIGNAL NAME
DESCRIPTION
Single ended transmitter1 o/p
BALL NO.
TX1
TX2
TX3
RX1
RX2
RX3
RX4
O
O
O
I
B4
B6
B8
M2
K2
H2
F2
R3
Transmitters
Single ended transmitter2 o/p
Single ended transmitter3 o/p
Single ended receiver1 i/p
Single ended receiver2 i/p
Single ended receiver3 i/p
Single ended receiver4 i/p
Power on reset for chip. Active low
I
Receivers
Reset
I
I
NRESET
I
In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input
reference clock port
CLKP
I
I
B15
Reference
Oscillator
In XTAL mode: Differential port for reference crystal
In External clock mode: Connect this port to ground
CLKM
C15
A14
Reference clock output from clocking subsystem
after cleanup PLL (1.4V output voltage swing).
Reference clock
Bandgap voltage
OSC_CLKOUT
O
O
VBGAP
VDDIN
Device's Band Gap Reference Output
B10
H15, N11, P15, R6
G15
Power 1.2V digital power supply
VIN_SRAM
VNWA
Power 1.2V power rail for internal SRAM
Power 1.2V power rail for SRAM array back bias
P14
I/O Supply (3.3V or 1.8V): All CMOS I/Os would
operate on this supply
VIOIN
Power
R10, F15
Power supply
VIOIN_18
VIN_18CLK
VIOIN_18DIFF
VPP
Power 1.8V supply for CMOS IO
Power 1.8V supply for clock module
Power 1.8V supply for LVDS port
Power Voltage supply for fuse chain
R9
B11
D15
L13
1.3V Analog and RF supply,VIN_13RF1 and
Power
VIN_13RF1
G5, H5, J5
VIN_13RF2 could be shorted on the board
VIN_13RF2
VIN_18BB
VIN_18VCO
Power 1.3V Analog and RF supply
Power 1.8V Analog base band power supply
Power 1.8V RF VCO supply
C2,D2
K5, F5
B12
Power supply
L5, L6, L8, L10, K7,
K8, K9, K10, K11,
J6, J7, J8, J10, H7,
H9, H11, G6, G7,
G8, G10, F9, F11,
E5, E6, E8, E10,
E11, R15
VSS
Ground Digital ground
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INTERFACE
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PIN
TYPE
SIGNAL NAME
DESCRIPTION
BALL NO.
A1, A3, A5, A7, A9,
A13, A15, B1, B3,
B5, B7, B9, B14,
C1, C3, C4, C5, C6,
C7, C8, C9, C14,
E1, E2, E3, F3, G1,
G2, G3, H3, J1, J2,
J3, K3, L1, L2, L3,
M3, N1, N2, N3, R1
VSSA
Ground Analog ground
VOUT_14APLL
O
Internal LDO output
A10
B13
VOUT_14SYNTH
O
Internal LDO output
Internal LDO output.
Internal LDO output/
inputs
When internal PA LDO is used, this pin provides the
output voltage of the LDO. When the internal PA
LDO is bypassed, and disabled, the 1-V supply
should be fed on this pin. This is mandatory in the
3TX simultaneous use case.
VOUT_PA
IO
A2, B2
Analog Test1 / GPADC1
Analog Test2 / GPADC2
Analog Test3 / GPADC3
Analog Test4 / GPADC4
ANAMUX / GPADC5
IO
IO
IO
IO
IO
IO
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
Analog IO dedicated for ADC service
P1
Test and Debug
output for pre-
production phase.
Can be pinned out
on production
hardware for field
debug
P2
P3
R2
C13
D14
VSENSE / GPADC6
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8 Specifications
8.1 Absolute Maximum Ratings
PARAMETERS(1) (2)
MIN
–0.5
–0.5
–0.5
MAX
1.4
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
1.4
1.4
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for LVDS port
–0.5
–0.5
–0.5
2
2
2
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
VIN_13RF1
(1-V Internal LDO
bypass mode)
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be kept
bypassed.
–0.5
1.4
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN_18BB
1.8-V Analog baseband power supply
1.8-V RF VCO supply
–0.5
–0.5
2
2
V
V
VIN_18VCO supply
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
VIOIN + 0.3
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal
–0.5
2
V
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
–55
105
150
°C
°C
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM)(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002
(1) ANSI/ESDA/JEDEC JS0991 specification.
8.3 Power-On Hours (POH)
JUNCTION
OPERATING
TEMPERATURE (Tj)
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
CONDITION
(1)
105°C Tj
50% RF duty cycle
1.2
100,000
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
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8.4 Recommended Operating Conditions
MIN
1.14
1.14
1.14
3.135
1.71
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
1.8
MAX
1.32
1.32
1.32
3.465
1.89
1.9
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
VIOIN
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for LVDS port
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
1.9
1.9
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
VIN_13RF1
(1-V Internal LDO
bypass mode)
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be
kept bypassed.
0.95
1
1.05
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN18BB
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.17
2.25
1.8
1.8
1.9
1.9
V
V
VIN_18VCO
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
VIH
VIL
V
V
0.3*VIOIN
0.62
VOH
VOL
VIOIN – 450
mV
mV
450
0.45
VIH (1.8V Mode)
0.96
1.57
NRESET
SOP[2:0]
V
VIL (3.3V Mode)
0.65
VIH (3.3V Mode)
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8.5 Power Supply Specifications
Table 8-1 describes the four rails from an external power supply block of the IWR6843 device.
Table 8-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
1.8 V
1.3 V (or 1 V in internal
LDO bypass mode)(1)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
(1) Three simultaneous transmitter operation is supported only in 1-V LDO
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 8-2 are defined to meet a
target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB
relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted
are rms levels for a sinusoidal input applied at the specified frequency.
Table 8-2. Ripple Specifications
RF RAIL
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
1.3 V (µVRMS
)
1.8 V (µVRMS)
(µVRMS
)
137.5
275
7
5
648
76
22
4
83
21
11
6
550
3
1100
2200
4400
6600
2
11
13
22
82
93
117
13
19
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8.6 Power Consumption Summary
Table 8-3 and Table 8-4 summarize the power consumption at the power terminals.
Table 8-3. Maximum Current Ratings at Power Terminals
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Total current drawn by all
nodes driven by 1.2V rail
VDDIN, VIN_SRAM, VNWA
1000
Total current drawn by all
nodes driven by 1.3V rail
(or 1V rail in LDO Bypass
mode), when only 2
VIN_13RF1, VIN_13RF2
2000
transmitters are used.(3)
Current consumption(1)
mA
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by all
nodes driven by 1.8V rail
850
50
Total current drawn by all
nodes driven by 3.3V
rail(2)
VIOIN
(1) The specified current values are at typical supply voltage level.
(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.
(3) Simultaneous 3 Transmitter operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply
needs to be fed on the VOUT_PA pin. In this case, the peak 1-V supply current goes up to 2500 mA. To enable the LDO bypass mode,
see the Interface Control document in the mmWave software development kit (SDK).
Table 8-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
MIN
TYP MAX UNIT
1TX, 4RX
Regular power ADC mode 6.4
Msps complex transceiver,
13.13-ms frame, 64 chirps, 256
samples/chirp, 8.5-µs interchirp
time, DSP + Hardware
1.19
24% duty cycle
2TX, 4RX(1)
1TX, 4RX
1.25
1.0-V internal
LDO bypass
mode
accelerator active
Average power
consumption
W
Regular power ADC mode 6.4
Msps complex transceiver,
13.13-ms frame, 64 chirps, 256
samples/chirp, 8.5-µs interchirp
time, DSP + Hardware
1.62
48% duty cycle
2TX, 4RX(1)
1.75
accelerator active
(1) Two TX antennas are on simultaneously.
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8.7 RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
12
MAX UNIT
dB
Noise figure
60 to 64 GHz
1-dB compression point (Out Of Band)(1)
–12
48
dBm
Maximum gain
dB
Gain range
18
dB
Gain step size
2
dB
Receiver
IF bandwidth(2)
10 MHz
25 Msps
12.5 Msps
Bits
A2D sampling rate (real)
A2D sampling rate (complex 1x)
A2D resolution
12
–90
12
Idle Channel Spurs
Output power
dBFS
dBm
Transmitter
Power backoff range
Frequency range
26
dB
60
64 GHz
250 MHz/µs
dBc/Hz
Clock
subsystem
Ramp rate
Phase noise at 1-MHz offset
60 to 64 GHz
–93
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off
frequency.
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set
of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
HPF2
175, 235, 350, 700
350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
8.8 CPU Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
600
32
MAX UNIT
Clock Speed
DSP
MHz
KB
L1 Code Memory
Subsystem
(C674
Family)
L1 Data Memory
32
KB
L2 Memory
256
200
512
192
KB
Master
Clock Speed
MHz
KB
Controller
Subsystem
(R4F Family)
Tightly Coupled Memory - A (Program)
Tightly Coupled Memory - B (Data)
KB
Shared
Memory
Shared L3 Memory
768
KB
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8.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
THERMAL METRICS(1)
°C/W(2) (3)
4.92
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
PsiJB
Junction-to-case
Junction-to-board
6.57
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
22.3
N/A (4)
4.92
6.4
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(4) N/A = not applicable
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8.10 Timing and Switching Characteristics
8.10.1 Power Supply Sequencing and Reset Timing
The IWR6843 device expects all external voltage rails to be stable before reset is deasserted. Figure 8-1
describes the device wake-up sequence.
SOP
Setup
Time
SOP
Hold time to
nRESET
DC power
Stable before
nRESET
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
DC
Power
notOK
DC
Power
OK
QSPI
READ
release
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP IO
Reuse
SOP IO‘s can be used as functional IO‘s
SOP[2.1.0]
nRESET
WARMRESET
OUTPUT
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
QSPI_CS
OUTPUT
8 ms (XTAL Mode)
850 µs (REFCLK Mode)
A. MCU_CLK_OUT in autonomous mode, where IWR6843 application is booted from the serial flash, MCU_CLK_OUT is not enabled by
default by the device bootloader.
Figure 8-1. Device Wake-up Sequence
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8.10.2 Input Clocks and Oscillators
8.10.2.1 Clock Specifications
The IWR6843 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for initial
boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device
pins. Figure 8-2 shows the crystal implementation.
Cf1
XTALP
Cp
40 MHz
XTALM
Cf2
Figure 8-2. Crystal Implementation
Note
The load capacitors, Cf1 and Cf2 in Figure 8-2, should be chosen such that Equation 1 is satisfied. CL
in the equation is the load specified by the crystal manufacturer. All discrete components used to
implement the oscillator circuit should be placed as close as possible to the associated oscillator
CLKP and CLKM pins.
C f2
CL = C f1
´
+CP
C
f1 +C f2
(1)
Table 8-5 lists the electrical characteristics of the clock crystal.
Table 8-5. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
fP
Parallel resonance crystal frequency
40
CL
Crystal load capacitance
Crystal ESR
5
8
12
50
ESR
Ω
Temperature range Expected temperature range of operation
–40
–50
105
°C
Frequency
Crystal frequency tolerance(1) (2) (3)
tolerance
50
ppm
µW
Drive level
50
200
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
(3) Crystal tolerance affects radar sensor accuracy.
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM
is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-6
lists the electrical characteristics of the external clock signal.
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Table 8-6. External Clock Mode Specifications
SPECIFICATION
PARAMETER
MIN
TYP
MAX
Frequency
40
MHz
mV (pp)
V
AC-Amplitude
700
0.00
1.6
1200
0.20
1.95
–132
–143
–152
–153
65
DC-Vil
DC-Vih
V
Input Clock:
External AC-coupled sine wave or DC-
coupled square wave
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
Phase Noise referred to 40 MHz
35
Freq Tolerance
Freq Tolerance
–50
–50
50
ppm
50
ppm
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8.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.10.3.1 Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The
MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or another
microcontroller.
Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
•
•
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals
8.10.3.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit
transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be
partitioned into multiple transfer group with variable number of buffers each.
Section 8.10.3.2.2 and Section 8.10.3.2.3 assume the operating conditions stated in Section 8.10.3.2.1.
8.10.3.2.1 SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
8.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
PARAMETER
Cycle time, SPICLK(4)
MIN
25
TYP
MAX UNIT
1
tc(SPC)M
256tc(VCLK)
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
2(4)
ns
3(4)
ns
ns
td(SPCH-
Delay time, SPISIMO valid before SPICLK low, (clock
polarity = 0)
SIMO)M
4(4)
td(SPCL-
Delay time, SPISIMO valid before SPICLK high, (clock
polarity = 1)
0.5tc(SPC)M – 3
SIMO)M
tv(SPCL-
Valid time, SPISIMO data valid after SPICLK low, (clock
polarity = 0)
0.5tc(SPC)M
–
10.5
SIMO)M
5(4)
ns
ns
tv(SPCH-
Valid time, SPISIMO data valid after SPICLK high, (clock
polarity = 1)
0.5tc(SPC)M
–
10.5
SIMO)M
CSHOLD = 0
(C2TDELAY
+2)*tc(VCLK)
(C2TDELAY+2)
* tc(VCLK) + 7
–
Setup time CS active until SPICLK
high
6(5)
tC2TDELAY
7.5
(clock polarity = 0)
CSHOLD = 1
(C2TDELAY +3)
* tc(VCLK) – 7.5
(C2TDELAY+3)
* tc(VCLK) + 7
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NO.
PARAMETER
MIN
TYP
CSHOLD = 0
CSHOLD = 1
(C2TDELAY
(C2TDELAY+2)
+2)*tc(VCLK)
–
* tc(VCLK) + 7
Setup time CS active until SPICLK low
(clock polarity = 1)
7.5
(C2TDELAY +3)
* tc(VCLK) – 7.5
(C2TDELAY+3)
* tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M
(T2CDELAY +
1) *tc(VCLK) – 7
+
0.5*tc(SPC)M
(T2CDELAY +
1) * tc(VCLK)
7.5
+
+
7(5)
tT2CDELAY
ns
0.5*tc(SPC)M
+
0.5*tc(SPC)M
+
(T2CDELAY +
1) *tc(VCLK) – 7
(T2CDELAY +
1) * tc(VCLK)
+
7.5
tsu(SOMI-
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
5
3
3
SPCL)M
8(4)
ns
ns
tsu(SOMI-
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
SPCH)M
th(SPCL-
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
SOMI)M
9(4)
th(SPCH-
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
SOMI)M
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
11
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 8-3. SPI Master Mode External Timing (CLOCK PHASE = 0)
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Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 8-4. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
8.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
PARAMETER
Cycle time, SPICLK(4)
MIN
25
TYP
MAX UNIT
1
tc(SPC)M
256tc(VCLK)
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
ns
3(4)
ns
ns
td(SPCH-
Delay time, SPISIMO valid before SPICLK low, (clock polarity 0.5tc(SPC)M – 3
= 0)
SIMO)M
4(4)
td(SPCL-
Delay time, SPISIMO valid before SPICLK high, (clock
polarity = 1)
0.5tc(SPC)M – 3
SIMO)M
tv(SPCL-
Valid time, SPISIMO data valid after SPICLK low, (clock
polarity = 0)
0.5tc(SPC)M
–
10.5
SIMO)M
5(4)
ns
tv(SPCH-
Valid time, SPISIMO data valid after SPICLK high, (clock
polarity = 1)
0.5tc(SPC)M
–
10.5
SIMO)M
tC2TDELAY
Setup time CS active until SPICLK
high
(clock polarity = 0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
(C2TDELAY +
2)*tc(VCLK) – 7
0.5*tc(SPC)M
(C2TDELAY
+2) * tc(VCLK)
7.5
+
+
0.5*tc(SPC)M
(C2TDELAY +
2)*tc(VCLK) – 7
+
0.5*tc(SPC)M
+
(C2TDELAY
+2) * tc(VCLK)
+
7.5
6(5)
ns
0.5*tc(SPC)M
(C2TDELAY
+2)*tc(VCLK)
0.5*tc(SPC)M
+
0.5*tc(SPC)M
+
(C2TDELAY
–
7
+2) * tc(VCLK)
+
Setup time CS active until SPICLK
low
(clock polarity = 1)
7.5
+
0.5*tc(SPC)M
+
(C2TDELAY
(C2TDELAY
+3)*tc(VCLK)
–
7
+3) * tc(VCLK) +
7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY +
1) *tc(VCLK)
(T2CDELAY +
1) *tc(VCLK) + 7
–
7.5
7(5)
tT2CDELAY
ns
ns
(T2CDELAY +
(T2CDELAY +
1) *tc(VCLK) + 7
1) *tc(VCLK)
–
7.5
tsu(SOMI-
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
8(4)
5
SPCL)M
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NO.
PARAMETER
MIN
TYP
tsu(SOMI-
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
SPCH)M
th(SPCL-
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3
3
SOMI)M
9(4)
ns
th(SPCH-
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
SOMI)M
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns,
where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 8-5. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 8-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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8.10.3.3 SPI Slave Mode I/O Timings
8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output) (1) (2) (3)
NO.
PARAMETER
MIN
25
TYP
MAX
UNIT
1
tc(SPC)S
Cycle time, SPICLK(4)
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
td(SPCH-SOMI)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
10
2(5)
ns
ns
10
10
3(5)
10
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0)
10
10
4(5)
ns
ns
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
2
5(5)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
10
10
4(5)
5(5)
6(5)
7(5)
ns
ns
ns
ns
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
2
2
3
3
1
1
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
Setup time, SPISIMO before SPICLK low (clock
polarity = 0; clock phase = 0) OR (clock polarity =
1; clock phase = 1)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock
tsu(SIMO-SPCH)S polarity = 1; clock phase = 0) OR (clock polarity =
0; clock phase = 1)
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
th(SPCL-SIMO)S
(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
(3) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 8-7. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 8-8. SPI Slave Mode External Timing (CLOCK PHASE = 1)
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8.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 8-9 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x4321
0x1234
CRC
0x5678
0x8765
MOSI
MISO
IRQ
0xDCBA
0xABCD
CRC
16 bytes
Figure 8-9. SPI Communication
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8.10.4 LVDS Interface Configuration
The supported IWR6843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane
(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The
LVDS interface supports the following data rates:
•
•
•
•
•
•
•
900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 8-10. LVDS Interface Lane Configuration And Relative Timings
8.10.4.1 LVDS Interface Timings
Table 8-7. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Duty Cycle Requirements
max 1 pF lumped capacitive load on
LVDS lanes
48%
52%
Output Differential Voltage
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
250
450
mV
Output Offset Voltage
Trise and Tfall
1125
1275
mV
ps
20%-80%, 900 Mbps
900 Mbps
330
80
Jitter (pk-pk)
ps
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Trise
LVDS_CLK
Clock Jitter = 6sigma
LVDS_TXP/M
LVDS_FRCLKP/M
1100 ps
Figure 8-11. Timing Parameters
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8.10.5 General-Purpose Input/Output
Section 8.10.5.1 lists the switching characteristics of output timing relative to load capacitance.
8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (2)
PARAMETER
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
VIOIN = 3.3V
UNIT
2.8
6.4
9.4
2.8
6.4
9.4
3.3
6.7
9.6
3.1
6.6
9.6
3.0
6.9
tr
tf
tr
tf
Max rise time
CL = 50 pF
ns
CL = 75 pF
10.2
2.8
Slew control = 0
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
Max fall time
Max rise time
Max fall time
6.6
ns
ns
ns
9.8
3.3
7.2
10.5
3.1
Slew control = 1
6.6
9.6
(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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8.10.6 Controller Area Network - Flexible Data-rate (CAN-FD)
The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.
CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD
devices can coexist on the same network without any conflict.
The CAN-FD has the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Conforms with CAN Protocol 2.0 A, B and ISO 11898-1
Full CAN FD support (up to 64 data bytes per frame)
AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 11-bit filter elements
Internal Loopback mode for self-test
Mask-able interrupts, two interrupt lines
Two clock domains (CAN clock / Host clock)
Parity / ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
•
Full Message Memory capacity (4352 words).
8.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
UNIT
td(CAN_FD_tx)
td(CAN_FD_rx)
Delay time, transmit shift register to CAN_FD_tx
pin(1)
15
ns
Delay time, CAN_FD_rx pin to receive shift
register(1)
10
ns
(1) These values do not include rise/fall times of the output buffer.
8.10.7 Serial Communication Interface (SCI)
The SCI has the following features:
•
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Standard non-return to zero (NRZ) format
Double-buffered receive and transmit functions
Asynchronous or iso-synchronous communication modes with no CLK pin
Capability to use Direct Memory Access (DMA) for transmit and receive data
Two external pins: RS232_RX and RS232_TX
8.10.7.1 SCI Timing Requirements
MIN
TYP
921.6
MAX
UNIT
f(baud)
Supported baud rate at 20 pF
kHz
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8.10.8 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between
devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus™.
This module will support any slave or master I2C compatible device.
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398
393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-master transmitter/ slave receiver mode
– Multi-master receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
•
•
•
•
•
•
•
•
•
Note
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second byte every
time it sends the slave address first byte)
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8.10.8.1 I2C Timing Requirements (1)
STANDARD MODE
FAST MODE
MIN
10
MAX
MIN
2.5
MAX
tc(SCL)
Cycle time, SCL
μs
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low
(for a repeated START condition)
4.7
0.6
th(SCLL-SDAL)
Hold time, SCL low after SDA low
4
0.6
μs
(for a START and a repeated START condition)
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SCLL-SDA)
tw(SDAH)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45(1)
0.9
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high
(for STOP condition)
4
0.6
0
μs
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(2) (3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the
SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 8-12. I2C Timing Diagram
Note
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period
(tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode
I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line tr max + tsu(SDA-SCLH)
.
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8.10.9 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or quad read
access to external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI
works as a master only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash
memories.
The QSPI supports the following features:
•
•
•
•
•
•
•
Programmable clock divider
Six-pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Section 8.10.9.2 and Section 8.10.9.3 assume the operating conditions stated in Section 8.10.9.1.
8.10.9.1 QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
8.10.9.2 Timing Requirements for QSPI Input (Read) Timings (1) (2)
MIN
7.3
TYP
MAX
UNIT
ns
tsu(D-SCLK)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
1.5
ns
Setup time, final d[3:0] bit valid before final falling sclk edge
Hold time, final d[3:0] bit valid after final falling sclk edge
7.3 – P(3)
1.5 + P(3)
ns
ns
(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-
standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.
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8.10.9.3 QSPI Switching Characteristics
NO.
Q1
Q2
Q3
PARAMETER
Cycle time, sclk
MIN
12.5
TYP
MAX
UNIT
ns
tc(SCLK)
tw(SCLKL)
tw(SCLKH)
td(CS-SCLK)
Pulse duration, sclk low
Y*P – 3(1) (2)
Y*P – 3(1)
ns
Pulse duration, sclk high
ns
Delay time, sclk falling edge to cs active edge
–M*P + 2.5(1)
ns
Q4
Q5
–M*P – 1(1) (3)
N*P – 1(1) (3)
(3)
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge
N*P + 2.5(1)
ns
(3)
Q6
Q7
Q8
td(SCLK-D1)
tena(CS-D1LZ)
tdis(CS-D1Z)
td(SCLK-D1)
Delay time, sclk falling edge to d[1] transition
Enable time, cs active edge to d[1] driven (lo-z)
Disable time, cs active edge to d[1] tri-stated (hi-z)
–3.5
–P – 4(3)
–P – 4(3)
7
–P +1(3)
–P +1(3)
ns
ns
ns
ns
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
Q9
–3.5 – P(3)
7 – P(3)
Q12
Q13
tsu(D-SCLK)
th(SCLK-D)
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
7.3
1.5
ns
ns
ns
Setup time, final d[3:0] bit valid before final falling
sclk edge
Q14
Q15
7.3 — P(3)
1.5 + P(3)
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk
edge
ns
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/
2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period in ns.
(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2
PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_02
Figure 8-13. QSPI Read (Clock Mode 0)
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PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 8-14. QSPI Write (Clock Mode 0)
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8.10.10 ETM Trace Interface
Section 8.10.10.2 and List item. assume the recommended operating conditions stated in Section 8.10.10.1.
8.10.10.1 ETMTRACE Timing Conditions
MIN
TYP
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
2
20
pF
8.10.10.2 ETM TRACE Switching Characteristics
NO.
1
PARAMETER
Cycle time, TRACECLK period
Pulse Duration, TRACECLK High
Pulse Duration, TRACECLK Low
Clock and data rise time
MIN
TYP
MAX
UNIT
ns
tcyc(ETM)
th(ETM)
tl(ETM)
20
9
2
ns
3
9
ns
4
tr(ETM)
tf(ETM)
3.3
3.3
7
ns
5
Clock and data fall time
ns
td(ETMTRACE Delay time, ETM trace clock high to ETM data valid
1
1
ns
6
7
CLKH-
ETMDATAV)
td(ETMTRACE Delay time, ETM trace clock low to ETM data valid
7
ns
CLKl-
ETMDATAV)
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 8-15. ETMTRACECLKOUT Timing
Figure 8-16. ETMDATA Timing
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8.10.11 Data Modification Module (DMM)
A Data Modification Module (DMM) gives the ability to write external data into the device memory.
The DMM has the following features:
•
•
Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the
RAM trace port [RTP] module)
•
Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined
by direct data mode of RTP module)
•
•
Configurable port width (1, 2, 4, 8 pins)
Up to 100 Mbit/s pin data rate
8.10.11.1 DMM Timing Requirements
MIN
10
1
TYP
MAX
UNIT
ns
tcyc(DMM)
tR
Clock period
Clock rise time
3
3
ns
tF
Clock fall time
1
ns
th(DMM)
tl(DMM)
tssu(DMM)
tsh(DMM)
tdsu(DMM)
tdh(DMM)
High pulse width
6
ns
Low pulse width
6
ns
SYNC active to clk falling edge setup time
DMM clk falling edge to SYNC deactive hold time
DATA to DMM clk falling edge setup time
DMM clk falling edge to DATA hold time
2
ns
3
ns
2
ns
3
ns
tl(DMM)
th(DMM)
tf
tr
tcyc(DMM)
Figure 8-17. DMMCLK Timing
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 8-18. DMMDATA Timing
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8.10.12 JTAG Interface
Section 8.10.12.2 and Section 8.10.12.3 assume the operating conditions stated in Section 8.10.12.1.
8.10.12.1 JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
8.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
MAX
UNIT
ns
1
tc(TCK)
Cycle time TCK
66.66
26.67
26.67
2.5
1a
1b
tw(TCKH)
Pulse duration TCK high (40% of tc)
Pulse duration TCK low(40% of tc)
Input setup time TDI valid to TCK high
Input setup time TMS valid to TCK high
Input hold time TDI valid from TCK high
Input hold time TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
2.5
ns
18
ns
18
ns
8.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
25
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 8-19. JTAG Timing
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9 Detailed Description
9.1 Overview
The IWR6843 device includes the entire Millimeter Wave blocks and analog baseband signal chain for three
transmitters and four receivers, as well as a customer-programmable MCU and DSP. This device is applicable
as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity and application
code size. These could be cost-sensitive industrial radar sensing applications. Examples are:
•
•
•
•
•
•
Industrial-level sensing
Industrial automation sensor fusion with radar
Traffic intersection monitoring with radar
Industrial radar-proximity monitoring
People counting
Gesturing
In terms of scalability, the IWR6843 device could be paired with a low-end external MCU, to address more
complex applications that might require additional memory for a larger application software footprint and faster
interfaces. The IWR6843 has an embedded DSP for signal processing, processing the radar signals for FFT,
magnitude, detection, and other applications.
9.2 Functional Block Diagram
Serial Flash interface
QSPI
Cortex R4F
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
@ 200MHz
(User programmable)
Data
External MCU
interface
SPI
PMIC control
SPI / I2C
CAN-FD
Digital
Front-end
Prog RAM
Boot
ROM
CAN-FD Communication
RAM
(Decimation
filter chain)
DMA
Debug
UARTs
For debug
Master sub-system
(Customer programmed)
Test/
Debug
JTAG for debug/
development
Phase
Shift
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Phase
Shift
Synth
(20 GHz)
Ramp
Generator
PA
x3
C674x DSP
@600 MHz
High-speed input for
hardware-in-loop verification
Phase
Shift
ADC
Buffer
PA
GPADC
Osc.
(IWR6843 only)
6
HW
Accel
L1P
(32kB)
L1D
(32kB)
L2
(256kB)
Temp
DMA
CRC
Radar Data Memory
(L3)
DSP sub-system
(Customer programmed)
RF/Analog sub-system
Figure 9-1. Functional Block Diagram
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9.3 Subsystems
9.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,
IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit
channels can be operated up to a maximum of two at a time (simultaneously) in 1.3-V mode. The three Transmit
channels simultaneous operation is supported only with 1-V LDO bypass and PA LDO disabled mode for
transmit beamforming purpose, as required. In this mode, the 1-V supply needs to be fed on the VIN_13RF1,
VIN_13RF2, and VOUT PA pin; whereas, the four receive channels can all be operated simultaneously.
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9.3.1.1 Clock Subsystem
The IWR6843 clock subsystem generates 60 to 64 GHz from an input reference of 40-MHz crystal. It has a built-
in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is
then processed by an X3 multiplier to create the required frequency in the 60 to 64 GHz spectrum. The RF
synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor
operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the
quality of the generated clock.
Figure 9-2 describes the clock subsystem.
Self Test
SYNC_OUT
RX LO
Timing Engine
x3 MULT
SYNC_IN
TX LO
RFSYNTH
Lock Detect
Clean-Up
PLL
SoC
Clock
XO / Slicer
CLK Detect
OSC_CLKOUT
40 MHz
Figure 9-2. Clock Subsystem
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9.3.1.2 Transmit Subsystem
The IWR6843 transmit subsystem consists of three parallel transmit chains, each with independent phase and
amplitude control. The device supports 6-bit linear phase modulation for MIMO radar, Tx Beam forming
applications, and interference mitigation.
The transmit chains also support programmable backoff for system optimization.
Figure 9-3 describes the transmit subsystem.
Loopback
Path
Self Test
0 or 180°
(from Timing Engine)
PCB
50 W
DF
LO
6-bit Linear Phase
Shifter
Figure 9-3. Transmit Subsystem (Per Channel)
9.3.1.3 Receive Subsystem
The IWR6843 receive subsystem consists of four parallel channels. A single receive channel consists of an LNA,
mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational at the same
time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the IWR6843 device supports a complex baseband architecture, which
uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver
channel. The IWR6843 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff
frequencies above 175 kHz and can support bandwidths up to 10 MHz.
Figure 9-4 describes the receive subsystem.
Self Test
DAC
Loopback
Path
DSM
PCB
I
RSSI
50 W
GSG
LO
Q
DSM
DAC
Figure 9-4. Receive Subsystem (Per Channel)
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9.3.2 Processor Subsystem
Unified
128 KB x 2
ROM
L2
Cache/
RAM
TCM A 512 KB
Master
R4F
L1P
32 KB
32 KB
EDMA
DSP
HWA
HIL
JTAG
CRC
HIL
TCM B 192 KB
L1d
DSP/HWA Interconnect œ 128 bit @ 200 MHz
Master Interconnect
BSS Interconnect
Data
Handshake
Memory
CRC
ADC Buffer
Mail
Box
MSS
DMA
L3
32 KB
32 KB Ping-Pong
(static sharing
with R4F Space)
Interconnect
LVDS
PWM,
PMIC
CLK
I2C
QSPI
UART
CAN-FD
SPI
Figure 9-5. Processor Subsystem
Figure 9-5 shows the block diagram for customer programmable processor subsystems in the IWR6843 device.
At a high level there are two customer programmable subsystems, as shown separated by a dotted line in the
diagram. Left hand side shows the DSP Subsystem which contains TI's high-performance C674x DSP(IWR6843
only), hardware accelerator, a high-bandwidth interconnect for high performance (128-bit, 200MHz), and
associated peripherals – four DMAs for data transfer. LVDS interface for Measurement data output, L3 Radar
data cube memory, ADC buffers, CRC engine, and data handshake memory (additional memory provided on
interconnect).
The C674x DSP and L1/L2 RAM portion of the DSP subsystem is not supported on the IWR6443 device and
therefore, the available memory is 1.4MB compared to 1.75MB on the IWR6843 device. For more information on
the features supported and not supported on each device, see the Device Features Comparison table.
The right side of the diagram shows the Master subsystem. Master subsystem as name suggests is the master
of the device and controls all the device peripherals and house-keeping activities of the device. Master
subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and house-keeping
components such as DMAs, CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking module, PWM, and
others) connected to Master Interconnect through Peripheral Central Resource (PCR interconnect).
Details of the DSP CPU core can be found at https://www.ti.com/product/TMS320C6748.
HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the
captured data from outside into the device without involving the RF subsystem. HIL on master SS is for
controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL modules
uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of the two.
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9.3.3 Host Interface
The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial
interface for industrial applications is transcoded to a different serial standard.
The IWR6843 device communicates with the host radar processor over the following main interfaces:
•
•
Reference Clock – Reference clock available for host processor after device wakeup
Control – 4-port standard SPI (slave) for host control . All radio control commands (and response) flow
through this interface.
•
•
•
Reset – Active-low reset for device wakeup from host
Host Interrupt - an indication that the mmwave sensor needs host interface
Error – Used for notifying the host in case the radio controller detects a fault
9.3.4 Master Subsystem Cortex-R4F
The master system includes an ARM Cortex R4F processor, clock with a maximum operating frequency of 200
MHz. User applications executing on this processor control the overall operation of the device, including radar
control through well-defined API messages, radar signal processing (assisted by the radar hardware
accelerator), and peripherals for external interfaces.
See the Technical Reference Manual for a complete description and memory map.
9.3.5 DSP Subsystem
The DSP subsystem includes TI’s standard TMS320C674x megamodule and several blocks of internal memory
(L1P, L1D, and L2). For complete information including memory map, please refer to Technical Reference
Manual.
9.3.6 Hardware Accelerator
The Radar Hardware Accelerator (HWA) is an IP that enables off-loading the burden of certain frequently used
computations in FMCW radar signal processing from the main processor. FMCW radar signal processing
involves the use of FFT and Log-Magnitude computations to obtain a radar image across the range, velocity, and
angle dimensions. Some of the frequently used functions in FMCW radar signal processing can be done within
the radar hardware accelerator, while still retaining the flexibility of implementing other proprietary algorithms in
the main processor. See the Radar Hardware Accelerator User's Guide for a functional description and features
of this module and see the Technical Reference Manual for a complete list of register and memory map.
9.4 Other Subsystems
9.4.1 ADC Channels (Service) for User Application
The IWR6843 device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2,
ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.
•
ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s
external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST subsystem. This API
could be linked with the user application running on the Master R4.
•
BIST subsystem firmware will internally schedule these measurements along with other RF and Analog
monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and
number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the
readings will be reported for each of the monitored voltages.
GPADC Specifications:
•
•
•
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution
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•
For 5 out of the 6 inputs, an optional internal buffer (0.4-1.4V input range) is available. Without the buffer, the
ADC has a switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic
capacitance (GPADC channel 6, the internal buffer is not available).
5
ANALOG TEST 1-4,
GPADC
ANAMUX
5
VSENSE
A. GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±7°C.
Figure 9-6. ADC Path
9.4.1.1 GP-ADC Parameter
PARAMETER
TYP
1.8
UNIT
V
ADC supply
ADC unbuffered input voltage range
ADC buffered input voltage range(1)
ADC resolution
0 – 1.8
0.4 – 1.3
10
V
V
bits
LSB
LSB
LSB
LSB
Ksps
ns
ADC offset error
±5
ADC gain error
±5
ADC DNL
–1/+2.5
±2.5
625
400
10
ADC INL
ADC sample rate(2)
ADC sampling time(2)
ADC internal cap
pF
ADC buffer input capacitance
ADC input leakage current
2
pF
3
uA
(1) Outside of given range, the buffer output will become nonlinear.
(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
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10 Monitoring and Diagnostics
10.1 Monitoring and Diagnostic Mechanisms
Table 10-1 is a list of the main monitoring and diagnostic mechanisms available in the Functional Safety-
Compliant targeted devices
Table 10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices
NO
FEATURE
DESCRIPTION
Device architecture supports hardware logic BIST (LBIST) engine self-test Controller (STC).
This logic is used to provide a very high diagnostic coverage (>90%) on the Master R4F
CPU core and Vectored Interrupt Module (VIM) at a transistor level.
LBIST for the CPU and VIM need to be triggered by application code before starting the
functional safety application. CPU stays there in while loop and does not proceed further if a
fault is identified.
Boot time LBIST For Master
R4F Core and associated
VIM
1
Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and
TCMB1. Device architecture supports a hardware programmable memory BIST (PBIST)
engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the
implemented Master R4F TCMs at a transistor level.
PBIST for TCM memories is triggered by Bootloader at the boot time before starting
download of application from Flash or peripheral interface. CPU stays there in while loop
and does not proceed further if a fault is identified.
Boot time PBIST for Master
R4F TCM Memories
2
3
TCMs diagnostic is supported by Single error correction double error detection (SECDED)
ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64-
bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme
provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU can be
configured to have predetermined response (Ignore or Abort generation) to single and
double bit error conditions.
End to End ECC for Master
R4F TCM Memories
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an
ECC fault.
Further, bit multiplexing scheme implemented such that the bits accessed to generate a
logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability
of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple
single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word,
this scheme improves the usefulness of the TCM ECC diagnostic.
Master R4F TCM bit
multiplexing
4
Both these features are hardware features and cannot be enabled or disabled by application
software.
Device architecture supports Three Digital Clock Comparators (DCCs) and an internal
RCOSC. Dual functionality is provided by these modules – Clock detection and Clock
Monitoring.
DCCint is used to check the availability/range of Reference clock at boot otherwise the
device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This
provides debug capability). DCCint is only used by boot loader during boot time. It is
disabled once the APLL is enabled and locked.
DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided
version with the Reference input clock of the device. Initially (before configuring APLL),
DCC1 is used by bootloader to identify the precise frequency of reference input clock
against the internal RCOSC clock source. Failure detection for DCC1 would cause the
device to go into limp mode.
5
Clock Monitor
DCC2 module is one which is available for user software . From the list of clock options
given in detailed spec, any two clocks can be compared. One example usage is to compare
the CPU clock with the Reference or internal RCOSC clock source. Failure detection is
indicated to the Master R4F CPU via Error Signaling Module (ESM).
Device architecture supports the use of an internal watchdog that is implemented in the real-
time interrupt (RTI) module. The internal watchdog has two modes of operation: digital
watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are
mutually exclusive; the designer can elect to use one mode or the other but not both at the
same time.
7
RTI/WD for Master R4F
Watchdog can issue either an internal (warm) system reset or a CPU non-mask able
interrupt upon detection of a failure.
The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot
process. Once the application code takes up the control, Watchdog can be configured again
for mode and timings based on specific customer requirements.
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Table 10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices
(continued)
NO
FEATURE
DESCRIPTION
Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial
separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It
is expected that the operating system controls the MPU and changes the MPU settings
based on the needs of each task. A violation of a configured memory protection policy
results in a CPU abort.
8
MPU for Master R4F
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
Peripheral SRAMs as well.
PBIST for peripheral SRAM memories can be triggered by the application. User can elect to
PBIST for Peripheral interface run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which
9
SRAMs - SPIs, CANs
can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory
contents, and as such are typically run only at boot time. However, the user has the freedom
to initiate the tests at any time if peripheral communication can be hindered.
Any fault detected by the PBIST results in an error indicated in PBIST status registers.
Peripheral interface SRAMs diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. When a single or double bit error is detected the
ECC for Peripheral interface Master R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset.
10
SRAMs – SPIs, CANs
Software must configure and enable this feature in the peripheral and ESM module. ECC
failure (both single bit corrected and double bit uncorrectable error conditions) is reported to
the Master R4F as an interrupt via ESM module.
All the Master SS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are
connected to interconnect via Peripheral Central resource (PCR). This provides two
diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated
per peripheral chip select in the PCR. This can be utilized to disable unused features such
that they cannot interfere. In addition, each peripheral chip select can be programmed to
limit access based on privilege level of transaction. This feature can be used to limit access
to entire peripherals to privileged operating system code only.
Configuration registers
protection for Master SS
peripherals
11
These diagnostic mechanisms are disabled after reset. Software must configure and enable
these mechanisms. Protection violation also generates an ‘aerror’ that result in abort to
Master R4F or error response to other masters such as DMAs.
Device architecture supports hardware CRC engine on Master SS implementing the below
polynomials.
•
•
•
•
•
•
•
CRC16 CCITT – 0x10
CRC32 Ethernet – 0x04C11DB7
CRC64
CRC 32C – CASTAGNOLI – 0x1EDC6F4
CRC32P4 – E2E Profile4 – 0xF4ACFB1
CRC-8 – H2F Autosar – 0x2F
CRC-8 – VDA CAN – 0x1D
Cyclic Redundancy Check –
Master SS
12
The read operation of the SRAM contents to the CRC can be done by CPU or by DMA. The
comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
Device architecture supports MPUs on Master SS DMAs. Failure detection by MPU is
reported to the Master R4F CPU core as an interrupt via ESM.
13
14
15
MPU for DMAs
DSPSS’s high performance EDMAs also includes MPUs on both read and writes master
ports. EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP
core as an interrupt via local ESM.
Device architecture supports hardware logic BIST (LBIST) even for BIST R4F core and
associated VIM module. This logic provides very high diagnostic coverage (>90%) on the
BIST R4F CPU core and VIM.
This is triggered by Master R4F boot loader at boot time and it does not proceed further if
the fault is detected.
Boot time LBIST For BIST
R4F Core and associated
VIM
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST
R4F TCMs.
PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed
further if the fault is detected.
Boot time PBIST for BIST
R4F TCM Memories
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Table 10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices
(continued)
NO
FEATURE
DESCRIPTION
BIST R4F TCMs diagnostic is supported by Single error correction double error detection
(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while
double bit error is communicated to Master R4F as an interrupt so that application code
becomes aware of this and takes appropriate action.
End to End ECC for BIST
R4F TCM Memories
16
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults
resulting in logical multi-bit faults.
BIST R4F TCM bit
multiplexing
17
18
Device architecture supports an internal watchdog for BIST R4F. Timeout condition is
reported via an interrupt to Master R4F and rest is left to application code to either go for SW
reset for BIST SS or warm reset for the device to come out of faulty condition.
RTI/WD for BIST R4F
Device architecture supports a hardware programmable memory BIST (PBIST) engine for
DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic coverage
(March-13n).
PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed
further if the fault is detected.
Boot time PBIST for L1P,
L1D, L2 and L3 Memories
19
20
Device architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is
reported to the CPU as an interrupt.
Note:- L1D memory is not covered by parity or ECC and need to be covered by application
level diagnostics.
Parity on L1P
Device architecture supports both Parity Single error correction double error detection
(SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB of memory
used to store program and Data sections for the DSP. A 12-bit code word is used to store the
ECC data as calculated over the 256-bit data bus (logical instruction fetch size). The ECC
logic for the L2 access is located in the DSP and evaluation is done by the ECC control logic
inside the DSP. This scheme provides end-to-end diagnostics on the transmissions between
DSP and L2. Byte aligned Parity mechanism is also available on L2 to take care of data
section.
21
ECC on DSP’s L2 Memory
L3 memory is used as Radar data section in Device. Device architecture supports Single
error correction double error detection (SECDED) ECC diagnostic on L3 memory. An 8-bit
code word is used to store the ECC data as calculated over the 64-bit data bus.
Failure detection by ECC logic is reported to the Master R4F CPU core as an interrupt via
ESM.
ECC on Radar Data Cube
(L3) Memory
22
23
Device architecture supports the use of an internal watchdog for BIST R4F that is
implemented in the real-time interrupt (RTI) module – replication of same module as used in
Master SS. This module supports same features as that of RTI/WD for Master/BIST R4F.
This watchdog is enabled by customer application code and Timeout condition is reported
via an interrupt to Master R4F and rest is left to application code in Master R4F to either go
for SW reset for DSP SS or warm reset for the device to come out of faulty condition.
RTI/WD for DSP Core
Device architecture supports dedicated hardware CRC on DSPSS implementing the below
polynomials.
•
•
•
CRC16 CCITT - 0x10
CRC32 Ethernet - 0x04C11DB7
CRC64
24
25
CRC for DSP Sub-System
The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The
comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
Device architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2
memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by
MPU is reported to the DSP core as an abort.
MPU for DSP
Device architecture supports various temperature sensors all across the device (next to
power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame
period.(1)
26
27
Temperature Sensors
Tx Power Monitors
Device architecture supports power detectors at the Tx output.(2)
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Table 10-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices
(continued)
NO
FEATURE
DESCRIPTION
When a diagnostic detects a fault, the error must be indicated. The device architecture
provides aggregation of fault indication from internal monitoring/diagnostic mechanisms
using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides
mechanisms to classify errors by severity and to provide programmable error response.
ESM module is configured by customer application code and specific error signals can be
enabled or masked to generate an interrupt (Low/High priority) for the Master R4F CPU.
device supports Nerror output signal (IO) which can be monitored externally to identify any
kind of high severity faults in the design which could not be handled by the R4F.
Error Signaling
Error Output
28
Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and
comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if
any, are detected and reported.
Synthesizer (Chirp) frequency
monitor
29
30
Device architecture supports a ball break detection mechanism based on Impedance
measurement at the TX output(s) to detect and report any large deviations that can indicate
a ball break.
Monitoring is done by TIs code running on BIST R4F and failure is reported to the Master
R4F via Mailbox.
Ball break detection for TX
ports (TX Ball break monitor)
It is completely up to customer SW to decide on the appropriate action based on the
message from BIST R4F.
Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,
inter-RX balance, etc.
31
32
33
34
RX loopback test
Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect
failure.
IF loopback test
Provision to detect ADC saturation due to excessive incoming signal level and/or
interference.
RX saturation detect
Boot time LBIST for DSP core
Device supports boot time LBIST for the DSP Core. LBIST can be triggered by the Master
R4F application code during boot time.
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the
temperature sensed via API by customer application.
a. Report the temperature sensed after every N frames
b. Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
(2) Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
a. Report the power detected after every N frames
b. Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
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10.1.1 Error Signaling Module
When a diagnostic detects a fault, the error must be indicated. IWR6843 architecture provides aggregation of
fault indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling module
(ESM). The ESM provides mechanisms to classify faults by severity and allows programmable error response.
Below is the high level block diagram for ESM module.
Low Priority
Low Priority
Interrupt
Interrupy
Handing
Error Group 1
Interrupt Enable
High Priority
Interrupt
Handing
High Priority
Interrupy
Interrupt Priority
Error Group 2
Error Group 3
Nerror Enable
Error Signal
Handling
Device Output
Pin
Figure 10-1. ESM Module Diagram
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11 Applications, Implementation, and Layout
Note
Information in the following Applications section is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
11.1 Application Information
Application information can be found on IWR Application web page.
11.2 Reference Schematic
Please check the device product page for latest Hardware design information under Design Kits - typically, at
Design & development.
Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.
•
•
Altium XWR6843 EVM Design Files
XWR6843 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions follow.
12.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, IWR6843). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ABL0161), the temperature range (for example, blank is the default commercial temperature
range). Figure 12-1 provides a legend for reading the complete device name for any IWR6843 device.
For orderable part numbers of IWR6843 devices in the ABL0161 package types, see the Package Option
Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the IWR6843, IWR6443 Device
Errata.
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6
8
43
B
IWR
G
ABL
Prefix
Qualification
XI = Pre-production industrial
IWR = Production
Blank= no special qual
Tray or Tape & Reel
Generation
R = Tape & Reel
Blank = Tray
1 = 77 GHz Band
6 = 60 GHz Band
Variant
Package
2 = FE
ABL = BGA
4 = FE + FFT + MCU
6 = FE + MCU + DSP
8 = FE + MCU + FFT + DSP
Security
G = General
S = Secure
Num RX/TX Channels
RX = 1,2,3,4
TX = 1,2,3
Silicon PG Revision
blank = Rev1.0
A = Rev 2.0
Features
blank = baseline
AA = Antenna on Package (AoP)
Safety Level
Q = Non-Functional Safety
B = SIL-2 Targeted
Figure 12-1. Device Nomenclature
12.2 Tools and Software
Models
IWR6843 BSDL model
IWR6843 IBIS model
Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
IWR6843 checklist for
schematic review, layout
review, bringup/wakeup
A set of steps in spreadsheet form to select system functions and pinmux
options. Specific EVM schematic and layout notes to apply to customer
engineering. A bringup checklist is suggested for customers.
12.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral follows.
Errata
IWR6843, IWR6443 device errata Describes known advisories, limitations, and cautions on silicon and
provides workarounds.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
ARM® and Cortex® are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
13.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
ABL0161B
FCBGA - 1.17 mm max height
SCALE 1.400
PLASTIC BALL GRID ARRAY
10.5
10.3
B
A
BALL A1 CORNER
10.5
10.3
1.17 MAX
C
SEATING PLANE
0.1 C
BALL TYP
0.37
TYP
0.27
9.1 TYP
PKG
(0.65) TYP
(0.65) TYP
R
P
N
M
L
K
J
PKG
H
G
F
9.1
TYP
E
D
C
0.45
161X
0.35
0.15
0.08
C A B
C
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
6
7
8
9 10 11
12 13 14 15
0.65 TYP
4223365/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.65) TYP
D
E
F
G
H
J
PKG
K
L
M
N
P
R
PKG
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.32)
METAL
(
0.32)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223365/A 10/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
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IWR6843, IWR6443
SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
www.ti.com
EXAMPLE STENCIL DESIGN
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
(0.65) TYP
D
E
F
G
H
J
PKG
K
L
M
N
P
R
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4223365/A 10/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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SWRS219D – OCTOBER 2018 – REVISED SEPTEMBER 2020
www.ti.com
13.2 Tray Information for ABL, 10.4 × 10.4 mm
Package
Type
Package
Name
Unit Array
Matrix
Max Temp.
(°C)
L
W
(mm)
K0
(mm)
P1
(mm)
CL
(mm)
CW
(mm)
Device
Pins
SPQ
(mm)
IWR6443AQGABL
IWR6843AQGABL
IWR6843ABGABL
FC/CSP
FC/CSP
FC/CSP
ABL
ABL
ABL
161
161
161
176
176
176
8 × 22
8 × 22
8 × 22
150
150
150
315.0
315.0
315.0
135.9
135.9
135.9
7.62
7.62
7.62
13.40
13.40
13.40
16.80
16.80
16.80
17.20
17.20
17.20
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
IWR6443AQGABL
ACTIVE
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
ABL
161
161
161
161
161
161
161
161
176
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
IWR6443
QG
678A
(678A ABL, 678
A ABL)
IWR6443AQGABLR
IWR6843ABGABL
IWR6843ABGABLR
IWR6843AQGABL
IWR6843AQGABLR
IWR6843AQSABL
IWR6843AQSABLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ABL
ABL
ABL
ABL
ABL
ABL
ABL
1000
176
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
IWR6443
QG
678A
(678A ABL, 678
A ABL)
Green (RoHS
& no Sb/Br)
IWR6843
BG
678A
(678A ABL, 678
A ABL)
1000
176
Green (RoHS
& no Sb/Br)
IWR6843
BG
678A
(678A ABL, 678
A ABL)
Green (RoHS
& no Sb/Br)
IWR6843
QG
678A
(678A ABL, 678
A ABL)
1000
176
Green (RoHS
& no Sb/Br)
IWR6843
QG
678A
(678A ABL, 678
A ABL)
Green (RoHS
& no Sb/Br)
IWR6843
QS
678A
(678A ABL, 678
A ABL)
1000
Green (RoHS
& no Sb/Br)
IWR6843
QS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Drawing Qty
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
(1)
(2)
(3)
(4/5)
(6)
678A
(678A ABL, 678
A ABL)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
IWR6443AQGABLR
IWR6843AQGABLR
FC/CSP
FC/CSP
ABL
ABL
161
161
1000
1000
330.0
330.0
24.4
24.4
10.7
10.7
10.7
10.7
1.65
1.65
16.0
16.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
IWR6443AQGABLR
IWR6843AQGABLR
FC/CSP
FC/CSP
ABL
ABL
161
161
1000
1000
336.6
336.6
336.6
336.6
41.3
41.3
Pack Materials-Page 2
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