IWR1642AQAGABL [TI]
集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 | ABL | 161 | -40 to 105;
| 型号： | IWR1642AQAGABL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 | ABL | 161 | -40 to 105 传感器 |
| 文件： | 总85页 (文件大小：1835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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IWR1642
ZHCSH27B –MAY 2017–REVISED APRIL 2018
IWR1642 单芯片 76 至 81GHz 毫米波传感器
1 器件概述
1.1 特性
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– 多达 6 个 ADC 通道
• FMCW 收发器
– 多达 2 个 SPI 通道
– 多达 2 个 UART
– CAN 接口
– I2C
– 集成式 PLL、发送器、接收器、基带和 A2D
– 76 至 81GHz 覆盖范围，具有 4GHz 的连续带宽
– 四个接收通道
– 两个发送通道
– GPIO
– 基于分数 N PLL 的超精确线性调频脉冲（计时）
引擎
– 用于原始 ADC 数据和调试仪表的 2 通道 LVDS
接口
– TX 功率：12.5dBm
– RX 噪声系数：
• IWR1642 高级 特性
– 嵌入式自监控，无需使用主机处理器
– 复基带架构
– 嵌入式干扰检测功能
• 电源管理
– 内置的 LDO 网络，可增强 PSRR
– I/O 支持双电压 3.3V/1.8V
• 时钟源
– 14dB（76 至 77GHz）
– 15dB（77 至 81GHz）
– 1MHz 时的相位噪声：
– –95dBc/Hz（76 至 77GHz）
– –93dBc/Hz（77 至 81GHz）
• 内置的校准和自检（监控）
– 配备基于 ARM® Cortex®基于 ARM® Cortex®-
R4F 的无线电控制系统
– 支持频率为 40MHz 的外部振荡器
– 内置的固件 (ROM)
– 支持外部驱动、频率为 40MHz 的时钟（方波/正
弦波）
– 针对频率和温度进行自校准的系统
• 用于 FMCW 信号处理的 C674x DSP
• 片上存储器：1.5MB
– 支持 40MHz 晶体与负载电容器相连接
• 轻松的硬件设计
– 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆
• 用于物体跟踪、分类和接口控制的 Cortex-R4F 微控
制器
晶 BGA 封装，可实现轻松组装和低成本 PCB 设
计
– 支持自主模式（从 QSPI 闪存加载用户应用）
• 具有 ECC 的内部存储器
• 集成外设
– 小尺寸解决方案
• 运行条件
– 结温范围:–40°C 至 105°C
1.2 应用
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用于测量距离、速度和角度的工业传感器
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接近感应
液箱液位探测雷达
位移感应
安全和监控
工厂自动化安全防护装置
人数统计
现场发送器
交通监控
运动检测
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS212
IWR1642
ZHCSH27B –MAY 2017–REVISED APRIL 2018
www.ti.com.cn
40-MHz
Crystal
Power
Management
QSPI Flash
POWER
SPI
Integrated MCU
ARM Cortex-R4F
UART Tx/Rx
Antenna
Structure
RX1
RX2
RX3
RX4
CAN
Radar
Front End
TX1
TX2
Integrated DSP
TI C674x
IWR1642
图 1-1. 适用于工业应用的自主 传感器
1.3 说明
IWR1642 器件是一款能够在 76 至 81GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感
器，具有高达 4GHz 的连续线性调频脉冲。该器件采用 TI 的低功耗 45nm RFCMOS 工艺进行构建，并且此
解决方案在极小的封装中实现了前所未有的集成度。IWR1642 是适用于工业 应用 （如楼宇自动化、工厂自
动化、无人机、物料处理、交通监控和监视）中的低功耗、自监控、超精确雷达系统的理想解决方案。
IWR1642 器件是一种自包含单芯片解决方案，能够简化 76 至 81GHz 频带中的毫米波传感器实施。
IWR1642 包含一个具有内置 PLL 和模数转换器的单片实施 2TX、4RX 系统。IWR1642 还集成了 DSP 子系
统，该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件包含一个基于 ARM R4F 的处理器子
系统，该子系统负责前端配置、控制和校准。简单编程模型更改可支持各种传感器实施，并且能够进行动态
重新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，该解决方案包括硬件
参考设计、软件驱动程序、样例配置、API 指南、培训以及用户文档。
器件信息(1)
封装
器件型号
封装尺寸
IWR1642AQAGABL（托盘）
IWR1642AQAGABLR（卷带封装）
FCBGA (161)
10.4mm × 10.4mm
(1) 更多信息请参见 节 10，机械封装和可订购产品信息。
2
器件概述
版权 © 2017–2018, Texas Instruments Incorporated
IWR1642
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ZHCSH27B –MAY 2017–REVISED APRIL 2018
1.4 功能框图
Serial Flash
interface
QSPI
Cortex-R4F
@ 200-MHz
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
RX1
Optional External
MCU interface
SPI
(User programmable)
LNA
RX2
SPI / I2C
DCAN
PMIC control
Digital Front
End
Prog
RAM
Data
RAM
Boot
ROM
Optional communication
interface
LNA
RX3
(256KB*) (192KB*)
(Decimation
filter chain)
DMA
RX4
LNA
Debug
UARTs
For debug
Master subsystem
JTAG for debug/
development
(Customer programmed)
Test/
Debug
TX1
TX2
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Synth
(20 GHz)
Ramp
Generator
PA
x4
High-speed input for
hardware-in-loop
verification
C674x DSP
@600 MHz
ADC
Buffer
6
RF Control/
BIST
L1P
(32KB)
L2
(256KB)
L1D
(32KB)
GPADC
Osc.
VMON
Temp
DMA
CRC
Radar Data Memory
(L3)
DSP subsystem
(Customer programmed)
768KB*
RF/Analog subsystem
* Up to 512KB of Radar Data Memory can be switched to the Master R4F if required
版权 © 2017–2018, Texas Instruments Incorporated
器件概述
3
IWR1642
ZHCSH27B –MAY 2017–REVISED APRIL 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 7
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Pin Diagram .......................................... 9
4.2 Pin Attributes ........................................ 13
4.3 Signal Descriptions.................................. 24
4.4 Pin Multiplexing ..................................... 29
Specifications ........................................... 33
5.1 Absolute Maximum Ratings......................... 33
5.2 ESD Ratings ........................................ 33
5.3 Power-On Hours (POH)............................. 33
5.4 Recommended Operating Conditions............... 34
5.5 Power Supply Specifications........................ 34
5.6 Power Consumption Summary...................... 35
5.7 RF Specification..................................... 36
5.8 CPU Specifications.................................. 37
5.10 Timing and Switching Characteristics ............... 38
Detailed Description ................................... 61
6.1 Overview ............................................ 61
6.2 Functional Block Diagram........................... 61
6.3 Subsystems ......................................... 61
6.4 Other Subsystems................................... 69
Monitoring and Diagnostics.......................... 71
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3
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7.1
Monitoring and Diagnostic Mechanisms ............ 71
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Applications, Implementation, and Layout........ 73
8.1 Application Information.............................. 73
8.2 Reference Schematic ............................... 73
8.3 Layout ............................................... 74
Device and Documentation Support ............... 75
9.1 Device Nomenclature ............................... 75
9.2 Tools and Software ................................. 76
9.3 Documentation Support ............................. 76
9.4 Community Resources.............................. 77
9.5 商标.................................................. 77
9.6 静电放电警告 ........................................ 77
9.7 出口管制提示 ........................................ 77
9.8 术语表 ............................................... 77
9
5
10 Mechanical, Packaging, and Orderable
Information .............................................. 78
10.1 Packaging Information .............................. 78
5.9
Thermal Resistance Characteristics for FCBGA
Package [ABL0161] ................................. 37
4
内容
版权 © 2017–2018, Texas Instruments Incorporated
IWR1642
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ZHCSH27B –MAY 2017–REVISED APRIL 2018
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from August 31, 2017 to April 30, 2018
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将 TX 功率从“12dBm”更新/更改成了“12.5dBm”................................................................................... 1
将 RX 噪声系数从“15dB（76 至 77GHz）”更新/更改成了“14dB（76 至 77GHz）” ......................................... 1
将 RX 噪声系数从“16dB（77 至 81GHz）”更新/更改成了“15dB（77 至 81GHz）” ......................................... 1
将 1MHz 时的相位噪声从“–93dBc/Hz（76 至 77GHz）”更新/更改成了“–95dBc/Hz（76 至 77GHz）”................... 1
将 1MHz 时的相位噪声从“–91dBc/Hz（77 至 81GHz）”更新/更改成了“–93dBc/Hz（77 至 81GHz）”................... 1
在 “特性”中 将“...物体检测和接口控制”更新/更改成了“物体跟踪、分类和接口控制”.......................................... 1
在 “特性”中 将“支持晶体...相连接”更新/更改成了“支持 40MHz 晶体...相连接” ................................................ 1
在“应用”中添加了“人数统计”和 “运动检测”......................................................................................... 1
将标题从“自主雷达传感器...”更新/更改成了“汽车传感器” ........................................................................ 2
在“器件信息”中添加了托盘器件编号 ................................................................................................ 2
在“器件信息”中将“XI1642QGABL（卷）”更新/更改成了“IWR1642AQAGABLR（卷）”..................................... 2
更新了功能框图 中的 RX 和 TX 连接............................................................................................... 3
在功能框图 中添加了“射频控制/BIST”框 ........................................................................................... 3
Removed "Cascade (20-GHz sync)" from Device Features Comparison ..................................................... 7
Updated/Changed pin B15 to GPIO_41 in Pin Diagram ....................................................................... 10
Corrected A10 pin to "VOUT_14APLL"........................................................................................... 10
Updated/Changed pin N14 from "RESERVED" to "DMM_SYNC" in Pin Diagram ......................................... 10
Updated/Changed Pin Attributes (ABL0161 Package) to match the AWR1642 device ................................... 14
Updated/Changed all instances of "CAN_FD_tx" to "Reserved" in Pin Attributes (ABL0161 Package)................. 15
Updated/Changed all instances of "CAN_FD_rx" to "Reserved" in Pin Attributes (ABL0161 Package)................. 15
Added two register tables after Pin Attributes ................................................................................... 21
Updated/Changed PAD IO Control Registers ................................................................................... 21
Cleaned up CLKP and CLKM signals in Signal Descriptions - Analog ...................................................... 27
Removed R14 from Power supply VIOIN ........................................................................................ 27
Added pin R15 to Power supply VSS ............................................................................................ 28
Removed duplicate Pin Multiplexing table ....................................................................................... 29
Updated/Changed all CAN_FD to Reserved .................................................................................... 29
Cleaned up VIN_13RF1 and VIN_13F2 in Absolute Maximum Ratings ..................................................... 33
Updated/Changed CLKP, CLKM row in Absolute Maximum ratings from "Input ports for reference crystal" to
"Input ports for reference crystal, or external oscillator input"................................................................. 33
Added table note to ESD Ratings................................................................................................. 33
Updated/Changed Power-On Hours (POH) ..................................................................................... 33
Added VIN_18VCO row to Recommended Operating Conditions............................................................ 34
Updated/Changed VIL in Recommended Operating Conditions............................................................... 34
Updated/Changed VOH MIN from "85% VIOIN" to "VIOIN – 450"............................................................. 34
Updated/Changed VOL MAX from "350" to "450" ............................................................................... 34
Added NRESET row to Recommended Operating Conditions................................................................ 34
Updated/Changed Ripple Specifications FREQUENCY from "4200" to "4400" ............................................ 35
Updated Average Power Consumption at Power Terminals .................................................................. 35
Updated/Changed RF Specification to match AWR16 ......................................................................... 36
Updated/Changed IMRR TYP from 40 dB to 21 dB ............................................................................ 36
Updated/Changed Power Supply Sequencing and Reset Timing image .................................................... 38
Updated/Changed Clock Specifications text from "(that is, a 40-MHz crystal) " to "(that is, a 40-MHz crystal or
external oscillator to CLKP) " ...................................................................................................... 39
Updated/Changed Crystal Implementation image from "40 and 50 MHz" to "40 MHz".................................... 39
Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40".......................................... 39
Added External Clock Mode Specifications...................................................................................... 40
Removed External Clock Electrical Characteristics table...................................................................... 40
Updated/Changed External Clock Mode Specifications table to match AWR16............................................ 40
Updated SPI Slave Mode Switching Parameters ............................................................................... 46
Updated SPI Slave Mode Timing Requirements................................................................................ 46
Updated/Changed all MIN values in Timing Requirements for QSPI Input (Read) Timings .............................. 55
Added "People Counting" and "Gesturing" to Detailed Description Overview .............................................. 61
Updated/Changed Clock Subsystem diagram................................................................................... 62
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Copyright © 2017–2018, Texas Instruments Incorporated
修订历史记录
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Updated/Changed Host Interrupt bullet in Host Interface...................................................................... 65
Removed Security Modules from Master Subsystem, Cortex-R4F Memory Map .......................................... 66
Removed "...and ENOB of ~9 bits" from ADC Channels (Service) for User Application .................................. 69
Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6"...................................... 69
Updated/Changed GP-ADC Parameter table to match AWR16 .............................................................. 69
Updated/Changed Monitoring and Diagnostic Mechanisms................................................................... 71
Added "People counting", "Gesturing", and "Motion detection" to Application Information................................ 73
Updated/Changed the Device Nomenclature image ........................................................................... 76
6
修订历史记录
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3 Device Comparison
Table 3-1. Device Features Comparison
FUNCTION
IWR1443
IWR1642
Number of receivers
Number of transmitters
On-chip memory
4
3
4
2
576KB
15
1.5MB
5
Max I/F (Intermediate Frequency) (MHz)
Max real sampling rate (Msps)
Max complex sampling rate (Msps)
Processor
37.5
18.75
12.5
6.25
MCU (R4F)
Yes
—
Yes
Yes
DSP (C674x)
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
Trace
1
2
Yes
1
Yes
1
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
PWM
—
Hardware In Loop (HIL/DMM)
GPADC
—
Yes
Yes
Yes
Yes
Yes
Yes
LVDS/Debug
CSI2
Hardware accelerator
1-V bypass mode
—
Yes
Yes
JTAG
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product status
AI(1)
PD(2)
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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3.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for industrial applications.
mmWave IWR The Texas Instruments IWR1xxx family of mmWave Sensors are highly integrated and
built on RFCMOS technology operating in 76- to 81-GHz frequency band. The devices have
a closed-loop PLL for precise and linear chirp synthesis, includes a built-in radio processor
(BIST) for RF calibration and safety monitoring. The devices have a very small-form factor,
low power consumption, and are highly accurate. Industrial applications from long range to
ultra short range can be realized using these devices.
Companion Products for IWR1642 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for IWR1642 The IWR1642 TI Designs Reference Design Library is a robust
reference design library spanning analog, embedded processor and connectivity. Created by
TI experts to help you jump-start your system design, all TI Designs include schematic or
block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
8
Device Comparison
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4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4,
and Figure 4-5 show the same pins, but split into four quadrants.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOUT
_14APLL
VOUT
_14SYNTH
OSC
_CLKOUT
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
GPIO_46
VSSA
VIN
_18CLK
VIN
_18VCO
VSSA
VSSA
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
GPIO_45
GPIO_43
GPIO_44
GPIO_42
VBGAP
GPADC5
SPIA_cs_n
SPIA_mosi
SPIA_clk
SPIB_mosi
SYNC_OUT
GPIO_0
GPIO_40
GPADC6
GPIO_41
VIN
_13RF2
VSSA
VSSA
CLKP
VIN
_13RF2
GPIO_39
SPIA_miso
SPIB_clk
CLKM
VIOIN
_18DIFF
VSSA
VSSA
VSSA
VSSA
VSSA
RX4
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VIN_18BB
VSS
VSS
VSS
VIOIN
VIN_SRAM
VDDIN
VIN
_13RF1
G
H
J
VSSA
RX3
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
SPIB_miso
SPIB_cs_n
VIN
_13RF1
VSSA
VSS
VIN
_13RF1
VSSA
RX2
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
GPIO_1
LVDS_TXP0 LVDS_TXM0
LVDS_TXP1 LVDS_TXM1
LVDS_CLKP LVDS_CLKM
K
L
VSSA
VIN_18BB
VSS
GPIO_2
VSSA
RX1
VSSA
VSS
VPP
LVDS
_FRCLKP
LVDS
_FRCLKM
M
N
P
R
VSSA
MCU
_CLKOUT
Warm
_Reset
VSSA
GPADC1
VSSA
VSSA
GPADC2
GPADC4
VSSA
rs232_rx
SYNC_in
GPIO_31
rs232_tx
GPIO_32
GPIO_33
nERROR_OUT nERROR_IN
TMS
TCK
VDDIN
QSPI_cs_n
TDI
QSPI[1]
TDO
DMM_SYNC
GPIO_47
VDDIN
PMIC
_CLKOUT
GPADC3
NRESET
GPIO_34
VDDIN
GPIO_36
GPIO_35
GPIO_38
GPIO_37
QSPI[3] SPI_HOST_INTR VNWA
VIOIN_18
VIOIN
QSPI_clk
QSPI[0]
QSPI[2]
VSS
Not to scale
Figure 4-1. Pin Diagram
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Terminal Configuration and Functions
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1
2
3
4
5
6
7
8
A
B
C
D
E
F
VSSA
VSSA
VSSA
VOUT_PA
VSSA
VSSA
VSSA
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
GPIO_45
GPIO_43
VIN
_13RF2
VSSA
VSSA
VIN
_13RF2
VSSA
VSSA
RX4
VSSA
VSSA
VSSA
VSS
VSS
VSS
VIN_18BB
VIN
_13RF1
G
VSSA
VSSA
VSS
VSS
VSS
Not to scale
1
3
2
4
Figure 4-2. Top Left Quadrant
10
Terminal Configuration and Functions
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9
10
11
12
13
14
15
VOUT
VOUT
OSC
A
B
C
D
E
F
GPIO_46
VSSA
_14APLL
_14SYNTH
_CLKOUT
VIN
_18CLK
VIN
GPIO_44
GPIO_42
VBGAP
GPADC5
SPIA_cs_n
SPIA_mosi
SPIA_clk
GPIO_40
GPIO_41
_18VCO
GPADC6
GPIO_39
SPIA_miso
SPIB_clk
CLKP
CLKM
VIOIN
VSS
VSS
VSS
_18DIFF
VSS
SPIB_mosi
VIOIN
VSS
SYNC_OUT
SPIB_miso
VIN_SRAM
G
Not to scale
1
3
2
4
Figure 4-3. Top Right Quadrant
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1
2
3
4
5
6
7
8
VIN
_13RF1
H
RX3
VSSA
VSS
VIN
_13RF1
J
VSSA
VSSA
RX2
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
K
L
VIN_18BB
VSSA
VSSA
VSSA
VSS
VSS
M
N
P
R
RX1
VSSA
MCU
_CLKOUT
VSSA
GPADC1
VSSA
VSSA
VSSA
rs232_rx
SYNC_in
GPIO_31
rs232_tx
GPIO_32
GPIO_33
nERROR_OUT nERROR_IN
GPADC2
GPADC4
GPADC3
NRESET
GPIO_34
VDDIN
GPIO_36
GPIO_35
GPIO_38
GPIO_37
Not to scale
1
3
2
4
Figure 4-4. Bottom Left Quadrant
12
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9
10
11
12
13
14
15
H
J
VSS
VSS
GPIO_0
SPIB_cs_n
VDDIN
VSS
VSS
VSS
GPIO_1
GPIO_2
VPP
LVDS_TXP0 LVDS_TXM0
LVDS_TXP1 LVDS_TXM1
LVDS_CLKP LVDS_CLKM
K
L
VSS
VSS
LVDS
_FRCLKP
LVDS
_FRCLKM
M
N
P
R
Warm
_Reset
TMS
TCK
VDDIN
QSPI_cs_n
TDI
QSPI[1]
TDO
DMM_SYNC
GPIO_47
VDDIN
PMIC
_CLKOUT
QSPI[3] SPI_HOST_INTR VNWA
VIOIN_18
VIOIN
QSPI_clk
QSPI[0]
QSPI[2]
VSS
Not to scale
1
3
2
4
Figure 4-5. Bottom Right Quadrant
4.2 Pin Attributes
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Table 4-1. Pin Attributes (ABL0161 Package)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
H13
J13
GPIO_0
GPIO_1
GPIO_13
0xFFFFEA04
0
IO
IO
O
O
O
IO
IO
O
I
Output Disabled
Pull Down
GPIO_0
1
PMIC_CLKOUT
ePWM1b
2
10
11
0
ePWM2a
GPIO_16
0xFFFFEA08
Output Disabled
Pull Down
GPIO_1
1
SYNC_OUT
DMM_MUX_IN
SPIB_cs_n_1
SPIB_cs_n_2
ePWM1SYNCI
GPIO_26
2
12
13
14
15
0
IO
IO
I
K13
GPIO_2
0xFFFFEA64
IO
IO
O
O
O
O
O
O
IO
I
Output Disabled
Pull Down
GPIO_2
1
OSC_CLKOUT
MSS_uartb_tx
BSS_uart_tx
SYNC_OUT
PMIC_CLKOUT
TRACE_DATA_0
GPIO_31
2
7
8
9
10
0
R4
GPIO_31
0xFFFFEA7C
Output Disabled
Pull Down
1
DMM0
2
MSS_uarta_tx
TRACE_DATA_1
GPIO_32
4
IO
O
IO
I
P5
R5
P6
GPIO_32
GPIO_33
GPIO_34
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
1
DMM1
2
TRACE_DATA_2
GPIO_33
0
O
IO
I
1
DMM2
2
TRACE_DATA_3
GPIO_34
0
O
IO
I
1
DMM3
2
ePWM3SYNCO
TRACE_DATA_4
GPIO_35
4
O
O
IO
I
R7
GPIO_35
0xFFFFEA8C
0
Output Disabled
Pull Down
1
DMM4
2
ePWM2SYNCO
4
O
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
P7
GPIO_36
GPIO_37
GPIO_38
GPIO_39
TRACE_DATA_5
GPIO_36
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEA9C
0
1
2
5
0
1
2
5
0
1
2
5
0
1
2
4
5
0
1
2
4
5
0
1
2
4
0
1
2
4
0
1
2
4
5
O
IO
I
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
Pull Down
DMM5
MSS_uartb_tx
TRACE_DATA_6
GPIO_37
O
O
IO
I
R8
P8
DMM6
BSS_uart_tx
TRACE_DATA_7
GPIO_38
O
O
IO
I
DMM7
DSS_uart_tx
TRACE_DATA_8
GPIO_39
O
O
IO
I
D14
DMM8
Reserved
IO
I
ePWM1SYNCI
TRACE_DATA_9
GPIO_40
B14
GPIO_40
0xFFFFEAA0
O
IO
I
Output Disabled
Pull Down
DMM9
Reserved
IO
O
O
IO
I
ePWM1SYNCO
TRACE_DATA_10
GPIO_41
B15
C9
GPIO_41
GPIO_42
GPIO_43
0xFFFFEAA4
0xFFFFEAA8
0xFFFFEAAC
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
DMM10
ePWM3a
O
O
IO
I
TRACE_DATA_11
GPIO_42
DMM11
ePWM3b
O
O
IO
I
C8
TRACE_DATA_12
GPIO_43
DMM12
ePWM1a
O
IO
CAN_tx
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
B9
GPIO_44
TRACE_DATA_13
GPIO_44
0xFFFFEAB0
0
1
2
4
5
0
1
2
4
0
1
2
4
0
1
2
0
1
2
0
1
12
0
0
O
IO
I
Output Disabled
Pull Down
DMM13
ePWM1b
O
I
CAN_rx
B8
A9
GPIO_45
GPIO_46
TRACE_DATA_14
GPIO_45
0xFFFFEAB4
0xFFFFEAB8
O
IO
I
Output Disabled
Output Disabled
Pull Down
Pull Down
DMM14
ePWM2a
O
O
IO
I
TRACE_DATA_15
GPIO_46
DMM15
ePWM2b
O
O
IO
I
N15
N14
N8
GPIO_47
TRACE_CLK
GPIO_47
0xFFFFEABC
0xFFFFEAC0
0xFFFFEA60
Output Disabled
Output Disabled
Output Disabled
Pull Down
Pull Down
Pull Down
DMM_CLK
TRACE_CTL
RESERVED
DMM_SYNC
GPIO_25
DMM_SYNC
MCU_CLKOUT
O
IO
I
IO
O
O
I
MCU_CLKOUT
ePWM1a
N7
N6
P9
nERROR_IN
nERROR_IN
nERROR_OUT
SOP[2]
0xFFFFEA44
0xFFFFEA4C
0xFFFFEA68
Input
nERROR_OUT
PMIC_CLKOUT
O
I
Hi-Z (Open Drain)
Output Disabled
During Power Up
Pull Down
GPIO_27
0
IO
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
I
PMIC_CLKOUT
ePWM1b
1
11
12
0
ePWM2a GPIO_8
R13
N12
QSPI[0]
QSPI[1]
0xFFFFEA2C
0xFFFFEA30
Output Disabled
Output Disabled
Pull Down
Pull Down
QSPI[0]
1
SPIB_miso
GPIO_9
2
0
QSPI[1]
1
SPIB_mosi
SPIB_cs_n_2
GPIO_10
QSPI[2]
2
8
R14
QSPI[2]
0xFFFFEA34
0
Output Disabled
Pull Down
1
Reserved
8
O
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
P12
R12
QSPI[3]
GPIO_11
QSPI[3]
0xFFFFEA38
0
IO
IO
I
Output Disabled
Pull Down
1
Reserved
GPIO_7
8
QSPI_clk
0xFFFFEA3C
0
IO
IO
IO
O
IO
IO
IO
IO
I
Output Disabled
Pull Down
QSPI_clk
SPIB_clk
1
2
DSS_uart_tx
GPIO_6
6
P11
N4
QSPI_cs_n
rs232_rx
0xFFFFEA40
0xFFFFEA74
0
Output Disabled
Input Enabled
Pull Up
Pull Up
QSPI_cs_n
SPIB_cs_n
GPIO_15
rs232_rx
1
2
0
1
MSS_uarta_rx
BSS_uart_tx
MSS_uartb_rx
Reserved
I2C_scl
2
I
6
IO
IO
I
7
8
9
IO
O
O
O
IO
O
IO
IO
IO
O
IO
O
O
I
ePWM2a
ePWM2b
ePWM3a
GPIO_14
rs232_tx
10
11
12
0
N5
rs232_tx
0xFFFFEA78
Output Enabled
1
MSS_uarta_tx
MSS_uartb_tx
BSS_uart_tx
Reserved
I2C_sda
5
6
7
10
11
12
13
14
15
0
ePWM1a
ePWM1b
NDMM_EN
ePWM2a
GPIO_3
O
IO
IO
I
E13
C13
SPIA_clk
0xFFFFEA14
0xFFFFEA18
Output Disabled
Output Disabled
Pull Up
Pull Up
SPIA_clk
1
CAN_rx
6
DSS_uart_tx
SPIA_cs_n
SPIA_cs_n
CAN_tx
7
O
IO
IO
O
SPIA_cs_n
0
1
6
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
E14
D13
SPIA_miso
SPIA_mosi
GPIO_20
0xFFFFEA10
0
1
2
0
1
2
8
0
1
2
6
7
8
0
1
2
6
7
8
9
0
1
2
6
0
1
2
0
1
6
0
1
6
7
9
IO
IO
O
IO
IO
I
Output Disabled
Pull Up
SPIA_miso
Reserved
GPIO_19
0xFFFFEA0C
Output Disabled
Pull Up
SPIA_mosi
Reserved
DSS_uart_tx
GPIO_5
O
IO
IO
I
F14
SPIB_clk
0xFFFFEA24
Output Disabled
Pull Up
SPIB_clk1
MSS_uarta_rx
MSS_uartb_tx
BSS_uart_tx
Reserved
O
O
I
H14
SPIB_cs_n
GPIO_4
0xFFFFEA28
IO
IO
O
O
IO
I
Output Disabled
Pull Up
SPIB_cs_n
MSS_uarta_tx
MSS_uartb_tx
BSS_uart_tx
QSPI_clk_ext
Reserved
O
IO
IO
IO
O
IO
IO
IO
IO
O
IO
IO
I
G14
SPIB_miso
GPIO_22
0xFFFFEA20
Output Disabled
Pull Up
SPIB_miso
I2C_scl
DSS_uart_tx
GPIO_21
F13
P13
P4
SPIB_mosi
0xFFFFEA1C
0xFFFFEA00
0xFFFFEA6C
Output Disabled
Output Disabled
Output Disabled
Pull Up
SPIB_mosi
I2C_sda
SPI_HOST_INTR
SYNC_in
GPIO_12
Pull Down
Pull Down
SPI_HOST_INTR
SPIB_cs_n_1
GPIO_28
SYNC_IN
MSS_uartb_rx
DMM_MUX_IN
SYNC_OUT
IO
I
O
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
PINCNTL
SIGNAL NAME [3]
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
BALL NUMBER [1]
BALL NAME [2]
MODE [5]
TYPE [6]
ADDRESS [4]
G13
SYNC_OUT
SOP[1]
0xFFFFEA70
During Power Up
I
Output Disabled
Pull Down
GPIO_29
0
IO
O
I
SYNC_OUT
DMM_MUX_IN
SPIB_cs_n_1
SPIB_cs_n_2
GPIO_17
1
9
10
IO
IO
IO
I
11
P10
TCK
0xFFFFEA50
0
Input Enabled
Pull Down
Pull Up
TCK
1
MSS_uartb_tx
Reserved
GPIO_23
2
O
O
IO
I
8
R11
N13
TDI
0xFFFFEA58
0xFFFFEA5C
0
Input Enabled
TDI
1
MSS_uarta_rx
SOP[0]
2
I
TDO
During Power Up
I
Output Enabled
GPIO_24
0
1
2
6
7
9
0
1
2
6
0
IO
O
O
O
O
I
TDO
MSS_uarta_tx
MSS_uartb_tx
BSS_uart_tx
NDMM_EN
GPIO_18
N10
N9
TMS
0xFFFFEA54
0xFFFFEA48
IO
I
Input Enabled
Pull Down
TMS
BSS_uart_tx
Reserved
Warm_Reset
O
I
Warm_Reset
IO
Hi-Z Input (Open
Drain)
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
4. PINCNTL ADDRESS: MSS Address for PinMux Control
5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has
bit range value.
6. TYPE: Signal type and direction:
–
–
I = Input
O = Output
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–
IO = Input or Output
7. BALL RESET STATE: The state of the terminal at power-on reset
8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or
disabled via software.
–
–
–
Pull Up: Internal pullup
Pull Down: Internal pulldown
An empty box means No pull.
9. Pin Mux Control Value maps to lower 4 bits of register.
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IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Table 4-2. PAD IO Control Registers
Default Pin/Ball Name
SPI_HOST_INTR
GPIO_0
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA00
0xFFFFEA04
0xFFFFEA08
0xFFFFEA0C
0xFFFFEA10
0xFFFFEA14
0xFFFFEA18
0xFFFFEA1C
0xFFFFEA20
0xFFFFEA24
0xFFFFEA28
0xFFFFEA2C
0xFFFFEA30
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
0xFFFFEA40
0xFFFFEA44
0xFFFFEA48
0xFFFFEA4C
0xFFFFEA50
0xFFFFEA54
0xFFFFEA58
0xFFFFEA5C
0xFFFFEA60
0xFFFFEA64
0xFFFFEA68
0xFFFFEA6C
0xFFFFEA70
0xFFFFEA74
0xFFFFEA78
P13
H13
J13
D13
E14
E13
C13
F13
G14
F14
H14
R13
N12
R14
P12
R12
P11
N7
GPIO_1
SPIA_MOSI
SPIA_MISO
SPIA_CLK
SPIA_CS_N
SPIB_MOSI
SPIB_MISO
SPIB_CLK
SPIB_CS_N
QSPI[0]
QSPI[1]
QSPI[2]
QSPI[3]
QSPI_CLK
QSPI_CSN_N
NERROR_IN
WARM_RESET
NERROR_OUT
TCK
N9
N6
P10
N10
R11
N13
N8
TMS
TDI
TDO
MCU_CLKOUT
GPIO_2
K13
P9
PMIC_CLKOUT
SYNC_IN
P4
SYNC_OUT
RS232_RX
RS232_TX
G13
N4
N5
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Table 4-2. PAD IO Control Registers (continued)
Default Pin/Ball Name
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
DMM_SYNC
Package Ball /Pin (Address)
Pin Mux Config Register
0xFFFFEA7C
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0xFFFFEA8C
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEA9C
0xFFFFEAA0
0xFFFFEAA4
0xFFFFEAA8
0xFFFFEAAC
0xFFFFEAB0
0xFFFFEAB4
0xFFFFEAB8
0xFFFFEABC
0xFFFFEAC0
R4
P5
R5
P6
R7
P7
R8
P8
D14
B14
B15
C9
C8
B9
B8
A9
N15
N14
22
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The register layout is as follows:
Table 4-3. PAD IO Register Bit Descriptions
RESET
BIT FIELD
TYPE
(POWER ON
DEFAULT)
DESCRIPTION
31-11 NU
RW
RW
0
0
Reserved
10
SC
IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
9
PUPDSEL
PI
RW
RW
RW
0
0
Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8
Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7
6
OE_OVERRIDE
1
1
Output Override
OE_OVERRIDE_CTR RW
L
Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral
block hardware it is associated with for example a SPI Chip select)
5
4
IE_OVERRIDE
RW
0
0
Input Override
IE_OVERRIDE_CTR RW
L
Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0
FUNC_SEL
RW
1
Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)
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4.3 Signal Descriptions
Table 4-4. Signal Descriptions - Digital
SIGNAL NAME
BSS_UART_TX
PIN TYPE
DESCRIPTION
BALL NO.
F14, H14, K13, N10, N13,
N4, N5, R8
O
Debug UART Transmit [Radar Block]
CAN_RX
CAN_TX
DMM0
I
IO
I
CAN (DCAN) Receive Signal
B9, E13
C13, C8
R4
CAN (DCAN) Transmit Signal
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Data Line
Debug Interface (Hardware In Loop) - Clock
DMM1
I
P5
DMM2
I
R5
DMM3
I
P6
DMM4
I
R7
DMM5
I
P7
DMM6
I
R8
DMM7
I
P8
DMM8
I
D14
B14
B15
C9
DMM9
I
DMM10
DMM11
DMM12
DMM13
DMM14
DMM15
DMM_CLK
I
I
I
C8
I
B9
I
B8
I
A9
I
N15
Debug Interface (Hardware In Loop) Mux Select between DMM1 and
DMM2 (Two Instances)
DMM_MUX_IN
I
G13, J13, P4
DMM_SYNC
DSS_UART_TX
EPWM1A
EPWM1B
EPWM1SYNCI
EPWM1SYNCO
EPWM2A
EPWM2B
EPWM2SYNCO
EPWM3A
EPWM3B
EPWM3SYNCO
GPIO_0
I
Debug Interface (Hardware In Loop) - Sync
Debug UART Transmit [DSP]
PWM Module 1 - Output A
N14
O
D13, E13, G14, P8, R12
O
C8, N5, N8
O
PWM Module 1 - Output B
B9, H13, N5, P9
I
D14, J13
O
B14
O
PWM Module 2- Output A
PWM Module 2 - Output B
B8, H13, N4, N5, P9
O
A9, N4
R7
O
O
PWM Module 3 - Output A
PWM Module 3 - Output B
B15, N4
C9
O
O
P6
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
H13
J13
GPIO_1
GPIO_2
K13
E13
H14
F14
GPIO_3
GPIO_4
GPIO_5
GPIO_6
P11
R12
R13
N12
R14
GPIO_7
GPIO_8
GPIO_9
GPIO_10
24
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
PIN TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
DESCRIPTION
BALL NO.
P12
P13
H13
N5
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43
GPIO_44
GPIO_45
GPIO_46
GPIO_47
I2C_SCL
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
I2C Clock
N4
J13
P10
N10
D13
E14
F13
G14
R11
N13
N8
K13
P9
P4
G13
C13
R4
P5
R5
P6
R7
P7
R8
P8
D14
B14
B15
C9
C8
B9
B8
A9
N15
G14, N4
F13, N5
J14
J15
K14
K15
L14
L15
M14
M15
I2C_SDA
LVDS_TXP[0]
LVDS_TXM[0]
LVDS_TXP[1]
LVDS_TXM[1]
LVDS_CLKP
LVDS_CLKM
LVDS_FRCLKP
LVDS_FRCLKM
I2C Data
Differential data Out – Lane 0
Differential data Out – Lane 1
Differential clock Out
O
O
O
O
O
O
Differential Frame Clock
O
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
MCU_CLKOUT
PIN TYPE
DESCRIPTION
Programmable clock given out to external MCU or the processor
Master Subsystem - UART A Receive
BALL NO.
O
I
N8
MSS_UARTA_RX
MSS_UARTA_TX
MSS_UARTB_RX
F14, N4, R11
H14, N13, N5, R4
N4, P4
O
IO
Master Subsystem - UART A Transmit
Master Subsystem - UART B Receive
F14, H14, K13, N13, N5,
P10, P7
MSS_UARTB_TX
NDMM_EN
O
I
Master Subsystem - UART B Transmit
Debug Interface (Hardware In Loop) Enable - Active Low Signal
N13, N5
Failsafe input to the device. Nerror output from any other device can
be concentrated in the error signaling monitor module inside the
device and appropriate action can be taken by Firmware
NERROR_IN
I
N7
Open drain fail safe output signal. Connected to
NERROR_OUT
O
PMIC/Processor/MCU to indicate that some severe criticality fault
has happened. Recovery would be through reset.
N6
PMIC_CLKOUT
QSPI[0]
O
IO
IO
I
Output Clock from IWR1642 device for PMIC
QSPI Data Line #0 (Used with Serial Data Flash)
QSPI Data Line #1 (Used with Serial Data Flash)
QSPI Data Line #2 (Used with Serial Data Flash)
QSPI Data Line #3 (Used with Serial Data Flash)
QSPI Clock (Used with Serial Data Flash)
QSPI Clock (Used with Serial Data Flash)
QSPI Chip Select (Used with Serial Data Flash)
Debug UART (Operates as Bus Master) - Receive Signal
Debug UART (Operates as Bus Master) - Transmit Signal
Sense On Power - Line#0
H13, K13, P9
R13
QSPI[1]
N12
QSPI[2]
R14
QSPI[3]
IO
IO
I
P12
QSPI_CLK
QSPI_CLK_EXT
QSPI_CS_N
RS232_RX
RS232_TX
SOP[0]
R12
H14
IO
I
P11
N4
O
I
N5
N13
SOP[1]
I
Sense On Power - Line#1
G13
SOP[2]
I
Sense On Power - Line#2
P9
SPIA_CLK
SPIA_CS_N
SPIA_MISO
SPIA_MOSI
SPIB_CLK
SPIB_CS_N
SPIB_CS_N_1
SPIB_CS_N_2
SPIB_MISO
SPIB_MOSI
SPI_HOST_INTR
SYNC_IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
I
SPI Channel A - Clock
E13
SPI Channel A - Chip Select
C13
SPI Channel A - Master In Slave Out
SPI Channel A - Master Out Slave In
SPI Channel B - Clock
E14
D13
F14, R12
SPI Channel B Chip Select (Instance ID 0)
SPI Channel B Chip Select (Instance ID 1)
SPI Channel B Chip Select (Instance ID 2)
SPI Channel B - Master In Slave Out
SPI Channel B - Master Out Slave In
Out of Band Interrupt to an external host communicating over SPI
Low frequency Synchronization signal input
Low Frequency Synchronization Signal output
JTAG Test Clock
H14, P11
G13, J13, P13
G13, J13, N12
G14, R13
F13, N12
P13
P4
SYNC_OUT
TCK
O
I
G13, J13, K13, P4
P10
R11
N13
N10
N15
N14
R4
TDI
I
JTAG Test Data Input
TDO
O
I
JTAG Test Data Output
TMS
JTAG Test Mode Signal
TRACE_CLK
TRACE_CTL
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
O
O
O
O
O
O
Debug Trace Output - Clock
Debug Trace Output - Control
Debug Trace Output - Data Line
Debug Trace Output - Data Line
P5
Debug Trace Output - Data Line
R5
Debug Trace Output - Data Line
P6
26
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
Debug Trace Output - Data Line
BALL NO.
R7
TRACE_DATA_4
TRACE_DATA_5
TRACE_DATA_6
TRACE_DATA_7
TRACE_DATA_8
TRACE_DATA_9
TRACE_DATA_10
TRACE_DATA_11
TRACE_DATA_12
TRACE_DATA_13
TRACE_DATA_14
TRACE_DATA_15
O
O
O
O
O
O
O
O
O
O
O
O
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
Debug Trace Output - Data Line
P7
R8
P8
D14
B14
B15
C9
C8
B9
B8
A9
Open drain fail safe warm reset signal. Can be driven from PMIC for
diagnostic or can be used as status signal that the device is going
through reset.
WARM_RESET
IO
N9
Table 4-5. Signal Descriptions - Analog
PIN
TYPE
INTERFACE
SIGNAL NAME
DESCRIPTION
BALL NO.
TX1
TX2
RX1
RX2
RX3
RX4
O
O
I
Single ended transmitter1 o/p
B4
B6
M2
K2
H2
F2
R3
Transmitters
Single ended transmitter2 o/p
Single ended receiver1 i/p
Single ended receiver2 i/p
Single ended receiver3 i/p
Single ended receiver4 i/p
Power on reset for chip. Active low
I
Receivers
Reset
I
I
NRESET
I
In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input
reference clock port
CLKP
I
C15
Reference
Oscillator
In XTAL mode: Differential port for reference crystal
In External clock mode: Connect this port to ground
CLKM
I
D15
A14
Reference clock output from clocking sub system
after cleanup PLL (1.8V output voltage swing).
Reference clock
Bandgap voltage
OSC_CLKOUT
O
VBGAP
VDDIN
O
Device's Band Gap Reference Output
1.2V digital power supply
B10
H15, N11, P15, R6
G15
Power
Power
Power
VIN_SRAM
VNWA
1.2V power rail for internal SRAM
1.2V power rail for SRAM array back bias
P14
I/O Supply (3.3V or 1.8V): All CMOS I/Os would
operate on this supply
VIOIN
Power
R10, F15
Power supply
VIOIN_18
VIN_18CLK
VIOIN_18DIFF
VPP
Power
Power
Power
Power
1.8V supply for CMOS IO
1.8V supply for clock module
1.8V supply for LVDS port
Voltage supply for fuse chain
R9
B11
E15
L13
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Table 4-5. Signal Descriptions - Analog (continued)
PIN
TYPE
INTERFACE
SIGNAL NAME
VIN_13RF1
DESCRIPTION
BALL NO.
1.3V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
Power
G5, H5, J5
VIN_13RF2
VIN_18BB
VIN_18VCO
Power
Power
Power
1.3V Analog and RF supply
1.8V Analog base band power supply
1.8V RF VCO supply
C2,D2
K5, F5
B12
L5, L6, L8, L10,
K7, K8, K9, K10,
K11, J6, J7, J8,
VSS
Ground Digital ground
J10, H7, H9, H11,
G6, G7, G8, G10,
F9, F11, E5, E6,
E8, E10, E11, R15
Power supply
A1, A3, A5, A7,
A15, B1, B3, B5,
B7, C1, C3, C4,
C5, C6, C7, E1,
E2, E3, F3, G1,
G2, G3, H3, J1, J2,
J3, K3, L1, L2, L3,
M3, N1, N2, N3,
R1
VSSA
Ground Analog ground
VOUT_14APLL
O
Internal LDO output
Internal LDO output
Internal LDO output
ADC Channel 1(1)
ADC Channel 2(1)
ADC Channel 3(1)
ADC Channel 4(1)
ADC Channel 5(1)
ADC Channel 6(1)
A10
A13
A2, B2
P1
Internal LDO
output/inputs
VOUT_14SYNTH
VOUT_PA
O
O
Analog Test1 / ADC1
Analog Test2 / ADC2
Analog Test3 / ADC3
Analog Test4 / ADC4
ANAMUX / ADC5
VSENSE / ADC6
IO
IO
IO
IO
IO
IO
Test and Debug
output for pre-
production phase.
Can be pinned out
on production
hardware for field
debug
P2
P3
R2
B13
C14
(1) For details, see Section 6.4.1.
28
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4.4 Pin Multiplexing
Table 4-6. Pin Multiplexing
MUXMODE[15:During Power Up] SETTINGS
BALL
NUMBER
ADDRESS
During
Power Up
0
1
2
4
5
6
7
8
9
10
11
12
13
14
15
0xFFFFEA00
0xFFFFEA04
0xFFFFEA08
0xFFFFEA0C
P13
GPIO_12
GPIO_13
GPIO_16
GPIO_19
SPI_HOST
_INTR
SPIB_cs_n
_1
H13
J13
D13
GPIO_0
PMIC_CLK
OUT
ePWM1b
ePWM2a
GPIO_1
SYNC_OU
T
DMM_MUX SPIB_cs_n SPIB_cs_n ePWM1SY
_IN _1 _2 NCI
SPIA_mosi Reserved
DSS_uart_t
x
0xFFFFEA10
0xFFFFEA14
E14
E13
GPIO_20
GPIO_3
SPIA_miso Reserved
SPIA_clk
CAN_rx
CAN_tx
DSS_uart_t
x
0xFFFFEA18
0xFFFFEA1C
0xFFFFEA20
C13
F13
G14
GPIO_30
GPIO_21
GPIO_22
SPIA_cs_n
SPIB_mosi I2C_sda
SPIB_miso I2C_scl
DSS_uart_t
x
0xFFFFEA24
0xFFFFEA28
F14
H14
GPIO_5
GPIO_4
SPIB_clk
MSS_uarta
_rx
MSS_uartb BSS_uart_t Reserved
_tx
x
SPIB_cs_n MSS_uarta
_tx
MSS_uartb BSS_uart_t QSPI_clk_e Reserved
_tx
x
xt
0xFFFFEA2C
0xFFFFEA30
R13
N12
GPIO_8
GPIO_9
QSPI[0]
QSPI[1]
SPIB_miso
SPIB_mosi
SPIB_cs_n
_2
0xFFFFEA34
0xFFFFEA38
0xFFFFEA3C
R14
P12
R12
GPIO_10
GPIO_11
GPIO_7
QSPI[2]
QSPI[3]
QSPI_clk
Reserved
Reserved
SPIB_clk
DSS_uart_t
x
0xFFFFEA40
0xFFFFEA44
P11
N7
GPIO_6
QSPI_cs_n SPIB_cs_n
nERROR_I
N
0xFFFFEA48
0xFFFFEA4C
0xFFFFEA50
0xFFFFEA54
0xFFFFEA58
0xFFFFEA5C
N9
Warm_Res
et
N6
nERROR_
OUT
P10
N10
R11
N13
GPIO_17
GPIO_18
GPIO_23
GPIO_24
TCK
TMS
TDI
MSS_uartb
_tx
Reserved
BSS_uart_t
x
Reserved
MSS_uarta
_rx
SOP[0]
TDO
MSS_uarta
_tx
MSS_uartb BSS_uart_t
_tx
NDMM_EN
x
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Table 4-6. Pin Multiplexing (continued)
MUXMODE[15:During Power Up] SETTINGS
BALL
NUMBER
ADDRESS
During
Power Up
0
1
2
4
5
6
7
8
9
10
11
12
13
14
15
0xFFFFEA60
0xFFFFEA64
0xFFFFEA68
0xFFFFEA6C
0xFFFFEA70
0xFFFFEA74
0xFFFFEA78
0xFFFFEA7C
0xFFFFEA80
0xFFFFEA84
0xFFFFEA88
0xFFFFEA8C
0xFFFFEA90
0xFFFFEA94
0xFFFFEA98
0xFFFFEA9C
0xFFFFEAA0
0xFFFFEAA4
0xFFFFEAA8
0xFFFFEAAC
0xFFFFEAB0
0xFFFFEAB4
0xFFFFEAB8
N8
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_15
GPIO_14
MCU_CLK
OUT
ePWM1a
K13
P9
GPIO_2
OSC_CLK
OUT
MSS_uartb BSS_uart_t SYNC_OU PMIC_CLK
_tx
x
T
OUT
SOP[2]
SOP[1]
PMIC_CLK
OUT
ePWM1b
ePWM2a
P4
SYNC_IN
MSS_uartb DMM_MUX
_rx _IN
SYNC_OU
T
G13
N4
N5
R4
P5
SYNC_OU
T
DMM_MUX SPIB_cs_n SPIB_cs_n
_IN
_1
_2
rs232_rx
MSS_uarta
_rx
BSS_uart_t MSS_uartb Reserved I2C_scl
ePWM2a
ePWM2b
ePWM3a
ePWM1a
x
_rx
rs232_tx
MSS_uarta MSS_uartb BSS_uart_t
Reserved I2C_sda
ePWM1b
NDMM_EN ePWM2a
_tx
_tx
x
TRACE_D GPIO_31
ATA_0
DMM0
DMM1
DMM2
DMM3
DMM4
DMM5
DMM6
DMM7
DMM8
DMM9
DMM10
DMM11
DMM12
DMM13
DMM14
DMM15
MSS_uarta
_tx
TRACE_D GPIO_32
ATA_1
R5
P6
TRACE_D GPIO_33
ATA_2
TRACE_D GPIO_34
ATA_3
ePWM3SY
NCO
R7
P7
TRACE_D GPIO_35
ATA_4
ePWM2SY
NCO
TRACE_D GPIO_36
ATA_5
MSS_uartb
_tx
R8
P8
TRACE_D GPIO_37
ATA_6
BSS_uart_t
x
TRACE_D GPIO_38
ATA_7
DSS_uart_t
x
D14
B14
B15
C9
C8
B9
TRACE_D GPIO_39
ATA_8
Reserved ePWM1SY
NCI
TRACE_D GPIO_40
ATA_9
Reserved ePWM1SY
NCO
TRACE_D GPIO_41
ATA_10
ePWM3a
TRACE_D GPIO_42
ATA_11
ePWM3b
TRACE_D GPIO_43
ATA_12
ePWM1a
ePWM1b
ePWM2a
ePWM2b
CAN_tx
CAN_rx
TRACE_D GPIO_44
ATA_13
B8
TRACE_D GPIO_45
ATA_14
A9
TRACE_D GPIO_46
ATA_15
30
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Table 4-6. Pin Multiplexing (continued)
MUXMODE[15:During Power Up] SETTINGS
BALL
NUMBER
ADDRESS
During
Power Up
0
1
2
4
5
6
7
8
9
10
11
12
13
14
15
0xFFFFEABC
0xFFFFEAC0
N15
N14
TRACE_CL GPIO_47
K
DMM_CLK
TRACE_CT RESERVE DMM_SYN
L
D
C
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32
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5 Specifications
5.1 Absolute Maximum Ratings(1)(2)
Tjunction temperature range (unless otherwise noted)
PARAMETERS
MIN
–0.5
–0.5
–0.5
MAX
1.4
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
1.4
1.4
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for port
–0.5
–0.5
2
2
V
V
VIN_18CLK
VIOIN_18DIFF
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
VIN_13RF1
1.8 V supply for LVDS port
–0.5
–0.5
2
V
V
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
1.45
1-V Internal LDO bypass mode. Device supports mode where
external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_13RF2
VIN_18BB
1.8-V Analog baseband power supply
1.8-V RF VCO supply
–0.5
–0.5
2
2
V
V
VIN_18VCO supply
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
VIOIN + 0.3
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal or external oscillator input
–0.5
2
V
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
–55
105
150
ºC
ºC
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM)(1)
Charged-device model (CDM)
V(ESD)
Electrostatic discharge
V
(1) ANSI/ESDA/JEDEC JS0991 specification.
5.3 Power-On Hours (POH)(1)
JUNCTION
TEMPERATURE (Tj)
OPERATING
CONDITION
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
90% at 85ºC Tj
10% at 105ºC Tj
80,000
50% duty cycle
1.2
100% at 85ºC Tj
100,000
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
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5.4 Recommended Operating Conditions
Tjunction temperature range (unless otherwise noted)
MIN
1.14
1.14
1.14
3.15
1.71
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
1.8
MAX
UNIT
VDDIN
1.2 V digital power supply
1.32
1.32
1.32
3.45
1.89
1.9
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
VIOIN
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for LVDS port
V
V
V
VIN_18CLK
VIOIN_18DIFF
1.9
1.9
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
VIN_13RF1
VIN_13RF2
1.23
1.23
1.3
1.3
1.36
1.36
V
V
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be
kept bypassed.
VIN_13RF1
(1-V Internal LDO
bypass mode)
0.95
1
1.05
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
0.95
1
1.05
V
VIN18BB
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.17
2.25
1.8
1.8
1.9
1.9
V
V
VIN_18VCO
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
VIH
VIL
V
V
0.3*VIOIN
0.62
VOH
VOL
VIOIN – 450
mV
mV
450
0.2
VIH (1.8V Mode)
0.96
1.57
NRESET
SOP[2:0]
V
VIL (3.3V Mode)
0.3
VIH (3.3V Mode)
5.5 Power Supply Specifications
Table 5-1 describes the four rails from an external power supply block of the IWR1642 device.
Table 5-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
1.8 V
1.3 V (or 1 V in internal
LDO bypass mode)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
34
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Table 5-2 lists tolerable ripple specifications for 1.3-V (1.0-V) and 1.8-V supply rails.
Table 5-2. Ripple Specifications
RF RAIL
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
(µVRMS
1.3 V (µVRMS
)
1.8 V (µVRMS)
)
137.5
275
7.76
5.83
648.73
76.48
22.74
4.05
83.41
21.27
11.43
6.73
550
3.44
1100
2200
4400
6600
2.53
11.29
13.65
22.91
82.44
93.35
117.78
13.39
19.70
29.63
5.6 Power Consumption Summary
Table 5-3 and summarize the power consumption at the power terminals.
Table 5-3. Maximum Current Ratings at Power Terminals
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Total current drawn by
all nodes driven by
1.2V rail
VDDIN, VIN_SRAM, VNWA
1000
Total current drawn by
all nodes driven by
1.3V rail
VIN_13RF1, VIN_13RF2
2000
850
50
Current consumption
mA
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by
all nodes driven by
1.8V rail
Total current drawn by
all nodes driven by
3.3V rail
VIOIN
Table 5-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
MIN
TYP MAX UNIT
1TX, 4RX
2TX, 4RX
1TX, 4RX
2TX, 4RX
1TX, 4RX
2TX, 4RX
1TX, 4RX
2TX, 4RX
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 128 chirps,
128 samples/chirp, 8-µs
interchirp time (25% duty
cycle), DSP active
1.3
25% Duty
Cycle
1.38
1.77
1.92
1.0-V internal
LDO bypass
mode
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 256 chirps,
128 samples/chirp, 8-µs
interchirp time (50% duty
cycle), DSP active
50% Duty
Cycle
Average power
consumption
W
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 128 chirps,
128 samples/chirp, 8-µs
interchirp time (25% duty
cycle), DSP active
1.4
25% Duty
Cycle
1.48
1.94
2.14
1.3-V internal
LDO enabled
mode
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 256 chirps,
128 samples/chirp, 8-µs
interchirp time (50% duty
cycle), DSP active
50% Duty
Cycle
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5.7 RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
14
15
–8
48
24
2
MAX UNIT
76 to 77 GHz
Noise figure (Complex 1x mode)
dB
77 to 81 GHz
1-dB compression point
Maximum gain
dBm
dB
Gain range
dB
Gain step size
dB
Image Rejection Ratio (IMRR)
IF bandwidth(1)
21
dB
5
MHz
A2D sampling rate (real)
A2D sampling rate (complex)
A2D resolution
12.5 Msps
6.25 Msps
Receiver
12
<–10
±0.5
±3
Bits
dB
dB
°
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS
In-band IIP2
20
35
dBm
dBm
RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm
Out-of-band IIP2
Idle Channel Spurs
Output power
–90
12.5
–145
dBFS
dBm
Transmitter
Amplitude noise
Frequency range
Ramp rate
dBc/Hz
76
81
GHz
100 MHz/µs
Clock
subsystem
76 to 77 GHz
77 to 81 GHz
–95
–93
Phase noise at 1-MHz offset
dBc/Hz
(1) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of
available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
HPF2
175, 235, 350, 700
350, 700, 1400, 2800
The filtering performed by the baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
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Figure 5-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed.
15.6
15.3
15
-20
-24
-28
-32
-36
-40
-44
-48
NF (db)
IB P1db (dBm)
14.7
14.4
14.1
13.8
13.5
24 26 28 30 32 34 36 38 40 42 44 46 48
RX Gain (dB)
Figure 5-1. Noise Figure, In-band P1dB vs Receiver Gain
5.8 CPU Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
600
32
MAX UNIT
Clock Speed
DSP
MHz
KB
L1 Code Memory
Subsystem
(C674
Family)
L1 Data Memory
32
KB
L2 Memory
256
200
256
192
KB
Master
Clock Speed
MHz
KB
Controller
Subsystem
(R4F Family)
Tightly Coupled Memory - A (Program)
Tightly Coupled Memory - B (Data)
KB
Shared
Memory
Shared L3 Memory
768
KB
5.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161](1)
THERMAL METRICS(2)
°C/W(3) (4)
4.92
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
PsiJB
Junction-to-case
Junction-to-board
6.57
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
22.3
N/A(1)
4.92
6.4
(1) N/A = not applicable
(2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(3) °C/W = degrees Celsius per watt.
(4) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 105ºC is assumed.
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5.10 Timing and Switching Characteristics
5.10.1 Power Supply Sequencing and Reset Timing
The IWR1642 device expects all external voltage rails to be stable before reset is deasserted. Figure 5-2
describes the device wake-up sequence.
PMIC_CLKOUT
Power down
sequence
(SOP[2]),
SYNC_OUT(SOP
[1]), TDO
001 (Functional)
CAN BE CHANGED
(SOP[0])
(VIOIN)
Includes ramping of VIOIN_18
(VIOIN_18DIFF)
(VDDIN)
(VIN_*)
Includes ramping of all other supplies VIN_18BB, VIN_18CLK, VIN_13RF*, VION_18DIFF
3mS
3mS
(NRESET)
MCU_CLK_OUT(1)
External
Signals
(1) MCU_CLK_OUT in autonomous mode, where IWR1642 application is booted from the serial flash, MCU_CLK_OUT is not enabled
by default by the device bootloader.
Controls HHV of IO
PORZ_1P8V
PORZ_TOP/ GEN_TOP
FUSE_SHIFT_EN
EFC_READY
Reset Control to Top Digital and Analog
~400 cycles
XTAL_DET_STAT
XTAL STATUS 1 if XTAL FOUND/ ‘0’ if EXTERNAL CLK is FORCED
XTAL_EN/ SLICER_EN
Reference Clock Stabilization time
~5mS
SLICER_REF_CLK
(CLKP+CLKM thru’ SLICER)
CPU CLK is REF CLK if STATUS is 1
ELSE INT_RCOSC_CLK if STATUS is 0
CPU_CLK
1 IF REF CLK is NOT PRESENT
LIMP_MODE_STATUS
PORZ_CPU/
PORZ_DIG/
GEN_ANA
Reset Control to Digital Processor and Analog/RF
Internal Signals
Wake Up Done
Mentioned for reference only
*Names are representative
Figure 5-2. Device Wake-up Sequence
38
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5.10.2 Input Clocks and Oscillators
5.10.2.1 Clock Specifications
The IWR1642 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for
initial boot and as a reference for an internal APLL hosted in the device.
An external crystal is connected to the device pins. Figure 5-3 shows the crystal implementation.
Cf1
XTALP
Cp
40 MHz
XTALM
Cf2
Figure 5-3. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-3, should be chosen such that Equation 1 is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator CLKP and CLKM pins.
C f2
CL = C f1
´
+CP
C
f1 +C f2
Table 5-5 lists the electrical characteristics of the clock crystal.
Table 5-5. Crystal Electrical Characteristics (Oscillator Mode)
(1)
NAME
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
40
8
MAX
UNIT
MHz
pF
fP
CL
Crystal load capacitance
Crystal ESR
5
12
50
ESR
Ω
Temperature range Expected temperature range of operation
–40
–50
105
ºC
Frequency
tolerance
Crystal frequency tolerance(1)(2)(3)
50
ppm
µW
Drive level
50
200
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
(3) Crystal tolerance affects radar sensor accuracy.
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In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only;
CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally.
Table 5-6 lists the electrical characteristics of the external clock signal.
Table 5-6. External Clock Mode Specifications
SPECIFICATION
PARAMETER
Frequency
UNIT
MIN
TYP
MAX
40
MHz
mV (pp)
V
AC-Amplitude
700
0.00
1.6
1200
0.20
1.95
–132
–143
–152
–153
65
DC-Vil
DC-Vih
V
Input Clock:
External AC-coupled sine wave or DC-
coupled square wave
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
Phase Noise referred to 40MHz
(80GHz)
35
Freq Tolerance
Freq Tolerance
–50
–50
50
ppm
50
ppm
40
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5.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.10.3.1 Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
•
•
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals
5.10.3.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
Table 5-8 to Table 5-11 assume the operating conditions stated in Table 5-7.
Table 5-7. SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
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Table 5-8. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
25
TYP
MAX
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
256tc(VCLK)
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
2(4)
3(4)
4(4)
5(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 0
Setup time CS active until SPICLK high
(clock polarity = 0)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 1
6(5)
tC2TDELAY
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7
7(5)
tT2CDELAY
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
(T2CDELAY + 1)
*tc(VCLK) – 7
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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Table 5-9. SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)
NO.
MIN
TYP
MAX
UNIT
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
5
8(2)
ns
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
3
3
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
9(2)
ns
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
11
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-4. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 5-5. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
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Table 5-10. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
25
TYP
MAX
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
256tc(VCLK)
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
2(4)
3(4)
4(4)
5(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 0
(C2TDELAY +
2)*tc(VCLK) – 7
(C2TDELAY+2) *
tc(VCLK) + 7.5
Setup time CS active until SPICLK high
(clock polarity = 0)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 1
CSHOLD = 0
(C2TDELAY +
2)*tc(VCLK) – 7
(C2TDELAY+2) *
tc(VCLK) + 7.5
6(5)
tC2TDELAY
ns
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY+2)*tc(
VCLK) – 7
Setup time CS active until SPICLK low
(clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 1
(C2TDELAY+3)*tc(
VCLK) – 7
(C2TDELAY+3) *
tc(VCLK) + 7.5
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
7(5)
tT2CDELAY
ns
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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Table 5-11. SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)
NO.
MIN
TYP
MAX
UNIT
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
5
5
3
3
8(2)
ns
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
9(2)
ns
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-6. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 5-7. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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5.10.3.3 SPI Slave Mode I/O Timings
Table 5-12. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)(1)(2)(3)
NO.
PARAMETER
Cycle time, SPICLK(4)
MIN
25
TYP
MAX
UNIT
1
tc(SPC)S
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
10
2(5)
3(5)
ns
ns
10
10
10
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
10
10
4(5)
ns
ns
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
2
5(5)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0; clock phase = 0) OR (clock polarity = 1;
clock phase = 1)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
10
10
4(5)
ns
ns
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1; clock phase = 0) OR (clock polarity = 0;
clock phase = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
2
2
5(5)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
(3) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Table 5-13. SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
NO.
MIN
3
TYP
MAX UNIT
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCL-SIMO)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0)
6(1)
ns
3
0
7(1)
ns
ns
0
Setup time, SPISIMO before SPICLK low (clock polarity = 0; clock phase = 0)
OR (clock polarity = 1; clock phase = 1)
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCL-SIMO)S
3
3
1
1
6(1)
Setup time, SPISIMO before SPICLK high (clock polarity = 1; clock phase =
0) OR (clock polarity = 0; clock phase = 1)
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0; clock
phase = 0) OR (clock polarity = 1; clock phase = 1)
7(1)
ns
Hold time, SPISIMO data valid after SPICLK high (clock polarity = 1; clock
phase = 0) OR (clock polarity = 0; clock phase = 1)
(1) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-8. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-9. SPI Slave Mode External Timing (CLOCK PHASE = 1)
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5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI
clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 5-10 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x4321
0x1234
CRC
0x5678
0x8765
MOSI
MISO
IRQ
0xDCBA
0xABCD
CRC
16 bytes
Figure 5-10. SPI Communication
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5.10.4 LVDS Interface Configuration
The supports four differential LVDS IOs/Lanes. The lane configuration supported is two Data lanes
(LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The
LVDS interface supports the following data rates:
•
•
•
•
•
•
•
900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to
data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 5-11. LVDS Interface Lane Configuration And Relative Timings
5.10.4.1 LVDS Interface Timings
twH1
twL1
twL2
LVDS_CLK
twH2
Calculation showing tw parameters:
Freq = 900MHz, Period = 1.11ns
At 50% twH1/twL1 = 1.11ns/2 = 0.55ns
Rise time = Fall time = 200ps (as per LVDS IO spec @1pF load)
twH2/twL2 = (1.11ns-2*200ps)/2 = 0.35ns
200ps
LVDS_CLK
Clock Jitter = 6sigma = 60ps
LVDS_TXP/M
LVDS_FRCLKP/M
200ps
200ps
1100ps
Figure 5-12. Timing Parameters
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Table 5-14. LVDS Electrical Characteristics
PARAMETER
twH1 / twL1
TEST CONDITIONS
MIN
TYP
0.55
0.35
MAX
UNIT
ns
twH2 / twL2
ns
max 1 pF lumped capacitive load on
LVDS lanes
48%
52%
Duty Cycle Requirements
VOH
VOL
1475
mV
mV
925
250
peak-to-peak single-ended with 100
Ω resistive load between differential
pairs
Output Differential Voltage
Output Offset Voltage
450
mV
mV
1125
1275
50
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5.10.5 General-Purpose Input/Output
Table 5-15 lists the switching characteristics of output timing relative to load capacitance.
Table 5-15. Switching Characteristics for Output Timing versus Load Capacitance (CL)(1)(2)
PARAMETER
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
2.878
6.446
9.43
VIOIN = 3.3V
3.013
UNIT
tr
tf
tr
tf
Max rise time
CL = 50 pF
6.947
ns
CL = 75 pF
10.249
2.883
Slew control = 0
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
2.827
6.442
9.439
3.307
6.77
Max fall time
Max rise time
Max fall time
6.687
ns
ns
ns
9.873
3.389
7.277
9.695
3.128
6.656
9.605
10.57
Slew control = 1
3.128
6.656
9.605
(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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5.10.6 Controller Area Network Interface (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable
serial communication or multiplexed wiring.
The DCAN has the following features:
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbps
Configurable Message objects
Individual identifier masks for each message object
Programmable FIFO mode for message objects
Suspend mode for debug support
Programmable loop-back modes for self-test operation
Direct access to Message RAM in test mode
Supports two interrupt lines - Level 0 and Level 1
Automatic Message RAM initialization
Table 5-16. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
15
UNIT
ns
td(CAN_tx)
td(CAN_rx)
Delay time, transmit shift register to CAN_tx pin(1)
Delay time, CAN_rx pin to receive shift register(1)
10
ns
(1) These values do not include rise/fall times of the output buffer.
5.10.7 Serial Communication Interface (SCI)
The SCI has the following features:
•
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Standard non-return to zero (NRZ) format
Double-buffered receive and transmit functions
Asynchronous or iso-synchronous communication modes with no CLK pin
Capability to use Direct Memory Access (DMA) for transmit and receive data
Two external pins: RS232_RX and RS232_TX
Table 5-17. SCI Timing Requirements
MIN
TYP
921.6
MAX
UNIT
kHz
f(baud)
Supported baud rate at 20 pF
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5.10.8 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by
an I2C-bus™. This module will support any slave or master I2C compatible device.
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
–
–
–
–
–
–
–
–
Bit/Byte format transfer
7-bit and 10-bit device addressing modes
General call
START byte
Multi-master transmitter/ slave receiver mode
Multi-master receiver/ slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
•
•
•
•
•
•
•
•
•
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
NOTE
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
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Table 5-18. I2C Timing Requirements(1)
STANDARD MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
tc(SCL)
Cycle time, SCL
10
2.5
μs
μs
Setup time, SCL high before SDA low
(for a repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low
(for a START and a repeated START condition)
th(SCLL-SDAL)
μs
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SCLL-SDA)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45(1)
0.9
Pulse duration, SDA high between STOP and START
conditions
tw(SDAH)
4.7
4
1.3
μs
μs
Setup time, SCL high before SDA high
(for STOP condition)
tsu(SCLH-SDAH)
tw(SP)
0.6
0
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(2)(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 5-13. I2C Timing Diagram
NOTE
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a
Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tsu(SDA-SCLH)
.
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5.10.9 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast
booting from quad-SPI flash memories.
The QSPI supports the following features:
•
•
•
•
•
•
•
Programmable clock divider
Six-pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Refer to the Technical Reference Manual for details on QSPI SFDP register and power on values MSS
BootROM required items.
Table 5-20 and Table 5-21 assume the operating conditions stated in Table 5-19.
Table 5-19. QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
Table 5-20. Timing Requirements for QSPI Input (Read) Timings(1)(2)
MIN
7.3
TYP
MAX
UNIT
ns
tsu(D-SCLK)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
1.5
ns
Setup time, final d[3:0] bit valid before final falling sclk edge
Hold time, final d[3:0] bit valid after final falling sclk edge
7.3 – P(3)
1.5 + P(3)
ns
ns
(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-
standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI sevices that
launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.
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Table 5-21. QSPI Switching Characteristics
NO.
Q1
Q2
Q3
PARAMETER
MIN
TYP
MAX
UNIT
ns
tc(SCLK)
Cycle time, sclk
25
tw(SCLKL)
tw(SCLKH)
Pulse duration, sclk low
Pulse duration, sclk high
Y*P – 3(1)(2)
Y*P – 3(1)(1)
ns
ns
–M*P +
2.5(1)(3)
Q4
Q5
td(CS-SCLK)
td(SCLK-CS)
Delay time, sclk falling edge to cs active edge
Delay time, sclk falling edge to cs inactive edge
–M*P – 1(1)(3)
N*P – 1(1)(3)
ns
ns
N*P +
2.5(1)(3)
Q6
Q7
Q8
td(SCLK-D1)
tena(CS-D1LZ)
tdis(CS-D1Z)
Delay time, sclk falling edge to d[1] transition
Enable time, cs active edge to d[1] driven (lo-z)
Disable time, cs active edge to d[1] tri-stated (hi-z)
–3.5
–P – 4(3)
–P – 4(3)
7
–P +1(3)
–P +1(3)
ns
ns
ns
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
Q9
td(SCLK-D1)
–3.5 – P(3)
7 – P(3)
ns
Q12
Q13
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
7.3
1.5
ns
ns
Setup time, final d[3:0] bit valid before final falling sclk
edge
Q14
Q15
tsu(D-SCLK)
th(SCLK-D)
7.3 — P(3)
1.5 + P(3)
ns
ns
Hold time, final d[3:0] bit valid after final falling sclk
edge
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period in ns.
(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2
PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_02
Figure 5-14. QSPI Read (Clock Mode 0)
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PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 5-15. QSPI Write (Clock Mode 0)
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5.10.10 ETM Trace Interface
Table 5-23 and assume the recommended operating conditions stated in Table 5-22.
Table 5-22. ETMTRACE Timing Conditions
MIN
TYP
MAX
UNIT
Output Conditions
CLOAD Output load capacitance
2
20
pF
Table 5-23. ETM TRACE Switching Characteristics
NO.
PARAMETER
Cycle time, TRACECLK period
Pulse Duration, TRACECLK High
Pulse Duration, TRACECLK Low
Clock and data rise time
MIN
20
9
TYP
MAX
UNIT
ns
1
2
3
4
5
tcyc(ETM)
th(ETM)
ns
tl(ETM)
9
ns
tr(ETM)
3.3
ns
tf(ETM)
Clock and data fall time
3.3
7
ns
td(ETMTRAC
ECLKH-
1
1
ns
6
7
Delay time, ETM trace clock high to ETM data valid
Delay time, ETM trace clock low to ETM data valid
ETMDATAV)
td(ETMTRAC
ECLKl-
7
ns
ETMDATAV)
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 5-16. ETMTRACECLKOUT Timing
Figure 5-17. ETMDATA Timing
58
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5.10.11 Data Modification Module (DMM)
A Data Modification Module (DMM) gives the ability to write external data into the device memory.
The DMM has the following features:
•
•
Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port [RTP] module)
•
Writes received data to consecutive addresses, which are specified by the DMM (leverages packets
defined by direct data mode of RTP module)
•
•
Configurable port width (1, 2, 4, 8, 16 pins)
Up to 65 Mbit/s pin data rate
Table 5-24. DMM Timing Requirements
MIN
TYP
MAX
UNIT
ns
tcyc(DMM)
Clock period
15.4
1
tR
Clock rise time
3
3
ns
tF
Clock fall time
1
ns
th(DMM)
tl(DMM)
tssu(DMM)
tsh(DMM)
tdsu(DMM)
tdh(DMM)
High pulse width
6
ns
Low pulse width
6
ns
SYNC active to clk falling edge setup time
DMM clk falling edge to SYNC deactive hold time
DATA to DMM clk falling edge setup time
DMM clk falling edge to DATA hold time
2
ns
3
ns
2
ns
3
ns
tl(DMM)
th(DMM)
tf
tr
tcyc(DMM)
Figure 5-18. DMMCLK Timing
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 5-19. DMMDATA Timing
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5.10.12 JTAG Interface
Table 5-26 and Table 5-27 assume the operating conditions stated in Table 5-25.
Table 5-25. JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
Table 5-26. Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
MAX
UNIT
ns
1
tc(TCK)
Cycle time TCK
66.66
26.67
26.67
2.5
1a
1b
tw(TCKH)
Pulse duration TCK high (40% of tc)
Pulse duration TCK low(40% of tc)
Input setup time TDI valid to TCK high
Input setup time TMS valid to TCK high
Input hold time TDI valid from TCK high
Input hold time TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
2.5
ns
18
ns
18
ns
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
25
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 5-20. JTAG Timing
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6 Detailed Description
6.1 Overview
The IWR1642 device includes the entire Millimeter Wave blocks and analog baseband signal chain for two
transmitters and four receivers, as well as a customer-programmable MCU and DSP. This device is
applicable as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity
and application code size. These could be cost-sensitive industrial radar sensing applications. Examples
are:
•
•
•
•
•
•
Industrial level sensing
Industrial automation sensor fusion with radar
Traffic intersection monitoring with radar
Industrial radar-proximity monitoring
People counting
Gesturing
In terms of scalability, the IWR1642 device could be paired with a low-end external MCU, to address more
complex applications that might require additional memory for larger application software footprint and
faster interfaces. The IWR1642 has an embedded DSP for signal processing, processing the radar signals
for FFT, magnitude, detection and other applications.
6.2 Functional Block Diagram
Serial Flash
interface
QSPI
Cortex-R4F
@ 200-MHz
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
RX1
Optional External
MCU interface
SPI
(User programmable)
RX2
RX3
RX4
SPI / I2C
DCAN
PMIC control
Digital Front
End
Prog
RAM
Data
RAM
Boot
ROM
Optional communication
interface
(256KB*) (192KB*)
(Decimation
filter chain)
DMA
Debug
UARTs
For debug
Master subsystem
JTAG for debug/
development
(Customer programmed)
Test/
Debug
TX1
TX2
PA
Mailbox
High-speed ADC output
interface (for recording)
LVDS
HIL
Synth
(20 GHz)
Ramp
Generator
PA
x4
High-speed input for
hardware-in-loop
verification
C674x DSP
@600 MHz
ADC
Buffer
6
RF Control/
BIST
L1P
(32KB)
L2
(256KB)
L1D
(32KB)
GPADC
Osc.
VMON
Temp
DMA
CRC
Radar Data Memory
(L3)
DSP subsystem
(Customer programmed)
768KB*
RF/Analog subsystem
* Up to 512KB of Radar Data Memory can be switched to the Master R4F if required
6.3 Subsystems
6.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA,
mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The two
transmit channels can be operated simultaneously. The four receive channels can be operated
simultaneously.
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6.3.1.1 Clock Subsystem
The IWR1642 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has
a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF
synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz
spectrum. The RF synthesizer output is modulated by the timing engine block to create the required
waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring
the quality of the generated clock.
Figure 6-1 describes the clock subsystem.
Self Test
RF SYNTH
Timing
SYNC_OUT
Engine
Lock Detect
SoC Clock
Clean-
Up PLL
x4
MULT
XO/
Slicer
CLK Detect
40 MHz
Figure 6-1. Clock Subsystem
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6.3.1.2 Transmit Subsystem
The IWR1642 transmit subsystem consists of two parallel transmit chains, each with independent phase
and amplitude control. The device supports binary phase modulation for MIMO radar and interference
mitigation.
Each transmit chain can deliver a maximum of 12.5 dBm at the antenna port on the PCB. The transmit
chains also support programmable backoff for system optimization.
Figure 6-2 describes the transmit subsystem.
Self Test
Loopback
Path
PCB
12 dBm
at 50 W
DF
LO
0 or 180°
(from Timing
Engine)
Figure 6-2. Transmit Subsystem (Per Channel)
6.3.1.3 Receive Subsystem
The IWR1642 receive subsystem consists of four parallel channels. A single receive channel consists of
an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational
at the same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the IWR1642 device supports a complex baseband architecture,
which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each
receiver channel. The IWR1642 is targeted for fast chirp systems. The band-pass IF chain has
configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 5 MHz.
Figure 6-3 describes the receive subsystem.
Self Test
DAC
Loopback
Path
DSM
PCB
I
RSSI
50 W
GSG
LO
Q
DSM
DAC
Figure 6-3. Receive Subsystem (Per Channel)
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6.3.2 Processor Subsystem
Unified
128KB x 2
ROM
L2
Cache/
RAM
TCM A 256KB
TCM B 192KB
L1P
32KB
32KB
EDMA
Master
R4F
DSP
HIL
JTAG
CRC
HIL
L1d
DSP Interconnect œ 128 bit @ 200 MHz
Master Interconnect
BSS Interconnect
Data
Handshake
Memory
CRC
ADC Buffer
Mail
Box
MSS
DMA
L3
32KB
32KB Ping-Pong
768KB
(static sharing
with R4F Space)
Interconnect
LVDS
PWM,
PMIC
CLK
I2C
QSPI
UART
CAN
SPI
Copyright © 2017, Texas Instruments Incorporated
Figure 6-4. Processor Subsystem
Figure 6-4 shows the block diagram for customer programmable processor subsystems in the IWR1642
device. At a high level there are two customer programmable subsystems, as shown separated by a
dotted line in the diagram. Left hand side shows the DSP Subsystem which contains TI's high-
performance C674x DSP, a high-bandwidth interconnect for high performance (128-bit, 200MHz) and
associated peripherals – four DMAs for data transfer, LVDS interface for Measurement data output, L3
Radar data cube memory, ADC buffers, CRC engine, and data handshake memory (additional memory
provided on interconnect).
The right side of the diagram shows the Master subsystem. Master subsystem as name suggests is the
master of the device and controls all the device peripherals and house-keeping activities of the device.
Master subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and house-
keeping components such as DMAs, CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking
module, PWM, and others) connected to Master Interconnect through Peripheral Central Resource (PCR
interconnect).
Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748.
HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the
captured data from outside into the device without involving the RF subsystem. HIL on master SS is for
controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL
modules uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of
the two.
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6.3.3 Host Interface
The host interface can be provided through a SPI, UART, or CAN interface. In some cases the serial
interface for industrial applications is transcoded to a different serial standard.
The IWR1642 device communicates with the host radar processor over the following main interfaces:
•
•
Reference Clock – Reference clock available for host processor after device wakeup
Control – 4-port standard SPI (slave) for host control. All radio control commands (and response) flow
through this interface.
•
•
•
Reset – Active-low reset for device wakeup from host
Host Interrupt - an indication that the mmwave sensor needs host interface
Error – Used for notifying the host in case the radio controller detects a fault
6.3.4 Master Subsystem Cortex-R4F Memory Map
Table 6-1 shows the master subsystem, Cortex-R4F memory map.
NOTE
There are separate Cortex-R4F addresses and DMA MSS addresses for the master
subsystem. See the Technical Reference Manual for a complete list.
Table 6-1. Master Subsystem, Cortex-R4F Memory Map
FRAME ADDRESS (HEX)
NAME
SIZE
DESCRIPTION
START
CPU Tightly-Coupled Memories
END
TCMA ROM
TCM RAM-A
0x0000_0000
0x0020_0000
0x0001_FFFF
128 KiB
512 KiB
Program ROM
0x0023_FFFF (or
0x0027_FFFF)
256/512KB based on variant
TCM RAM-B
0x0800_0000
0x0802_FFFF
192 KB
8 KB
Data RAM
S/W Scratch Pad Memory
SW_ Buffer
0x0C20_0000
0x0C20_1FFF
S/W Scratchpad memory
System Peripherals
Mail Box
MSS<->RADARSS
0xF060_1000
0xF060_2000
0xF060_8000
0xF060_17FF
0xF060_27FF
0xF060_80FF
2 KB
RADARSS to MSS mailbox memory space
MSS to RADARSS mailbox memory space
188 B
MSS to RADARSS mailbox Configuration
registers
0xF060_8060
0xF060_86FF
RADARSS to MSS mailbox Configuration
registers
Mail Box
MSS<->DSPSS
0xF060_4000
0xF060_5000
0xF060_8400
0xF060_8300
0xF060_6000
0xF060_7000
0xF060_8200
0xF060_47FF
0xF060_57FF
0xF060_84FF
0xF060_83FF
0xF060_67FF
0xF060_7FFF
0xF060_82FF
2 KB
DSPSS to MSS mailbox memory space
MSS to DSPSS mailbox memory space
188 B
2 KB
MSS to DSPSS mailbox Configuration registers
DSPSS to MSS mailbox Configuration registers
RADARSS to DSPSS mailbox memory space
DSPSS to RADARSS mailbox memory space
Mail Box
RADARSS<-
>DSPSS
188 B
RADARSS to DSPSS mailbox Configuration
registers
0xF060_8100
0xF060_81FF
DSPSS to RADARSS mailbox Configuration
registers
PRCM and Control
Module
0xFFFF_E100
0xFFFF_FF00
0xFFFF_EA00
0xFFFF_F800
0xFFFF_E2FF
0xFFFF_FFFF
0xFFFF_EBFF
0xFFFF_FBFF
756 B
256 B
512 KB
352 B
TOP Level Reset, Clock management registers
MSS Reset, Clock management registers
IO Mux module registers
General-purpose control registers
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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)
FRAME ADDRESS (HEX)
START END
NAME
SIZE
DESCRIPTION
GIO
0xFFF7_BC00
0xFFFF_F000
0xFCFF_F800
0xFCFF_F700
0xFCFF_F600
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_EE00
0xFFF7_BDFF
0xFFFF_F3FF
0xFCFF_FBFF
0xFCFF_F7FF
0xFCFF_F6FF
0xFFFF_FEFF
0xFFFF_FCFF
0xFFFF_EEFF
180 B
GIO module configuration registers
DMA-1
DMA-2
DMM-1
DMM-2
VIM
1 KB
DMA-1 module configuration registers
DMA-2 module configuration registers
DMM-1 module configuration registers
DMM-2 module configuration registers
VIM module configuration registers
RTI-A module configuration registers
RTI-B module configuration registers
1 KB
472 B
472 B
512 B
192 B
192 B
RTI-A/WD
RTI-B
Serial Interfaces and Connectivity
QSPI
0xC000_0000
0xC080_0000
0xFFF7_F400
0xFFF7_F600
0xFFF7_E500
0xFFF7_E700
0xFFF7_DC00
0xFFF7_C800
0xFFF7_A000
0xFFF7_D400
0xC07F_FFFF
0xC0FF_FFFF
0xFFF7_F5FF
0xFFF7_F7FF
0xFFF7_E5FF
0xFFF7_E7FF
0xFFF7_DDFF
0xFFF7_CFFF
0xFFF7_A1FF
0xFFF7_D4FF
8 MB
QSPI –flash memory space
116 B
512 B
512 B
148 B
148 B
512 B
768 B
452 B
112 B
QSPI module configuration registers
MIBSPI-A module configuration registers
MIBSPI-B module configuration registers
SCI-A module configuration registers
SCI-B module configuration registers
CAN module configuration registers
Reserved
MIBSPI-A
MIBSPI-B
SCI-A
SCI-B
CAN
RESERVED
Reserved
I2C
I2C module configuration registers
Interconnects
PCR-1
0xFFF7_8000
0xFCFF_1000
0xFFF7_87FF
0xFCFF_17FF
1 KiB
1 KiB
PCR-1 interconnect configuration port
PCR-2 interconnect configuration port
PCR-2
Safety Modules
CRC
0xFE00_0000
0xFFFF_E400
0xFFFF_E600
0xFFFF_EC00
0xFFFF_F400
0xFFFF_F500
0xFFFF_F600
0xFEFF_FFFF
0xFFFF_E5FF
0xFFFF_E7FF
0xFFFF_ECFF
0xFFFF_F4FF
0xFFFF_F5FF
0xFFFF_F6FF
16 KiB
464 B
284 B
44 B
CRC module configuration registers
PBIST module configuration registers
STC module configuration registers
DCC-A module configuration registers
DCC-B module configuration registers
ESM module configuration registers
CCMR4 module configuration registers
PBIST
STC
DCC-A
DCC-B
44 B
ESM
156 B
136 B
CCMR4
Other Subsystems
DSS_TPTC0
DSS_REG
DSS_TPTC1
DSS_REG2
DSS_TPCC0
DSS_RTIA/WDT
DSS_SCI
DSS_STC
DSS_CBUFF
DSS_TPTC2
DSS_TPTC3
DSS_TPCC1
DSS_ESM
DSS_RTIB
0x5000 0000
0x5000 0400
0x5000 0800
0x5000 0C00
0x5001 0000
0x5002 0000
0x5003 0000
0x5004 0000
0x5007 0000
0x5009 0000
0x5009 0400
0x500A 0000
0x500D 0000
0x500F 0000
0x5000 0317
0x5000 075F
0x5000 0B17
0x5000 0EA3
0x5001 3FFF
0x5002 00BF
0x5003 0093
0x5004 011B
0x5007 0233
0x5009 0317
0x5009 0717
0x500A 3FFF
0x500D 005B
0x500F 00BF
792 B
864 B
792 B
676 B
16 KB
192 B
148 B
284 B
564 B
792 B
792 B
16 KB
92 B
TPTC0 module configuration space
DSPSS control module registers
TPTC1 module configuration space
DSPSS control module registers
TPCC0 module configuration space
DSS_RTIA/WDT configuration space
SCI memory space
STC module configuration space
Common Buffer module configuration registers
TPTC2 module configuration space
TPTC3 module configuration space
TPCC1 module configuration space
ESM module configuration registers
RTI-B module configuration registers
192 B
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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)
FRAME ADDRESS (HEX)
START END
NAME
SIZE
DESCRIPTION
L3 shared memory space
DSS_L3RAM
0x5100 0000
0x511F FFFF
2 MB(1)
Shared memory
DSS_ADCBUF
Buffer
0x5200 0000
0x5200 7FFF
32 KB
ADC buffer memory space
DSS_CBUFF_FIFO 0x5202 0000
DSS_HSRAM1 0x5208 0000
0x5202 3FFF
0x5208 7FFF
0x577F FFFF
16 KB
32 KB
128 KB
Common buffer FIFO space
Handshake memory space
L2 RAM space
DSS_DSP_L2_UMA 0x577E 0000
P1
DSS_DSP_L2_UMA 0x5780 0000
P0
0x5781 FFFF
128 KB
L2 RAM space
DSS_DSP_L1P
DSS_DSP_L1D
0x57E0 0000
0x57F0 0000
0x57E0 7FFF
0x57F0 7FFF
32 KB
32 KB
L1 program memory space
L1 data memory space
Peripheral Memories (System and Nonsystem)
CAN RAM
0xFF1E_0000
0xFF50_0000
0xFFF8_0000
0xFCF8 1000
0xFFF8_2000
0xFF0C_0000
0xFF0C_0200
0xFF0E_0000
0xFF1F_FFFF
0xFF51_FFFF
0xFFF8_0FFF
0xFCF8_0FFF
0xFFF8_2FFF
0xFF0C_01FF
0xFF0C_03FF
0xFF0E_01FF
0xFF0E_03FF
128 KB
68 KB
4 KB
CAN RAM memory space
Reserved
RESERVED
DMA1 RAM
DMA1 RAM memory space
DMA2 RAM memory space
VIM RAM memory space
DMA2 RAM
4 KB
VIM RAM
2 KB
MIBSPIB-TX RAM
MIBSPIB-RX RAM
MIBSPIA-TX RAM
0.5 KB
0.5 KB
0.5 KB
0.5 KB
MIBSPIB-TX RAM memory space
MIBSPIB-RX RAM memory space
MIBSPIA-TX RAM memory space
MIBSPIA- RX RAM memory space
MIBSPIA- RX RAM 0xFF0E_0200
Debug Modules
Debug subsystem
0xFFA0_0000
0xFFAF_FFFF
244 KB
Debug subsystem memory space and registers
(1) 768 KB memory within 2 MB memory space
6.3.5 DSP Subsystem Memory Map
Table 6-2 shows the DSP C674x memory map.
Table 6-2. DSP C674x Memory Map
Name
Frame Address (Hex)
End
Size
Description
Start
DSP Memories
DSP_L1D
0x00F0_0000
0x00E0_0000
0x00F0_7FFF
32 KiB
32 KiB
L1 data memory space
DSP_L1P
0x00E0_7FFF
L1 program memory
space
DSP_L2_UMAP0
DSP_L2_UMAP1
EDMA
0x0080_0000
0x007E_0000
0x0081_FFFF
0x007F_FFFF
128 KiB
128 KiB
L2 RAM space
L2 RAM space
TPCC0
0x0201_0000
0x020A_0000
0x0200 0000
0x0200 0800
0x0209_0000
0x0201_3FFF
0x020A_3FFF
0x0200 03FF
0x0200 0BFF
0x0209_03FF
16 KiB
16 KiB
1 KiB
1 KiB
1 KiB
TPCC0 module
configuration space
TPCC1
TPTC0
TPTC1
TPTC2
TPCC1 module
configuration space
TPTC0 module
configuration space
TPTC1 module
configuration space
TPTC2 module
configuration space
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Table 6-2. DSP C674x Memory Map (continued)
Name
Frame Address (Hex)
End
Size
Description
Start
TPTC3
0x0209_0400
0x0209_07FF
1 KiB
TPTC3 module
configuration space
Control Registers
DSS_REG
0x0200_0400
0x0200_0C00
0x0200_07FF
0x0200_0FFF
864 B
624 B
DSPSS control module
registers
DSS_REG2
DSPSS control module
registers
System Memories
ADC Buffer
0x2100_0000
0x2102_0000
0x2100_7FFC
0x2102_3FFC
32 KiB
16 KiB
ADC buffer memory space
CBUFF-FIFO
Common buffer FIFO
space
L3-Shared memory
HS-RAM
0x2000_0000
0x2108_0000
0x201F_FFFF
0x2108_7FFC
2 MB(1)
32 KiB
L3 shared memory space
Handshake memory
space
System Peripherals
RTI-A/WD
0x0202_0000
0x020F_0000
0x0207_0000
0x5060_1000
0x5060_2000
0x0460_8000
0x0202_00FF
0x020F_00FF
0x0207_03FF
0x5060_17FF
0x5060_27FF
0x0460_80FF
192 B
192 B
564 B
2 KiB
RTI-A module
configuration registers
RTI-B
RTI-B module
configuration registers
CBUFF
Common Buffer module
Configuration registers
Mail Box
MSS<->RADARSS
RADARSS to MSS
mailbox memory space
MSS to RADARSS
mailbox memory space
188 B
MSS to RADARSS
mailbox Configuration
registers
0x0460_8060
0x0460_86FF
RADARSS to MSS
mailbox Configuration
registers
Mail Box
MSS<->DSPSS
0x5060_4000
0x5060_5000
0x0460_8400
0x0460_8300
0x5060_6000
0x5060_7000
0x0460_8200
0x5060_47FF
0x5060_57FF
0x0460_84FF
0x0460_83FF
0x5060_67FF
0x5060_7FFF
0x0460_82FF
2 KiB
188 B
2 KiB
188 B
DSPSS to MSS mailbox
memory space
MSS to DSPSS mailbox
memory space
MSS to DSPSS mailbox
Configuration registers
DSPSS to MSS mailbox
Configuration registers
Mail Box
RADARSS<->DSPSS
RADARSS to DSPSS
mailbox memory space
DSPSS to RADARSS
mailbox memory space
RADARSS to DSPSS
mailbox Configuration
registers
0x0460_8100
0x0460_81FF
DSPSS to RADARSS
mailbox Configuration
registers
Safety Modules
ESM
0x020D_0000
0x2200_0000
92 B
ESM module
Configuration registers
CRC
0x2200_03FF
1 KiB
CRC module
Configuration registers
(1) 768 KB memory within 2 MB memory space
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Table 6-2. DSP C674x Memory Map (continued)
Name
Frame Address (Hex)
End
Size
Description
Start
STC
0x0204_0000
0x0204_01FF
284 B
STC module Configuration
registers
Nonsystem Peripherals
SCI
0x0203_0000
0x0203_00FF
148 B
SCI module Configuration
registers
6.4 Other Subsystems
6.4.1 ADC Channels (Service) for User Application
The IWR1642 device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1,
ADC2, ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.
•
ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for
customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST
subsystem. This API could be linked with the user application running on the Master R4.
•
BIST subsystem firmware will internally schedule these measurements along with other RF and Analog
monitoring operations. The API allows configuring the settling time (number of ADC samples to skip)
and number of consecutive samples to take. At the end of a frame, the minimum, maximum and
average of the readings will be reported for each of the monitored voltages.
GPADC Specifications:
•
•
•
•
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution
For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a
switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic
capacitance (GPADC channel 6, the internal buffer is not available).
5
ANALOG TEST 1-4,
GPADC
ANAMUX
5
VSENSE
Figure 6-5. ADC Path
Table 6-3. GP-ADC Parameter
over Tjunction temperature range (unless otherwise noted)
PARAMETER
TYP
1.8
UNIT
V
ADC supply
ADC unbuffered input voltage range
0 – 1.8
V
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Table 6-3. GP-ADC Parameter (continued)
over Tjunction temperature range (unless otherwise noted)
PARAMETER
ADC buffered input voltage range(1)
TYP
0.4 – 1.3
10
UNIT
V
ADC resolution
bits
LSB
LSB
LSB
LSB
Ksps
ns
ADC offset error
±5
ADC gain error
±5
ADC DNL
–1/+2.5
±2.5
625
400
10
ADC INL
ADC sample rate(2)
ADC sampling time(2)
ADC internal cap
pF
ADC buffer input capacitance
ADC input leakage current
2
pF
3
uA
(1) Outside of given range, the buffer output will become nonlinear.
(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
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7 Monitoring and Diagnostics
7.1 Monitoring and Diagnostic Mechanisms
Below is the list given for the main monitoring and diagnostic mechanisms available in the IWR1642.
Table 7-1. Monitoring and Diagnostic Mechanisms for IWR1642
S No
Feature
Description
IWR1642 architecture supports various temperature sensors all across the device (next to
power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame
period.(1)
1
Temperature Sensors
Provision to detect ADC saturation due to excessive incoming signal level and/or
interference.
2
RX saturation detect
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the temperature
sensed via API by customer application.
•
•
Report the temperature sensed after every N frames
Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
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7.1.1 Error Signaling Module
When a diagnostic detects a fault, the error must be indicated. IWR1642 architecture provides aggregation
of fault indication from internal diagnostic mechanisms using a peripheral logic known as the error
signaling module (ESM). The ESM provides mechanisms to classify faults by severity and allows
programmable error response. Below is the high level block diagram for ESM module.
Low Priority
Low Priority
Interrupt
Interrupy
Handing
Error Group 1
Interrupt Enable
High Priority
Interrupt
Handing
High Priority
Interrupy
Interrupt Priority
Error Group 2
Error Group 3
Nerror Enable
Error Signal
Handling
Device Output
Pin
Figure 7-1. ESM Module Diagram
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8 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
8.1 Application Information
Key device features driving the following applications are:
•
•
Integration of Radar Front End and Programmable MCU
Flexible boot modes: Autonomous Application boot using a serial flash or external boot over SPI.
The IWR1642 can be a radar sensor, or can be combined with an MSP432, or for LVDS processing with a
LVDS to DSP subsystem for more advanced applications. Some applications are:
•
•
Liquid and solid level sensing for process sensors or industrial automation
Industrial proximity sensing, non contact sensing for security, traffic monitoring, and industrial
transportation
•
•
Sensor fusion of camera and radar instruments for security, factory automation, robotics
Sensor fusion with multiple camera and radar instruments for object identification, manipulation, and
flight avoidance for security, robotics, material handling or drone devices
•
•
•
People counting
Gesturing
Motion detection
8.2 Reference Schematic
The reference schematic and power supply information can be found in the IWR1642 EVM
Documentation.
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8.3 Layout
8.3.1 Layout Guidelines
General layout guidelines can be found in the IWR1642 EVM Documentation and IWR1642 Checklist for
Schematic Review, Layout Review, Bringup/Wakeup.
8.3.2 Layout Example
The IWR1642 EVM, RF layout can be found in the IWR1642BOOST Layout and Design Files, and
IWR1642BOOST Schematics, Assembly Files, and BOM.
8.3.3 Stackup Details
Layout Stackup details can be found in the IWR1642BOOST Layout and Design Files.
There are specific RF guidelines for the RF Tx and Rx. There are additional layout guidelines for other
sections in the IWR1642 Checklist for Schematic Review, Layout Review, Bringup/Wakeup.
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions follow.
9.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, IWR1642). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ABL0161), the temperature range (for example, blank is the default
commercial temperature range). Figure 9-1 provides a legend for reading the complete device name for
any IWR1642 device.
For orderable part numbers of IWR1642 devices in the ABL0161 package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the IWR1642 Device
Errata.
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1
6
42
A
Q
A
IWR
G
ABL
Qualification
Blank= no special qual
Tray or Tape & Reel
Prefix
IWR = Industrial
Generation
1 = 76 GHz to 81 GHz
Variant
2 = FE
R = Tape & Reel
Blank = Tray
Package
ABL = BGA
Security
4 = FE + FFT + MCU
6 = FE + MCU + DSP
Num RX/TX Channels
G = General
S = Secure
RX = 1,2,3,4
TX = 1,2,3
Temperature (Tj)
Silicon PG Revision
blank = Rev1.0
A = œ40°C to 105°C
A = Rev2.0
Features
blank = baseline
Safety Level
Q = Quality Manage
Figure 9-1. Device Nomenclature
9.2 Tools and Software
Models
IWR1642 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
IWR1642 IBIS Model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
IWR1642 Checklist for Schematic Review, Layout Review, Bringup/Wakeup
A
set of steps in
spreadsheet form to select system functions and pinmux options. Specific EVM schematic
and layout notes to apply to customer engineering. A bringup checklist is suggested for
customers.
9.3 Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (IWR1642). In the upper right corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral
follows.
Errata
IWR1642 Device Errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
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9.4 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com
中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
9.5 商标
E2E is a trademark of Texas Instruments.
配备基于 ARM, Cortex are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
9.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
9.7 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
9.8 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
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10 Mechanical, Packaging, and Orderable Information
10.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CAUTION
The following package information is subject to change without notice.
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PACKAGE OUTLINE
ABL0161B
FCBGA - 1.17 mm max height
SCALE 1.400
PLASTIC BALL GRID ARRAY
10.5
10.3
B
A
BALL A1 CORNER
10.5
10.3
1.17 MAX
C
SEATING PLANE
0.1 C
BALL TYP
0.37
0.27
TYP
9.1 TYP
PKG
(0.65) TYP
(0.65) TYP
R
P
N
M
L
K
J
PKG
H
G
F
9.1
TYP
E
D
C
0.45
161X
0.35
0.15
0.08
C A B
C
B
A
0.65 TYP
BALL A1 CORNER
1
3
4
5
6
7
8
9 10 11
12 13 14 15
2
0.65 TYP
4223365/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15
A
B
(0.65) TYP
C
D
E
F
G
H
J
PKG
K
L
M
N
P
R
PKG
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.32)
METAL
(
0.32)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223365/A 10/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
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EXAMPLE STENCIL DESIGN
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
8
9
1
2
3
4
5
6
7
10 11
12 13 14 15
A
B
C
(0.65) TYP
D
E
F
G
H
J
PKG
K
L
M
N
P
R
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4223365/A 10/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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2-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
IWR1642AQAGABL
ACTIVE
FCCSP
FCCSP
FCCSP
ABL
161
161
161
176
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
IWR1642
QG
502AC
502A
C
502AC ABL
IWR1642AQAGABLR
IWR1642AQASABL
ACTIVE
ACTIVE
ABL
ABL
1000 RoHS & Green
SNAGCU
SNAGCU
-40 to 105
-40 to 105
IWR1642
QG
502AC
502A
C
502AC ABL
176
RoHS & Green
IWR1642
QS
502AC
502A
C
502AC ABL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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2-Feb-2022
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
ABL 161
10.4 x 10.4, 0.65 mm pitch
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225978/A
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