ISOW7742FQDFMRQ1 [TI]
具有集成电源的汽车类、低发射、四通道 2/2 增强型数字隔离器 | DFM | 20 | -40 to 125;
| 型号： | ISOW7742FQDFMRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电源的汽车类、低发射、四通道 2/2 增强型数字隔离器 | DFM | 20 | -40 to 125 |
| 文件： | 总61页 (文件大小：5016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOW7741-Q1, ISOW7742-Q1
ZHCSLW9 –NOVEMBER 2022
具有集成式低辐射低噪声直流/直流转换器的ISOW774x-Q1 四通道数字隔离器
1 特性
2 应用
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
• 混合动力、电动和动力总成系统(EV/HEV)
– 电池管理系统(BMS)
– 车载充电器(OBC)
– 牵引逆变器
– 器件温度等级1：–40°C 至+125°C 的环境温
度范围
• 100 Mbps 数据速率
– 直流/直流转换器
• 低辐射、低噪声的集成式直流/直流转换器
3 说明
– 辐射经过优化，符合CISPR25
– 25 MHz 的低频电源转换器可实现低噪声性能
– 低输出波纹：24 mV
ISOW7741-Q1 和ISOW7742-Q1 器件是具有低辐射集
成式高效电源转换器的电隔离四通道数字隔离器。集成
式直流/直流转换器提供高达 550mW 的隔离式电源，
无需在空间受限的隔离设计中使用单独的隔离式电源。
• 高效率输出功率
– 最大负载时的效率：46%
– 高达0.55W 的输出功率
器件信息
– VISOOUT 精度为5%
ISOW774x-Q1
特性
– 5V 至5V：最大可用负载电流= 110mA
– 5V 至3.3V：最大可用负载电流= 140mA
– 3.3V 至3.3V：最大可用负载电流= 60mA
• 用于通道隔离器和电源转换器的独立电源
– 逻辑电源(VIO)：1.71V 至5.5V
– 电源转换器电源(VDD)：3V 至5.5V
• 优异的电磁兼容性(EMC)
ISOW774xF-Q1
10kVPK
5000VRMS
浪涌测试电压
隔离额定值
1000 VRMS/1500VPK
DFM (20)
工作电压
封装
12.83 mm x 7.5 mm
封装尺寸（标称值）
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
VISOIN
VIO
EN_IO2
Tx
Tx
INA
INB
• 增强型和基础型隔离选项
• 高CMTI：100 kV/µs（典型值）
• 安全相关认证：
OUTA
Rx
Rx
Rx
Tx
OUTB
OUTC
IND
INC
Tx
Rx
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标
准的VDE 增强型和基础型绝缘
OUTD
EN_IO1
– UL 1577 组件认证计划
– IEC 62368-1、IEC 61010-1、IEC 60601-1 和
GB 4943.1-2011 认证
GISOIN
GNDIO
GND1
GN
D2
VSEL
VDD
– ISOW774xB 器件已列入计划
• 扩展温度范围：–40°C 至+125°C
• 20 引脚宽体SOIC 封装
DC-DC
Primary
DC-DC
Secondary
EN/FLT
GND1
VISOOUT
GND2
ISOW7741-Q1 简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFK3
ISOW7741-Q1, ISOW7742-Q1
ZHCSLW9 –NOVEMBER 2022
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Table of Contents
7.18 Supply Current Characteristics Channel
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（接续）.....................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Power Ratings.............................................................8
7.6 Insulation Specifications............................................. 9
7.7 Safety-Related Certifications.................................... 10
7.8 Safety Limiting Values...............................................10
7.9 Electrical Characteristics - Power Converter.............11
7.10 Supply Current Characteristics - Power
Converter.....................................................................12
7.11 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 5-V..........................................................13
7.12 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 5-V...........................................13
7.13 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 3.3-V.......................................................15
7.14 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 1.8-V........................................19
7.19 Switching Characteristics - 5-V Supply...................21
7.20 Switching Characteristics - 3.3-V Supply................22
7.21 Switching Characteristics - 2.5-V Supply................23
7.22 Switching Characteristics - 1.8-V Supply................24
7.23 Insulation Characteristics Curves........................... 25
7.24 Typical Characteristics............................................26
8 Parameter Measurement Information..........................31
9 Detailed Description......................................................33
9.1 Overview...................................................................33
9.2 Functional Block Diagram.........................................34
9.3 Feature Description...................................................35
9.4 Device Functional Modes..........................................38
10 Application and Implementation................................40
10.1 Application Information........................................... 40
10.2 Typical Application.................................................. 40
11 Power Supply Recommendations..............................44
12 Layout...........................................................................45
12.1 Layout Guidelines................................................... 45
12.2 Layout Example...................................................... 46
13 Device and Documentation Support..........................47
13.1 Device Support....................................................... 47
13.2 Documentation Support.......................................... 47
13.3 Receiving Notification of Documentation Updates..47
13.4 支持资源..................................................................47
13.5 Trademarks.............................................................47
13.6 Electrostatic Discharge Caution..............................47
13.7 术语表..................................................................... 47
14 Mechanical, Packaging, and Orderable
Isolator - VIO, VISOIN = 3.3-V........................................15
7.15 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 2.5-V.......................................................17
7.16 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 2.5-V........................................17
7.17 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 1.8-V.......................................................19
Information.................................................................... 48
14.1 Package Option Addendum....................................52
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2022
*
Initial release.
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5 说明（接续）
电源转换器可在 –40°C 至+125°C 的宽工作环境温度范围内高效运行。该器件提供改进的发射性能，简化了电路
板设计，并提供了铁氧体磁珠以进一步衰减发射。ISOW7741-Q1 和 ISOW7742-Q1 设计时考虑了增强的保护功
能，包括软启动来限制浪涌电流、过压和欠压锁定、EN/FLT 引脚上的故障检测、过载和短路保护以及热关机。
ISOW7741-Q1 和 ISOW7742-Q1 器件提供高电磁抗扰度，同时隔离 CMOS 或低电压互补金属氧化物半导体
(LVCMOS) 数字 I/O 。该信号隔离通道具有逻辑输入和输出缓冲器，由双电容二氧化硅 (SiO2) 绝缘栅隔开，而电
源隔离则采用由薄膜聚合物隔开的片上变压器作为绝缘材料。如果输入信号丢失，则不具有 F 后缀的ISOW7741-
Q1 和ISOW7742-Q1 器件默认输出高电平，具有F 后缀的ISOW7741F-Q1 和ISOW7742-Q1 器件默认输出低电
平。通过在PCB 上将VIO 和 VDD 连接在一起，ISOW774x-Q1 可在 3V 至 5.5V 的单一电源下运行。如果需要较
低的逻辑电平，这些器件支持 1.71V 至 5.5V 逻辑电源 (VIO)，该电源独立于 3V 至 5.5V 的电源转换器电源
(VDD) 。VISOIN 和VISOOUT 需要通过铁氧体磁珠或通过LDO 馈电连接到电路板。
这些器件有助于防止数据总线（例如，CAN 和 LIN）或者其他电路上的噪声电流进入本地接地以及干扰或损坏敏
感电路。通过创新的芯片设计和布线技术，该器件的电磁兼容性得到了显著增强，可缓解系统级 ESD、EFT 、浪
涌和辐射合规性。器件采用20 引脚SOIC 宽体(SOIC-WB) DFM 封装。
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6 Pin Configuration and Functions
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
INC
4
5
6
17
16
15
OUTC
IND
OUTD
GNDIO
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
图6-1. ISOW7741-Q1 DFM Package 20-Pin SOIC-WB Top View
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
OUTC
OUTD
GNDIO
4
5
6
17
16
15
INC
IND
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
图6-2. ISOW7742-Q1 DFM Package 20-Pin SOIC-WB Top View
PIN
NO.
I/O
DESCRIPTION
NAME
GNDIO
ISOW7741-Q1
ISOW7742-Q1
6
6
Ground connection for VIO. GND1 and GNDIO needs to be shorted on board.
Ground connection for VDD. GND1 and GNDIO needs to be shorted on board.
—
—
GND1
GND2
10
10
Ground connection for VISOOUT. GND2 and GISOIN pins can be shorted on board or
connected through a ferrite bead. See the Layout Section for more information.
11
11
—
Ground connection for VISOIN. GND2 and GISOIN pins can be shorted on board or
connected through a ferrite bead. See the Layout Section for more information.
GISOIN
INA
15
2
15
2
—
I
Input channel A
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NAME
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PIN
NO.
I/O
DESCRIPTION
ISOW7741-Q1
ISOW7742-Q1
INB
INC
3
3
I
I
Input channel B
Input channel C
4
17
IND
16
19
18
16
19
18
I
Input channel D
Output channel A
Output channel B
OUTA
OUTB
O
O
OUTC
OUTD
17
5
4
5
O
O
Output channel C
Output channel D
Output Enable 1: When EN_IO1 is high or open then the channel output pins on side
1 are enabled. When EN_IO1 is low then the channel output pins on side 1 are in a
high impedance state and the transmitter of the channel input pins on side 1 are
disabled.
EN_IO1
EN_IO2
7
7
I
I
Output Enable 2: When EN_IO2 is high or open then the channel output pins on side
2 are enabled. When EN_IO2 is low then the channel output pins on side 2 are in a
high impedance state and the transmitter of the channel input pins on side 2 are
disabled.
14
14
Multi-function power converter enable input pin or fault output pin. Can only be used
as either an input pin or an output pin.
Power converter enable input pin: enables and disables the integrated DC-DC power
converter. Connect directly to microcontroller or through a series current limiting
resistor to use as an enable input pin. DC-DC power converted is enabled when
EN/FLT is high to the VIO voltage level and disabled when low at GND1 voltage level.
Fault output pin: Alert signal if power converter is not operating properly. This pin is
active low. Connect to microcontroller through a 5 kΩor greater pull-up resistor in
order to use as a fault outpin pin.
EN/FLT
8
8
I/O
See 节9.3.3 for more information
VISOOUT selection pin. VISOOUT = 5 V when VSEL shorted to VISOOUT. VISOOUT = 3.3
V, when VSEL shorted to GND2. For more information see the Device Functional
Modes.
VSEL
13
13
I
VIO
1
9
1
9
Side 1 logic supply.
—
—
VDD
Side 1 DC-DC converter power supply.
Side 2 supply voltage for isolation channels. VISOIN and VISOOUT pins can be shorted
on board or connected through a ferrite bead. See Application and Implementation
for more information.
VISOIN
20
12
20
12
—
—
Isolated power converter output voltage. VISOIN and VISOOUT pins can be shorted on
board or connected through a ferrite bead. See Application and Implementation for
more information.
VISOOUT
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
MAX
UNIT
V
VDD
Power converter supply voltage
6
6
VISOIN
Isolated supply voltage, input supply for secondary side isolation channels
V
Isolated supply voltage, Power converter output
VSEL shorted to GND2
VISOOUT
4
6
V
V
–0.5
–0.5
Isolated supply voltage, Power converter output
VSEL shorted to VISOOUT
VISOOUT
VIO
Primary side logic supply voltage
Voltage at INx, OUTx, EN_IOx(3)
Voltage at EN/FLT
6
VSI + 0.5
VSI + 0.5
VISOOUT + 0.5
15
V
V
–0.5
–0.5
–0.5
–0.5
–15
–40
–65
V
V
Voltage at VSEL
V
IO
Maximum output current through data channels
Junction temperature
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD, VISOIN VISOOUT, and VIO are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus
voltages are peak voltage values.
(3) VSI = input side supply; Cannot exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±3000
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
V(ESD)
±1500
±8000
V
Contact discharge per IEC 61000-4-2(2)
Isolation barrier withstand test
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
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7.3 Recommended Operating Conditions
Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
MIN
NOM
MAX
UNIT
Power Converter
3.3 V operation
5 V operation
2.97
4.5
3.3
5
3.63
5.5
V
V
Power converter supply
voltage
VDD
Positive threshold when
power converter supply is
rising
Positive threshold when power
converter supply is rising
VDD(UVLO+)
2.7
2.95
V
Positive threshold when
power converter supply is
falling
Positive threshold when power
converter supply is falling
VDD(UVLO-)
2.40
0.15
2.55
V
V
Power converter supply
voltage hysteresis
Power converter supply voltage
hysteresis
VDD(HYS)
Channel Isolation
1.8 V operation
1.71
2.25
1.89
5.5
V
V
(3)
VIO, VISOIN
Channel logic supply voltage
2.5 V, 3.3 V, and 5 V operation
VIO(UVLO+)
VIO(UVLO-)
VIO(HYS)
Rising threshold of logic supply voltage
1.55
1.41
1.7
V
Falling threshold of logic supply voltage
Logic supply voltage hysteresis
1.0
75
V
mV
mA
mA
mA
mA
mA
mA
mA
mA
V
VISOIN = 5 V
–4
–2
–1
–1
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
VISOIN = 5 V
IOH
High level output current(1)
Low level output current(1)
4
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
2
IOL
1
1
VIH
VIL
DR
High-level input voltage(2)
Low-level input voltage
Data rate
0.7 × VSI
0
VSI
0.3 × VSI
100
V
Mbps
Channel isolator ready after
power up or EN/FLT high
tPWRUP
TA
VISOIN > VIO(UVLO+)
5
ms
°C
Ambient temperature
125
–40
(1) This current is for data output channel.
(2) VSI = input side supply; VSO = output side supply
(3) The channel outputs are in undetermined state when 1.89 V < VSI < 2.25 V and 1.05 V < VSI < 1.71 V
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UNIT
7.4 Thermal Information
ISOW774x-Q1
DFM (SOIC)
20 PINS
68.5
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
24.6
53.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.1
ΨJT
50.9
ΨJB
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VDD = VIO = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.48
0.74
0.74
UNIT
W
PD
Maximum power dissipation (both sides) VDD = 5.5 V, VIO = 5.5 V, VISOOUT
=
VISOIN, IISOOUT = 100 mA, TJ = 150°C,
TA ≤80°C, CL = 15 pF, input a 50-MHz
50% duty-cycle square wave
PD1
PD2
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
W
W
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7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
Minimum internal gap (internal clearance –capacitive
signal isolation)
> 17
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
I-IV
I-IV
I-III
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1500
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
1000
1500
7071
VRMS
VDC
VPK
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
6250
≤5
≤5
VPK
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and
preconditioning (type test),
Vini = 1.2 × VIOTM, tini = 1 s;
≤5
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance(5)
~3.5
> 1012
> 1011
> 109
pF
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V, TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
VISO(UL) Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISOW77xx is suitable for safe electrical insulation and ISOW77xxB is suitable for basic electrical insulation only within the safety
ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
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(5) All pins on each side of the barrier tied together creating a two-terminal device.
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to DIN
EN IEC 60747-17 (VDE
0884-17)
Recognized under UL
1577 Component
Recognition Program
Certified according to EN
61010-1:2010/A1:2019
and EN 62368-1:2014
Certified according to IEC
62368-1, and IEC 60601-1
Certified according to
GB 4943.1-2011
CSA 62368-1-19 and IEC
62368-1:2018 Ed. 3 and EN
62368-1:2020. (pollution degree
2, material group I) 600
VRMS (Reinforced) maximum
working voltage;
Reinforced insulation;
Maximum transient
isolation voltage, 7071
5000 VRMS Reinforced
insulation per EN 61010-
1:2010 up to working
voltage of 600 VRMS;
5000 VRMS Reinforced
insulation per EN
62368-1:2014 up to
working voltage of 600
VRMS (Reinforced)
Reinforced Insulation,
Altitude ≤5000 m,
Tropical Climate, 700
VRMS maximum working
voltage;
VPK
;
2 MOPP (Means of Patient
Single protection, 5000
Maximum repetitive peak
isolation voltage, 1500
Protection) per CSA 60601-1:14 VRMS
and IEC 60601-1 Ed. 3+A1, 250
VRMS maximum working
voltage. Temperature rating is
90°C for reinforced insulation
and 125°C for basic insulation;
see certificate for details.
VPK
;
Maximum surge isolation
voltage, 6250 VPK
Certificate #: Pending
Master Contract#: Pending
File #: Pending
Certificate #: Pending
Client ID: Pending
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C,
332
TA = 25°C
θJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
θJA = 68.5°C/W, TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current(1)
mA
R
507
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
R
1825
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% and VISOIN power externally, GND1 = GNDIO, GND2 = GISOIN (over recommended
operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, VISOOUT = 5 V, VSEL = VISOOUT
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 55 mA
External IISOOUT = 0 to 110 mA
4.75
4.5
5
5
5.25
5.25
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 110 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x-Q1); VI =0 V
(ISOW774x-Q1 with F suffix).
Efficiency at maximum load
current (1)
EFF
46%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
24
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 5 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 70 mA
External IISOOUT = 0 to 140 mA
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 70 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 140 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 140 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x-Q1); VI =0 V
(ISOW774x-Q1 with F suffix).
Efficiency at maximum load
current (1)
EFF
36%
Output ripple on isolated supply 20-MHz bandwidth , CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
30
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 3.3 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 30 mA
External IISOOUT = 0 to 60 mA
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 30 mA, VDD = 3.0 V to 3.6 V
IISOOUT = 0 to 60 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 60 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x-Q1); VI =0 V
(ISOW774x-Q1 with F suffix).
Efficiency at maximum load
current (1)
EFF
43%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
14
mV
mA
(pk-pk)
IISOOUT = 60 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
185
(1) Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.
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7.10 Supply Current Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless otherwise
noted).
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Converter Disabled
Power converter supply
current
EN/FLT = GND1, VISOOUT = No ILOAD
EN/FLT = GND1
IDD
0.28
0.27
0.45
0.57
mA
mA
Logic supply current
IIO
Power Converter Enabled
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = GND2
VDD = 5 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 5 V
ILOAD = 55 mA
ILOAD = 110 mA
ILOAD = 70 mA
ILOAD = 140 mA
ILOAD = 30 mA
ILOAD = 60 mA
VSEL = VISOOUT
VSEL = GND2
VSEL = GND2
115
225
127
250
74
171
316
169
310
112
216
mA
mA
mA
mA
mA
mA
mA
mA
mA
Power converter supply
current input
IDD
143
110
140
60
Power converter output
current (1)
VDD = 5 V
IISOOUT
VDD = 3.3 V
(1) ILOAD does not take into account the channel isolator current. See Supply Current Characteristics Channel Isolator section for details.
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7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
–25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –4 mA, see Switching Characteristics
VSO
–
0.4
VOH
VOL
High level output voltage
Low level output voltage
V
V
Test Circuit and Voltage Waveforms
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.4
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7741-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741-
Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
IDD_IO
2.8
4.3
4.1
6.3
mA
mA
IISOIN
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
4.3
2.8
4.3
6.1
5.5
4.4
4.9
5
4.1
6.3
4.1
6.3
8.4
7.9
6.3
7.1
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
6.3
12.2
25
8.9
14.2
32
100 Mbps
ISOW7742-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742-
IDD_IO
IISOIN
3.1
3.9
4.7
5.6
mA
mA
Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.9
3.1
3.9
5.4
6.2
4.7
5.6
4.7
5.6
7.7
8.5
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742-Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
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VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.2
5.1
6.3
7.2
7.6
8.3
20
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
5.5
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
6.3
16.7
17.33
22
(1) VCCI = VIO or VISOIN
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7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –2 mA, see Switching Characteristics
VSO
–
0.3
VOH
VOL
High level output voltage
Low level output voltage
V
V
Test Circuit and Voltage Waveforms
IO = 2 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.3
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7741-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741-
Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
IDD_IO
2.8
4.2
4
mA
mA
IISOIN
6.3
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
4.2
2.8
4.2
6.1
5.5
4.4
4.9
4.8
5.9
9.4
17.5
4
6.3
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
6.3
8.3
7.9
6.3
7.1
6.7
8.3
12
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
25
ISOW7742-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742-
IDD_IO
IISOIN
3.1
3.9
4.6
5.5
mA
mA
Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.9
3.1
3.9
5.4
6.2
4.6
5.5
4.6
5.5
7.6
8.5
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742-Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
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VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.2
5.1
4.9
5.7
13
6.3
7.2
7
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
7.9
16.6
17.5
13.7
(1) VCCI = VIO or VISOIN
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7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –1 mA, see Switching Characteristics
VSO
–
0.1
VOH
VOL
High level output voltage
Low level output voltage
V
V
Test Circuit and Voltage Waveforms
IO = 1 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.1
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7741-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741-
Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
IDD_IO
2.7
4.2
4.3
6.3
mA
mA
IISOIN
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.7
4.2
2.7
4.2
6.1
5.4
4.4
4.9
4.7
5.6
8.2
14.6
4.3
6.3
4.3
6.3
8.3
7.9
6.3
7.1
8.3
7.9
11.2
18.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7742-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742-
IDD_IO
IISOIN
3.1
3.8
4.6
5.5
mA
mA
Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.8
3.1
3.8
5.3
6.1
4.6
5.5
4.6
5.4
7.5
8.4
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742-Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
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VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.2
5.1
6.3
7.2
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
4.7
6.8
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
5.6
7.7
10.9
11.7
14.5
15.5
(1) VCCI = VIO or VISOIN
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7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –1 mA, see Switching Characteristics
VSO
–
0.1
VOH
VOL
High level output voltage
Low level output voltage
V
V
Test Circuit and Voltage Waveforms
IO = 1 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.1
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7741-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741-
Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
IDD_IO
2.4
3.8
3.6
5.6
mA
mA
IISOIN
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.4
3.8
2.4
3.8
5.5
4.9
4
3.6
5.6
3.6
5.6
7.8
7.3
5.7
6.5
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1);
VI = 0 V (ISOW7741-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741-Q1);
VI = VCCI (ISOW7741-Q1 with F suffix)
1 Mbps
4.4
4.2
5.2
6.9
12
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
7.3
9.6
15.8
100 Mbps
ISOW7742-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742-
IDD_IO
IISOIN
2.8
3.4
4.3
5.1
mA
mA
Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Supply current - Disable
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
3.4
2.8
3.4
5
4.3
5.1
4.3
5.1
7.4
8.1
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742-Q1);
VI = 0 V (ISOW7742-Q1 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742-Q1);
VI = VCCI (ISOW7742-Q1 with F suffix)
5.6
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VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.2
4.5
4.3
5.0
9.1
9.7
6.3
7.2
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
6.6
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
7.5
12.5
13.3
(1) VCCI = VIO or VISOIN
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7.19 Switching Characteristics - 5-V Supply
VISOIN = 5 V ±10%, VIO = 5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
10.7
0.9
MAX UNIT
tPLH, tPHL
PWD
7.6
15.7
5
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
210
473.8
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4
5.5
3.6
3.5
ns
ns
ns
ns
Output signal rise time
2.5
2.4
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
217
217
237
237
237
237
286
286
333
333
333
333
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1 with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1 with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
216 –1 PRBS data at 100 Mbps
tie
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.20 Switching Characteristics - 3.3-V Supply
VISOIN = 3.3 V ±10%, VIO = 3.3 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
PWD
6
16.2
4.7
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
0.6
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
220
474
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
4.5
2.7
2.4
ns
ns
ns
ns
Output signal rise time
1.8
1.6
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
230
230
226
226
225
225
300.4
299.6
318.9
319.1
317.9
317.6
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1 with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1 with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.3
μs
216 –1 PRBS data at 100 Mbps
tie
0.65
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.21 Switching Characteristics - 2.5-V Supply
VISOIN = 2.5 V ±10%, VIO = 2.5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
tPLH, tPHL
PWD
7.5
18
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
0.36
5.1
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
225
478
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
6
ns
ns
ns
ns
Output signal rise time
2
3.26
3.2
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
1.8
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
237
236
228
228
227
227
326
325
360
360
350
350
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1 with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1 with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
216 –1 PRBS data at 100 Mbps
tie
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.22 Switching Characteristics - 1.8-V Supply
VISOIN = 1.8 V ±5%, VIO = 1.8 V ±5%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
15
0
MAX UNIT
tPLH, tPHL
PWD
7.5
21.5
5.8
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
243
475
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
8.6
3
ns
ns
ns
ns
Output signal rise time
1.9
1.8
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
3
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
260
260
240
240
237
237
410
406
444
444
439
439
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x-Q1 with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x-Q1 with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
216 –1 PRBS data at 100 Mbps
tie
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.23 Insulation Characteristics Curves
550
VDD = VIO = VISOIN = 3.6 V
VDD = VIO = VISOIN = 5.5 V
500
450
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (C)
图7-2. Thermal Derating Curve for Safety Limiting
图7-1. Thermal Derating Curve for Safety Limiting
Power for DFM-20 Package
Current for DFM-20 Package
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7.24 Typical Characteristics
3.4
3.38
3.36
3.34
3.32
3.3
5.1
5.08
5.06
5.04
5.02
5
VDD = 5 V
VDD = 3.3 V
3.28
3.26
3.24
3.22
3.2
4.98
4.96
4.94
4.92
4.9
0
20
40
60
80
100
120
140
0
10 20 30 40 50 60 70 80 90 100 110 120
Load Current (mA)
Load Current (mA)
VSEL = GND2
TA = 25°C
VISOOUT = 3.3 V
VSEL = VISOOUT
TA = 25°C
VISOOUT = 5 V
图7-3. Isolated Supply Voltage (VISOOUT) vs Load
Current (IISOOUT
图7-4. Isolated Supply Voltage (VISOOUT) vs Load
Current (IISOOUT
)
)
270
240
210
180
150
120
90
48
45
42
39
36
33
30
27
24
21
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
60
30
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Load Current (mA)
Load Current (mA)
TA = 25°C
TA = 25°C
图7-5. Supply Current (IDD) vs Load Current
(IISOOUT
图7-6. Efficiency vs Load Current (IVISOOUT
)
)
800
700
600
500
400
300
200
100
0
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.26
3.25
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
0
20
40
60
80
100
120
140
Output Load Current (mA)
VSEL = GND2
VDD = 5 V
No VISOOUT Load
TA = 25°C
图7-8. 3.3-V Isolated Supply Voltage (VISOOUT) vs
图7-7. Power Dissipation vs Load Current (IISOOUT
)
Free-Air Temperature
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5.05
5.04
5.03
5.02
5.01
5
340
320
300
280
260
240
220
200
180
160
4.99
4.98
4.97
4.96
4.95
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
Temperature (C)
Input Supply Voltage, VDD (mA)
VSEL = VISOOUT
VDD = 5 V
No VISOOUT Load
VSEL = VISOOUT VISOOUT = GND2 TA = 25°C = GND1
图7-9. 5-V Isolated Supply Voltage (VISOOUT) vs
图7-10. Short-Circuit Supply Current (ICC) vs
Free-Air Temperature
Supply Voltage (VCC)
24
20
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
22
18
16
14
12
10
8
20
18
16
14
12
10
8
IISOIN, VISOIN = 3.3 V
6
6
4
4
2
2
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Data Rate (Mbps)
Data Rate (Mbps)
CL = 15 pF
TA = 25°C
CL = 0 pF
TA = 25°C
图7-11. ISOW7741-Q1 Channel Supply Currents vs 图7-12. ISOW7741-Q1 Channel Supply Currents vs
Data Rate For CL = 15 pF
Data Rate For CL = 0 pF
18
16
14
12
10
8
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V
6
4
2
0
10
20
30
40
50
60
70
80
90 100
Data Rate (Mbps)
CL = 0 pF
TA = 25°C
CL = 15 pF
TA = 25°C
图7-14. ISOW7742-Q1 Channel Supply Currents vs
图7-13. ISOW7742-Q1 Channel Supply Currents vs
Data Rate For CL = 0 pF
Data Rate For CL = 15 pF
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3
2.75
2.5
17
16
15
14
13
12
11
10
9
tPHL, VIO = 5 V, VISOIN = 5 V
tPLH, VIO = 5 V, VISOIN = 5 V
tPHL, VIO = 5 V, VISOIN = 3.3 V
tPLH, VIO = 5 V, VISOIN = 3.3 V
tPHL, VIO = 3.3 V, VISOIN = 3.3 V
tPLH, VIO = 3.3 V, VISOIN = 3.3 V
VIO UVLO+
VIO UVLO-
VISOIN UVLO+
VISOIN UVLO-
VDD UVLO+
VDD UVLO-
2.25
2
1.75
1.5
1.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
图7-16. Propagation Delay Time vs Free-Air
图7-15. Power-Supply Undervoltage Threshold vs
Temperature
Free Air Temperature
5
0.8
0.6
0.4
0.2
4.5
VSO = 3.3 V
VSO = 5 V
4
3.5
3
VSO = 3.3 V
VSO = 5 V
0
2.5
0
3
6
9
12
15
-15
-12
-9
-6
-3
0
Low-Level Output Current (mA)
High-Level Output Current (mA)
TA = 25°C
TA = 25°C
图7-18. Low-Level Output Voltage vs Low-Level
图7-17. High-Level Output Voltage vs High-Level
Output Current
Output Current
VDD = 5 V VISOOUT = 3.3
V
TA = 25°C
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
图7-19. 10-mA to 110-mA Load Transient
Response
图7-20. Soft Start at 10-mA Load For VISOOUT = 3.3
V
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VDD = 5 V VISOOUT = 3.3
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
V
图7-21. Soft Start at 50-mA Load For VISOOUT = 3.3 图7-22. Soft Start at 110-mA Load For VISOOUT = 3.3
V
V
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
图7-24. Soft Start at 50-mA Load For VISOOUT = 5 V
图7-23. Soft Start at 10-mA Load For VISOOUT = 5 V
VDD = 3.3 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
图7-26. VISOOUT Ripple Voltage at 3.3 V with 10 uF
Capacitor and 60 mA load
图7-25. Soft Start at 110-mA Load For VISOOUT = 5
V
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VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
VDD = 3.3 V VISOOUT = 3.3
V
100 uF
Capacitor on
VISOOUT
图7-27. VISOOUT Ripple Voltage at 5 V with 10 uF
图7-28. VISOOUT Ripple Voltage at 3.3 V with 100 uF
Capacitor and 110 mA load
Capacitor and 60 mA load
VDD = 5 V VISOOUT = 5 V
100 uF
Capacitor on
VISOOUT
TA = 25°C
图7-30. VISOOUT Ripple Voltage vs Load Capacitor
图7-29. VISOOUT Ripple Voltage at 5 V with 100 uF
Capacitor and 110 mA load
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8 Parameter Measurement Information
In the below images, VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively.
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. CL = 15 pF and The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3
ns, tf ≤3ns, ZO = 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-1. Switching Characteristics Test Circuit and Voltage Waveforms
VCC1
VCC / 2
VCC / 2
VI
0 V
VOH
tPZH
VO
IN
OUT
0 V or 3 V
50%
0.5 V
VO
EN
0 V
RL = 1 kꢀ 1%
tPHZ
CL
See Note B
tPZL
tPLZ
Input
Generator
(See Note A)
VOH
0.5 V
VOL
VI
50 ꢀ
VO
50%
A. A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3ns,
ZO = 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
VCCI
See Note B
V
CCI
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
备注
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
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备注
B. Power Supply Ramp Rate = 10 mV/ns.
图8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
5V
Connected to Visoout on PCB
VISOIN
VIO
0.01uF
1uF
10uF
10uF
1uF
0.01uF
VIO
GND1
OUT
IN
5V
GND1
VDD
C
L
10uF
1uF
0.01uF
GND1
GND2
+
–
V
CM
备注
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
备注
Pass-fail criteria: Outputs must remain stable.
图8-4. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISOW774x-Q1 family of devices have low-noise, low-emissions isolated DC-DC converter, and four high-
speed isolated data channels. 节9.2 shows the functional block diagram of the ISOW774x device.
9.1.1 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve upto 46% typical efficiency. The integrated transformer uses thin film polymer as
the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using VSEL pin. The
DC-DC converter can be switched off using the EN/FLT pin to save power. The output voltage, VISOOUT , is
monitored and feedback information is conveyed to the primary side through a dedicated isolation channel.
VISOOUT needs to be connected to VISOIN to ensure the feedback channel is properly powered to regulate the
DC-DC converter. This can be achieved by connecting the pins directly or through an LDO that remains powered
up at all times. A ferrite bead is recommended between Visoout and Visoin to further reduce emissions. See the
节 10.2 section. The duty cycle of the primary switching stage is adjusted accordingly. The fast feedback control
loop of the power converter ensures low overshoots and undershoots during load transients. Undervoltage
lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOIN supplies which ensures robust fails-safe
system performance under noisy conditions. An integrated soft-start mechanism ensures controlled inrush
current and avoids any overshoot on the output during power up.
9.1.2 Signal Isolation
The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across
the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the
signal after signal conditioning and produces the output through a buffer stage. The signal-isolation channels
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions from the high frequency carrier and IO buffer switching. 图 9-1 shows a functional block diagram of a
typical signal isolation channel. In order to keep any noise coupling from power converter away from signal path,
power supplies on side 1 for power converter (VDD) and signal path(VIO) are kept separate. Similarly on side 2,
power converter output (VISOOUT) needs to be connected to VISOIN externally on PCB. Emissions can be further
improved by placing a ferrite bead between VISOOUT and VISOIN as well as between the GND2 pins. For more
details, refer to the Layout Guidelines section.
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9.2 Functional Block Diagram
V
V
ISOIN
IO
Isolation Barrier
VISOOUT and
VISOIN needs to
be directly
connected or
through an
LDO on board
that is always
powered.
Data Channels
(4)
Data Channels
(4)
I/O Channels
I/O Channels
FB Controller
V
ref
FB Channel (Rx)
FB Channel (Tx)
Thermal
Shutdown,
UVLO, Soft-start
UVLO, Soft-start
Transformer
Driver
Power
Controller
Rectifier
V
ISOOUT
V
DD
Transformer
图9-1. Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图9-2. Conceptual Block Diagram of a Capacitive Data Channel
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图9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description
表9-1 shows an overview of the device features.
表9-1. Device Features
DEFAULT OUTPUT
PART NUMBER(1)
CHANNEL DIRECTION
MAXIMUM DATA RATE
RATED ISOLATION(2)
STATE
ISOW7741-Q1
High
3 forward, 1 reverse
ISOW7741-Q1 with F
suffix
Low
High
Low
100 Mbps
5 kVRMS / 7071 VPK
ISOW7742-Q1
2 forward, 2 reverse
ISOW7742-Q1 with F
suffix
(1) The F suffix is part of the orderable part number. See the 节14 section for the full orderable part number.
(2) For detailed isolation ratings, see the 节7.7 table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW7741-Q1 and ISOW7742-Q1 devices use emissions reduction schemes for the internal oscillator and
advanced internal layout scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW7741-Q1 and ISOW7742-Q1 devices incorporate many chip-level design improvements for overall system
robustness. Some of these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
• Power path and signal path separated to minimize internal high frequency coupling and allowing for an
external filtering knob using ferrite beads available to further reduce emissions
• Reduced power converter switching frequency to 25 Mhz to reduce strength of high frequency components in
emissions spectrum
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9.3.2 Power-Up and Power-Down Behavior
The ISOW774x-Q1 device has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and
negative-going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to
be present for the device to work. If either of them is below its UVLO, both the signal path and the power
converter are disabled.
When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter
initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits
primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner,
avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO or VDD
voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the
secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower
threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data
outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to
discharge to zero.
9.3.3 Protection Features
The ISOW7741-Q1 and ISOW7742-Q1 devices have multiple protection features to create a robust system level
solution.
• The Enable DC-DC / FAULT protection feature (EN/FLT) can be used as either an input pin, to enable or
disable the integrated DC-DC power converter, or as an output pin, which works as an alert signal if the
power converter is not operating properly. In the /FAULT use case, an alert is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
5 kΩ
Powers Down Isolator Channels
and DC-DC Converter.
EN/FLT
MCU OUTPUT
IQ < 1 mA Typical
MCU INPUT
Fault Reported If
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
图9-4. EN/FLT Fault Pin Diagram
• An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V, when VSEL =
VISOOUT, or 4 V, when VSEL = GND2, if there is an increase in voltage seen on VISOOUT. It is recommended
that the VISOOUT stays lower than the over-clamp voltage for device reliability.
• Over-voltage lock out on VDD will occur when a voltage higher than 7 V is seen. The device will go into a low
power state and the EN/FLT pin will go low.
• The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
• The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
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• The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
• Thermal protection is also integrated to help prevent the device from getting damaged during overload and
short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to
increase. When the temperature goes above 165°C, thermal shutdown activates and the primary controller
turns off which removes the energy supplied to the VISOOUT load, which causes the device to cool off. When
the junction temperature goes below 150°C, the device starts to function normally. If an overload or output
short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to
prevent the device junction temperatures from reaching such high values.
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9.4 Device Functional Modes
表9-2 lists the supply configurations for these devices.
表9-2. Supply Configuration Function Table
(1)
(3)
VDD
VIO
VSEL
VISOOUT
OFF
< VDD(UVLO+)
>VDD(UVLO+)
5 V
>VIO(UVLO+)
<VIO(UVLO+)
1.71 V to 5.5 V
1.71 V to 5.5 V
X
X
OFF
High (shorted to VISOOUT
)
5 V
5 V or 3.3 V
Low (shorted to GND2)(2)
3.3 V
(1) VDD= 3.3 V, VSEL shorted to VISOOUT(essentially VISOOUT = 5 V) is not the recommended mode of operation
(2) The VSEL pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the VSEL pin should be strongly connected to the GND2
pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High
表9-3 lists the channel isolators functional modes for these devices.
表9-3. Channel Isolator Function Table
CHANNEL
OUTPUT
SUPPLY (VCCO
IO ENABLE
(EN_IOx)
CHANNEL INPUT
OUTPUT
(OUTx)
(1)
INPUT (INx)
COMMENTS
SUPPLY (VCCI
)
(1)
)
H or
Open
H
L
H
L
Normal Operation: A channel output
assumes the logic state of its input.
H or Open
Default mode(2): When INx is open, the
corresponding channel output goes to its
default logic state.
Open
X
H or Open
Default
PU
PU
A low value of output enable causes the
outputs of the same side to be high
impedance and the output of opposite
side to be fail-safe default state.
L
Z and Default
Default mode(2): When VCCI is
unpowered, a channel output assumes
the logic state based on the selected
default option. When VCCI transitions
from unpowered to powered-up, a
channel output assumes the logic state of
the input. When VCCI transitions from
powered-up to unpowered, channel
output assumes the selected default
state.
PD
PU
X
H or Open
Default
(1) VCCI = Input-side VIO or VISOIN; VCCO = Output-side VIO or VISOIN; PU = Powered up (VIO > 1.7 V, VISOIN > 1.7 V); PD = Powered down
(VIO < 1 V, VISOIN < 1 V); X = Irrelevant; H = High level; L = Low level.
(2) In the default condition, the output is high for the ISOW774x-Q1 device and low with the F suffix.
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9.4.1 Device I/O Schematics
INx (Devices without F suffix)
INx (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
VSEL
OUTx
VCCO
VISOOUT
VISOOUT
VISOOUT
~20 ꢀ
1970 ꢀ
OUTx
SEL
2 Mꢀ
EN_IOx
EN/FLT
VCCI
VCCI
VCCI
VIO
VIO
VIO
VCCI
VIO
550 kꢀ
550 kꢀ
INx
INx
Fault
1mA
图9-5. Device I/O Schematics
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used to
power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses
single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because
of the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between
the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device is
also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
图10-1 shows the typical schematic for SPI isolation.
Reference
10 ꢀF
1 ꢀF 10 nF
10 nF
1 ꢀF
10 ꢀF
3.3 VIN
VIO
VISOIN
3.3VOUT
DVCC
AVDD
DVDD
REF
CS
INA
INB
OUTA
OUTB
CS
HV+ to
Chassis
HV- to
SCLK
SCLK
ADC
MCU
DVSS
SDO
SDI
INC
OUTC
IND
SDI
Chassis
OUTD
SDO
AGND DGND
ISOW7741
GNDIO
GISOIN
330 ꢁ at 100 MHz
(BLM15EX331SN
1D)
VSEL
VISOOUT
VDD
IN OUT
1 ꢀF
10 nF
10 nF
1 ꢀF
10 ꢀF
10 ꢀF
GND
GND1
GND2
330 ꢁ at 100 MHz
(BLM15EX331SN
1D)
Optional LDO
图10-1. Isolated Power and SPI for ADC Sensing Application with ISOW7741-Q1
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10.2.1 Design Requirements
To design with this device, use the parameters listed in 表10-1.
表10-1. Design Parameters
PARAMETER
VDD input voltage
VALUE
3 V to 5.5 V
1.71 V to 5.5 V
VIO input voltage
VISOIN input voltage
1.71 V to 5.5 V
VDD decoupling capacitors
VIO decoupling capacitors
VISOIN decoupling capacitors
VISOOUT decoupling capacitors
VISOOUT to VISOIN series inductor
GND2 to GISOIN series inductor
VIO series inductor
10 µF + 1 µF + 0.01 µF + optional additional capacitance
0.1 µF + optional additional capacitance
0.1 µF + optional additional capacitance
10 µF + 1 µF + 0.01 µF + optional additional capacitance
BLM15ELX9331SN1D
BLM15ELX9331SN1D
BLM15ELX9331SN1D
VDD series inductor
BLM15ELX9331SN1D
GND1 to GNDIO series inductor
BLM15ELX9331SN1D
Because of very-high current flowing through the ISOW7741-Q1 device device VDD and VISOOUT supplies, higher
decoupling capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is
adequate, higher decoupling capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective
grounds are strongly recommended to achieve the best performance.
10.2.2 Detailed Design Procedure
The devices requires specific placement of external bypass capacitors and ferrite beads to operate at high
performance. These low-ESR ceramic bypass capacitors must be placed as close to the chip pads as possible.
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10
1
F
F
10
1
F
F
VIO
330 at 100 MHz
(BLM15EX331SN1D)
10 nF
10 nF
VISOIN
1
20
OUTA
OUTB
OUTC
IND
2
3
19
18
INA
INB
4
5
17
16
INC
OUTD
GNDIO
EN_IO1
GISOIN
EN_IO2
6
7
15
14
VIO
VISOIN
EN/FLT
VSEL
8
9
13
12
VISOOUT
FAULT OUT
330 at 100 MHz
(BLM15EX331SN1D)
330 at 100 MHz
(BLM15EX331SN1D)
VISOOUT
GND2
VISOIN
VDD
1
F
10 nF
1 F
10
10 nF
F
10
F
GND1
10
11
330 at 100 MHz
(BLM15EX331SN1D)
330 at 100 MHz
(BLM15EX331SN1D)
图10-2. Typical ISOW7741-Q1 Circuit Hook-Up
10.2.3 Application Curve
The following typical eye diagrams of the ISOW774x-Q1 device indicates low jitter and wide open eye at the data
rate of 50 Mbps.
Time = 5 ns / div
Time = 5 ns / div
图10-4. Eye Diagram at 50 Mbps PRBS 216 –1, 3.3
图10-3. Eye Diagram at 50 Mbps PRBS 216 –1, 5 V
V and 25°C
and 25°C
10.2.4 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 10-5 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
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insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 10-6 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图10-5. Test Setup for Insulation Lifetime Measurement
图10-6. Insulation Lifetime Projection Data
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11 Power Supply Recommendations
To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. VISOOUT needs to be connected to VISOIN to ensure the
feedback channel is properly powered to regulate the DC-DC converter. If VISOOUT and VISOIN are not connected,
the DC-DC converter will run open loop and the VISOOUT voltage will drift until the over-voltage clamp clamps at 6
V. There are two ways to connect VISOOUTand VISOIN
:
1) connect VISOOUT and VISOIN directly with a ferrite bead. A ferrite bead is recommended between VISOOUTand
VISOIN to further reduce emissions.
2) connect VISOOUT and VISOIN with a ferrite bead through an LDO that remains powered up at all times. If the
LDO has an EN pin then keep the EN high at all times.
The input supply (VIO and VDD) must have an appropriate current rating to support output load and switching at
the maximum data rate required by the end application. For more information, refer to the 节10.2 section.
For an output load current of 110 mA, it is recommended to have >600 mA of input current limit and for lower
output load currents, the input current limit can be proportionally lower.
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12 Layout
12.1 Layout Guidelines
A low cost two layer PCB should be sufficient to achieve good EMC performance:
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective
GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature
of the device from rising to unacceptable levels.
图 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must be
followed to meet application EMC requirements:
• High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
• Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
• Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
• Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on VISOOUT and GND2 path so that any
high frequency noise from power converter output sees a high impedance before it goes to other components
on PCB.
• Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT pin12
and GND2 pin11. VSEL pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for
output voltage selection.
• Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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12.2 Layout Example
Ground plane on
side 2
Ground plane on
side 1
<2mm
<2mm
C
C
C
C
C
C
FB
5
VISOIN
Input supply 1
VIO
20
19
1
10 F
10 nF
1 F
10
F
1
F
10 nF
INA
INB
INC
OUTA
2
OUTB
OUTC
3
4
18
17
16
15
14
13
OUTD
GNDIO
5
IND
GISOIN
Ground plane on side 1
6
EN_IO1
EN/FLT
VDD
7
EN_IO2
VSEL
Ground
plane on
side 2
8
10
F
1
F
10 nF
10 nF
1 F
10 F
FB
4
FB
1
Input supply 2
9
12 VISOOUT
C
C
C
C
C
C
FB
3
FB
2
GND1
GND2
11
Ground plane
on side 1
10
<1mm
2-4mm
Keep-out zone for any metal
2-4mm
<1mm
图12-1. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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14.1 Package Option Addendum
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14.1.1 Packaging Information
Status Packag
Packag
e
Drawing
Packag Eco Plan
e Qty
Lead/Ball
Finish(4)
MSL Peak
Temp (3)
Op Temp
(°C)
Orderable Device
Pins
20
Device Marking(5) (6)
XISOW7741
(1)
(2)
e Type
Green
ACTIV
E
Level-3-260C-1
68 HR
XISOW7741DFMR
XISOW7741FDFMR
SOIC
SOIC
DFM
DFM
2000
2000
(RoHS & CU NIPDAU
no Sb/Br)
-40 to 125
Green
(RoHS & CU NIPDAU
no Sb/Br)
ACTIV
E
Level-3-260C-1
68 HR
20
-40 to 125
XISOW7741F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using
this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please
check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS
requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the
die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free
(RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb)
based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
space
(4) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will
appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device
Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI
bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and
accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers
consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to
Customer on an annual basis.
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14.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
XISOW7741DFMR
XISOW7741FDFMR
SOIC
SOIC
DFM
DFM
20
20
2000
2000
330.0
330.0
16.4
16.4
10.75
10.75
10.7
10.7
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
2000
2000
Length (mm) Width (mm)
Height (mm)
43.0
XISOW7741DFMR
XISOW7741FDFMR
SOIC
SOIC
DFM
DFM
20
20
350.0
350.0
350.0
350.0
43.0
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PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
9
8
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (0.6)
16X (2)
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW7741FQDFMRQ1
ISOW7741QDFMRQ1
ISOW7742FQDFMRQ1
ISOW7742QDFMRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DFM
DFM
DFM
DFM
20
20
20
20
850
850
850
850
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISOW7741F
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
ISOW7741
ISOW7742F
ISOW7742
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISOW7741-Q1, ISOW7742-Q1 :
Catalog : ISOW7741, ISOW7742
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
重要声明和免责声明
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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