ISO1412BDW [TI]
具有 EMC 保护功能的 500Kbps、全双工、5kVrms 隔离式 RS-485 和 RS-422 收发器 | DW | 16 | -40 to 125;
| 型号： | ISO1412BDW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 EMC 保护功能的 500Kbps、全双工、5kVrms 隔离式 RS-485 和 RS-422 收发器 | DW | 16 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总49页 (文件大小：4352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
EMC 性能优异的 ISO14xx 5kVRMS 隔离式 RS-485/RS-422 收发器
1 特性
3 说明
1
•
符合 TIA/EIA-485-A 标准
在 5V 总线侧电源下与 PROFIBUS 兼容
总线 I/O 保护
ISO14xx 器件是适用于 TIA/EIA RS-485 和 RS-422 应
用的电隔离差分线路收发器。这些抗噪声收发器设计用
于恶劣的工业环境。这些器件的总线引脚可承受高级别
的 IEC 静电放电 (ESD) 和 IEC 电子快速瞬变 (EFT)
事件，无需在总线上使用额外组件进行系统级保护。这
些器件提供有基础型和增强型隔离可供选择（请参阅
增强型和基础型隔离选项）。
•
•
–
–
–
±30kV HBM
±16kV IEC 61000-4-2 接触放电
±4kV IEC 61000-4-4 电气快速瞬变
•
•
低 EMI 500kbps、12Mbps 和 50Mbps 数据速率
1.71V 至 5.5V 逻辑侧电源 (VCC1)，3V 至 5.5V 总
器件信息(1)
线侧电源 (VCC2
)
器件型号
封装
封装尺寸（标称值）
•
•
•
•
•
•
•
•
失效防护接收器（总线开路、短路和空闲）
1/8 单位负载：多达 256 个总线节点
100kV/µs（典型值）高共模瞬态抗扰度
扩展温度范围为 -40°C 至 +125°C
适用于热插拔功能的无干扰加电和断电
宽体 SOIC-16 封装
ISO1410、ISO1410B
ISO1412、ISO1412B
ISO1430、ISO1430B
ISO1432、ISO1432B
ISO1450、ISO1450B
ISO1452、ISO1452B
SOIC (16)
10.30mm x 7.50mm
引脚兼容大多数隔离式 RS-485 收发器
安全相关认证：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
符合 DIN VDE V 0884-11:2017-01 标准的
7071VPK VIOTM 和 1500VPK VIORM（增强型和基
本型选项）
增强型和基础型隔离选项
特性
ISO14xx
加强版
VDE 标准的浪涌测试电压 10000VPK
ISO14xxB
基础版
保护级别
–
–
UL 1577 标准下，长达 1 分钟的 5000VRMS 隔
离
6000VPK
UL 标准的隔离等级
5000VRMS
5000VRMS
IEC 60950-1、IEC 62368-1、IEC 60601-1 和
IEC 61010-1 认证
1060VRMS
1500VPK
/
1060VRMS
1500VPK
/
VDE 标准的工作电压
–
–
CQC、TUV 和 CSA 认证
VDE（增强型）、UL、CQC 和 TUV 认证完
成；VDE（基本型）和 CSA 审批正在处理中
简化应用电路原理图
2 应用
Logic Supply
Bus-Side Supply
VCC1
VCC2
•
•
•
•
•
电网基础设施
VDD
光伏逆变器
TI Isolated
Transceiver
工厂自动化与控制
电机驱动器
DE
D
A
B
MCU
RS485 Bus
HVAC 系统和楼宇自动化
R
RE
GND1
Isolated Ground
DGND
GND2
Logic Ground
Galvanic Isolation
Barrier
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF22
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.16 Typical Characteristics.......................................... 17
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 4
Device Options....................................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
8.1 Absolute Maximum Ratings ...................................... 7
8.2 ESD Ratings.............................................................. 7
8.3 Recommended Operating Conditions....................... 7
8.4 Thermal Information.................................................. 8
8.5 Power Ratings........................................................... 8
8.6 Insulation Specifications............................................ 9
8.7 Safety-Related Certifications................................... 10
8.8 Safety Limiting Values ............................................ 10
8.9 Electrical Characteristics: Driver ............................. 11
8.10 Electrical Characteristics: Receiver ...................... 11
8.11 Supply Current Characteristics: Side 1 (ICC1)....... 13
8.12 Supply Current Characteristics: Side 2 (ICC2)....... 14
8.13 Switching Characteristics: Driver .......................... 15
8.14 Switching Characteristics: Receiver...................... 15
8.15 Insulation Characteristics Curves ......................... 16
9
Parameter Measurement Information ................ 23
10 Detailed Description ........................................... 26
10.1 Overview ............................................................... 26
10.2 Functional Block Diagram ..................................... 26
10.3 Feature Description............................................... 27
10.4 Device Functional Modes...................................... 28
11 Application and Implementation........................ 31
11.1 Application Information.......................................... 31
11.2 Typical Application ................................................ 32
12 Power Supply Recommendations ..................... 35
13 Layout................................................................... 35
13.1 Layout Guidelines ................................................. 35
13.2 Layout Example .................................................... 36
14 器件和文档支持 ..................................................... 37
14.1 文档支持................................................................ 37
14.2 相关链接................................................................ 37
14.3 接收文档更新通知 ................................................. 37
14.4 社区资源................................................................ 37
14.5 商标....................................................................... 37
14.6 静电放电警告......................................................... 37
14.7 Glossary................................................................ 38
15 机械、封装和可订购信息....................................... 38
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (May 2019) to Revision E
Page
•
•
•
•
Added footnote to Pin functions table for NC pins ................................................................................................................ 5
Changed certification information in Safety related certifications table................................................................................ 10
Changed the Vth+ spec in Electrical characteristics: Receiver for -15 ≤ VCM ≤ 15 V from -20 mV to -10 mV................... 11
Added 1 line item for Vth+ in Electrical characteristics: Receiver for -7 ≤ VCM ≤ 12 V....................................................... 11
Changes from Revision C (April 2019) to Revision D
Page
•
已添加 在整个数据表中添加了 B 器件编号 ............................................................................................................................ 1
Changes from Revision B (November 2018) to Revision C
Page
•
•
•
•
•
•
•
已更改 将整个数据表中引用的 ISO141x 更改为 ISO14xx ...................................................................................................... 1
已添加 在“器件信息”表中添加了 ISO1430、ISO1432、ISO1450、ISO1452......................................................................... 1
Changed the position of Device Features tabels .................................................................................................................. 4
Added footnote to Pin Functions: Full-Duplex Device............................................................................................................ 5
Added footnote to Pin Functions: Half-Duplex Device ........................................................................................................... 6
已添加 Typical curves for ISO143x and ISO145x in Typical Characteristics ...................................................................... 17
已添加 Section 11.2.3 Application Curves and Section 11.2.3.1 Insulation Lifetime ........................................................... 33
2
版权 © 2018–2019, Texas Instruments Incorporated
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
www.ti.com.cn
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
Changes from Revision A (August 2018) to Revision B
Page
•
已更改 将状态更改为生产数据................................................................................................................................................ 1
Changes from Original (July 2018) to Revision A
Page
•
•
•
•
Changed the designator of common mode voltage in Recommended operating condition to VI .......................................... 7
Added test condition for CMTI in Electrical characteristics: Driver ................................................................................... 11
Added test condition for CMTI in Electrical characteristics: Receiver.................................................................................. 12
已更改 VTEST to VCM in the Common Mode Transient Immunity (CMTI)—Full Duplex and Common Mode Transient
Immunity (CMTI)—Half Duplex figures in the Parameter Measurement Information section .............................................. 23
•
•
已更改 tPLH to tPZH and tPLZ to tPHZ in the first Driver Enable and Disable Times timing diagram in the Parameter
Measurement Information section ........................................................................................................................................ 24
已添加 tPHZ to the first Receiver Enable and Disable Times timing diagram in the Parameter Measurement
Information section .............................................................................................................................................................. 25
版权 © 2018–2019, Texas Instruments Incorporated
3
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
5 说明 （续）
这些器件用于长距离通信。隔离会破坏通信节点之间的接地回路，从而获得更大的共模电压范围。经测试，每个器
件的对称隔离栅可在总线收发器和逻辑电平接口之间按照 UL 1577 标准提供为时 1 分钟的 5000V RMS 隔离。
ISO14xx 器件可由 1 侧的 1.71V 至 5.5V 电压供电运行，此电压范围使器件能够与低压 FPGA 和 ASIC 连接。2 侧
上具有 3V 至 5.5V 的宽电源电压范围，因此无需在隔离侧提供稳压电源。这些器件支持 -40°C 至 +125°C 的宽工
作环境温度范围。
6 Device Options
Table 1 shows an overview of the options available for this family of devices.
Table 1. Device Features
PART NUMBER
ISO1410, ISO1410B
ISO1412, ISO1412B
ISO1430, ISO1430B
ISO1432, ISO1432B
ISO1450, ISO1450B
ISO1452, ISO1452B
ISOLATION
DUPLEX
Half
DATA RATE
500 Kbps
500 Kbps
12 Mbps
PACKAGE
16-pin DW
16-pin DW
16-pin DW
16-pin DW
16-pin DW
16-pin DW
Full
Half
Reinforced, Basic
Full
12 Mbps
Half
50 Mbps
Full
50 Mbps
4
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
www.ti.com.cn
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
7 Pin Configuration and Functions
DW Package
16-Pin SOIC
Full-Duplex Device Top View
VCC1
GND1
R
1
2
3
4
5
6
7
8
16
VCC2
GND2
A
15
14
13
12
11
10
9
RE
B
DE
Z
D
Y
NC
NC
GND2
GND1
Not to scale
Pin Functions: Full-Duplex Device
PIN
I/O
DESCRIPTION
NAME
NO.
14
13
6
A
B
D
I
I
I
Receiver non-inverting input on the bus side
Receiver inverting input on the bus side
Driver input
Driver enable. This pin enables the driver output when high and disables the driver
output when low or open.
DE
5
I
GND1(1)
GND1(1)
GND2(1)
GND2(1)
NC(2)
2
8
—
—
—
—
—
—
O
Ground connection for VCC1
Ground connection for VCC1
Ground connection for VCC2
Ground connection for VCC2
No internal connection
No internal connection
Receiver output
9
15
7
NC(2)
10
3
R
Receiver enable. This pin disables the receiver output when high or open and
enables the receiver output when low.
RE
4
I
VCC1
VCC2
Y
1
—
—
O
Logic-side power supply
Transceiver-side power supply
Driver non-inverting output
Driver inverting output
16
11
12
Z
O
(1) For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
(2) Device functionality is not affected if NC pins are connected to supply or ground on PCB
Copyright © 2018–2019, Texas Instruments Incorporated
5
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
DW Package
16-Pin SOIC
Half-Duplex Device Top View
VCC1
GND1
R
1
2
3
4
5
6
7
8
16
VCC2
GND2
NC
15
14
13
12
11
10
9
RE
B
DE
A
D
NC
NC
NC
GND1
GND2
Not to scale
Pin Functions: Half-Duplex Device
PIN
I/O
DESCRIPTION
NAME
NO.
12
13
6
A
B
D
I/O
I/O
I
Transceiver non-inverting input or output (I/O) on the bus side
Transceiver inverting input or output (I/O) on the bus side
Driver input
Driver enable. This pin enables the driver output when high and disables the driver
output when low or open.
DE
5
I
GND1(1)
GND1(1)
GND2(1)
GND2(1)
NC(2)
NC(2)
NC(2)
NC(2)
2
8
—
—
—
—
—
—
—
—
O
Ground connection for VCC1
Ground connection for VCC1
Ground connection for VCC2
Ground connection for VCC2
No internal connection
No internal connection
No internal connection
No internal connection
Receiver output
9
15
7
10
11
14
3
R
Receiver enable. This pin disables the receiver output when high or open and
enables the receiver output when low.
RE
4
I
VCC1
VCC2
1
—
—
Logic-side power supply
16
Transceiver-side power supply
(1) For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
(2) Device functionality is not affected if NC pins are connected to supply or ground on PCB
6
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
www.ti.com.cn
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
-0.5
-0.5
-0.5
-15
MAX
UNIT
V
VCC1
VCC2
VIO
Supply voltage, side 1
6
Supply voltage, side 2
6
V
Logic voltage level (D, DE, RE, R)
Output current on R pin
VCC1+0.5(3)
V
IO
15
18
mA
V
VBUS
TJ
Voltage on bus pins (A, B, Y, Z w.r.t GND2)
Junction temperature
-18
-40
150
150
℃
℃
TSTG
Storage temperature
-65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
8.2 ESD Ratings
VALUE
UNIT
V(ESD)
V(ESD)
V(ESD)
Contact Discharge, per IEC 61000-4-2
Contact Discharge, per IEC 61000-4-2
Pins Bus terminals and GND2
±16000
V
ISO141x, Pins Bus terminals and GND1
(across isolation barrier)
±8000
±8000
V
ISO143x, Pins Bus terminals and GND1
(across isolation barrier)
All pins except bus pins(1)
Contact Discharge, per IEC 61000-4-2
V
V
Electrostatic discharge
±6000
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
Bus terminals to GND2(1)
±30000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
All pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
MAX
1.89
5.5
UNIT
Supply Voltage, Side 1, 1.8-V operation
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
Supply Voltage, Side 2
1.71
V
V
VCC1
2.25
VCC2
VI
3
5.5
V
Common Mode voltage at any bus terminal: A or B
High-level input voltage (D, DE, RE inputs)
Low-level input voltage (D, DE, RE inputs)
Differential input voltage, A with respect to B
Output current, Driver
-7
12
V
VIH
VIL
0.7*Vcc1
Vcc1
0.3*Vcc1
15
V
0
-15
-60
-4
V
VID
IO
V
60
mA
mA
Ω
IOR
RL
Output current, Receiver
4
Differential load resistance
54
1/tUI
1/tUI
1/tUI
TA
Signaling rate ISO141x
500
12
kbps
Mbps
Mbps
°C
Signaling Rate ISO143x
Signaling rate ISO145x
50
Operating ambient temperature
-40
125
Copyright © 2018–2019, Texas Instruments Incorporated
7
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
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8.4 Thermal Information
ISO14xx
DW (SOIC)
16 PINS
67.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
27.7
29.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.9
ψJB
28.8
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO1410_ISO1412
PD
Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
556
28
mW
mW
load = 54 Ω ||50pF, Load on R=15pF
PD1
Maximum power dissipation (side-1)
Input a 250kHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
PD2
Maximum power dissipation (side-2)
528
mW
ISO1430_ISO1432
PD
Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
352
33
mW
mW
load = 54 Ω ||50pF, Load on R=15pF
Input a 6MHz 50% duty cycle square
wave to D pin with
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
319
mW
VDE=VCC1, VRE=GND1
ISO1450_ISO1452
PD
Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
588
49
mW
mW
load = 54 Ω ||50pF, Load on R=15pF
PD1
Maximum power dissipation (side-1)
Input a 25MHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
PD2
Maximum power dissipation (side-2)
539
mW
8
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
www.ti.com.cn
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
8.6 Insulation Specifications
SPECIFICATIONS
UNIT
PARAMETER
TEST CONDITIONS
DW-16
IEC 60664-1
(1)
CLR
CPG
DTI
External clearance
External creepage
Side 1 to side 2 distance through air
>8
mm
mm
µm
V
(1)
Side 1 to side 2 distance across package surface >8
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
CTI
>600
I
According to IEC 60664-1
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
1500
1060
1500
7071
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test; see 图 56
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
1.2 × VIOTM, t = 1 s (100% production)
=
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 10000 VPK
(qualification)
6250
4615
VPK
(3)
ISO141x
VIOSM
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6000 VPK
(qualification)
Maximum surge isolation voltage
VPK
(3)
ISO141xB
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 ≤ 5
s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
ISO14xx: Vpd(m) = 1.6 × VIORM , tm = 10 s
≤ 5
(4)
qpd
Apparent charge
pC
ISO14xxB: Vpd(m) = 1.2 × VIORM , tm = 10 s
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM, tini
1 s;
=
≤ 5
ISO14xx: Vpd(m) = 1.875 × VIORM , tm = 1 s
ISO14xxB: Vpd(m) = 1.5 × VIORM , tm = 1 s
(5)
CIO
RIO
Barrier capacitance, input to output
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
1
pF
> 1012
> 1011
> 109
2
(5)
Insulation resistance, input to output
VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/
21
UL 1577
VTEST = VISO , t = 60 s (qualification);
VTEST = 1.2 × VISO , t = 1 s (100% production)
VISO
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO14xx is suitable for safe electrical insulation and ISO14xxB is suitable for basic electrical insulation only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
Copyright © 2018–2019, Texas Instruments Incorporated
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8.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014
Plan to certify according
to IEC 60950-1, IEC
62368-1 and IEC 60601-1 Recognition Program
Recognized under UL
1577 Component
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to
GB4943.1-2011
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
for pollution degree 2,
material group I
ISO141x, ISO143x,
ISO145x: 800 VRMS
reinforced isolation
EN 61010-
1:2010 /A1:2019
ISO141x, ISO143x,
ISO145x: 600 VRMS
reinforced isolation
ISO141xB, ISO143xB,
ISO145xB: 1000 VRMS
basic isolation
----------------
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014
ISO141x, ISO143x,
ISO145x: 800 VRMS
reinforced isolation
ISO141xB, ISO143xB,
ISO145xB: 1060 VRMS
basic isolation
Maximum transient
isolation voltage,
7071 VPK
;
Maximum repetitive peak
isolation voltage,
ISO141xB, ISO143xB,
Reinforced insulation,
Altitude ≤ 5000 m,
Tropical Climate,
700 VRMS maximum
working voltage
1500 VPK
;
ISO145xB: 800 VRMS
Single protection,
basic isolation
5000 VRMS
Maximum surge isolation
voltage,
ISO141x, ISO143x,
ISO145x: 6250 VPK
(Reinforced)
ISO141xB, ISO143xB,
ISO145xB: 4600 VPK
(Basic)
----------------
CSA 60601- 1:14 and IEC
60601-1 Ed. 3.1,
ISO141x, ISO143x,
ISO145x: 2 MOPP
(Means of Patient
Protection) 250 VRMS (354
VPK) maximum working
voltage
Reinforced
Certificate:40040142
Basic certificate planned
Certificate number:
CQC15001121716
Certificate planned
File number: E181974
Client ID number: 77311
8.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 PACKAGE
R
θJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C,
334
511
669
974
TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see 图 1
θJA = 67.9°C/W, TJ = 150°C, TA = 25°C,
see 图 2
R
IS
Safety input, output, or supply current
mA
R
R
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1837
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
10
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ISO1450, ISO1452
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
8.9 Electrical Characteristics: Driver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Open circuit voltage, unloaded bus,
3 V ≤ VCC2 ≤ 5.5 V
1.5
5
VCC2
V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see 图 35), 3 V ≤
1.5
1.5
2.3
2.3
V
VCC2 ≤ 3.6 V, TA<100C
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see 图 35), 3.1 V ≤
VCC2 ≤ 3.6 V, TA>100C
Driver differential-output voltage
magnitude
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see 图 35)
|VOD
|
2.1
2
3.7
4.2
2.3
V
V
V
RL = 100 Ω (see 图 36), RS-422 load
RL = 54 Ω (see 图 36), RS-485 load, VCC2 = 3 V to
3.6 V
1.5
RL = 54 Ω (see 图 36), RS-485 load,
4.5 V < VCC2 < 5.5 V
2.1
3.7
V
Change in differential output voltage
between two states
Δ|VOD
|
RL = 54 Ω or RL = 100 Ω, see 图 36
RL = 54 Ω or RL = 100 Ω, see 图 36
RL = 54 Ω or RL = 100 Ω, see 图 36
–200
1
200
3
mV
V
VOC
Common-mode output voltage
0.5 × VCC2
change in steady-state common-mode
output voltage between two states
ΔVOC(SS)
–200
200
mV
VD = VCC1 or VD = VGND1, VDE = VCC1, VCC2=3.3V ±
10%
–7 V ≤ V ≤ 12 V, see 图 45
–250
250
10
mA
mA
IOS
Short-circuit output current
VD = VCC1 or VD = VGND1, VDE = VCC1, VCC2=5V ±
10%
–7 V ≤ V ≤ 12 V, see 图 45
250
Ii
Input current
VD and VDE = 0 V or VD and VDE = VCC1
–10
85
µA
VD=VCC1 or GND1, VCC1 = 1.71 V to 5.5 V, VCM
1200 V, ISO141x, See 图 38
=
=
=
CMTI
Common-mode transient immunity
100
100
100
kV/µs
VD=VCC1 or GND1, VCC1 = 1.71 V to 5.5 V, VCM
1200 V, ISO143x, See 图 38
CMTI
CMTI
Common-mode transient immunity
Common-mode transient immunity
85
85
kV/µs
kV/µs
VD=VCC1 or GND1, VCC1 = 2.25 V to 5.5 V, VCM
1200 V, ISO145x, See 图 38
8.10 Electrical Characteristics: Receiver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 500-kbps
devices, VI = –7 V or VI = 12 V, other input at 0 V
Ii1
Ii1
Ii1
Ii1
Bus input current
–100
125
µA
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 12-Mbps and
50-Mbps devices, VI = –7 V or VI = 12 V,
other input at 0 V
Bus input current
Bus input current
Bus input current
–100
-200
125
125
125
µA
µA
µA
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 500-kbps
devices, VI = –15 V or VI = 15 V, other input at 0 V
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 12-Mbps and
50-Mbps devices, VI = –15 V or VI = 15 V,
-200
other input at 0 V
–15 V ≤ VCM ≤ 15 V
–7 V ≤ VCM ≤ 12 V
(1)
See
-100
-100
–10
–20
mV
mV
VTH+
Positive-going input threshold voltage
(1)
See
Negative-going input threshold
voltage
(1)
VTH–
Vhys
–15 V ≤ VCM ≤ 15 V
–200
–130
30
See
mV
Input hysteresis (VTH+ – VTH–
)
–15 V ≤ VCM ≤ 15 V
mV
V
VCC1=5V ± 10%, IOH = –4 mA, VID = 200 mV
VCC1=3.3V ± 10%, IOH = –2 mA, VID = 200 mV
VCC1 – 0.4
VCC1 – 0.3
V
VOH
Output high voltage on the R pin
VCC1=2.5V ± 10%, 1.8V+/-5%, IOH = –1 mA, VID
200 mV
=
VCC1 – 0.2
V
(1) Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–
Copyright © 2018–2019, Texas Instruments Incorporated
.
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Electrical Characteristics: Receiver (continued)
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1=5V ± 10%, IOL = 4 mA, VID = –200 mV
VCC1=3.3V ± 10%, IOL = 2 mA, VID = –200 mV
0.4
V
0.3
V
VOL
Output low voltage on the R pin
VCC1=2.5V ± 10%, 1.8V ± 5%, IOL = 1 mA, VID
–200 mV
=
0.2
V
Output high-impedance current on
the R pin
IOZ
Ii
VR = 0 V or VR = VCC1, VRE = VCC1
VRE = 0 V or VRE = VCC1
–1
–10
85
1
µA
µA
Input current on the RE pin
10
VCC1=1.71 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM
1200 V, ISO141x, See 图 38
=
=
=
CMTI
Common-mode transient immunity
100
100
100
kV/µs
VCC1=1.71 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM
1200 V, ISO143x, See 图 38
CMTI
CMTI
Common-mode transient immunity
Common-mode transient immunity
85
85
kV/µs
kV/µs
VCC1=2.25 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM
1200 V, ISO145x, See 图 38
12
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ISO1450, ISO1452
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
8.11 Supply Current Characteristics: Side 1 (ICC1
)
Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side
VD = VCC1, VCC1 = 5 V ± 10%
supply current
2.6
2.6
3.2
3.2
3.2
3.2
3.6
3.4
4.4
4.4
5.1
5.1
5.1
5.1
5.3
5.2
mA
mA
mA
mA
mA
mA
mA
mA
Logic-side
VD = VCC1, VCC1 = 3.3 V ± 10%
supply current
Logic-side
supply current
ISO141x, D = 500-kbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
ISO141x, D = 500-kbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
ISO143x, D = 12-Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
ISO143x, D = 12-Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
ISO145x, D = 50-Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
ISO145x, D = 50-Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
Logic-side
supply current
Logic-side
supply current
Logic-side
supply current
Logic-side
supply current
Logic-side
supply current
DRIVER ENABLED, RECEIVER ENABLED
Logic-side
supply current
VRE = VGND1, loopback if full-duplex device, VD = VCC1, VCC1 = 5 V ± 10%
2.6
2.6
3.3
3.2
4.1
3.8
6.3
5.3
4.4
4.4
5.1
5.1
6
mA
mA
mA
mA
mA
mA
mA
mA
Logic-side
supply current
VRE = VGND1, loopback if full-duplex device, VD = VCC1, VCC1 = 3.3 V ± 10%
Logic-side
supply current
ISO141x, VRE = VGND1, loopback if full-duplex device, D = 500-kbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
ISO141x, VRE = VGND1, loopback if full-duplex device, D = 500-kbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
ISO143x, VRE = VGND1, loopback if full-duplex device, D = 12-Mbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
ISO143x, VRE = VGND1, loopback if full-duplex device, D= 12-Mbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF
5.7
8.9
7.8
Logic-side
supply current
ISO145x, VRE = VGND1, loopback if full-duplex device, D = 50-Mbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
ISO145x, VRE = VGND1, loopback if full-duplex device, D= 50-Mbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF
DRIVER DISABLED, RECEIVER ENABLED
Logic-side
supply current
V
(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10%
(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10%
1.6
1.6
1.7
1.6
2.6
2.2
4.7
3.7
3.1
3.1
3.1
3.1
4
mA
mA
mA
mA
mA
mA
mA
mA
Logic-side
supply current
V
(1)
Logic-side
supply current
ISO141x, (A-B) = 500-kbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)
15 pF
=
(1)
Logic-side
supply current
ISO141x, (A-B) = 500-kbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)
= 15 pF
(1)
Logic-side
supply current
ISO143x, (A-B) = 12-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)
15 pF
=
(1)
Logic-side
supply current
ISO143x, (A-B) = 12-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)
= 15 pF
3.7
6.7
5.7
(1)
Logic-side
supply current
ISO145x, (A-B) = 50-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)
15 pF
=
(1)
Logic-side
supply current
ISO145x, (A-B) = 50-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)
= 15 pF
DRIVER DISABLED, RECEIVER DISABLED
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
1.6
1.6
3.1
3.1
mA
mA
Logic-side
supply current
(1) CL(R) is the load capacitance on the R pin.
Copyright © 2018–2019, Texas Instruments Incorporated
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MAX UNIT
8.12 Supply Current Characteristics: Side 2 (ICC2
VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
DRIVER ENABLED, BUS UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 3.3 V ± 10%
4
6.1
6.6
mA
mA
current
Bus-side supply
current
VD = VCC1, VCC2 = 5 V ± 10%
4.5
DRIVER ENABLED, BUS LOADED
Bus-side supply
current
VD = VCC1, RL = 54 Ω, VCC2 = 3.3 V ± 10%
VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10%
48
74
58
88
mA
mA
mA
mA
mA
mA
mA
mA
Bus-side supply
current
Bus-side supply ISO141x, D = 500-kbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ±
current
63
95
10%
Bus-side supply
current
ISO141x, D = 500-kbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
113
56
160
75
Bus-side supply
current
ISO143x, D = 12-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ± 10%
ISO143x, D = 12-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
ISO145x, D = 50-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ± 10%
ISO145x, D = 50-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
Bus-side supply
current
97
122
103
162
Bus-side supply
current
84
Bus-side supply
current
134
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 3.3 V ± 10%
current
2.6
2.8
4.3
4.5
mA
mA
Bus-side supply
VD = VCC1, VCC2 = 5 V ± 10%
current
14
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
www.ti.com.cn
ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
8.13 Switching Characteristics: Driver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
500-kbps DEVICES
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see 图 37
tPHL, tPLH Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
460
310
4
680
570
50
ns
ns
ns
ns
ns
RL = 54 Ω, CL = 50 pF, see 图 37
RL = 54 Ω, CL = 50 pF, see 图 37
See 图 40, and 图 41
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
12-Mbps DEVICES
125
160
200
600
See 图 40, and 图 41
RL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to
5.5 V, see 图 37
10
25
ns
ns
tr, tf
Differential output rise time and fall time
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6
V, see 图 37
27.8
tPHL, tPLH Propagation delay
RL = 54 Ω, CL = 50 pF, see 图 37
RL = 54 Ω, CL = 50 pF, see 图 37
See 图 40, and 图 41
68
2
125
10
ns
ns
ns
ns
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
50-Mbps DEVICES
75
75
125
160
See 图 40, and 图 41
RL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to
5.5 V, see 图 37
4.7
6
ns
ns
tr, tf
Differential output rise time and fall time
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6
V, see 图 37
7.8
tPHL, tPLH Propagation delay
RL = 54 Ω, CL = 50 pF, see 图 37
RL = 54 Ω, CL = 50 pF, see 图 37
See 图 40, and 图 41
19
1
41
6
ns
ns
ns
ns
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
25
32
46
78
See 图 40, and 图 41
(1) Also known as pulse skew.
8.14 Switching Characteristics: Receiver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
500-kbps DEVICES
tr, tf Differential output rise time and fall time CL = 15 pF, see 图 42
tPHL, tPLH Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
92
4.5
9
4
135
12.5
30
ns
ns
ns
ns
ns
CL = 15 pF, see 图 42
CL = 15 pF, see 图 42
See 图 43 and 图 44
See 图 43 and 图 44
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
12-Mbps DEVICES
5
20
tr, tf
Differential output rise time and fall time CL = 15 pF, see 图 42
1
75
1
4
120
10
ns
ns
ns
ns
ns
tPHL, tPLH Propagation delay
CL = 15 pF, see 图 42
CL = 15 pF, see 图 42
See 图 43 and 图 44
See 图 43 and 图 44
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
50-Mbps DEVICES
9
30
5
20
tr, tf
Differential output rise time and fall time CL = 15 pF, see 图 42
1
4
ns
ns
tPHL, tPLH Propagation delay
CL = 15 pF, see 图 42
36
60
(1) Also known as pulse skew.
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Switching Characteristics: Receiver (continued)
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CL = 15 pF, Measured with 50kHz, 50%
Duty Clock, see 图 42
PWD
Pulse width distortion(1), |tPHL – tPLH
|
2
6
ns
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
See 图 43 and 图 44
See 图 43 and 图 44
9
5
30
20
ns
ns
8.15 Insulation Characteristics Curves
1200
2500
2000
1500
1000
500
VCC = 1.89 V
VCC = 2.75 V
VCC = 3.6 V
VCC = 5.5 V
1000
800
600
400
200
0
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D001
d002
图 1. Thermal Derating Curve for Limiting Current per VDE
图 2. Thermal Derating Curve for Limiting Power per VDE
16
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8.16 Typical Characteristics
70
120
110
100
90
80
70
60
50
40
30
20
10
0
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
60
50
40
30
20
10
0
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
0
100
200 300
Data rate (kbps)
400
500
0
100
200 300
Data rate (kbps)
400
500
D001
D002
DE = VCC1
RE = GND1
TA = 25°C
DE = VCC1
TA = 25°C
RE = GND1
Driver Load = 54 Ω
|| 50pF
Load On R = 15 pF
图 3. ISO141x Supply Current Vs Data Rate- No Load
图 4. ISO141x Supply Current Vs Data Rate- With 54Ω||50pf
Load
90
80
70
60
50
40
50
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
45
40
35
30
25
20
15
10
5
ICC1 (Vcc1=3.3V)
ICC2 (Vcc2=3.3V)
ICC2 (Vcc2=5V)
30
20
10
0
0
100
200 300
Data rate (kbps)
400
500
0
D003
0
2
4
6
Data rate (Mbps)
8
10
12
DE = VCC1
TA = 25°C
RE = GND1
Driver Load = 120
d001
Ω || 50pF
DE = VCC1
TA = 25°C
RE = GND1
Load On R = 15 pF
图 6. ISO143x Supply Current Vs. Data Rate - No Load
图 5. ISO141x Supply Current Vs Data Rate- With 120Ω||50pf
Load
100
120
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
90
100
80
60
40
20
0
80
70
60
50
40
30
20
10
0
0
2
4
6
Data rate (Mbps)
8
10
12
0
2
4
6
Data rate (Mbps)
8
10
12
d002
d003
DE = VCC1
TA = 25°C
RE = GND1
DE = VCC1
TA = 25°C
RE = GND1
Driver Load = 120
50pF, Load On R =
15pf
Driver Load = 54 Ω
50pF, Load On R =
15pf
Ω || 50pF
|| 50pF
图 8. ISO143x Supply Current Vs Data Rate- 54Ω||50pF Load
图 7. ISO143x Supply Current Vs. Data Rate - 120Ω||50pF
Load
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Typical Characteristics (接下页)
120
140
120
100
80
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
100
80
60
40
20
0
60
40
20
0
0
5
10
15
20
25
30
Data rate (Mbps)
35
40
45
50
0
10
20 30
Data rate (Mbps)
40
50
d009
d010
DE = VCC1
TA = 25°C
RE = GND1
DE = VCC1
TA = 25°C
RE = GND1
Driver Load = 120
50pF, Load On R =
15pf
图 9. ISO145x Supply Current Vs Data Rate- No Load
Ω || 50pF
图 10. ISO145x Supply Current Vs Data Rate- 120Ω||50pF
Load
5
5.35
Voh
Vol
5.3
5.25
5.2
4.5
4
3.5
3
5.15
5.1
2.5
2
5.05
5
1.5
1
4.95
4.9
0.5
0
4.85
4.8
0
10
20
30
40
50
60
Driver output current (mA)
70
80
90 100
4.75
D004
-40
-20
0
20
40
60
80
100 120 140
DE = VCC1
TA = 25°C
D = GND1
VCC1 = 3.3 V
Ambient temp ( èC )
d011
VCC2 = 5 V
DE = VCC1
TA = 25°C
RE = GND1
Driver Load = 54 Ω
50pF, Load On R =
15pf
图 12. Driver Output Voltage Vs Driver Output Current
|| 50pF
图 11. ISO145x Supply Current Vs Data Rate- 54Ω||50pF
Load
5
4.5
4
6
5.5
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
VOD (3.3 V, 120 W)
VOD (3.3 V, 54 W)
VOD (5V, 120 W)
VOD (5V, 54 W)
1
0.5
0
1.5
1
0
10
20
30
Driver output current (mA)
40
50
60
70
80
90 100
-40
-20
0
20
40
60
80
100 120 140
Ambient temperature (èC)
D005
D006
DE = VCC1
TA = 25°C
D = GND1
VCC1 = 3.3 V
VCC2 = 5 V
图 13. Driver Differential Output Voltage Vs Driver Output
图 14. Driver Differential Output Voltage Vs Temperature
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Typical Characteristics (接下页)
80
70
60
50
40
30
20
10
0
580
560
540
520
500
480
460
440
420
0
0.5
1
1.5
2
Supply voltage VCC2 (V)
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
Ambient temp ( èC )
D007
D008
RL = 54 Ω
DE = D = VCC1
TA = 25°C
VCC1 = 3.3 V
VCC2 = 5 V
图 15. Driver Output Current Vs Supply Voltage (VCC2
)
图 16. ISO141x Driver Rise/fall Time (ns) Vs Temperature (c)
9.5
5.35
5.3
5.25
5.2
9
8.5
8
5.15
5.1
5.05
5
4.95
4.9
7.5
7
4.85
4.8
4.75
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient temp ( èC )
Ambient temp ( èC )
d004
d011
VCC1 = 3.3 V
VCC2 = 5 V
VCC1 = 3.3 V
VCC2 = 5 V
图 17. ISO143x Driver Rise/Fall Time (ns) Vs Temperature (C)
图 18. ISO145x Driver Rise/Fall Time (ns) Vs Temperature (C)
350
345
340
335
330
325
320
315
310
305
300
69
68.5
68
67.5
67
66.5
66
65.5
65
64.5
64
-40
-20
0
20
40
60
80
100 120 140
Ambient temperature ( èC )
63.5
D009
-40
-20
0
20
40
60
80
100 120 140
VCC1 = 3.3 V
VCC2 = 5 V
Ambient temp ( èC )
d005
VCC1 = 3.3 V
VCC2 = 5 V
图 19. ISO141x Driver Propagation Delay (ns) Vs
图 20. ISO143x Driver Propagation Delay (ns) Vs
Temperature (c)
Temperature (C)
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Typical Characteristics (接下页)
5
4.5
4
21.5
21
20.5
20
3.5
3
2.5
2
19.5
19
1.5
1
Voh (1.8V)
Voh (3.3V)
Voh (5V)
0.5
0
18.5
18
-15
-10 -5
High level output current (mA)
0
D010
-40
-20
0
20
40
60
80
100
120
TA = 25° C
Ambient temp ( èC )
d012
VCC1 = 3.3 V
VCC2 = 5 V
图 22. Receiver Buffer High Level Output Voltage Vs High
图 21. ISO145x Driver Propagation Delay (ns) Vs
Level Output Current
Temperature (C)
91
88
85
82
79
76
73
70
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VOL (1.8V)
VOL (3.3V)
VOL((5V)
0
2
4
6
Low level output current (mA)
8
10
12
14
16
-40
-20
0
20
40
60
80
100 120 140
Ambient temperature ( èC )
D011
D012
TA = 25°C
VCC1 = 3.3 V
VCC2 = 5 V
图 23. Receiver Buffer Low Level Output Voltage Vs Low
图 24. ISO141x Receiver Propagation Delay (ns) Vs
Level Output Current
Temperature (c)
80
79
78
77
76
75
44.5
44
43.5
43
42.5
42
41.5
41
40.5
40
39.5
39
38.5
38
37.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temp ( èC)
Ambient temperature ( èC )
d006
d013
VCC1 = 3.3 V
VCC2 = 5 V
VCC1 = 3.3 V
VCC2 = 5 V
图 25. ISO143x Receiver Propagation Delay (ns) Vs.
图 26. ISO145x Receiver Propagation Delay (ns) Vs.
Temperature (C)
Temperature (C)
20
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Typical Characteristics (接下页)
1050
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
600
550
500
450
400
350
300
250
200
2
3
4
5
6
Data Rate (Mbps)
7
8
9
10
11
12
0
5
10
15
20
Data Rate (Mbps)
25
30
35
40
45
50
d007
d014
For PWD ≤±5%
图 27. ISO143x Receiver VID vs Signaling Rate
For PWD ≤±5%
图 28. ISO145x Receiver VID vs Signaling Rate
VCC1 = 3.3 V
DE = VCC1
VCC2 = 5 V
TA = 25° C
VCC1 = 3.3 V
DE = VCC1
VCC2 = 5 V
TA = 25° C
图 29. ISO141x Driver Propagation Delay
图 30. ISO143x Driver Propagation Delay
VCC1 = 3.3 V
DE = VCC1
VCC2 = 5 V
TA = 25° C
VCC1 = 3.3 V
DE = GND1
VCC2 = 5 V
RE = GND1
TA = 25° C
图 31. ISO145x Driver Propagation Delay
图 32. ISO141x Receiver Propagation Delay
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Typical Characteristics (接下页)
图 34. VCC2 Power Up/Power Down - Glitch Free Behavior
图 33. VCC1 Power Up/Power Down - Glitch Free Behavior
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9 Parameter Measurement Information
VCC2
375 ꢀ
DE = VCC1
A or Y
RL
VOD
D = 0 or
VCC1
VTEST
B or Z
GND2
375 ꢀ
+
œ
图 35. Driver Voltages
RL(1) / 2
A or Y
VOD
B or Z
0 V or
VCC1
A
VA
VB
D
RL(1) / 2
B
VOC
VOC
GND2
ûVOC(SS)
VOC(PP)
(1) RL = 100 Ω for RS422, RL = 54 Ω for RS-485
图 36. Driver Voltages
VCC1
DE = VCC1
VI
50%
VOD
A or Y
B or Z
(1)
CL
50 pF 20%
RL
54 ꢀ 1%
D
tPHL
tPLH
VOD (H)
Input
Generator
90%
90%
tf
50 ꢀ
VI
0 V
10%
0 V
10%
tr
VOD
VOD (L)
GND1
(1) CL includes fixture and instrumentation capacitance.
图 37. Driver Switching Specifications
VCC1
DE
VCC2
0.1 µF
10 µF
10 µF
+
VOH or VOL
œ
VCC1
0.1 µF
GND1
Y
D
54 ꢀ
54 ꢀ
Z
A
GND1
1.5 V or 0 V
0 V or 1.5 V
R
RE
B
+
VOH or VOL
œ
CL
15 pF(1)
1 kꢀ
GND1
GND2
+ VCM
œ
(1) Includes probe and fixture capacitance.
图 38. Common Mode Transient Immunity (CMTI)—Full Duplex
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Parameter Measurement Information (接下页)
VCC1
VCC2
VCC1
DE
0.1 µF
10 µF
10 µF
0.1 µF
GND1
A
B
+
VOH or VOL
œ
D
54 ꢀ
GND1
+
VOH or VOL
œ
R
RE
CL
15 pF(1)
1 kꢀ
GND1
GND2
+ VCM
œ
(1) Includes probe and fixture capacitance.
图 39. Common Mode Transient Immunity (CMTI)—Half Duplex
A or Y
S1
VCC1
D
VO
50 % 50 %
VI
B or Z
DE
0 V
VOH
(1)
CL
50 pF
RL
110 ꢀ
tPZH
90%
Input
Generator
50 ꢀ
50%
VI
VO
≈ 0 V
tPHZ
GND2
GND1
(1) CL includes fixture and instrumentation capacitance
图 40. Driver Enable and Disable Times
VCC2
RL
110 ꢀ
VCC1
A or Y
50 % 50 %
VI
D
0 V
S1
B or Z
tPZL
tPLZ
(1)
CL
50 pF
DE
VCC2
VO
50%
10%
Input
Generator
VOL
50 ꢀ
VI
GND2
GND1
图 41. Driver Enable and Disable Times
24
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Parameter Measurement Information (接下页)
3 V
50 %
50 %
A
B
VI
R
VO
0 V
VOH
Input
Generator
(1)
CL
15 pF
1.5 V
50 ꢀ
tPLH
tPHL
VI
RE
90%
50%
10%
50%
VO
VOL
tr
tf
(1) CL includes fixture and instrumentation capacitance.
图 42. Receiver Switching Specifications
VCC1
50%
VI
0 V
tPZH
tPHZ
VOH
90%
VO
50%
≈ 0 V
VCC1
VOL
tPZL
tPLZ
VO
50%
10%
图 43. Receiver Enable and Disable Times
VCC1
VCC1
VI
50%
A
B
1 kꢀ
0 V
0 V or 1.5 V
1.5 V or 0 V
R
VO
CL
15 pF
S1
tPZH
VOH
≈ 0 V
VCC1
VOL
A at 1.5 V
B at 0 V
S1 to GND
RE
VO
50%
Input
Generator
tPZL
VI
50 ꢀ
A at 0 V
B at 1.5 V
S1 to
VO
50%
VCC1
图 44. Receiver Enable and Disable Times
A or Y
A or Y
B or Z
Steady-State
Logic Input
(1 or 0)
Steady State
Logic Input
(1 or 0)
œ7 V ≤ V ≤ 12 V
I(1)
G
G
V
B or Z
C
C
GND
GND
(1) The driver should not sustain any damage with this configuration.
图 45. Short-Circuit Current Limiting
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10 Detailed Description
10.1 Overview
The ISO14xx devices are isolated RS-485/RS-422 transceivers designed to operate in harsh industrial
environments. ISO141x, ISO143x and ISO145x devices support up to 500 kbps, 12 Mbps and 50 Mbps signaling
rates respectively. This family of devices has a 3-channel digital isolator and an RS-485 transceiver in a 16-pin
wide-body SOIC package. The silicon-dioxide based capacitive isolation barrier supports an isolation withstand
voltage of 5 kVRMS and an isolation working voltage of 1500 VPK. Isolation breaks the ground loop between the
communicating nodes and allows for data transfer in the presence of large ground potential differences. These
devices have a higher typical differential output voltage (VOD) than traditional transceivers for better noise
immunity. A minimum differential output voltage of 2.1 V is specified at a VCC2 voltage of 5 V ±10% which meets
the requirements for Profibus applications. The wide logic supply of the device (VCC1) supports interfacing with
1.8-V, 2.5-V, 3.3-V, and 5-V control logic. The 3-V to 5.5-V bus side supply (VCC2) removes the need of a well-
regulated isolated supply in end systems. 图 46 shows the functional block diagram of the full-duplex devices and
图 47 shows the functional block diagram of a half-duplex devices.
10.2 Functional Block Diagram
VCC2
VCC1
VCC2
Rx
VCC
Tx
Tx
Rx
DE
D
Y
Z
Rx
Tx
D
Full duplex
B
A
R
R
RE
GND1
GND2
GND2
图 46. Full-Duplex Block Diagram
VCC2
VCC1
VCC2
VCC
Tx
Tx
Rx
Rx
DE
D
Rx
D
A
B
Half duplex
Tx
R
R
RE
GND2
GND1
GND2
图 47. Half-Duplex Block Diagram
26
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10.3 Feature Description
10.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO14xx
devices incorporate dedicated circuitry to protect the transceiver from ±16 kV ESD per IEC61000-4-2 and ±4 kV
EFT per IEC 61000-4-4. System designers can achieve the ±4-kV EFT Criterion A with careful system design
(data communication between nodes in the presence of transient noise with minimum to no data loss).
10.3.2 Failsafe Receiver
The differential receiver of the ISO14xx devices has failsafe protection from invalid bus states caused by:
•
•
•
Open bus conditions such as a broken cable or a disconnected connector
Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
Idle bus conditions that occur when no driver on the bus is actively driving
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.
The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the does
not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID) is
greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a
logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that
determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always
cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200
mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+
threshold which makes the receiver output logic high. The receiver output goes to a low state only when the
differential input decreases by VHYS to less than VTH+
.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required
with traditional isolated RS-485 transceivers as shown in 图 48.
Traditional
transceiver
ISO1410
(R1 and R2 not needed)
VCC2
VCC2
VCC1
VCC2
VCC1
VCC2
R1
A
A
RS-485
Bus
RS-485
Bus
RT
RT
B
B
R2
GND2
GND1
GND2
GND1
ISO
Ground
ISO
Ground
Galvanic
Isolation Barrier
Galvanic
Isolation Barrier
图 48. Failsafe Transceiver
10.3.3 Thermal Shutdown
The ISO14xx devices have a thermal shutdown circuit to protect against damage when a fault condition occurs.
A driver output short circuit or bus contention condition can cause the driver current to increase significantly
which increases the power dissipation inside the device. An increase in the die temperature is monitored and the
device is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the
temperature. The device is enabled when the junction temperature becomes 165℃ (typical).
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Feature Description (接下页)
Bus short circuit for an extended duration and/or beyond voltage levels specified in recommended operating
condition should be avoided. Repeated or prolonged exposure to bus shorts can result in high junction
temperatures and affect device reliability.
10.3.4 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in an RS485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the
device is:
•
•
•
Hot plugged into the network in an unpowered state
Hot plugged into the network in a powered state and disabled state
Powered up or powered down in a disabled state when already connected to the bus
The ISO14xx devices do not cause any false data toggling on the bus when powered up or powered down in a
disabled state with supply ramp rates from 100 µs to 10 ms.
10.4 Device Functional Modes
表 2 shows the driver functional modes.
表 2. Driver Functional table(1)
OUTPUTS(2)
DRIVER ENABLE
VCC1
VCC2
INPUT D
DE
Y, A
H
Z, B
L
H
L
H
H
L
H
PU
PU
X
L
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
L
X
Open
H
Open
X
PD(3)
X
PU
PD
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
X
(1) PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
(2) The driver outputs are Y and Z for a full-duplex device. The driver outputs are A and B for a half-duplex device.
(3) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
The description that follows is specific to half-duplex device but the same logic applies to full-duplex device with
the outputs being Y and Z.
When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data
input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the
differential output voltage defined by 公式 1 is positive.
VOD = VA – VB
(1)
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential
output voltage defined by 公式 1 is negative. A logic low at the DE input causes both outputs to go to the high-
impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has
an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the
DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes low
when the D pin is left open while the driver enabled.
表 3 shows the receiver functional modes.
28
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ISO1450, ISO1452
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
表 3. Receiver Functional Table(1)
VCC1
VCC2
DIFFERENTIAL INPUT
VID = VA – VB
RECEIVER ENABLE RE
OUTPUT R
–0.02 V ≤ VID
L
H
–0.2 V < VID < 0.02 V
L
Indeterminate
V
ID≤ –0.2 V
L
H
L
PU
PU
X
X
Hi-Z
Hi-Z
H
Open
L
Open, Short, Idle
PD(2)
PU
PD(2)
PU
PD
PD
X
X
X
X
Hi-Z
H
L
X
Hi-Z
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by 公式 2 is greater than the positive input threshold, VTH+
.
VID = VA – VB
(2)
The receiver output, R, goes low when the differential input voltage defined by 公式 2 is less than the negative
input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The
receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic
high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the
transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or
the bus is not actively driven (idle bus).
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10.4.1 Device I/O Schematics
D and RE Inputs
VCC1 VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
VCC1
1.5 Mꢀ
985 ꢀ
985 ꢀ
Input
Input
1.5 Mꢀ
R Output
VCC1
~20 ꢀ
R
图 49. Device I/O Schematics
30
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ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
11 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The ISO14xx devices are designed for bidirectional data transfer on multipoint RS-485 networks. The design of
each RS-485 node in the network requires an ISO14xx device and an isolated power supply as shown in 图 52.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated
with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance,
Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable
length.
Full-duplex implementation, as shown in 图 50, requires two signal pairs (four wires). Full-duplex implementation
lets each node to transmit data on one pair while simultaneously receiving data on the other pair. In half-duplex
implementation, as shown in 图 51, the driver and receiver enable pins let any node at any given moment be
configured in either transmit or receive mode which decreases cable requirements.
Y
Z
A
B
RT
RT
R
RE
DE
D
R
RE
DE
D
ISO1412
Master
ISO1412
Slave
B
A
Z
Y
RT
RT
A
B
Z
Y
图 50. Typical RS-485 Network With Full-Duplex Isolated Transceivers
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Application Information (接下页)
Integrated isolation barrier allows for communication between
nodes with ground potential differences of up to 1500 V
R
R
A
B
A
B
RE
DE
D
RE
DE
D
ISO1410
RT
RT
ISO1410
A
B
A
B
图 51. Typical RS-485 Network With Half-Duplex Isolated Transceivers
11.2 Typical Application
图 52 shows the application circuit of the ISO1410 device.
4
8
1
3
5
4
GND
D2
IN
OUT
NC
EN
SN6505
3
2
7
6
3.3 V
TPS76350
EN
VCC
2
GND
1
5
CLK
D1
1
2
16
VCC2
0.1 …F
VDD
3
14
13
GPIO1
4
5
MCU
GPIO2
ISO1410
12
A
6
L1 3.3V
NC 10,11
GPIO3
DGND
Optional bus
protection
N
PSU
7
8
0V
PE
9,15
Galvanic
Isolation Barrier
Protective Chasis
Earth
Digital
Ground
ISO
Ground
Ground
图 52. Application Circuit of ISO1410
11.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO14xx devices only require external bypass capacitors to operate.
32
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Typical Application (接下页)
11.2.2 Detailed Design Procedure
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.
11.2.2.1 Data Rate and Bus Length
The RS-485 standard has typical curves similar to those shown in 图 53. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 53. Cable Length vs Data Rate Characteristics
Use 图 53 as a guideline for cable selection, data rate, cable length and subsequent jitter budgeting.
11.2.2.2 Stub Length
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in 公式 3.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver.
c is the speed of light (3 × 108 m/s).
v is the signal velocity of the cable or trace as a factor of c.
(3)
11.2.2.3 Bus Loading
The current supplied by the driver must supply into a load because the output of the driver depends on this
current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO14xx devices have 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
11.2.3 Application Curves
Below eye diagram of ISO145x device indicates low jitter and wide open eye at maximum data rate of 50 Mbps.
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Typical Application (接下页)
图 54. Eye Diagram at 50 Mbps Clock, VCC2 = 5 V, 25°C
11.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 55 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 56 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based
on the TDDB data, the intrinsic capability of the insulation is 1060 VRMS with a lifetime of 220 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 is specified up to 1060 VRMS . At the lower working voltages, the
corresponding insulation lifetime is much longer than 220 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图 55. Test Setup for Insulation Lifetime Measurement
34
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ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
Typical Application (接下页)
Working Isolation Voltage = 1060 VRMS
TA up to 150°C
Projected Insulation Lifetime = 220 Years
Applied Voltage Frequency = 60 Hz
图 56. Insulation Lifetime Projection Data
12 Power Supply Recommendations
To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near
to the supply pins as possible. Additionally, a 10 µF bulk capacitor on VCC2 improves transceiver performance
during bus transitions in transmit mode. If only one primary-side power supply is available in an application,
isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's
SN6505B device. For such applications, detailed power supply design and transformer selection
recommendations are available in the SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
data sheet.
13 Layout
13.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 57). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Copyright © 2018–2019, Texas Instruments Incorporated
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Layout Guidelines (continued)
图 58 shows the recommended placement and routing of the device bypass capacitors and optional TVS diodes.
Put the VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use vias to
complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer is
needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack
mechanically stable and prevents it from warping. Also the power and ground plane of each power system can
be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.
13.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
13.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 57. Recommended Layer Stack
Minimize
distance to
supply pins
VCC1
VCC2
Optional bus
protection
0.1 µF
VCC1
GND1
R
VCC2
GND2
NC
0.1 µF
C
C
MCU
RE
B
D1
RS-485
DE
A
D
NC
NC
NC
GND1
GND2
GND1
Plane
GND2
Plane
图 58. Layout Example
36
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ZHCSID5E –APRIL 2018–REVISED SEPTEMBER 2019
14 器件和文档支持
14.1 文档支持
14.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
德州仪器 (TI)，《数字隔离器设计指南》
德州仪器 (TI)，《隔离相关术语》
德州仪器 (TI)，《隔离式 RS-485 半双工评估模块》用户指南
德州仪器 (TI)，《如何隔离 RS-485 系统的信号和电源》TI 技术手册
德州仪器 (TI) 《适用于工业长途通信的可靠隔离式 RS-485》TI 技术手册
14.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
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立即订购
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技术文档
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工具与软件
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ISO1410
ISO1412
ISO1430
ISO1432
ISO1450
ISO1452
ISO1410B
ISO1412B
ISO1430B
ISO1432B
ISO1450B
ISO1452B
14.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
14.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
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14.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
38
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1410BDW
ISO1410BDWR
ISO1410DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISO1410B
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO1410B
ISO1410
ISO1410
ISO1412B
ISO1412B
ISO1412
ISO1412
ISO1430B
ISO1430B
ISO1430
ISO1430
ISO1432B
ISO1432B
ISO1432
ISO1432
ISO1450B
ISO1450B
ISO1450
ISO1450
ISO1410DWR
ISO1412BDW
ISO1412BDWR
ISO1412DW
ISO1412DWR
ISO1430BDW
ISO1430BDWR
ISO1430DW
ISO1430DWR
ISO1432BDW
ISO1432BDWR
ISO1432DW
ISO1432DWR
ISO1450BDW
ISO1450BDWR
ISO1450DW
ISO1450DWR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1452BDW
ISO1452BDWR
ISO1452DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISO1452B
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ISO1452B
ISO1452
ISO1452
ISO1452DWR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1410BDWR
ISO1410DWR
ISO1412BDWR
ISO1412DWR
ISO1430BDWR
ISO1430DWR
ISO1432BDWR
ISO1432DWR
ISO1450BDWR
ISO1450DWR
ISO1452BDWR
ISO1452DWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO1410BDWR
ISO1410DWR
ISO1412BDWR
ISO1412DWR
ISO1430BDWR
ISO1430DWR
ISO1432BDWR
ISO1432DWR
ISO1450BDWR
ISO1450DWR
ISO1452BDWR
ISO1452DWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO1410BDW
ISO1410DW
ISO1412BDW
ISO1412DW
ISO1430BDW
ISO1430DW
ISO1432BDW
ISO1432DW
ISO1450BDW
ISO1450DW
ISO1452BDW
ISO1452DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
16
16
16
16
16
16
16
16
16
16
16
16
40
40
40
40
40
40
40
40
40
40
40
40
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
506.98
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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