INA286AQDGKRQ1 [TI]
AEC-Q100、-14V 至 80V 双向电流感应放大器 | DGK | 8 | -40 to 125;
| 型号： | INA286AQDGKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AEC-Q100、-14V 至 80V 双向电流感应放大器 | DGK | 8 | -40 to 125 放大器 光电二极管 |
| 文件： | 总34页 (文件大小：1178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1
SBOS554B –MARCH 2012–REVISED DECEMBER 2015
INA28x-Q1 Automotive Grade, –14-V to +80-V, Bidirectional, High Accuracy,
Low- or High-Side, Voltage Output, Current Shunt Monitor
1 Features
3 Description
The INA28x-Q1 family includes the INA282-Q1,
INA283-Q1, INA284-Q1, INA285-Q1, and INA286-Q1
devices. These devices are voltage output current
shunt monitors that can sense drops across shunts at
common-mode voltages from –14 V to +80 V,
independent of the supply voltage. The low offset of
the zero-drift architecture enables current sensing
with maximum drops across the shunt as low as 10
mV full-scale.
1
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified With the Following Results
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C5
•
•
•
•
Wide Common-Mode Range: –14 V to +80 V
Offset Voltage: ±20 μV
CMRR: 140 dB
These current sense amplifiers operate from a single
2.7-V to 18-V supply, drawing a maximum of 900 μA
of supply current. These devices are specified over
the extended operating temperature range of –40°C
to +125°C, and offered in SOIC-8 and VSSOP-8
packages.
Accuracy:
–
–
–
±1.4% Gain Error (Maximum)
0.3 μV/°C Offset Drift
Device Information(1)
0.005%/°C Gain Drift (Maximum)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
•
Available Gains:
INA28xAQDRQ1
SOIC (8)
–
–
–
–
–
50 V/V: INA282-Q1
100 V/V: INA286-Q1
200 V/V: INA283-Q1
500 V/V: INA284-Q1
1000 V/V: INA285-Q1
INA28xAQDGKRQ1 VSSOP (8)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
•
Quiescent Current: 900 μA (Maximum)
Detailed Block Diagram
Bus Supply
œ14 V to +80 V
2.7 V to 18 V
Load
2 Applications
•
•
•
•
•
•
EV and HEV Battery Management
EV and HEV Chargers
+IN
œIN
V+
Electric Power Steering (EPS) Systems
Body Control Modules
•1
•2
•2
•1
Brake Systems
Electronic Stability Control (ESC) Systems
•2
•2
•1
•1
OUT
Zer•-
Drift
Output
33.3 kꢀ
33.3 kꢀ
REF2
REF1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1
SBOS554B –MARCH 2012–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 21
Power Supply Recommendations...................... 25
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1 Related Links ........................................................ 26
11.2 Community Resources.......................................... 26
11.3 Trademarks........................................................... 26
11.4 Electrostatic Discharge Caution............................ 26
11.5 Glossary................................................................ 26
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Revision A (July 2015) to Revision B
Page
•
Changed VSSOP package from product preview to production data .................................................................................... 1
Changes from Original (March 2012) to Revision A
Page
•
Changed data sheet title from High-Accuracy, Wide Common-Mode Range, Bi-Directional CURRENT SHUNT
MONITOR Zerø-Drift Series to INA28x-Q1 Automotive Grade, –14-V to 80-V, Bidirectional, High Accuracy, Low- or
High-Side, Voltage Output Current Shunt Monitor ................................................................................................................. 1
Added DGK (VSSOP) package to data sheet........................................................................................................................ 1
Changed Applications............................................................................................................................................................. 1
Changed front page diagram.................................................................................................................................................. 1
•
•
•
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added RVRR as symbol for reference rejection ratio ........................................................................................................... 5
Changed order of figures in Typical Characteristics section .................................................................................................. 7
Changed Figure 16................................................................................................................................................................. 9
Changed VDRIVE condition in Figure 20 and Figure 21 ......................................................................................................... 10
Added functional block diagram ........................................................................................................................................... 13
Changed Figure 32 and Figure 33 ....................................................................................................................................... 15
Changed Figure 34 and Figure 35 ....................................................................................................................................... 16
Changed Figure 36 and Figure 37 ....................................................................................................................................... 17
Changed Figure 38............................................................................................................................................................... 17
Changed Reference Common-Mode Rejection to Reference Voltage Rejection Ratio....................................................... 18
Changed RCMR to RVRR in Table 1 and Table 2 ................................................................................................................. 19
Changed Figure 39 .............................................................................................................................................................. 20
Changed Figure 40 .............................................................................................................................................................. 21
Changed Figure 42 .............................................................................................................................................................. 23
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
5 Pin Configuration and Functions
D and DGK Package
8-Pin SOIC and VSSOP
Top View
-IN
GND
1
2
3
4
8
7
6
5
+IN
REF1
V+
REF2
NC(1)
OUT
(1) NC: This pin is not internally connected. The NC pin should either be left floating or connected to GND.
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
–IN
Analog input
Analog
Connection to negative side of shunt resistor.
2
GND
Ground
Reference voltage, 0 V to V+. See Reference Pin Connection Options section for connection
options.
3
4
REF2
NC
Analog input
—
This pin is not internally connected. The NC pin should either be left floating or connected to
GND.
5
6
OUT
V+
Analog output Output voltage
Analog
Power supply, 2.7 V to 18 V
Reference voltage, 0 V to V+. See Reference Pin Connection Options section for connection
options.
7
8
REF1
+IN
Analog input
Analog input
Connection to positive side of shunt resistor.
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INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1
SBOS554B –MARCH 2012–REVISED DECEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted.(1)
MIN
MAX
UNIT
V
Supply voltage, V+
18
(3)
Differential (V+IN) – (V–IN
)
–5
–14
5
80
V
Analog inputs,
V+IN, V–IN
(2)
Common-Mode
V
REF1, REF2, OUT
GND–0.3
(V+) + 0.3
5
V
Input current into any pin
Junction temperature
mA
°C
°C
150
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) V+IN and V–IN are the voltages at the +IN and –IN pins, respectively.
(3) Input voltages must not exceed common-mode rating.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
12
MAX
UNIT
VCM
V+
Common-mode input voltage
Operating supply voltage
V
V
5
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
INA28x-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
134.9
72.9
DGK (VSSOP)
8 PINS
164.1
56.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.3
85.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.9
6.5
ψJB
54.3
83.3
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
6.5 Electrical Characteristics
at TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VOS
Offset Voltage, RTI(1)
VSENSE = 0 mV
±20
±0.3
3
±70
μV
μV/°C
μV/V
V
dVOS/dT vs Temperature
TA = –40°C to 125°C
±1.5
PSRR
VCM
vs Power Supply
VS = 2.7 V to 18 V, VSENSE = 0 mV
TA = –40°C to 125°C
Common-Mode Input Range
–14
120
+80
V+IN = –14 V to 80 V, VSENSE = 0 mV
TA = –40°C to 125°C
CMRR
Common-Mode Rejection
140
dB
IB
Input Bias Current per Pin(2)
Input Offset Current
VSENSE = 0 mV
VSENSE = 0 mV
25
1
μA
μA
kΩ
IOS
Differential Input Impedance
6
REFERENCE INPUTS
Reference Input Gain
1
V/V
V
Reference Input Voltage Range(3)
Divider Accuracy(4)
0
VGND + 9
±0.5%
±75
±0.2%
±25
μV/V
μV/V/°C
μV/V
INA282-Q1
TA = –40°C to 125°C
0.055
±13
±30
±25
±10
±45
INA283-Q1
TA = –40°C to 125°C
0.040
±6
μV/V/°C
μV/V
Reference Voltage Rejection Ratio
(VREF1 = VREF2 = 40 mV to 9 V,
V+ = 18 V)
RVRR
INA284-Q1
TA = –40°C to 125°C
0.015
±4
μV/V/°C
μV/V
INA285-Q1
TA = –40°C to 125°C
0.010
±17
μV/V/°C
μV/V
INA286-Q1
TA = –40°C to 125°C
0.040
μV/V/°C
GAIN(5) (GND + 0.5 V ≤ VOUT ≤ (V+) – 0.5 V; VREF1 = VREF2 = (V+) / 2 for all devices)
INA282-Q1, V+ = 5 V
INA283-Q1, V+ = 5 V
50
200
V/V
V/V
V/V
V/V
V/V
G
Gain
INA284-Q1, V+ = 5 V
500
INA285-Q1, V+ = 5 V
1000
100
INA286-Q1, V+ = 5 V
INA282-Q1, INA283-Q1, INA286-Q1
INA284-Q1, INA285-Q1
TA = –40°C to 125°C
±0.4%
±0.4%
0.0008
±1.4%
±1.6%
0.005
Gain Error
%/°C
(1) RTI = referred-to-input.
(2) See typical characteristic graph Figure 7 .
(3) The average of the voltage on pins REF1 and REF2 must be between VGND and the lesser of (VGND+9 V) and V+.
(4) Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 36.
(5) See typical characteristic graph Figure 12.
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
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Electrical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Nonlinearity Error
Output Impedance
±0.01%
1.5
1
Ω
Maximum Capacitive Load
No sustained oscillation
nF
(6)
VOLTAGE OUTPUT
V+ = 5 V, RLOAD = 10 kΩ to GND
TA = –40°C to 125°C
Swing to V+ Power-Supply Rail
(V+)–0.17
(V+)–0.4
V
V
Swing to GND
TA = –40°C to 125°C
GND+0.015 GND+0.04
FREQUENCY RESPONSE
INA282-Q1
INA283-Q1
INA284-Q1
INA285-Q1
INA286-Q1
10
10
4
BW
Effective Bandwidth(7)
kHz
2
10
(1)
NOISE, RTI
Voltage Noise Density
1 kHz
110
nV/√Hz
POWER SUPPLY
VS
IQ
Specified Voltage Range
Quiescent Current
TA = –40°C to 125°C
2.7
18
V
600
900
μA
TEMPERATURE RANGE
Specified Range
–40
125
°C
(6) See typical characteristic graphs Figure 16 through Figure 18.
(7) See typical characteristic graph Figure 1 and the Effective Bandwidth section in the Applications Information.
6
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
6.6 Typical Characteristics
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
60
50
40
30
20
10
0
120
110
100
90
80
70
60
INA282-Q1 (50V/V)
INA285-Q1 (1kV/V)
INA284-Q1 (500V/V)
INA283-Q1 (200V/V)
INA286-Q1 (100V/V)
50
40
-10
-20
30
20
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 1. Gain vs Frequency
Figure 2. INA282-Q1 PSRR (RTI) vs Frequency
150
140
130
120
110
100
90
0.1
0.01
0.001
0.0001
0.00001
0.000001
80
70
1k
10k
100k
1M
1
10
100
1k
10k
100k
VCM Slew Rate (V/sec)
Frequency (Hz)
Figure 4. INA282-Q1 Common-Mode Slew Rate Induced
Offset
Figure 3. INA284-Q1 Common-Mode Rejection Ratio (RTI)
1k
0.06
VSENSE = -50mV to +50mV
0.04
0.02
100
10
1
0
V+ = 18V
-0.02
V+ = 3.5V
-0.04
0.1
-0.06
10
100
1k
10k
100k
1M
0
3
6
9
12
15
18
Frequency (Hz)
VOUT (V)
Figure 5. INA286-Q1 Output Impedance vs Frequency
Figure 6. INA282-Q1 Typical Nonlinearity vs Output Voltage
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
900
850
800
750
700
650
600
550
500
450
400
30
20
V+ = 5V
V+ = 2.7V
10
V+ = 18V
V+ = 5V
V+ = 18V
0
-10
-20
-30
-40
V+ = 2.7V
-20 -10
0
10
20
30
40
50
60
70
80
-20
0
20
40
60
80
Common-Mode Voltage (V)
Common-Mode Voltage (V)
Figure 7. INA283-Q1 +IN BIAS Current vs Common-Mode
Voltage
Figure 8. INA283-Q1 Quiescent Current vs Common-Mode
Voltage
900
800
700
600
500
400
300
200
100
0
170
160
V+ = 12V
150
140
130
120
V+ = 5V
110
100
90
80
-75 -50 -25
0
25
50
75
100 125 150
2
4
6
8
10
12
14
16
18
Temperature (°C)
Supply Voltage (V)
Figure 10. Common-Mode Rejection Ratio vs Temperature
Figure 9. Quiescent Current vs Supply Voltage
980
880
780
680
580
480
380
280
180
80
1.0
0.8
0.6
V+ = 18V
V+ = 5V
0.4
V+ = 5V
0.2
0
-0.2
V+ = 12V
-0.4
V+ = 2.7V
-0.6
-0.8
-1.0
-75 -50 -25
0
25
50
75
100 125 150
-75 -50 -25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 11. Quiescent Current vs Temperature
Figure 12. Deviation in Gain vs Temperature
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SBOS554B –MARCH 2012–REVISED DECEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
0
-5
-10
V+ = 2.7V
-15
-20
V+ = 5V
-25
V+ = 18V
-30
-35
VCM = 0V
-40
Time (1s/div)
-75 -50 -25
0
25
50
75
100 125 150
Temperature (°C)
Figure 14. INA282-Q1 0.1-Hz to 10-Hz Voltage Noise, RTI
Figure 13. +IN BIAS Current vs Temperature
V+
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.12
0.11
0.10
0.09
0.08
0.07
0.06
18V
5V
2.7V
(V+) – 2
(V+) – 4
(V+) – 6
(V+) – 8
GND + 8
GND + 6
GND + 4
GND + 2
GND
0
1
2
3
4
5
6
7
8
9
10
100
1k
10k
100k
Frequency (Hz)
IOUT (mA)
Figure 16. INA284-Q1 Output Voltage Swing vs Output
Current
Figure 15. INA282-Q1 Voltage Noise vs Frequency
800
700
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
+25°C
+85°C
+125°C
+125°C
-40°C
2.7V Swing
5V Swing
18V Swing
+85°C
2.7V Swing
5V Swing
+25°C
0.5
-40°C
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
IOUT, Sourcing (mA)
0
1.0
1.5
2.0
2.5
IOUT, Sinking (mA)
Figure 18. INA283-Q1 Swing to Ground vs Output Current
Figure 17. INA283-Q1 Swing to Rail vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
VREF = GND, VSENSE = 50mV, RLOAD = 10kW, CLOAD = 10pF
VOUT
CLOAD = 10pF
VREF = GND
VOUT
VSENSE = 50mV
RLOAD = 10kW
V+
V+
250ms/div
25ms/div
Figure 20. Start-Up Transient Response
Figure 19. Start-Up Transient Response
VOUT
VOUT
VCM
VCM
2.5ms/div
2.5ms/div
Figure 21. 12-V Common-Mode Step Response
Figure 22. 12-V Common-Mode Step Response
VOUT
VOUT
VCM
VCM
2.5ms/div
2.5ms/div
Figure 23. 12-V Common-Mode Step Response
Figure 24. 12-V Common-Mode Step Response
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
VOUT
VCM
VOUT
VCM
5ms/div
5ms/div
Figure 25. 50-V Common-Mode Step Response
Figure 26. 50-V Common-Mode Step Response
10ms/div
10ms/div
Figure 27. 100-mV Step Response
Figure 28. 500-mV Step Response
25ms/div
25ms/div
Figure 29. 4-V Step Response
Figure 30. 17-V Step Response
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V+IN = 12 V, VREF1 = VREF2 = 2.048 V referenced to GND, and VSENSE = V+IN – V–IN, unless otherwise
noted.
Input Drive (1V to 0V)
VOUT (5V to midsupply)
25ms/div
Figure 31. Input Overload
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7 Detailed Description
7.1 Overview
The INA28x-Q1 family of voltage output current-sensing amplifiers are specifically designed to accurately
measure voltages developed across current-sensing resistors on common-mode voltages that far exceed the
supply voltage powering the devices. This family features a common-mode range that extends 14 V less than the
negative supply rail, as well as up to 80 V, allowing for either low-side or high-side current sensing while the
device is powered from supply voltages as low as 2.7 V.
The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as 70
µV with a maximum temperature contribution of 1.5 µV/°C over the full temperature range of –40°C to 125°C.
7.2 Functional Block Diagram
V+
œIN
œ
œ
OUT
+
+
REF2
+IN
REF1
GND
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7.3 Feature Description
7.3.1 Selecting RS
The zero-drift offset performance of the INA28x-Q1 family offers several benefits. Most often, the primary
advantage of the low offset characteristic enables lower full-scale drops across the shunt. For example, nonzero-
drift, current-shunt monitors typically require a full-scale range of 100 mV. The INA28x-Q1 family gives equivalent
accuracy at a full-scale range on the order of 10 mV. This accuracy reduces shunt dissipation by an order of
magnitude, with many additional benefits. Alternatively, applications that must measure current over a wide
dynamic range can take advantage of the low offset on the low end of the measurement. Most often, these
applications can use the lower gains of the INA282-Q1, INA286-Q1, or INA283-Q1 to accommodate larger shunt
drops on the upper end of the scale. For instance, an INA282-Q1 operating on a 3.3-V supply can easily handle
a full-scale shunt drop of 55 mV, with only 70 μV of offset.
7.3.2 Effective Bandwidth
The extremely high DC CMRR of the INA28x-Q1 results from the switched capacitor input structure. Because of
this architecture, the INA28x-Q1 exhibits discrete time system behaviors as illustrated in the gain versus
frequency graph of Figure 3 and the step response curves of Figure 21 through Figure 28. The response to a
step input depends somewhat on the phase of the internal INA28x-Q1 clock when the input step occurs. It is
possible to overload the input amplifier with a rapid change in input common-mode voltage (see Figure 4). Errors
as a result of common-mode voltage steps and/or overload situations typically disappear within 15 μs after the
disturbance is removed.
7.3.3 Transient Protection
The –14-V to 80-V common-mode range of the INA28x-Q1 is ideal for withstanding automotive fault conditions
that range from 12-V battery reversal up to 80-V transients; no additional protective components are needed up
to those levels. In the event that the INA28x-Q1 is exposed to transients on the inputs in excess of its ratings,
then external transient absorption with semiconductor transient absorbers (Zener or Transzorbs) will be
necessary. Use of MOVs or VDRs is not recommended except when they are used in addition to a
semiconductor transient absorber. Select the transient absorber such that it cannot allow the INA28x-Q1 to be
exposed to transients greater than 80 V (that is, allow for transient absorber tolerance, as well as additional
voltage as a result of transient absorber dynamic impedance). Despite the use of internal zener-type electrostatic
discharge (ESD) protection, the INA28x-Q1 does not lend itself to using external resistors in series with the
inputs without degrading gain accuracy.
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7.4 Device Functional Modes
7.4.1 Reference Pin Connection Options
Figure 32 illustrates a test circuit for reference divider accuracy. The output of the INA28x-Q1 can be connected
for unidirectional or bidirectional operation. Neither the REF1 pin nor the REF2 pin may be connected to any
voltage source lower than GND or higher than V+, and that the effective reference voltage (REF1 + REF2)/2
must be 9 V or less. This parameter means that the V+ reference output connection shown in Figure 34 is not
allowed for V+ greater than 9 V. However, the split-supply reference connection shown in Figure 36 is allowed for
all values of V+ up to 18 V.
V+
V+
+IN
œIN
See Note (1)
œ
OUT
REF2
REF1
Input Stage
+
GND
(1) Reference divider accuracy is determined by measuring the output with the reference voltage applied to alternate
reference resistors, and calculating a result such that the amplifier offset is cancelled in the final measurement.
Figure 32. Test Circuit for Reference Divider Accuracy
7.4.1.1 Unidirectional Operation
Unidirectional operation allows the INA28x-Q1 to measure currents through a resistive shunt in one direction. In
the case of unidirectional operation, the output could be set at the negative rail (near ground, and the most
common connection) or at the positive rail (near V+) when the differential input is 0V. The output moves to the
opposite rail when a correct polarity differential input voltage is applied.
The required polarity of the differential input depends on the output voltage setting. If the output is set at the
positive rail, the input polarity must be negative to move the output down. If the output is set at ground, the
polarity is positive to move the output up.
The following sections describe how to configure the output for unidirectional operation.
7.4.1.1.1 Ground Referenced Output
When using the INA28x-Q1 in this mode, both reference inputs are connected to ground; this configuration takes
the output to the negative rail when there is 0V differential at the input (as Figure 33 shows).
V+
V+
+IN
œIN
œ
OUT
REF2
REF1
Input Stage
+
GND
Figure 33. Ground Referenced Output
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Device Functional Modes (continued)
7.4.1.1.2 V+ Referenced Output
This mode is set when both reference pins are connected to the positive supply. It is typically used when a
diagnostic scheme requires detection of the amplifier and the wiring before power is applied to the load (as
shown in Figure 34).
V+
+IN
œIN
V+
œ
OUT
REF2
REF1
Input Stage
+
GND
Figure 34. V+ Referenced Output
7.4.1.2 Bidirectional Operation
Bidirectional operation allows the INA28x-Q1 to measure currents through a resistive shunt in two directions. In
this case, the output can be set anywhere within the limits of what the reference inputs allow (that is, from 0 V to
9 V, but never to exceed the supply voltage). Typically, it is set at half-scale for equal range in both directions. In
some cases, however, it is set at a voltage other than half-scale when the bidirectional current is nonsymmetrical.
The quiescent output voltage is set by applying voltage(s) to the reference inputs. REF1 and REF2 are
connected to internal resistors that connect to an internal offset node. There is no operational difference between
the pins.
7.4.1.2.1 External Reference Output
Connecting both pins together and to a reference produces an output at the reference voltage when there is no
differential input; this configuration is illustrated in Figure 35. The output moves down from the reference voltage
when the input is negative relative to the –IN pin and up when the input is positive relative to the –IN pin. This
technique is the most accurate way to bias the output to a precise voltage.
V+
+IN
œIN
V+
œ
OUT
REF2
REF1
Input Stage
+
REF3020
2.048-V
Reference
GND
Figure 35. External Reference Output
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Device Functional Modes (continued)
7.4.1.2.2 Splitting the Supply
By connecting one reference pin to V+ and the other to the ground pin, the output is set at half of the supply
when there is no differential input, as shown in Figure 36. This method creates a midscale offset that is
ratiometric to the supply voltage; thus, if the supply increases or decreases, the output remains at half the
supply.
V+
+IN
œIN
V+
œ
OUT
REF2
REF1
Input Stage
Output
+
GND
Figure 36. Split-Supply Output
7.4.1.2.3 Splitting an External Reference
In this case, an external reference is divided by 2 with an accuracy of approximately 0.5% by connecting one
REF pin to ground and the other REF pin to the reference (as Figure 37 illustrates).
V+
+IN
œIN
V+
œ
OUT
REF2
REF1
Input Stage
+
REF02
5-V
Reference
GND
Figure 37. Split Reference Output
7.4.2 Shutdown
While the INA28x-Q1 family does not provide a shutdown pin, the quiescent current of 600 μA enables the
device to be powered from the output of a logic gate. Take the gate low to shut down the INA28x-Q1 family
devices.
7.4.3 Extended Negative Common-Mode Range
Using a negative power supply can extend the common-mode range 14 V more negative than the supply used.
For instance, a –10 V supply allows up to –24-V negative common-mode. Remember to keep the total voltage
between the GND pin and V+ pin to less than 18 V. The positive common-mode decreases by the same amount.
The reference input simplifies this type of operation because the output quiescent bias point is always based on
the reference connections. Figure 38 shows a circuit configuration for common-mode ranges from –24 V to 70 V.
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Device Functional Modes (continued)
V+ = 5 V
V+
Bus Supply
Load
œ24 V to +70 V
+IN
œIN
œ
OUT
REF2
REF1
Input Stage
Output
+
See Note (1)
GND
Connect to œ10 V
(1) Connect the REF pins as desired; however, they cannot exceed 9 V greater than the GND pin voltage.
Figure 38. Circuit Configuration for Common-Mode Ranges from –24 V to 70 V
7.4.4 Calculating Total Error
The electrical specifications for the INA28x-Q1 family of devices include the typical individual errors terms such
as gain error, offset error, and nonlinearity error. Total error including all of these individual error components is
not specified in the Electrical Characteristics table. To accurately calculate the expected error of the device, the
operating conditions of the device must first be known. Some current shunt monitors specify a total error in the
product data sheet. However, this total error term is accurate under only one particular set of operating
conditions. Specifying the total error at this one point has little practical value because any deviation from these
specific operating conditions no longer yields the same total error value. This section discusses the individual
error sources, with information on how to apply them to calculate the total error value for the device under any
normal operating conditions.
The typical error sources that have the largest impact on the total error of the device are input offset voltage,
common-mode rejection ratio, gain error, and nonlinearity error. For the INA28x-Q1, an additional error source
referred to as reference voltage rejection ratio is also included in the total error value.
The nonlinearity error of the INA28x-Q1 is relatively low compared to the gain error specification. This low error
results in a gain error that can be expected to be relatively constant throughout the linear input range of the
device. While the gain error remains constant across the linear input range of the device, the error associated
with the input offset voltage does not. As the differential input voltage developed across a shunt resistor at the
input of the INA28x-Q1 decreases, the inherent input offset voltage of the device becomes a larger percentage of
the measured input signal resulting in an increase in error in the measurement. This varying error is present
among all current shunt monitors, given the input offset voltage ratio to the voltage being sensed by the device.
The relatively low input offset voltages present in the INA28x-Q1 devices limit the amount of contribution the
offset voltage has on the total error term.
The term reference voltage rejection ratio refers to the amount of error induced by applying a reference voltage
to the INA28x-Q1 device that deviates from the inherent bias voltage present at the output of the first stage of the
device. The output of the switched-capacitor network and first-stage amplifier has an inherent bias voltage of
approximately 2.048 V. Applying a reference voltage of 2.048 V to the INA28x-Q1 reference pins results in no
additional error term contribution. Applying a voltage to the reference pins that differs from 2.048 V creates a
voltage potential in the internal difference amplifier, resulting in additional current flowing through the resistor
network. As a result of resistor tolerances, this additional current flow causes additional error at the output
because of resistor mismatches. Additionally, as a result of resistor tolerances, this additional current flow causes
additional error at the output based on the common-mode rejection ratio of the output stage amplifier. This error
term is referred back to the input of the device as additional input offset voltage. Increasing the difference
between the 2.048-V internal bias and the external reference voltage results in a higher input offset voltage. Also,
as the error at the output is referred back to the input, there is a larger impact on the input-referred offset, VOS
,
for the lower-gain versions of the device.
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Device Functional Modes (continued)
Two examples are provided that detail how different operating conditions can affect the total error calculations.
Typical and maximum calculations are shown as well, to provide the user more information on how much error
variance is present from device to device.
7.4.4.1 Example 1 INA282-Q1
Table 1. V+ = 5 V; VCM = 12 V; VREF1 = VREF2 = 2.048 V; VSENSE = 10 mV
TERM
SYMBOL
EQUATION
TYPICAL VALUE
MAXIMUM VALUE
Initial input offset
voltage
VOS
—
20 μV
70 μV
Added input offset
voltage because of
common-mode
voltage
1
CMRR_dB
´ (VCM - 12V)
(
VOS_CM
0 μV
0 μV
(
20
10
RVRR ì 2.048 V œ V
Added input offset
voltage because of
reference voltage
VOS_REF
VOS_Total
Error_VOS
0 μV
20 μV
0.20%
0 μV
70 μV
0.70%
REF
Total input offset
voltage
2
(VOS)2 + (VOS_CM)2 + (VOS_REF
)
VOS_Total
Error from input offset
voltage
´ 100
VSENSE
Gain error
Error_Gain
Error_Lin
—
—
0.40%
0.01%
1.40%
0.01%
Nonlinearity error
(Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2
Total error
—
0.45%
1.56%
7.4.4.2 Example 2 INA286-Q1
Table 2. V+ = 5 V; VCM = 24 V; VREF1 = VREF2 = 0 V; VSENSE = 10 mV
TERM
SYMBOL
EQUATION
TYPICAL VALUE
MAXIMUM VALUE
Initial input offset
voltage
VOS
—
20 μV
70 μV
Added input offset
voltage because of
common-mode
voltage
1
CMRR_dB
´ (VCM - 12V)
(
VOS_CM
1.2 μV
12 μV
(
20
10
RVRR ì 2.048 V œ V
Added input offset
voltage because of
reference voltage
VOS_REF
VOS_Total
Error_VOS
34.8 μV
40.2 μV
0.40%
92.2 μV
116.4 μV
1.16%
REF
Total input offset
voltage
2
(VOS)2 + (VOS_CM)2 + (VOS_REF
)
VOS_Total
Error from input offset
voltage
´ 100
VSENSE
Gain error
Error_Gain
Error_Lin
—
—
0.40%
0.01%
1.40%
0.01%
Nonlinearity error
(Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2
Total error
—
0.57%
1.82%
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA28x-Q1 family of devices measure the voltage developed across a current-sensing resistor when current
passes through it. The ability to drive the reference pins to adjust the functionality of the output signal is shown in
multiple configurations.
8.1.1 Basic Connections
Figure 39 shows the basic connection of an INA28x-Q1 family device. Connect the input pins, +IN and –IN, as
close as possible to the shunt resistor to minimize any resistance in series with the shunt resistance.
Device Supply
2.7 V to 18 V
CBYPASS
0.1 ꢀF
Bus Supply
Load
œ14 V to +80 V
V+
+IN
œIN
œ
OUT
REF2
REF1
Input Stage
Output
+
GND
Figure 39. Basic Connections
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
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8.2 Typical Applications
8.2.1 Current Summing
The outputs of multiple INA28x-Q1 family devices are easily summed by connecting the output of one INA28x-Q1
family device to the reference input of a second INA28x-Q1 family device. The circuit configuration shown in
Figure 39 is an easy way to achieve current summing.
First Circuit
Second Circuit
+IN
œIN
+IN
œIN
Input Stage
Input Stage
+
œ
+
œ
OUT
OUT
Output
Output
Summed
Output
VREF
V+
V+
GND
GND
V+
V+
NOTE: The voltage applied to the reference inputs must not exceed 9 V.
Figure 40. Summing the Outputs of Multiple INA28x-Q1 Family Devices
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Typical Applications (continued)
8.2.1.1 Design Requirements
In order to sum multiple load currents, multiple INA28x-Q1 devices must be connected. Figure 40 shows
summing for two devices. Summing beyond two devices is possible by repeating this connection. The reference
input of the first INA28x-Q1 family device sets the output quiescent level for all the devices in the string.
8.2.1.2 Detailed Design Procedures
Connect the output of one INA28x-Q1 family device to the reference input of the next INA28x-Q1 family device in
the chain. Use the reference input of the first circuit to set the reference of the final summed output. The currents
sensed at each circuit in the chain are summed at the output of the last device in the chain.
8.2.1.3 Application Curve
Figure 41 shows an example output response of a summing configuration. The reference pins of the first circuit
are connected to ground, and sine waves at different frequencies are applied to the two circuits to produce a
summed output as shown. The sine wave voltage input for the first circuit is offset so that the whole wave is
above GND.
Output
Inputs
Time (4 ms/div)
VREF = 0 V
Figure 41. Current Summing Application Output Response
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Typical Applications (continued)
8.2.2 Current Differencing
Occasionally, the need arises to confirm that the current into a load is identical to the current out of a load,
usually as part of diagnostic testing or fault detection. This situation requires precision current differencing, which
is the same as summing except that the two amplifiers have the inputs connected opposite of each other.
First Circuit
Second Circuit
Bus Supply
Load
+IN
œIN
+IN
œIN
Input Stage
Input Stage
+
œ
+
œ
OUT
OUT
Output
Output
Difference
Output
VREF
V+
V+
GND
GND
V+
V+
NOTE: The voltage applied to the reference inputs must not exceed 9 V.
Figure 42. Current Differencing Using an INA28x-Q1 Device
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Typical Applications (continued)
8.2.2.1 Design Requirements
For current differencing, connect two INA28x-Q1 devices, and connect the inputs opposite to each other, as
shown in Figure 42. The reference input of the first INA28x-Q1 family device sets the output quiescent level for
all the devices in the string.
8.2.2.2 Detailed Design Procedure
Connect the output of one INA28x-Q1 family device to the reference input of the second INA28x-Q1 family
device. The reference input of the first circuit sets the reference at the output. This circuit example is identical to
the current summing example, except that the two shunt inputs are reversed in polarity. Under normal operating
conditions, the final output is very close to the reference value and proportional to any current difference. This
current differencing circuit is useful in detecting when current into and out of a load do not match.
8.2.2.3 Application Curves
Figure 43 shows an example output response of a difference configuration. The reference pins of the first circuit
are connected to a reference voltage of 2.048 V. The inputs to each circuit is a 100-Hz sine wave, 180° out of
phase with each other, resulting in a zero output as shown. The sine wave input to the first circuit is offset so that
the input wave is completely above GND.
Output
Inputs
Time (4 ms/div)
VREF = 2.048 V
Figure 43. Current Differencing Application Output Response
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9 Power Supply Recommendations
The INA28x-Q1 can make accurate measurements well outside of its own power-supply voltage, V+, because its
inputs (+IN and –IN) may operate anywhere from –14 V to 80 V independent of V+. For example, the V+ power
supply can be 5 V while the common-mode voltage being monitored by the shunt may be as high as 80 V. Of
course, the output voltage range of the INA28x-Q1 is constrained by the supply voltage that powers it on V+.
When the power to the INA28x-Q1 is off (that is, no voltage is supplied to the V+ pin), the input pins (+IN and
–IN) are high impedance with respect to ground and typically leak less than ±1 μA over the full common-mode
range of –14 V to 80 V.
10 Layout
10.1 Layout Guidelines
Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique
makes sure that only the current-sensing resistor impedance is detected between the input pins. Poor routing of
the current-sensing resistor commonly results in additional resistance present between the input pins. Given the
very low ohmic value of the current resistor, any additional high-current carrying impedance causes significant
measurement errors.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. TI recommends a
bypass capacitor with a value of 0.1 uF. Add additional decoupling capacitance to compensate for noisy or high-
impedance power supplies.
10.2 Layout Example
œIN
+IN
REF1
V+
GND
REF2
NC
Supply Voltage
OUT
Output Signal Trace
VIA to Power Plane
VIA to Ground Plane
Supply Bypass
Capacitor
Figure 44. Layout Example
Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links: INA282-Q1 INA283-Q1 INA284-Q1 INA285-Q1 INA286-Q1
INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1
SBOS554B –MARCH 2012–REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
INA282-Q1
INA283-Q1
INA284-Q1
INA285-Q1
INA286-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: INA282-Q1 INA283-Q1 INA284-Q1 INA285-Q1 INA286-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2015
PACKAGING INFORMATION
Orderable Device
INA282AQDGKRQ1
INA282AQDRQ1
INA283AQDGKRQ1
INA283AQDRQ1
INA284AQDGKRQ1
INA284AQDRQ1
INA285AQDGKRQ1
INA285AQDRQ1
INA286AQDGKRQ1
INA286AQDRQ1
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
PREVIEW
VSSOP
SOIC
DGK
8
8
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
11GF
ACTIVE
PREVIEW
ACTIVE
D
DGK
D
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
282Q1
11FF
VSSOP
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAU
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
283Q1
11HF
284Q1
11IF
PREVIEW
ACTIVE
VSSOP
SOIC
DGK
D
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAU
Green (RoHS
& no Sb/Br)
PREVIEW
ACTIVE
VSSOP
SOIC
DGK
D
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAU
Green (RoHS
& no Sb/Br)
285Q1
11JF
PREVIEW
ACTIVE
VSSOP
SOIC
DGK
D
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAU
Green (RoHS
& no Sb/Br)
286Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2015
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA282-Q1, INA283-Q1, INA284-Q1, INA285-Q1, INA286-Q1 :
Catalog: INA282, INA283, INA284, INA285, INA286
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA282AQDRQ1
INA283AQDRQ1
INA284AQDRQ1
INA285AQDRQ1
INA286AQDRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
8
8
8
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA282AQDRQ1
INA283AQDRQ1
INA284AQDRQ1
INA285AQDRQ1
INA286AQDRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
8
8
8
8
2500
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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