INA1620RTWT [TI]
具有集成薄膜电阻器和 EMI 滤波功能的高保真音频运算放大器 | RTW | 24 | -40 to 125;
| 型号： | INA1620RTWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成薄膜电阻器和 EMI 滤波功能的高保真音频运算放大器 | RTW | 24 | -40 to 125 放大器 薄膜电阻器 运算放大器 |
| 文件： | 总37页 (文件大小：2627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA1620
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
具有集成薄膜电阻器的 INA1620 高保真音频运算放大器和 EMI 滤波器
1 特性
3 说明
1
•
匹配精度为 0.004%（典型值）的高质量
薄膜电阻器
INA1620 将 4 个高精度匹配薄膜电阻器对和片上 EMI
滤波与一个低失真、高输出电流、双路音频运算放大器
集成在一起。该放大器在 1kHz 频率下具有
•
•
•
集成 EMI 滤波器
超低噪声：1kHz 时为 2.8nV/√Hz
2.8nV/√Hz 的极低噪声密度和 –119.2dB 的超低
THD+N，能够以 150mW 的输出功率驱动一个 32Ω 的
负载。集成式薄膜电阻器的匹配精度在 0.004% 以内，
可用于创建大量具有极高性能的音频电路。
超低总谐波失真 + 噪声：
–119dB THD+N（以 142mW/通道的功率驱动
32Ω/通道的负载）
•
宽增益带宽产品：
32MHz (G = +1000)
INA1620 具有 ±2V 至 ±18V 的极宽电源电压范围，每
通道电源电流仅为 2.6mA。INA1620 还具有关断模
式，允许放大器从正常运行状态切换至待机状态（待机
电流通常小于 5µA）。关断模式经专门设计，可消除
进入或退出关断模式时产生的“咔嗒”和“噗噗”噪声。
•
•
•
•
•
高压摆率：10V/μs
高容性负载驱动能力：> 600pF
高开环增益：136dB（600Ω 负载）
低静态电流：每通道 2.6mA
具有更低的“噗噗”和“咔嗒”噪声的低功耗关断模式：
每通道 5μA
INA1620 具有独特的内部布局，可将串扰降到最低，
即使在过驱动或过载时也不受通道间相互作用的影响。
此器件的额定工作温度范围为 –40°C 至 +125°C。
•
•
•
短路保护
宽电源电压范围：±2V 至 ±18V
采用小型 24 引脚 WQFN 封装
器件信息(1)
器件型号
INA1620
封装
WQFN (24)
封装尺寸（标称值）
2 应用
4.00mm x 4.00mm
•
•
•
•
高保真 (HiFi) 耳机驱动器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
专业音频设备
模数混合控制台
音频测试和测量
INA1620 简化内部原理图
快速傅立叶变换 (FFT)：1kHz、32Ω 负载、50mW
0
œ20
œ40
œ60
œ80
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
R1C
VCC
GND
R2C
OUT A
EN
EMI Filtering
œ100
-133.6 dBc (Second Harmonic)
œ120
œ140
œ160
œ180
4mm X 4mm QFN
Package
NC
NC
VEE
R4C
OUT B
R3C
0
5k
10k
15k
20k
EMI Filtering
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
Frequency (Hz)
C005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS859
INA1620
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: ........................................ 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 18
8
9
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 24
8.3 Other Application Examples.................................... 27
Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 29
11.1 器件支持................................................................ 29
11.2 文档支持................................................................ 29
11.3 接收文档更新通知 ................................................. 29
11.4 社区资源................................................................ 29
11.5 商标....................................................................... 30
11.6 静电放电警告......................................................... 30
11.7 术语表 ................................................................... 30
12 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2018) to Revision A
Page
•
首次发布生产数据数据表 ....................................................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
INA1620
www.ti.com.cn
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
5 Pin Configuration and Functions
RTW Package
24-Pin QFN
Top View
23
22
21
20
19
24
1
2
3
18
17
16
R1C
VCC
GND
R2C
OUT A
EN
Thermal
Pad
4
5
6
15
14
13
NC
NC
VEE
R4C
OUT B
R3C
7
8
9
10
11
12
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
EN
NO.
3
—
I
Connect to ground
16
22
21
9
Shutdown (logic low), enable (logic high)
Noninverting input, channel A
Inverting input, channel A
IN+ A
IN- A
IN+ B
IN- B
NC
I
I
I
Noninverting input, channel B
Inverting input, channel B
10
4
I
—
—
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
No internal connection
NC
15
17
14
24
23
1
No internal connection
OUT A
OUT B
R1A
Output, channel A
Output, channel B
Resistor pair 1, end point A
Resistor pair 1, center point
Resistor pair 1, end point C
Resistor pair 2, end point A
Resistor pair 2, center point
Resistor pair 2, end point C
Resistor pair 3, end point A
Resistor pair 3, center point
Resistor pair 3, end point C
Resistor pair 4, end point A
Resistor pair 4, center point
Resistor pair 4, end point C
Positive (highest) power supply
Negative (lowest) power supply
Exposed thermal die pad on underside; connect thermal die pad to V–.
R1B
R1C
R2A
19
20
18
12
11
13
7
R2B
R2C
R3A
R3B
R3C
R4A
R4B
8
R4C
V+
6
2
V–
5
Thermal pad
Copyright © 2018, Texas Instruments Incorporated
3
INA1620
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
Supply voltage, VS = (V+) – (V–)
Voltage
Input voltage (signal inputs, enable, ground)
Input differential voltage
Input current (all pins except power-supply and resistor pins)
Through each resistor
(V–) – 0.5
(V+) + 0.5
±0.5
V
±10
mA
°C
Current
30
Output short-circuit(2)
Continuous
125
Operating, TA
–55
–65
Temperature
Junction, TJ
150
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
NOM
MAX
36
UNIT
Single-supply
Dual-supply
Supply voltage, (V+) – (V–)
V
±2
±18
15
Current per resistor
mA
°C
Specified temperature
–40
125
6.4 Thermal Information
INA1620
THERMAL METRIC(1)
RTW (QFN)
24 PINS
33.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26.5
13.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
13.1
RθJC(bot)
3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2018, Texas Instruments Incorporated
INA1620
www.ti.com.cn
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
6.5 Electrical Characteristics:
at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.000025%
–132
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 2 kΩ,
80-kHz measurement bandwidth
dB
dB
dB
dB
dB
0.000025%
–132
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 600 Ω,
80-kHz measurement bandwidth
0.000071%
–123
G = 1, f = 1 kHz, POUT = 10 mW, RL = 128 Ω,
80-kHz measurement bandwidth
Total harmonic distortion +
noise
THD+N
0.000158%
–116
G = 1, f = 1 kHz, POUT = 10 mW, RL = 32 Ω,
80-kHz measurement bandwidth
0.000224%
–113
G = 1, f = 1 kHz, POUT = 10 mW, RL = 16 Ω,
80-kHz measurement bandwidth
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz),
0.000018%
G = 1, VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement
bandwidth
–135
dB
dB
IMD
Intermodulation distortion
0.000032%
–130
CCIF twin-tone (19 kHz and 20 kHz), G = 1,
VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth
FREQUENCY RESPONSE
G = 1000
G = 1
32
8
GBW
SR
Gain-bandwidth product
MHz
Slew rate
G = –1
10
V/μs
MHz
ns
Full-power bandwidth(1)
Overload recovery time
Channel separation (dual)
EMI filter corner frequency
VO = 1 VP
G = –10
f = 1 kHz
1.6
300
140
500
dB
MHz
NOISE
Input voltage noise
f = 20 Hz to 20 kHz
f = 10 Hz
2.1
6.5
3.5
2.8
1.6
0.8
μVPP
en
Input voltage noise density(2)
f = 100 Hz
f = 1 kHz
nV/√Hz
f = 10 Hz
In
Input current noise density
pA/√Hz
f = 1 kHz
OFFSET VOLTAGE
±0.1
±1
±1.2
±2.5
3
VOS
Input offset voltage
mV
TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT Input offset voltage drift(2)
-0.5
0.1
μV/°C
μV/V
PSRR
Power-supply rejection ratio
INPUT BIAS CURRENT
1.2
2
2.2
IB
Input bias current
Input offset current
μA
TA = –40°C to 125°C(2)
TA = –40°C to 125°C(2)
±10
±100
±140
IOS
nA
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
(V–) + 1.5
108
(V+) – 1
V
(V–) + 1.5 V ≤ VCM ≤ (V+) – 1 V, TA = –40°C to 125°C, VS
= ±18 V
CMRR
127
dB
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
Copyright © 2018, Texas Instruments Incorporated
5
INA1620
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
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Electrical Characteristics: (continued)
at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT IMPEDANCE
Differential
60k || 0.8
Ω || pF
Ω || pF
Common-mode
500M || 0.9
OPEN-LOOP GAIN
(V–) + 2 V ≤ VO ≤ (V+) – 2 V, RL = 32 Ω, VS = ± 5 V
114
120
120
136
AOL
Open-loop voltage gain
dB
(V–) + 1.5 V ≤ VO ≤ (V+) – 1.5 V, RL = 600 Ω, VS = ± 18 V
OUTPUT
No load
Positive rail
800
1000
800
RL = 600 Ω
VO
Voltage output swing from rail
mV
No load
Negative rail
RL = 600 Ω
1000
IOUT
ZO
Output current
图 38
图 40
mA
Ω
Open-loop output impedance
Short-circuit current
Capacitive load drive
ISC
VS = ±18 V
+145 / –130
mA
pF
CLOAD
图 24
ENABLE PIN
0.82
0.78
VIH
Logic high threshold
V
TA = –40°C to 125°C(2)
0.95
VIL
IIH
Logic low threshold
Input current
V
TA = –40°C to 125°C(2)
VEN = 1.8 V
0.65
1.5
μA
RESISTOR PAIRS
Resistor ratio matching(3)
Resistors in same pair
TA = –40°C to 125°C(2)
0.004%
0.02%
0.023%
Resistor ratio matching
temperature coefficient
Resistors in same pair
±0.07
±0.15 ppm/°C
1.15 kΩ
Individual resistor value
0.84
1
2
Individual resistor temperature
coefficient
20 ppm/°C
POWER SUPPLY
2.6
5
3.3
mA
4.2
VEN = 2 V, IOUT = 0 A
TA = –40°C to 125°C(2)
Quiescent current
(per channel)
IQ
VEN = 0 V, IOUT = 0 A
10
μA
(3) Resistor ratio matching refers to the matching between the two 1-kΩ resistors in each resistor pair. There are four pairs on each
INA1620: RXA, RXB, RXC and RXD, where X is the terminal connection number. See Resistor Tolerance for more details.
6
版权 © 2018, Texas Instruments Incorporated
INA1620
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ZHCSHW8B –MARCH 2018–REVISED JULY 2018
6.6 Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
D027
D030
VOS (mV)
VOS Drift (mV/èC)
9818 channels
50 channels
图 1. Input Offset Voltage Histogram
图 2. Input Offset Voltage Drift Histogram
300
œ60
œ62
œ64
œ66
œ68
œ70
œ72
œ74
œ76
œ78
œ80
VCM = -16.5 V
200
100
VCM = 17 V
0
œ100
œ200
œ300
0
10
20
œ20
œ10
0
25
50
75
100 125 150
œ75 œ50 œ25
VCM (V)
Temperature (°C)
C001
C001
4 typical units
图 4. Input Offset Voltage vs Common-Mode Voltage
图 3. Input Offset Voltage vs Temperature
100
10
1
10
1
+31
-31
0.1
1
10
100
1k
10k 100k
1M
10M 100M
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
C307
C306
图 5. Input Voltage Noise Spectral Density vs Frequency
图 6. Input Current Noise Spectral Density vs Frequency
版权 © 2018, Texas Instruments Incorporated
7
INA1620
ZHCSHW8B –MARCH 2018–REVISED JULY 2018
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
1000
100
10
Source Resistor Noise Contribution
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
Time (2 s/div)
10
100
1k
10k
100k
1M
Source Resistance (ꢀ)
C017
C302
图 7. 0.1-Hz to 10-Hz Noise
图 8. Voltage Noise vs Source Resistance
18
140
225
16
120
100
80
VS = ±15V
14
12
10
8
180
135
90
60
40
6
VS = ±5V
20
4
VS = ±2V
0
2
0
œ20
45
10k
100k
1M
10M
1
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
Frequency (Hz)
C303
C005
图 9. Maximum Output Voltage vs Frequency
图 10. Open-Loop Gain and Phase vs Frequency
5.0
4.0
5.0
4.0
3.0
2.0
1.0
0.0
VS = ±2 V
VS = ±2 V
3.0
2.0
1.0
0.0
VS = ±18 V
VS = ±18 V
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
œ1.0
œ2.0
œ3.0
œ4.0
œ5.0
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
600-Ω load
图 11. Open-Loop Gain vs Temperature
2-kΩ load
图 12. Open-Loop Gain vs Temperature
8
版权 © 2018, Texas Instruments Incorporated
INA1620
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ZHCSHW8B –MARCH 2018–REVISED JULY 2018
Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
40
0.01
0.001
-80
G = +10
G = -1, 600-ꢀ Load
G = -1
G = +1
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
20
0
-100
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
0.0001
0.00001
-120
-20
-140
20k
100
1k
10k
100k
1M
10M
20
200
2k
Frequency (Hz)
Frequency (Hz)
C004
C004
C004
C004
3.5 VRMS, 80-kHz measurement bandwidth
图 13. Closed-Loop Gain vs Frequency
图 14. THD+N Ratio vs Frequency
0.1
-60
0.1
0.01
-60
G = -1, 128-ꢀ Load
G = -1, 32-ꢀ Load
G = -1, 16-ꢀ Load
G = +1, 128-ꢀ Load
G = +1, 32-ꢀ Load
G = +1, 16-ꢀ Load
0.01
-80
-80
Inverting
0.001
0.0001
-100
-120
-140
0.001
-100
-120
-140
0.0001
0.00001
Noninverting
2k-ꢀ Load
600-ꢀ Load
0.00001
20
200
2k
20k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS
)
C004
10 mW, 80-kHz measurement bandwidth
1 kHz, 80-kHz measurement bandwidth
图 15. THD+N Ratio vs Frequency
图 16. THD+N Ratio vs Output Amplitude
0.1
0.01
-60
0.1
-60
2k-ꢀ Load
32-ꢀ Load
-80
0.01
0.001
-80
Inverting
SMPTE
0.001
-100
-120
-140
-100
-120
-140
Noninverting
0.0001
0.00001
0.0001
0.00001
128-ꢀ Load
32-ꢀ Load
16-ꢀ Load
CCIF
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Amplitude (VRMS
)
Output Amplitude (VRMS
)
C004
1 kHz, 80-kHz measurement bandwidth
90-kHz measurement bandwidth
图 18. Intermodulation Distortion vs Output Amplitude
图 17. THD+N Ratio vs Output Amplitude
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
160
140
120
100
80
-80
No Load
PSRR+
32-ꢀ Load
600-ꢀ Load
PSRR-
-100
-120
-140
-160
60
40
20
0
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C004
C115
图 19. Channel Separation vs Frequency
图 20. PSRR vs Frequency (Referred to Input)
5
4
140
120
100
80
3
2
1
0
60
-1
-2
-3
-4
-5
40
20
0
0
25
50
75
100 125 150
œ75 œ50 œ25
1
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
C001
C004
图 21. PSRR vs Temperature
图 22. CMRR vs Frequency (Referred to Input)
1
0.8
0.6
0.4
0.2
0
90
80
70
60
50
40
30
20
10
0
VS = ±2 V, (Vœ) +1.5 ≤ VCM ≤ (V+) œ 1 V
G = +1
G = -1
VS = ±18 V, (Vœ) +1.5 ≤ VCM ≤ (V+) œ 1V
-0.2
-0.4
-0.6
-0.8
-1
0
200
400
600
800
1000
0
25
50
75
100 125 150
œ75 œ50 œ25
Capacitive Load (pF)
Temperature (°C)
C308
C001
图 24. Phase Margin vs Capacitive Load
图 23. CMRR vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Time (2.5 ꢀs/div)
Time (2.5 ꢀs/div)
C017
C017
G = 1, 10 mV
G = 1, 10 V
图 25. Small-Signal Step Response
图 26. Large-Signal Step Response
VOUT
VIN
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
C017
C017
G = –10
G = –10
图 27. Negative Overload Recovery
图 28. Positive Overload Recovery
1.5
1.4
1.3
1.2
1.1
1
VOUT
VIN
IB-
IB+
0.9
Time (500 ms/div)
0
25
50
75
100
125
œ50
œ25
Temperature (ºC)
C017
C304
图 29. No Phase Reversal
图 30. IB vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
5
1.5
1.4
1.3
1.2
1.1
1
4
3
2
1
0
25
50
75
100
125
œ50
-1.5
0
œ25
-20
-10
0
10
20
Temperature (ºC)
Common-Mode Voltage (V)
C305
C001
VS = ±18 V
图 31. IOS vs Temperature
图 32. IB vs Common-Mode Voltage
5
4.5
4
1.3
1.25
1.2
3.5
3
VS = ±18 V
VS = ±2 V
2.5
2
1.5
1
1.15
1.1
0.5
0
0
25
50
75
100 125 150
œ75 œ50 œ25
-1
-0.5
0
0.5
1
1.5
Temperature (°C)
Common-Mode Voltage (V)
C001
C002
VS = ±2 V
图 34. Quiescent Current vs Temperature
图 33. IB vs Common-Mode Voltage
5
4
3
2
1
0
3
2.5
2
125ºC
85ºC
1.5
1
25ºC
-40ºC
0.5
0
0.5
1
1.5
2
2
4
6
8
10
12
14
16
18
20
Enable Voltage (V)
Supply Voltage (V)
C002
C001
图 36. Quiescent Current vs Enable Voltage
图 35. Quiescent Current vs Supply Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
18
16
14
12
10
8
200
180
ISC, Source
160
140
120
6
ISC, Sink
125°C
25°C
100
4
80
60
85°C
œ40°C
2
0
0
20
40
60
80 100 120 140 160 180 200
0
25
50
75
100 125 150
œ75 œ50 œ25
IO (mA)
C001
Temperature (°C)
C001
图 38. Positive Output Voltage vs Output Current
图 37. Short-Circuit Current vs Temperature
0
-2
100
10
1
125°C
25°C
-4
85°C
-6
œ40°C
-8
-10
-12
-14
-16
-18
0
20
40
60
80 100 120 140 160 180 200
1
10
100
1k
10k 100k 1M
10M 100M
IO (mA)
C001
Frequency (Hz)
C001
图 39. Negative Output Voltage vs Output Current
图 40. Open-Loop Output Impedance vs Frequency
25
22.5
20
20
18
16
14
12
10
8
17.5
15
12.5
10
7.5
5
6
4
2.5
0
2
0
D028
D026
Resistance (W)
Resistor Ratio Matching Error (%)
19635 resistors
19639 resistor pairs
图 41. Resistor Absolute Value Histogram
图 42. Resistor Pair Matching Histogram
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
D029
Resistor Ratio Matching Drift (ppm/èC)
64 resistor pairs
图 43. Resistor Pair Matching Drift Histogram
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7 Detailed Description
7.1 Overview
The INA1620 integrates a dual, bipolar-input, audio operational amplifier with four high-precision thin-film resistor
pairs on the same die. The internal amplifiers and resistor pairs are pinned out to allow for many circuit
configurations.
The internal amplifiers of the INA1620 use a unique topology to deliver high output current with extremely low
distortion while consuming minimal supply current. A single gain-stage architecture, combining a high-gain
transconductance input stage and a unity-gain output stage, allows the INA1620 to achieve an open-loop gain of
136 dB, even with 600-Ω loads.
A separate enable circuit maintains control of the input and output stage when the amplifier is placed into its
shutdown mode and limits transients at the amplifier output when transitioning to and from this state. The enable
circuit features logic levels referenced to the amplifier ground pin. This configuration simplifies the interface
between the amplifier and the ground-referenced GPIO pins of microcontrollers. The addition of a ground pin to
the amplifier provides several additional benefits. For example, the compensation capacitor between the input
and output stages of the INA1620 is referenced to the ground pin, greatly improving PSRR.
7.2 Functional Block Diagram
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
R1C
VCC
GND
R2C
OUT A
EN
EMI Filtering
4mm X 4mm QFN
Package
NC
NC
VEE
R4C
OUT B
R3C
EMI Filtering
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
7.3 Feature Description
7.3.1 Matched Thin-Film Resistor Pairs
The INA1620 integrates four thin-film resistor pairs. Each pair is made up of two thin-film resistors with a nominal
resistance of 1 kΩ. While the absolute value of the resistor is not trimmed and can vary significantly, the two
resistors in an pair are designed to match each other extremely well. The resistors in an pair typically match to
within 0.004% of each other's value. This matching is also preserved well over temperature, with the matching
drift having a 0.2 ppm/°C maximum specification. Each node in the resistor pair is bonded out to a pad on the
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Feature Description (接下页)
INA1620 package allowing the resistor pairs to be used in multiple configurations. The nodes in the pair are
protected from damage due to electrostatic discharge (ESD) events by diodes tied to the power supplies of the
IC. For this reason, voltages beyond the power supplies cannot be applied to the resistors without forward-
biasing the ESD protection diodes. The resistor pairs should not be used if there is no power applied to the
INA1620. The configuration of the ESD protection diodes is shown in 图 44.
V+
V+
V+
1 kꢀ
1 kꢀ
RxC
RxA
V-
V-
V-
RxB
图 44. ESD Protection Diodes on Each Resistor Pair
Although the resistor pairs and amplifier core are fabricated on the same silicon substrate, they can be used in
separate circuits as long as the previously-mentioned voltage limits are observed. The functional state of the
amplifier (enabled or shutdown) does not affect the resistor pair's performance.
7.3.2 Power Dissipation
The INA1620 is capable of high output current with power-supply voltages up to ±18 V. Internal power dissipation
increases when operating at high supply voltages. The power dissipated in the op amp (POPA) is calculated using
公式 1:
VOUT
POPA = V - V
ìI
= V - V
ì
(
)
(
)
+
OUT
OUT
+
OUT
RL
(1)
In order to calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered
separately.
In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp
occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is
sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,
modify 公式 2 to include the negative supply voltage instead of the positive.
2
V
V+
≈
’
+
POPA(MAX _DC) = POPA ∆
=
÷
◊
2
4RL
«
(2)
The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurs
when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages:
2
2V
2∂ V+
≈
’
+
POPA(MAX _ AC) = POPA ∆
=
÷
◊
p2 ∂RL
p
«
(3)
The dominant pathway for the INA1620 to dissipate heat is through the package thermal pad and pins to the
PCB. Copper leadframe construction used in the INA1620 improves heat dissipation compared to conventional
materials. PCB layout greatly affects thermal performance. Connect the INA1620 package thermal pad to a
copper pour at the most negative supply potential. This copper pour can be connected to a larger copper plane
within the PCB using vias to improve power dissipation. 图 45 shows an analogous thermal circuit that can be
used for approximating the junction temperature of the INA1620. The power dissipated in the INA1620 is
represented by current source PD; the ambient temperature is represented by voltage source 25ºC; and the
junction-to-board and board-to-ambient thermal resistances are represented by resistors RθJB and RθBA
,
respectively. The board-to-ambient thermal resistance is unique to every application. The sum of RθJB and RθBA is
the junction-to-ambient thermal resistance of the system. The value for junction-to-ambient thermal resistance
reported in the Thermal Information table is determined using the JEDEC standard test PCB. The voltages in the
analogous thermal circuit at the points TJ and TPCB represent the INA1620 junction and PCB temperatures,
respectively.
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Feature Description (接下页)
TJ
,
JB
TPCB
PD
,
BA
25ºC
图 45. Approximate Thermal System Model of the INA1620 Soldered to a PCB
7.3.3 Thermal Shutdown
If the junction temperature of the INA1620 exceeds 175°C, a thermal shutdown circuit disables the amplifier in
order to protect the device from damage. The amplifier is automatically re-enabled after the junction temperature
falls below approximately 160°C. If the condition that caused excessive power dissipation has not been removed,
the amplifier oscillates between a shutdown and enabled state until the output fault is corrected.
7.3.4 EN Pin
The enable pin (EN) of the INA1620 is used to toggle the amplifier enabled and disabled states. The logic levels
defining these two states are: VEN ≤ 0.78 V (shutdown mode), and VEN ≥ 0.82 V (enabled). These threshold
levels are referenced to the device ground (GND) pin. The EN pin can be driven by a GPIO pin from the system
controller, discrete logic gates, or can be connected directly to the V+ supply. Do not leave the EN pin floating
because the amplifier is prevented from being enabled. Likewise, do not place GPIO pins used to control the EN
pin in a high-impedance state because this placement also prevents the amplifier from being enabled. A small
current flows into the enable pin when a voltage is applied. Using the simplified internal schematic shown in 图
46, use 公式 4 to estimate the enable pin current:
VEN - 0.7 V
700 kꢀ
IEN
=
(4)
As illustrated in 图 46, the EN pin is protected by diodes to the amplifier power supplies. Do not connect the EN
pin to voltages outside the limits defined in the Specifications section.
To
Amplifier
VCC
500 kꢀ
EN
VEE
VCC
200 kꢀ
GND
VEE
图 46. EN Pin Simplified Internal Schematic
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Feature Description (接下页)
7.3.5 GND Pin
The inclusion of a ground (GND) pin in the INA1620 architecture allows the internal enable circuitry to be
referenced to the system ground, eliminating the need for level shifting circuitry in many applications. The internal
amplifier compensation capacitors are also referenced to this pin, greatly increasing the ac PSRR. For highest
performance, connect the GND pin to a low-impedance reference point with minimal noise present. As shown in
图 46, the GND pin is protected by ESD diodes to the amplifier power supplies. Do not connect the GND pin to
voltages outside the limits defined in the Specifications section.
7.3.6 Input Protection
The amplifier input pins of the INA1620 are protected from excessive differential voltage with back-to-back
diodes, as 图 47 shows. In most circuit applications, the input protection circuitry has no consequence. However,
in low-gain or G = +1 circuits, fast-ramping input signals can forward bias these diodes because the output of the
amplifier cannot respond quickly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not
inherently limited, use an input series resistor (RI) or a feedback resistor (RF) to limit the signal input current. This
input series resistor degrades the low-noise performance of the INA1620 and is examined in the Noise
Performance section. 图 47 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF
–
Device
Output
RI
+
Input
图 47. Pulsed Operation
7.4 Device Functional Modes
The INA1620 has two operating modes determined by the voltage between the EN and GND pins: a shutdown
mode (VEN ≤ 0.78 V) and an enabled mode (VEN ≥ 0.82 V). The measured datasheet performance parameters
specified in the Typical Characteristics and Specifications sections are given with the amplifier in the enabled
mode, unless otherwise noted.
7.4.1 Shutdown Mode
When the EN pin voltage is below the logic low threshold, the INA1620 enters a shutdown mode with minimal
power consumption. In this state the output transistors of the amplifier are not powered on. However, do not
consider the amplifier output to be high-impedance. Applying signals to the output of the INA1620 while the
device is in the shutdown mode can parasitically power the output stage, causing the INA1620 output to draw
current.
The INA1620 enable circuitry limits transients at the output when transitioning into or out of shutdown mode.
However, small output transients do still accompany this transition, as illustrated in 图 48 and 图 49. Note that in
both figures the time scale is 1 µs per division, indicating that the output transients are extremely brief in nature,
and therefore not likely to be audible in headphone applications.
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Device Functional Modes (接下页)
Enable (2 V/div)
Enable (2 V/div)
Output (20 mV/div)
Output (20 mV/div)
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C001
C002
图 48. INA1620 Output Voltage When EN Pin Transitions
High (32-Ω Load Connected)
图 49. INA1620 Output Voltage When EN Pin Transitions
Low (32-Ω Load Connected)
7.4.2 Output Transients During Power Up and Power Down
To minimize the possibility of output transients that might produce an audible click or pop, ramp the supply
voltages for the INA1620 symmetrically to their nominal values. Asymmetrical supply ramping can cause output
transients during power up that can be audible in headphone applications. If possible, hold the EN pin low while
the power supplies are ramping up or down. If the EN pin is not being independently controlled (for example, by
a GPIO pin), use a voltage divider to hold the enable pin voltage below the logic-high threshold until the power
supplies reach the specified minimum voltage, as shown in 图 50.
VCC
22.1 kꢀ
To enable
pin on IC
10.7 kꢀ
图 50. Voltage Divider Used to Hold Enable Low at Power-Up or Power-Down
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low noise and distortion of the INA1620 make the device useful for a variety of applications in professional
and consumer audio products. However, these same performance metrics also make the INA1620 useful for
industrial, test-and-measurement, and data-acquisition applications. The example shown here is only one
possible application where the INA1620 provides exceptional performance.
8.1.1 Noise Performance
图 51 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration
(no feedback resistor network, and therefore no additional noise contributions).
The INA1620 is shown with total circuit noise calculated. The op amp contributes both a voltage noise
component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current, and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest
noise op amp for a given application depends on the source impedance. For low source impedance, current
noise is negligible, and voltage noise generally dominates. The low voltage and current noise of the INA1620
internal op amps make the device an excellent choice for use in applications where the source impedance is less
than 10 kΩ as shown in 图 51.
1000
Source Resistor Noise Contribution
100
10
Total Noise
1
Voltage Noise Contribution
Current Noise Contribution
0.1
10
100
1k
10k
100k
1M
Source Resistance (ꢀ)
C302
图 51. Noise Performance of the INA1620 Internal Amplifiers
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Application Information (接下页)
8.1.2 Resistor Tolerance
The INA1620 integrated resistor pairs use an advanced thin film process to create resistor pairs that have
excellent matching. Each specific resistor pair is specifically designed for accurate matching between the two
resistors. 图 42 shows the distribution of resistor matching for a typical device population. The equation used to
calculate matching between resistors in a pair is shown in 公式 5.
RXA -RXB
Resistor Ratio Matching % =
ì100
(
)
Average RXA,RXB
(5)
In addition to excellent matching between resistors in each resistor pair, all resistors on a single INA1620 achieve
good matching due to inherent process matching across each device. 图 52 shows a typical distribution of the
worst-case matching across all resistors on a single INA1620. The matching was calculated using the highest
value resistance on a device matched with the lowest resistance value on the same device.
22
20
18
16
14
12
10
8
6
4
2
0
D032
Resistor Matching, Maximum to Minimum (%)
图 52. Matching Histogram, Maximum to Minimum
8.1.3 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit approximately
matching EMIRR performance.
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects, as
the amplifier does not have sufficient loop gain to correct for signals with spectral content outside its bandwidth.
Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC offsets, transient
voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy
radio signals and digital clocks and interfaces.
The EMIRR IN+ of the INA1620 amplifiers is plotted versus frequency as shown in 图 53. See also EMI Rejection
Ratio of Operational Amplifiers, available for download from www.ti.com.
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Application Information (接下页)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
100M
1G
10G
Frequency (Hz)
D033
图 53. INA1620 EMIRR IN+
表 1 lists the EMIRR IN+ values for the INA1620 at particular frequencies commonly encountered in real-world
applications. Applications listed in 表 1 may be centered on or operated near the particular frequency shown.
This information may be of special interest to designers working with these types of applications, or working in
other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical
(ISM) radio band.
表 1. INA1620 EMIRR IN+ for Frequencies of Interest
FREQUENCY
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
APPLICATION OR ALLOCATION
EMIRR IN+
18 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
33 dB
26 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
40 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
55 dB
22
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8.1.4 EMIRR +IN Test Configuration
图 54 shows the circuit configuration for testing the EMIRR IN+. An RF source connects to the op amp
noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with the
output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the
op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. A multimeter samples and measures the resulting DC offset voltage. The LPF
isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
图 54. EMIRR +IN Test Configuration
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8.2 Typical Application
The low distortion and high output-current capabilities of the INA1620 make this device an excellent choice for
headphone-amplifier applications in portable or studio applications. These applications typically employ an audio
digital-to-analog converter (DAC) and a separate headphone amplifier circuit connected to the DAC output. High-
performance audio DACs can have an output signal that is either a varying current or voltage. Voltage output
configurations require less external circuitry, and therefore have advantages in cost, power consumption, and
solution size. However, these configurations can offer slightly lower performance than current output
configurations. Differential outputs are standard on both types of DACs. Differential outputs double the output
signal levels that can be delivered on a single, low-voltage supply, and also allow for even-harmonics common to
both outputs to be cancelled by external circuitry. A simplified representation of a voltage-output audio DAC is
shown in 图 55. Two ac voltage sources (VAC) deliver the output signal to the complementary outputs through
their associated output impedances (ROUT). Both output signals have a dc component as well, represented by dc
voltage source VDC. The headphone amplifier circuit connected to the output of an audio DAC must convert the
differential output into a single-ended signal and be capable of producing signals of sufficient amplitude at the
headphones to achieve reasonable listening levels.
100 pF
ROUT
1 kꢀ
1 kꢀ
5V
VAC
œ
Headphone Output
+
VDC
VAC
-5V
ROUT
1 kꢀ
1 kꢀ
INA1620
Audio DAC
100 pF
图 55. INA1620 Used as a Headphone Amplifier for a Voltage-Output Audio DAC
8.2.1 Design Requirements
•
•
•
•
±5-V power supplies
150-mW output power (32-Ω load)
< –110-dB THD+N at maximum output (32-Ω load)
< 0.01-dB magnitude deviation (20 Hz to 20 kHz)
8.2.2 Detailed Design Procedure
图 55 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configured as a
difference amplifier that converts the differential output voltage to single-ended.
The gain of the difference amplifier in 图 55 is determined by the resistor values, and includes the output
impedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shown
in 公式 6:
R2
VOUT = V
DAC R1 + ROUT
(6)
The output voltage required for headphones depends on the headphone impedance, as well as the headphone
efficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level
(typically given at 1 mW). The headphone SPL at other power levels is calculated using 公式 7:
24
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Typical Application (接下页)
P
≈
’
IN
SPL(dB) = h +10log
∆
«
÷
◊
1 mW
where
•
•
η = efficiency
PIN = input power to the headphones
(7)
图 56 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically,
over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.
150
140
130
120
110
100
90-dB/mW
90
80
70
60
95-dB/mW
100-dB/mW
105-dB/mW
110-dB/mW
115-dB/mW
0.01
0.1
1
10
100
1000
Input Power (mW)
C001
图 56. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies
In-ear headphones can have efficiencies of 115 dB/mW or greater, and therefore have much lower power
requirements. The output power goal for this design is 150 mW — sufficient power to produce extremely loud
sound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for this
requirement because 32 Ω is a very common value in headphones for portable applications. 公式 8 shows the
voltage required for 32-Ω headphones:
VO = PìR = 150 mW ì32 ꢀ = 2.191 VRMS
(8)
Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interfering
signals. The maximum value of these capacitors is determined by the limitations on frequency response
magnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 to
form a pole, as shown in 公式 9:
1
fP =
2p(R2,R4 )(C1,C2 )
(9)
Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements using 公式 10:
f
20 kHz
fP í
í
í 416.6 kHz
2
2
1
1
≈
’
≈
’
-1
-1
∆
«
÷
∆
«
÷
◊
G
0.999
◊
where
•
G represents the gain in decimal for a –0.01-dB deviation at 20 kHz.
(10)
25
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Typical Application (接下页)
Use 公式 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimal
magnitude deviation at 20 kHz.
1
1
C1,C2 Ç
Ç
Ç 382 pF
2p(R2,R4 )FP 2p(1 kꢀ)(416.6 kHz)
(11)
For this design, 100-pF capacitors were used because they meet the design requirements for amplitude
deviation in the audio bandwidth.
8.2.3 Application Curves
图 57 shows the maximum output voltage achievable for a 32-Ω load before the onset of clipping (±5-V supplies),
indicated by a sharp increase in distortion. As more current is delivered by the output transistors of an amplifier,
additional distortion is produced. At low frequencies, this distortion is corrected by the feedback loop of the
amplifier. However, as the loop gain of the amplifier begins to decline at high frequencies, the overall distortion
begins to climb. The unique output stage design of the INA1620 greatly reduces the additional distortion at high
frequency when delivering large currents, as shown in 图 58. High-ordered harmonics (above the 2nd and 3rd)
are also kept to a minimal level at high output powers, as shown in 图 59.
-60
-70
-80
-82
-84
Left Channel
Right Channel
Left Channel
Right Channel
-86
-88
-80
-90
-92
-94
-96
-90
-98
-100
-110
-120
-100
-102
-104
-106
-108
-110
0.01
0.1
1
5
10
100
1k
10k
Output Level (Vrms)
Frequency (Hz)
22.4-kHz measurement bandwidth
90-kHz measurement bandwidth, 1-VRMS output
图 57. THD+N vs Output Voltage for a 32-Ω Load
图 58. THD+N vs Frequency for a 32-Ω Load
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
5000
10000
Frequency (Hz)
15000
20000
1 kHz, 32-Ω load, 1 VRMS
图 59. Output Spectrum
26
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8.3 Other Application Examples
8.3.1 Preamplifier for Professional Microphones
图 60 shows a preamplifier designed for high performance applications that require low-noise and high common-
mode rejection. Both channels of the INA1620 are configured as a two-op amp instrumentation amplifier with a
variable gain from 6 to 40 dB. The excellent matching of the integrated 1kΩ resistors allows for high common-
mode rejection in the circuit. An OPA197 is configured as a buffered power supply divider to provide a biasing
voltage to the circuit, allowing the system to operate properly on a single 9-V battery. The additional components
at the INA1620 inputs are for phantom power, EMI, and ESD protection.
9 V
9 V
0.1 ꢀF
100 kꢁ
OPA197
+
VBIAS
œ
1 ꢀF
100 kꢁ
10-kꢁ Potentiometer
(Logarithmic)
20 ꢁ
VBIAS
R3B
R2B
1 kꢁ
48 V Phantom Power
R2A
R2C R3A
R3C
1 kꢁ
1 kꢁ
1 kꢁ
9 V
9 V
D1
0.1 ꢀF
47 kꢁ
VCC
GND
OUTA
IN-B
10 V
6.8 kꢁ
6.8 kꢁ
D2
IN-A
47 ꢀF
68 ꢁ
œ
œ
47 ꢀF
Microphone
Input
Output
INA1620
+
+
OUTB
68 ꢁ
30 ꢁ
IN+A
100
pF
47 kꢁ
VBIAS
2.2 kꢁ
IN+B
2
3
100
pF
1
22 kꢁ
68 ꢁ
100
pF
2.2 kꢁ
47 ꢀF
30 ꢁ
XLR Connector
D3
D4
Copyright © 2018, Texas Instruments Incorporated
图 60. Preamplifier for Professional Microphones
版权 © 2018, Texas Instruments Incorporated
27
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9 Power Supply Recommendations
The INA1620 operates from ±2-V to ±18-V supplies, while maintaining excellent performance. However, some
applications do not require equal positive and negative output voltage swing. With the INA1620, power-supply
voltages do not need to be equal. For example, the positive supply could be set to 25 V with the negative supply
at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. Key parameters are
specified over the temperature range of TA = –40°C to 125°C. Parameters that vary with operating voltage or
temperature are shown in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry, because noise can propagate into analog circuitry through the power
pins of the circuit as a whole and the op amp specifically.
•
•
•
•
Connect the device ground pin to a low-impedance, low-noise, system reference point, such as an analog
ground.
Place the external components as close to the device as possible. As shown in 图 61, keep feedback
resistors close to the inverting input to minimize parasitic capacitance and the feedback loop area.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2 Layout Example
IN-
Minimize capacitance
at amplifier inputs
IN+
Minimize feedback
loop area
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
GND
EMI Filtering
Place bypass
capacitors as close to
IC as possible
OUT A
EN
OUT
VCC
GND
GND
IC ground pin
connected to low-
impedance, low-noise
system ground
NC
NC
VEE
OUT
OUT B
EMI Filtering
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
GND
IN+
IN-
Copper pour for thermal
pad must be connected to
negative supply (VEE)
图 61. Board Layout for a Difference Amplifier Configuration
28
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA-TI 软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 软件是 TINA 软件的一款免
费的全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传统
的 SPICE 直流、瞬态和频域分析以及其他设计功能。
TINA-TI 软件可从模拟电子实验室设计中心免费下载，它可提供广泛的后处理功能，使用户能够以多种方式设置结
果的格式。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 TI 高精度设计
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。TI 高精度设计是由 TI 公司高
精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板
(PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档
如需相关文档，请参阅：
•
•
•
•
•
•
•
《反馈曲线图定义运算放大器交流性能》
《电路板布局技巧》，SLOA089
《适用于电压输出音频 DAC 的耳机放大器参考设计》
《面向耳机应用的差分放大器稳定化 》
《减少 CMOS 模拟开关导致的失真》
《运算放大器的电磁干扰 (EMI) 抑制比》
《高保真音响电路设计》
11.3 接收文档更新通知
要接收文档更新通知，请在 ti.com.cn 上查找器件产品文件夹。单击右上角的通知我 即可接收产品信息更改每周摘
要。有关更改的详细信息，请参阅任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
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11.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA1620RTWR
INA1620RTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
INA1620
INA1620
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
www.ti.com
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