INA111AU/1K [TI]
高速 FET 输入仪表放大器 | DW | 16 | -40 to 85;型号: | INA111AU/1K |
厂家: | TEXAS INSTRUMENTS |
描述: | 高速 FET 输入仪表放大器 | DW | 16 | -40 to 85 放大器 仪表 光电二极管 仪表放大器 |
文件: | 总17页 (文件大小:346K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INA111
®
INA111
INA111
High Speed FET-Input
INSTRUMENTATION AMPLIFIER
FEATURES
DESCRIPTION
● FET INPUT: IB = 20pA max
The INA111 is a high speed, FET-input instrumenta-
tion amplifier offering excellent performance.
● HIGH SPEED: TS = 4µs (G = 100, 0.01%)
● LOW OFFSET VOLTAGE: 500µV max
The INA111 uses a current-feedback topology provid-
ing extended bandwidth (2MHz at G = 10) and fast
settling time (4µs to 0.01% at G = 100). A single
external resistor sets any gain from 1 to over 1000.
● LOW OFFSET VOLTAGE DRIFT:
5µV/°C max
● HIGH COMMON-MODE REJECTION:
Offset voltage and drift are laser trimmed for excellent
DC accuracy. The INA111’s FET inputs reduce input
bias current to under 20pA, simplifying input filtering
and limiting circuitry.
106dB min
● 8-PIN PLASTIC DIP, SOL-16 SOIC
The INA111 is available in 8-pin plastic DIP, and
SOL-16 surface-mount packages, specified for the
–40°C to +85°C temperature range.
APPLICATIONS
● MEDICAL INSTRUMENTATION
● DATA ACQUISITION
V+
(13)
7
INA111
Feedback
(12)
–
VIN
2
(4)
A1
10kΩ
10kΩ
DIP Connected
Internally
1
25kΩ
25kΩ
(2)
6
A3
VO
RG
(11)
8
50kΩ
RG
G = 1 +
(15)
5
A2
Ref
+
VIN
3
(10)
10kΩ
10kΩ
(5)
4
(7)
DIP
(SOIC)
V–
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1143E
Printed in U.S.A. March, 1998
SBOS015
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
INA111BP, BU
TYP
INA111AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
Initial
vs Temperature
vs Power Supply
Impedance, Differential
Common-Mode
Input Common-Mode Range
Common-Mode Rejection
TA = +25°C
A = TMIN to TMAX
S = ±6V to ±18V
±100 ± 500/G ±500 ± 2000/G
±200 ± 500/G ±1000 ±5000/G
µV
µV/°C
µV/V
Ω || pF
Ω || pF
V
T
V
±2 ± 10/G
2 +10/G
1012 || 6
1012 || 3
±12
±5 ± 100/G
30 + 100/G
±2 ± 20/G
±10 ± 100/G
✻
✻
✻
✻
✻
V
DIFF = 0V
±10
✻
V
CM = ±10V, ∆RS = 1kΩ
G = 1
G = 10
G = 100
G = 1000
80
96
106
106
90
75
90
100
100
✻
✻
✻
✻
dB
dB
dB
dB
110
115
115
BIAS CURRENT
±2
±20
±10
✻
✻
✻
✻
pA
pA
OFFSET CURRENT
±0.1
NOISE VOLTAGE, RTI
f = 100Hz
f = 1kHz
G = 1000, RS = 0Ω
13
10
10
1
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
f = 10kHz
fB = 0.1Hz to 10Hz
Noise Current
f = 10kHz
0.8
✻
✻
fA/√Hz
GAIN
Gain Equation
Range of Gain
Gain Error
1 + (50kΩ/RG)
V/V
V/V
%
%
%
%
ppm/°C
ppm/°C
1
10000
±0.02
±0.5
±0.5
±1
✻
✻
0.05
✻
±0.7
±2
G = 1, RL = 10kΩ
G = 10, RL = 10kΩ
G = 100, RL = 10kΩ
±0.01
±0.1
±0.15
±0.25
±1
✻
✻
✻
✻
✻
✻
G = 1000, RL = 10kΩ
Gain vs Temperature
50kΩ Resistance(1)
G = 1
±10
±100
✻
✻
±25
Nonlinearity
G = 1
G = 10
G = 100
G = 1000
±0.0005
±0.001
±0.001
±0.005
±0.005
±0.005
±0.005
±0.02
✻
✻
✻
✻
✻
% of FSR
% of FSR
% of FSR
% of FSR
±0.01
±0.01
±0.04
OUTPUT
Voltage
Load Capacitance Stability
Short Circuit Current
I
O = 5mA, TMIN to TMAX
±11
±12.7
1000
+30/–25
✻
✻
✻
✻
V
pF
mA
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1
G = 10
G = 100
G = 1000
2
2
450
50
17
2
2
4
30
1
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
MHz
MHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
Slew Rate
Settling Time, 0.01%
V
O = ±10V, G = 2 to 100
G = 1
G = 10
G = 100
G = 1000
50% Overdrive
Overload Recovery
POWER SUPPLY
Voltage Range
Current
±6
±15
±3.3
±18
±4.5
✻
✻
✻
✻
✻
V
mA
V
IN = 0V
TEMPERATURE RANGE
Specification
Operating
–40
–40
85
125
✻
✻
✻
✻
°C
°C
θJA
100
✻
°C/W
✻ Specification same as INA111BP.
NOTE: (1) Temperature coefficient of the “50kΩ” term in the gain equation.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
INA111
PIN CONFIGURATIONS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Top View
DIP
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
RG
1
2
3
4
8
7
6
5
RG
V+
VO
Ref
V–
IN
IN
V+
V–
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Top View
SOL-16 Surface Mount
NC
1
2
3
4
5
6
7
8
16 NC
ORDERING INFORMATION
RG
15 RG
PRODUCT
PACKAGE
TEMPERATURE RANGE
NC
14 NC
INA111AP
INA111BP
INA111AU
INA111BU
8-Pin Plastic DIP
8-Pin Plastic DIP
SOL-16 Surface-Mount
SOL-16 Surface-Mount
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
V–
13 V+
IN
IN
V+
12 Feedback
11 VO
NC
V–
PACKAGE INFORMATION
10 Ref
PACKAGE DRAWING
NUMBER(1)
NC
9
NC
PRODUCT
PACKAGE
INA111AP
INA111BP
INA111AU
INA111BU
8-Pin Plastic DIP
8-Pin Plastic DIP
16-Pin Surface Mount
16-Pin Surface Mount
006
006
211
211
ABSOLUTE MAXIMUM RATINGS(1)
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Supply Voltage .................................................................................. ±18V
Input Voltage Range .......................................... (V–) –0.7V to (V+) +15V
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: Stresses above these ratings may cause permanent damage.
®
3
INA111
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
GAIN vs FREQUENCY
10k
COMMON-MODE REJECTION vs FREQUENCY
120
100
80
60
40
20
0
G = 1k
1k
G = 100
100
G = 1k
G = 10
10
G = 100
G = 10
G = 1
1
G = 1
0.1
10
10
1
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
INPUT COMMON-MODE VOLTAGE RANGE
vs OUTPUT VOLTAGE
POWER SUPPLY REJECTION vs FREQUENCY
15
10
5
120
100
80
60
40
20
0
–
VD/2
VD/2
VCM
VO
+
–
+
G = 1k
0
(Any Gain)
G = 100
G = 10
A3 – Output
Swing Limit
A3 + Output
Swing Limit
–5
–10
–15
G = 1
–15
–10
–5
0
5
10
15
100
1k
10k
100k
1M
Frequency (Hz)
Output Voltage (V)
INPUT-REFERRED NOISE VOLTAGE vs FREQUENCY
SETTLING TIME vs GAIN
1k
100
10
100
10
1
G = 1
0.01%
G = 10
G = 100, 1k
0.1%
1
1
10
100
1k
10k
10
100
1000
Frequency (Hz)
Gain (V/V)
®
4
INA111
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
OFFSET VOLTAGE WARM-UP vs TIME
INPUT BIAS CURRENT vs TEMPERATURE
75
50
300
200
100
0
10n
1n
Ib
IOS
25
100p
10p
0
G ≥ 10
–25
–50
–75
–100
–200
–300
1p
G = 1
0.1p
0.01p
0
1
2
3
4
5
–75
–50
–25
0
25
50
75
100
125
Time From Power Supply Turn-On (Minutes)
Temperature (°C)
INPUT BIAS CURRENT
INPUT BIAS CURRENT
vs DIFFERENTIAL INPUT VOLTAGE
vs COMMON-MODE INPUT VOLTAGE
–10m
–1m
–10m
–1m
–15.7V
–15.7V
–100µ
–10µ
+1p
–100µ
–10µ
+1p
G = 1
G = 10 G = 100
G = 1k
G = 1
G = 10
G = 100
+10p
+100p
G = 1k
+15.7V
15
+15.7V
+10p
–20
–15
–10
–5
0
5
10
15
20
–20
–15
–10
–5
0
5
10
20
Differential Overload Voltage (V)
NOTE: One input grounded.
Common-Mode Voltage (V)
MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
OUTPUT CURRENT LIMIT vs TEMPERATURE
30
25
20
15
10
5
50
40
30
20
10
0
+ICL
–ICL
0
–75
–50
–25
0
25
50
75
100
125
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
®
5
INA111
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
QUIESCENT CURRENT vs TEMPERATURE
1
0.1
3.5
3.4
3.3
3.2
3.1
3.0
VO = 3Vrms, RL = 2kΩ
Measurement BW = 80kHz
G = 1k
Single-Ended Drive G = 1
G = 100
G = 10
0.01
0.001
0.0001
Differential Drive G = 1
–75
–50
–25
0
25
50
75
100 125
20
100
1k
10k 20k
Temperature (°C)
Frequency (Hz)
LARGE SIGNAL RESPONSE, G = 100
SMALL SIGNAL RESPONSE, G = 1
+10
0
+0.1
0
–0.1
–10
0
10
20
0
10
20
Time (µs)
Time (µs)
LARGE SIGNAL RESPONSE, G = 100
SMALL SIGNAL RESPONSE, G = 1
+10
+0.1
0
0
–10
–0.1
0
10
20
0
10
20
Time (µs)
Time (µs)
®
6
INA111
The 50kΩ term in equation 1 comes from the sum of the two
internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute val-
ues. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi-
cations of the INA111.
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA111. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 2Ω in series with the Ref pin will cause a typical
device with 90dB CMR to degrade to approximately 80dB
CMR (G = 1).
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance, which will contribute additional gain error (pos-
sibly an unstable gain error) in gains of approximately 100
or greater.
SETTING THE GAIN
Gain of the INA111 is set by connecting a single external
resistor, RG:
DYNAMIC PERFORMANCE
The typical performance curve “Gain vs Frequency” shows
that the INA111 achieves wide bandwidth over a wide range
of gain. This is due to the current-feedback topology of the
INA111. Settling time also remains excellent over wide
gains.
50kΩ
RG
G = 1 +
(1)
Commonly used gains and resistor values are shown in
Figure 1.
V+
0.1µF
Pin numbers are
for DIP package.
7
–
VIN
INA111
2
1
A1
VO = G • (VI+N – VI–N
)
10kΩ
10kΩ
50kΩ
RG
25kΩ
25kΩ
G = 1 +
6
A3
RG
+
8
3
VO
Load
–
5
A2
+
VIN
Ref
10kΩ
10kΩ
4
0.1µF
DESIRED
GAIN
RG
(Ω)
NEAREST 1% RG
Also drawn in simplified form:
V–
(Ω)
–
VIN
1
2
5
10
20
50
100
200
500
1000
2000
5000
10000
No Connection
50.00k
12.50k
5.556k
2.632k
1.02k
No Connection
49.9k
12.4k
5.62k
2.61k
1.02k
511
INA111
Ref
VO
RG
+
VIN
505.1
251.3
100.2
50.05
25.01
10.00
5.001
249
100
49.9
24.9
10
4.99
FIGURE 1. Basic Connections
®
7
INA111
The INA111 exhibits approximately 6dB rise in gain at
2MHz in unity gain. This is a result of its current-feedback
topology and is not an indication of instability. Unlike an op
amp with poor phase margin, the rise in response is a
predictable +6dB/octave due to a response zero. A simple
pole at 700kHz or lower will produce a flat passband
response (see Input Filtering).
INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA111 is extremely high—
approximately 1012Ω. However, a path must be provided for
the input bias current of both inputs. This input bias current
is typically less than 10pA. High input impedance means
that this input bias current changes very little with varying
input voltage.
The INA111 provides excellent rejection of high frequency
common-mode signals. The typical performance curve,
“Common-Mode Rejection vs Frequency” shows this be-
havior. If the inputs are not properly balanced, however,
common-mode signals can be converted to differential sig-
nals. Run the VI+N and VI–N connections directly adjacent each
other, from the source signal all the way to the input pins. If
possible use a ground plane under both input traces. Avoid
running other potentially noisy lines near the inputs.
Input circuitry must provide a path for this input bias current
if the INA111 is to operate properly. Figure 3 shows various
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceeds the common-mode range of the INA111 and the
input amplifiers will saturate.
If the differential source resistance is low, the bias current
return path can be connected to one input (see the thermo-
couple example in Figure 3). With higher source impedance,
using two resistors provides a balanced input with possible
advantages of lower input offset voltage due to bias current
and better high-frequency common-mode rejection.
NOISE AND ACCURACY PERFORMANCE
The INA111’s FET input circuitry provides low input bias
current and high speed. It achieves lower noise and higher
accuracy with high impedance sources. With source imped-
ances of 2kΩ to 50kΩ the INA114 may provide lower offset
voltage and drift. For very low source impedance (≤1kΩ),
the INA103 may provide improved accuracy and lower
noise.
Crystal or
Ceramic
INA111
Transducer
1MΩ
1MΩ
OFFSET TRIMMING
The INA111 is laser trimmed for low offset voltage and
drift. Most applications require no external offset adjust-
ment. Figure 2 shows an optional circuit for trimming the
output offset voltage. The voltage applied to Ref terminal is
summed at the output. Low impedance must be maintained
at this node to assure good common-mode rejection. The op
amp shown maintains low output impedance at high fre-
quency. Trim circuits with higher source impedance should
be buffered with an op amp follower circuit to assure low
impedance on the Ref pin.
Thermocouple
INA111
10kΩ
INA111
–
VIN
V+
VO
INA111
RG
100µA
Center-tap provides
bias current return.
+
1/2 REF200
Ref
VIN
100Ω(1)
100Ω(1)
OPA177
±10mV
Adjustment Range
FIGURE 3. Providing an Input Common-Mode Current Path.
10kΩ(1)
INPUT COMMON-MODE RANGE
The linear common-mode range of the input op amps of the
INA111 is approximately ±12V (or 3V from the power
supplies). As the output voltage increases, however, the
linear input range will be limited by the output voltage swing
of the input amplifiers, A1 and A2. The common-mode range
is related to the output voltage of the complete amplifier—
see performance curve “Input Common-Mode Range vs
Output Voltage”.
100µA
1/2 REF200
NOTE: (1) For wider trim range required
in high gains, scale resistor values larger
V–
FIGURE 2. Optional Trimming of Output Offset Voltage.
®
8
INA111
A combination of common-mode and differential input
voltage can cause the output of A1 or A2 to saturate. Figure
4 shows the output voltage swing of A1 and A2 expressed in
terms of a common-mode and differential input voltages.
For applications where input common-mode range must be
maximized, limit the output voltage swing by connecting the
INA111 in a lower gain (see performance curve “Input
Common-Mode Voltage Range vs Output Voltage”). If
necessary, add gain after the INA111 to increase the voltage
swing.
the 1N4148 may have leakage currents far greater than the
input bias current of the INA111 and are usually sensitive to
light.
INPUT FILTERING
The INA111’s FET input allows use of an R/C input filter
without creating large offsets due to input bias current.
Figure 6 shows proper implementation of this input filter to
preserve the INA111’s excellent high frequency common-
mode rejection. Mismatch of the common-mode input ca-
pacitance (C1 and C2), either from stray capacitance or
Input-overload often produces an output voltage that appears
normal. For example, consider an input voltage of +14V on
one input and +15V on the other input will obviously exceed
the linear common-mode range of both input amplifiers.
Since both input amplifiers are saturated to the nearly the
same output voltage limit, the difference voltage measured
by the output amplifier will be near zero. The output of the
INA111 will be near 0V even though both inputs are
overloaded.
V+
D1
D2
VI–N
R1
R2
VO
INA111
RG
INPUT PROTECTION
VI+N
Inputs of the INA111 are protected for input voltages from
0.7V below the negative supply to 15V above the positive
power supply voltages. If the input current is limited to less
than 1mA, clamp diodes are not required; internal junctions
will clamp the input voltage to safe levels. If the input source
can supply more than 1mA, use external clamp diodes as
shown in Figure 5. The source current can be limited with
series resistors R1 and R2 as shown. Resistor values greater
than 10kΩ will contribute noise to the circuit.
D3
D4
V+
2N4117A
1pA Leakage
=
Diodes:
A diode formed with a 2N4117A transistor as shown in
Figure 5 assures low leakage. Common signal diodes such as
FIGURE 5. Input Protection Voltage Clamp.
V+
G • VD
VCM
–
2
INA111
A1
10kΩ
10kΩ
VD
50kΩ
RG
G = 1 +
2
25kΩ
25kΩ
A3
VO = G • VD
RG
VD
2
A2
10kΩ
10kΩ
VCM
G • VD
2
VCM
+
V–
FIGURE 4. Voltage Swing of A1 and A2.
®
9
INA111
mismatched values, causes a high frequency common-mode
signal to be converted to a differential signal. This degrades
common-mode rejection. The differential input capacitor,
C3, reduces the bandwidth and mitigates the effects of
mismatch in C1 and C2. Make C3 much larger than C1 and
C2. If properly matched, C1 and C2 also improve CMR.
Surface-mount package
version only.
VI–N
C1
Feedback
1000pF
RG
INA111
Ref
VI+N
OUTPUT VOLTAGE SENSE
(SOL-16 Package Only)
Load
The surface-mount version of the INA111 has a separate
output sense feedback connection (pin 12). Pin 12 must be
connected, usually to the output terminal, pin 11, for proper
operation. (This connection is made internally on the DIP
version of the INA111.)
Equal resistance here preserves
good common-mode rejection.
FIGURE 8. Remote Load and Ground Sensing.
The output feedback connection can be used to sense the
output voltage directly at the load for best accuracy. Figure 8
shows how to drive a load through series interconnection
resistance. Remotely located feedback paths may cause
instability. This can be generally be eliminated with a high
frequency feedback path through C1.
C1
VO
INA111
Ref
RG
C2
R1
R2
1
fc
=
2πR1C1
1
f−3 d B
=
C1
2
C1
4 π R1 C 3 +
R1
R2
NOTE: To preserve good low frequency CMR,
make R1 = R2 and C1 = C2.
VI–N
VO
INA111
C3
C2
FIGURE 9. High-Pass Input Filter.
VI+N
Ref
R1 = R2
C1 = C2
C
±6V to ±18V
Isolated Power
3 ≈ 10C1
V+ V–
±15V
FIGURE 6. Input Low-Pass Filter.
VI–N
VO
INA111
Ref
ISO122
+10V
VI+N
G = 500
Bridge
VO
RG
100Ω
INA111
Ref
Isolated
Common
FIGURE 10. Galvanically Isolated Instrumentation
Amplifier.
FIGURE 7. Bridge Transducer Amplifier.
®
10
INA111
VIN
OPA177
C1
50nF
–
VO
VIN
+
RG
INA111
Ref
R1
1MΩ
C1
0.1µF
R1
10kΩ
RG
R2
INA111
1
Ref
f–3dB
=
2πR1C1
OPA602
VIN
IL
=
•
= 1.59Hz
G
R2
Load
50k
RG
Make G ≤ 10 where G = 1 +
FIGURE 11. AC-Coupled Instrumentation Amplifier.
FIGURE 12. Voltage Controlled Current Source.
VI–N
VI+N
VO
22.1kΩ
22.1kΩ
511Ω
INA111
Ref
100Ω
For G = 100
RG = 511Ω // 2(22.1kΩ)
effective RG = 505Ω
NOTE: Driving the shield minimizes CMR degradation
due to unequally distributed capacitance on the input
line. The shield is driven at approximately 1V below
the common-mode input voltage.
OPA602
FIGURE 13. Shield Driver Circuit.
+5V
+
–
VIN
Channel 1
Channel 8
12 Bits
Out
MPC800
MUX
ADS574
INA111
Ref
RG
+
–
VIN
FIGURE 14. Multiplexed-Input Data Acquisition System.
®
11
INA111
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA111AP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
INA111AP
Samples
INA111APG4
INA111AU
LIFEBUY
ACTIVE
PDIP
SOIC
P
8
50
40
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
INA111AP
INA111AU
DW
16
Level-3-260C-168 HR
-40 to 85
-40 to 85
Samples
Samples
Samples
Samples
INA111AU/1K
INA111BP
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SOIC
DW
P
16
8
1000 RoHS & Green
Call TI
NIPDAU
NIPDAU
Level-3-260C-168 HR
N / A for Pkg Type
INA111AU
INA111BP
INA111BU
50
40
RoHS & Green
RoHS & Green
INA111BU
DW
16
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA111AU/1K
SOIC
DW
16
1000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
INA111AU/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA111AP
INA111APG4
INA111AU
INA111BP
INA111BU
P
P
PDIP
PDIP
SOIC
PDIP
SOIC
8
8
50
50
40
50
40
506
506
507
506
507
13.97
13.97
12.83
13.97
12.83
11230
11230
5080
4.32
4.32
6.6
DW
P
16
8
11230
5080
4.32
6.6
DW
16
Pack Materials-Page 3
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