INA101 [TI]
极高精度仪表放大器;
| 型号： | INA101 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 极高精度仪表放大器 放大器 仪表 仪表放大器 |
| 文件： | 总12页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
INA101
High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
● LOW DRIFT: 0.25µV/°C max
● LOW OFFSET VOLTAGE: 25µV max
● LOW NONLINEARITY: 0.002%
● LOW NOISE: 13nV/√Hz
● STRAIN GAGES
● THERMOCOUPLES
● RTDs
● REMOTE TRANSDUCERS
● LOW-LEVEL SIGNALS
● HIGH CMR: 106dB AT 60Hz
● HIGH INPUT IMPEDANCE: 1010Ω
● MEDICAL INSTRUMENTATION
● 14-PIN PLASTIC, CERAMIC DIP,
SOL-16, AND TO-100 PACKAGES
DESCRIPTION
The INA101 is a high accuracy instrumentation ampli-
fier designed for low-level signal amplification and
general purpose data acquisition. Three precision op
amps and laser-trimmed metal film resistors are inte-
grated on a single monolithic integrated circuit.
The INA101 is packaged in TO-100 metal, 14-pin
plastic and ceramic DIP, and SOL-16 surface-mount
packages. Commercial, industrial and military tem-
perature range models are available.
Offset
Adj.
Offset
Adj.
A1 Output
TO-100 PACKAGE
DIP PACKAGE
INA101
2
3
6
7 8
INA101
–Input
10
3
–Input
A1
A1
1kΩ
1kΩ
10kΩ
10kΩ
10kΩ
10kΩ
Gain Sense 1
1
4
5
20kΩ
20kΩ
20kΩ
20kΩ
Gain Set 1
RG
Output
Output
A3
A3
RG
10
11
8
1
Gain Set 2
4
5
Gain Sense 2
+Input
Common
7
Common
14
1kΩ
1kΩ
A2
A2
12
10kΩ
10kΩ
10kΩ
10kΩ
+Input
9
6
2
13
9
+VCC –VCC
+VCC –VCC
A2 Output
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1981 Burr-Brown Corporation
PDS-454K
Printed in U.S.A. July, 1998
SBOS133
SPECIFICATIONS
ELECTRICAL
At +25°C with ±15VDC power supply and in circuit of Figure 1, unless otherwise noted.
INA101AM, AG
TYP
INA101SM, SG
INA101CM, CG
TYP
INA101HP, KU
TYP
PARAMETER
MIN
MAX
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
GAIN
Range of Gain
Gain Equation
Error from Equation, DC(1)
1
1000
*
*
*
*
*
*
*
*
V/V
V/V
%
G = 1 + (40k/RG)
±(0.04 + 0.00016G
–0.02/G)
*
*
*
*
*
±(0.1 + 0.0003G
–0.05/G)
±(0.1 +
0.00015G)
–0.05/G
±(0.3 +
0.0002G)
–0.10/G
Gain Temp. Coefficient(3)
G = 1
G = 10
2
20
22
22
5
100
110
110
*
*
*
*
*
*
*
10
11
11
±(0.001
+10–5 G)
*
*
*
*
*
*
*
*
*
*
*
*
*
ppm/°C
ppm/°C
ppm/°C
ppm/°C
% of p-p FS
G = 100
G = 1000
Nonlinearity, DC
*
*
*
(2)
±(0.002 + 10–5 G)
±(0.005 + 2 x 10–5 G)
±(0.001
+10–5 G)
±(0.002
+10–5 G)
±(0.002
+10–5 G)
RATED OUTPUT
Voltage
Current
Output Impedance
Capacitive Load
±10
±5
±12.5
±10
0.2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
mA
Ω
1000
pF
INPUT OFFSET VOLTAGE
Initial Offset at +25°C
±(25 + 200/G)
±(50 + 400/G)
±(2 + 20/G)
±10+
100/G)
±(25
±(10+
100/G)
±(25 +
200/G)
±(0.25 +
10/G)
±(125 +
450/G)
±(2 + 20/G)
±(250 +
900/G)
µV
+200/G)
±(0.75
+ 10/G)
vs Temperature
µV/°C
vs Supply
vs Time
±(1 + 20/G)
±(1 + 20/G)
*
*
*
*
*
*
µV/V
µV/mo
INPUT BIAS CURRENT
Initial Bias Current
(each input)
vs Temperature
vs Supply
±15
±0.2
±0.1
±15
±30
±30
±10
*
*
±10
*
*
*
±5
*
*
±5
*
±20
±20
*
*
*
*
*
*
*
nA
nA/°C
nA/V
nA
Initial Offset Current
vs Temperature
±0.5
nA/°C
INPUT IMPEDANCE
Differential
Common-mode
1010 || 3
1010 || 3
*
*
*
*
*
*
Ω || pF
Ω || pF
INPUT VOLTAGE RANGE
Range, Linear Response
CMR with 1kΩ Source Imbalance
DC to 60Hz, G = 1
DC to 60Hz, G = 10
DC to 60Hz, G = 100 to 1000
±10
±12
*
*
*
*
*
*
V
80
96
106
90
106
110
*
*
*
*
*
*
*
*
*
*
*
*
65
90
100
85
95
105
dB
dB
dB
INPUT NOISE
Input Voltage Noise
fB = 0.01Hz to 10Hz
Density, G = 1000
0.8
*
*
*
µV, p-p
f
O = 10Hz
fO = 100Hz
O = 1kHz
18
15
13
*
*
*
*
*
*
*
*
*
nV/√Hz
nV/√Hz
nV/√Hz
f
Input Current Noise
fB = 0.01Hz to 10Hz
Density
50
*
*
*
pA, p-p
f
O = 10Hz
fO = 100Hz
O = 1kHz
0.8
0.46
0.35
*
*
*
*
*
*
*
*
*
pA/√Hz
pA/√Hz
pA/√Hz
f
DYNAMIC RESPONSE
Small Signal, ±3dB Flatness
G = 1
G = 10
G = 100
300
140
25
*
*
*
*
*
*
*
*
*
*
*
*
kHz
kHz
kHz
kHz
G = 1000
2.5
Small Signal, ±1% Flatness
G = 1
G = 10
G = 100
G = 1000
Full Power, G = 1 to 100
Slew Rate, G = 1 to 100
Settling Time (0.1%)
G = 1
G = 100
G = 1000
20
10
1
200
6.4
0.4
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
kHz
kHz
kHz
Hz
kHz
V/µs
0.2
*
*
*
30
40
350
40
55
470
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
µs
µs
µs
Settling Time (0.01%)
G = 1
G = 100
30
50
500
45
70
650
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
µs
µs
µs
G = 1000
POWER SUPPLY
Rated Voltage
Voltage Range
Current, Quiescent(2)
±15
*
*
*
*
*
*
V
V
mA
±5
±20
±8.5
*
*
*
*
*
*
*
*
*
±6.7
TEMPERATURE RANGE(5)
Specification
Operation
–25
–55
–65
+85
+125
+150
–55
*
*
+125
*
*
*
*
*
*
*
*
0
–25
–40
+70
+85
+85
°C
°C
°C
Storage
* Specifications same as for INA101AM, AG.
NOTES: (1) Typically the tolerance of RG will be the major source of gain error. (2) Nonlinearity is the maximum peak deviation from the best straight-line as a percentage of peak-to-peak full scale output. (3) Not including the TCR of RG. (4) Adjustable
to zero at any one gain. (5) θJC output stage = 113°C/W, θJC quiescent circuitry = 19°C/W, θCA = 83°C/W.
®
2
INA101
PIN CONFIGURATIONS
Top View
TO-100
DIP
G and P Package
M Package
–In
Output
+VCC
1
2
3
4
5
6
7
14 Common
13 –VCC
10
Gain Set
+VCC
1
4
9
6
–Input
12 +Input
Offset
Adjust
Output
2
3
8
7
Gain Sense 1
Gain Set 1
Offset Adj.
Offset Adj.
11 Gain Sense 2
10 Gain Set 2
SOIC
U Package
Offset
Adjust
Common
9
8
A2 Output
A1 Output
Gain
Set
–VCC
Output
+VCC
1
2
3
4
5
6
7
8
16 Common
15 –VCC
5
+In
–Input
14 +Input
Gain Sense 1
Gain Set 1
Offset Adj.
Offset Adj.
NC
13 Gain Sense 2
12 Gain Set 2
11 A2 Output
10 A1 Output
9
NC
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
PRODUCT
PACKAGE
TEMPERATURE RANGE
Supply Voltage ................................................................................... ±20V
Power Dissipation .......................................................................... 600mW
Input Voltage Range .......................................................................... ±VCC
Output Short Circuit (to ground) ............................................... Continuous
Operating Temperature M, G Package ........................... –55°C to +125°C
P, U Package ................................................................. –25°C to +85°C
Storage Temperature M, G Package .............................. –65°C to +150°C
P, U Package ................................................................. –40°C to +85°C
Lead Temperature (soldering, 10s) M, G, P Package ................... +300°C
Lead Temperature (wave soldering, 3s) U Package...................... +260°C
INA101AM
INA101CM
INA101AG
INA101CG
INA101HP
INA101KU
INA101SG
INA101SM
10-Pin Metal TO-100
10-Pin Metal TO-100
14-Pin Ceramic DIP
14-Pin Ceramic DIP
14-Pin Plastic DIP
SOL-16 Surface-Mount
14-Pin Ceramic DIP
10-Pin Metal TO-100
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
PACKAGE INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE DRAWING
NUMBER(1)
PRODUCT
PACKAGE
INA101AM
INA101CM
INA101AG
INA101CG
INA101HP
INA101KU
INA101SG
INA101SM
10-Pin Metal TO-100
10-Pin Metal TO-100
14-Pin Ceramic DIP
14-Pin Ceramic DIP
14-Pin Plastic DIP
SOL-16 Surface-Mount
14-Pin Ceramic DIP
10-Pin Metal TO-100
007
007
169
169
010
211
169
007
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
INA101
TYPICAL PERFORMANCE CURVES
At +25°C, VCC = ±15V unless otherwise noted.
GAIN NONLINEARITY vs GAIN
0.01
GAIN vs FREQUENCY
G = 1000
G = 100
G = 10
G = 1
60
40
20
0
0.003
Max
Typ
0.001
1% Error
0.0003
1
10
100
1000
100
1k
10k
100k
1M
Gain (V/V)
Frequency (Hz)
WARM-UP DRIFT vs TIME
CMR vs FREQUENCY
10
8
120
100
80
G = 100, 1000
G = 10
6
G = 1
4
Balanced
Source
60
2
0
0
1
2
3
4
5
1
10
100
1k
10k
Time (Minutes)
Frequency (Hz)
QUIESCENT CURRENT vs SUPPLY
STEP RESPONSE
±9
±8
±7
±6
±5
G = 1
+10
+5
0
G = 1000
–5
–10
0
±5
±10
±15
±20
0
100
200
300
400
500
600
Supply Voltage (V)
Time (µs)
®
4
INA101
TYPICAL PERFORMANCE CURVES (CONT)
At +25°C, VCC = ±15V unless otherwise noted.
OUTPUT NOISE vs GAIN
SETTLING TIME vs GAIN
1000
100
10
30
20
10
0
RL = 2kΩ
CL = 1000pF
0.01%
0.1%
RS = 1MΩ
RS = 1000kΩ
RS = 10kΩ
RS = 0
1%
0
10
100
1000
1
10
100
1000
Gain (V/V)
Gain (V/V)
INPUT NOISE VOLTAGE
vs FREQUENCY (100 ≤ GAIN ≤ 1000)
1000
100
10
1
0
10
100
1000
Frequency (Hz)
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA101. (Pin numbers shown are for the TO-100
metal package.) Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
The 40kΩ term in equation (1) comes from the sum of the
two internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute val-
ues. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi-
cations of the INA101.
The output is referred to the output Common terminal which
is normally grounded. This must be a low-impedance con-
nection to assure good common-mode rejection. A resis-
tance greater than 0.1Ω in series with the Common pin will
cause common-mode rejection to fall below 106dB.
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance which will contribute additional gain error (possi-
bly an unstable gain error) in gains of approximately 100 or
greater. The gain sense connections on the DIP and SOL-16
packages (see Figure 2) reduce the gain error produced by
wiring or socket resistance.
SETTING THE GAIN
Gain of the INA101 is set by connecting a single external
resistor, RG:
40kΩ
RG
(1)
G = 1 +
®
5
INA101
OFFSET TRIMMING
voltage can be adjusted with the optional trim circuit con-
nected to the Common pin as shown in Figure 2. The voltage
applied to Common terminal is summed with the output.
Low impedance must be maintained at this node to assure
good common-mode rejection. The op amp connected as a
buffer provides low impedance.
The INA101 is laser trimmed for low offset voltage and
drift. Most applications require no external offset adjust-
ment. Figure 2 shows connection of an optional potentio-
meter connected to the Offset Adjust pins for trimming the
input offset voltage. (Pin numbers shown are for the DIP
package.) Use this adjustment to null the offset voltage in
high gain (G ≥ 100) with both inputs connected to ground.
Do not use this adjustment to null offset produced by the
source or other system offset since this will increase the
offset voltage drift by 0.3µV/°C per 100µV of adjusted
offset.
THERMAL EFFECTS ON OFFSET VOLTAGE
To achieve lowest offset voltage and drift, prevent air
currents from circulating near the INA101. Rapid changes in
temperature will produce a thermocouple effect on the
package leads that will degrade offset voltage and drift. A
shield or cover that prevents air currents from flowing near
the INA101 will assure best performance.
Offset of the output amplifier usually dominates when the
INA101 is used in unity gain (G = 1). The output offset
No
Connection
TO-100 PACKAGE
INA101
2
3
10
1
E2
A1
10kΩ
10kΩ
20kΩ
20kΩ
Output
VO = G (E1 – E2)
8
40kΩ
RG
A3
G = 1 +
RG
4
5
A2
7
E1
10kΩ
10kΩ
9
6
Tantalum
Tantalum
+
+
1µF
1µF
+15V –15V
FIGURE 1. Basic Connections.
+15V
100kΩ
Input Offset Adjustment
Do not use to null source or system
offset (see text).
A1 Output
DIP PACKAGE
INA101
6
7
3
E2
A1
10kΩ
10kΩ
4
5
20kΩ
20kΩ
RG
A3
V
O = G (E1 – E2) +VCOM
10
1
11
40kΩ
RG
G = 1 +
Common
+15V
VCOM
A2
12
E1
14
10kΩ
10kΩ
Approximately
±15mV Range
2
13
OPA177
1MΩ
Pinout shown
is for DIP packages.
+15V –15V
A2 Output
100kΩ
–15V
Output Offset
Adjustment
1kΩ
FIGURE 2. Optional Trimming of Input and Output Offset Voltage.
®
6
INA101
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA101AG
INA101AM
INA101CM
INA101HP
NRND
NRND
NRND
ACTIVE
CDIP SB
TO-100
TO-100
PDIP
JD
LME
LME
N
14
10
10
14
1
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
AU
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
INA101AG
20
20
25
Call TI
Call TI
NIPDAU
INA101AM
INA101CM
INA101HP
-55 to 125
-55 to 125
Samples
INA101HPG4
INA101KU
LIFEBUY
ACTIVE
PDIP
SOIC
N
14
16
25
40
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
INA101HP
INA101KU
DW
Level-3-260C-168 HR
Samples
Samples
INA101KU/1K
INA101SM
ACTIVE
NRND
SOIC
DW
16
10
1000 RoHS & Green
20 RoHS & Green
NIPDAU
AU
Level-3-260C-168 HR
N / A for Pkg Type
INA101KU
INA101SM
TO-100
LME
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA101KU/1K
SOIC
DW
16
1000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
INA101KU/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA101AG
INA101AM
INA101CM
INA101HP
INA101HPG4
INA101KU
INA101SM
JD
LME
LME
N
CDIP SB
TO-CAN
TO-CAN
PDIP
14
10
10
14
14
16
10
1
506.98
532.13
532.13
506
15.24
21.59
21.59
13.97
13.97
12.83
21.59
12290
889
NA
NA
20
20
25
25
40
20
889
NA
11230
11230
5080
889
4.32
4.32
6.6
N
PDIP
506
DW
LME
SOIC
507
TO-CAN
532.13
NA
Pack Materials-Page 3
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