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HPC003U20/883 [TI]

16-BIT, MROM, 20MHz, MICROCONTROLLER, CPGA68, CERAMIC, PGA-68;
HPC003U20/883
型号： HPC003U20/883
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

16-BIT, MROM, 20MHz, MICROCONTROLLER, CPGA68, CERAMIC, PGA-68

PC 微控制器 外围集成电路
文件： 总10页 (文件大小：90K)
中文：  中文翻译
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MILITARY DATA SHEET  
Original Creation Date: 08/25/94  
Last Update Date: 08/25/94  
MNHPC16003-20-X REV 0A0  
Last Major Revision Date: 08/25/94  
16 BIT HIGH PERFORMANCE MICROCONTROLLER  
General Description  
The HPC16003 and HPC16083 are members of the HPC family of High Performance  
microControllers. Each member of the family has the same core CPU with a unique memory and  
I/O configuration to suit specific applications. The HPC16083 has 8k bytes of on-chip ROM.  
The HPC16003 has no on-chip ROM and is intended for use with external direct memory. Each  
part is fabricated in National's advanced microCMOS technology. This process combined with  
an advanced architecture provides fast, flexible I/O control, efficient data manipulation,  
and high speed computation.  
The HPC devices are complete microcomputers on a single chip. All system timing, internal  
logic, ROM, RAM, and I/O are provided on the chip to produce a cost effective solution for  
high performance applications. On-chip functions such as UART, up to eight 16-bit timers  
with 4 input capture registers, vectored interrupts, WATCHDOG(TM) logic and  
MICROWIRE/PLUS(TM) provide a high level of system integration. The ability to address up  
to 64k bytes of external memory enables the HPC to be used in powerful applications  
typically performed by microprocessors and expensive peripheral chips.  
The microCMOS process results in very low current drain and enables the user to select the  
optimum speed/power product for his/her system. The IDLE and HALT modes provide further  
current savings. The HPC is available in a 68-pin PGA package.  
Industry Part Number  
NS Part Numbers  
HPC16003  
HPC003U20/883  
Prime Die  
HPCS083  
Processing  
Subgrp Description  
Temp (oC)  
MIL-STD-883, Method 5004  
1
Static tests at  
+25  
2
Static tests at  
+125  
-55  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
+25  
Quality Conformance Inspection  
5
+125  
-55  
6
MIL-STD-883, Method 5005  
7
+25  
8A  
8B  
9
+125  
-55  
+25  
10  
11  
+125  
-55  
1
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
Features  
- HPC family-core features:  
- 16-bit architecture, both byte and word  
- 16-bit data bus, ALU, and registers  
- 64k bytes of external direct memory addressing  
- FAST-200 ns for fastest instruction when using 20.0MHz clock  
- High code efficiency-most instructions are single byte  
- 16 x 16 multiply and 32 x 16 divide  
- Eight vectored interrupt sources  
- Four 16-bit timer/counters with 4 synchronous outputs and WATCHDOG logic  
- MICROWIRE/PLUS serial I/O interface  
- CMOS-very low power with two power save modes: IDLE and HALT  
- UART-full duplex, programmable baud rate  
- Four additional 16-bit timer/counters with pulse width modulated outputs  
- Four input capture registers  
- 52 general purpose I/O lines (memory mapped)  
- 8k bytes of ROM, 256 bytes of RAM on chip  
- ROMless version available (HPC16003)  
- -55 C to +125 C temperature range  
2
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
(Absolute Maximum Ratings)  
(Note 1)  
Total Allowable Source or Sink  
Storage Temperature Range  
Lead Temperature (Soldering, 10 Sec.)  
Vcc with Respect to GND  
100mA  
-65 C to +150 C  
300 C  
-0.5V to 7.0V  
Vcc+0.5V to GND-0.5V  
Voltage All Other Pins  
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur.  
DC and AC electrical specifications are not ensured when operating the device at  
absolute maximum ratings.  
3
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
Electrical Characteristics  
DC PARAMETERS  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
DC: Vcc = 5V +10%  
PIN-  
NAME  
SUB-  
SYMBOL  
Vih1  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
MAX UNIT  
GROUPS  
Logical 1 Input  
Voltage  
RESET, NMI, CKI AND WO, B10-B13, B15  
3, 4  
.9Vcc  
V
1, 2,  
3
Vih2  
Vih3  
Logical 1 Input  
Voltage  
All Inputs Except Port A  
Port A, Vcc = 4.5V  
3, 4  
1
.7Vcc  
3.95  
4.65  
V
1, 2,  
3
Logical 1 Input  
Voltage  
V
V
1, 2,  
3
Port A, Vcc = 5.5V  
1
1, 2,  
3
Vil1  
Vil2  
Vil3  
Logical 0 Input  
Voltage  
RESET, NMI, CKI AND WO  
All Inputs Except Port A  
Port A, Vcc = 4.5V  
3, 4  
3, 4  
2
.1Vcc V  
.2Vcc V  
1, 2,  
3
Logical 0 Input  
Voltage  
1, 2,  
3
Logical 0 Input  
Voltage  
.5  
.7  
V
1, 2,  
3
Port A, Vcc = 5.5V  
2
V
1, 2,  
3
Voh2  
Voh3  
Voh4  
Voh5  
Vol2  
Vol3  
Vol4  
Vol5  
Ioz  
Logical 1 Output Ioh = -7mA (A0-A15, B10-B12, B15, CK2)  
Voltage  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
2.4  
2.4  
2.4  
2.4  
V
1, 2,  
3
Logical 1 Output Ioh3 = -1.6mA (B0-B9, B13-B14, P0-P3),  
V
1, 2,  
3
Voltage  
WO (Open Drain)  
Logical 1 Output Ioh = -6mA (ST1, ST2)  
Voltage  
V
1, 2,  
3
Logical 1 Output Ioh = -1mA (A0-A15, B10-B12, B15) when  
V
1, 2,  
3
Voltage  
used as an external address/data bus  
Logical 0 Output Iol = 3mA (CK2, A0-A15, B10-B12, B15)  
Voltage  
.4  
.4  
.4  
.4  
+5  
+2  
-3  
7
V
1, 2,  
3
Logical 0 Output Iol = .5mA (B0-B9, B13-B14, P0-P3), WO  
V
1, 2,  
3
Voltage  
(Open Drain)  
Logical 0 Output Iol = 1.6mA (ST1, ST2)  
Voltage  
V
1, 2,  
3
Logical 0 Output Iol = 3mA (A0-A15, B10-B12, B15) when  
V
1, 2,  
3
Voltage  
used as an external address/data bus  
TRI-STATE Leakage Vss <= Vin <= Vcc (WO, PORT A, PORT  
B), Vcc = 5.5V  
uA  
uA  
uA  
mA  
1, 2,  
3
Ili1  
Ili2  
Ili3  
Input Leakage  
Current  
Vss <= Vin <= Vcc, Vcc=5.5V (I0-I7,  
D0-D7, CKI, RESET, EXM, EI)  
1, 2,  
3
Input Pullup  
Current  
Vin = 0 (RDY/HLD, EXUI), Vcc=5.5V  
-50  
1
1, 2,  
3
PORT B12 Pulldown Vin = Vcc, PORT B12, Vcc = 5.5V  
During Reset  
3, 4  
1, 2,  
3
4
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
Electrical Characteristics  
DC PARAMETERS(Continued)  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
DC: Vcc = 5V +10%  
PIN-  
NAME  
SUB-  
SYMBOL  
VRAM  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
2.5  
MAX UNIT  
GROUPS  
RAM Keep Alive  
Voltage  
Test Duration is 100mS  
3, 4  
V
1, 2,  
3
Icc1  
Icc2  
Icc3  
Supply Current  
Dynamic  
Fin=20MHz, RESET=Vss, Ioh=0mA,  
Iol=0mA, Vcc=5.5V  
6
6
6
55  
mA  
mA  
mA  
1, 2,  
3
Idle Mode Current Fin=20MHz, External Clock  
3.5  
2
1, 2,  
3
HALT Mode Current NMI = Vcc  
1, 2,  
3
CI  
Input Capacitance ftest=1.0MHz, Input pin to ground  
3
3
10  
20  
pF  
pF  
4
4
CI/O  
Input/Output  
Capacitance  
ftest=1.0MHz, I/O pin to ground  
AC PARAMETERS  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: Vcc = 4.5V and 5.5V  
fC=CKI  
freq.  
Operating  
Frequency  
4
4
4
5
5
4
5
2
20  
MHz 9, 10,  
11  
tC1=1/FC  
Clock Period  
Timing Cycle  
ALE Pulse Width  
50  
100  
41  
18  
100  
nS  
nS  
nS  
nS  
nS  
9, 10,  
11  
tC=2/FC  
9, 10,  
11  
tLL=1/2tC  
-9  
9, 10,  
11  
tST=1/4tC  
-7  
Address Valid to  
ALE Falling Edge  
9, 10,  
11  
tWAIT = tC Wait State Period  
= WS  
9, 10,  
11  
FMW =  
0.0625fC  
External  
Microwire/Plus  
CLK Input Freq.  
1.25  
2.5  
55  
MHz 9, 10,  
11  
fU=0.125fC External UART  
Clock Input  
4
MHz 9, 10,  
11  
Frequency  
tDCIC2  
CK2 Delay From  
CKI  
5, 7  
5
nS  
nS  
9, 10,  
11  
tARR=1/4tC ALE Falling Edge  
-5  
20  
9, 10,  
11  
to RD Falling  
Edge  
tRW=1/2tC+ RD Pulse Width  
WS-10  
5, 8  
140  
nS  
9, 10,  
11  
5
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
Electrical Characteristics  
AC PARAMETERS(Continued)  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: Vcc = 4.5V and 5.5V  
PIN-  
NAME  
SUB-  
GROUPS  
SYMBOL  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
MAX UNIT  
tDR=3/4tC  
- 15  
Data Hold After  
5
0
60  
85  
nS  
nS  
nS  
nS  
nS  
9, 10,  
11  
Rising Edge of RD  
tRD=1/2tC+ RD Falling Edge  
WS-65 to Data In Valid  
5, 8  
9, 10,  
11  
tRDA=tC-15 RD Rising Edge to  
Address Valid  
5
5
5
85  
20  
45  
9, 10,  
11  
tVP=1/4tC- Address Hold from  
5
9, 10,  
11  
ALE Falling Edge  
tARW=1/2tC ALE Trailing Edge  
-5  
9, 10,  
11  
to WR Falling  
Edge  
tWW=3/4tC+ WR Pulse Width  
WS-15  
5, 8  
5
160  
20  
nS  
nS  
9, 10,  
11  
tHW=1/4tC- Data Hold After  
9, 10,  
11  
5
Trailing Edge of  
WR  
tV=1/2tC  
+ WS-5  
Data Valid Before  
Rising Edge of WR  
5, 8  
5, 8  
145  
nS  
nS  
9, 10,  
11  
tDAR=1/4tC Falling Edge of  
+WS-50  
75  
9, 10,  
11  
ALE to Falling  
Edge of RDY  
tRWP=tC  
tSALE =  
RDY Pulse Width  
5
5
100  
115  
nS  
nS  
9, 10,  
11  
Falling Edge of  
3/4tC + 40 HLD to Rising  
Edge of ALE  
9, 10,  
11  
tHWP=tC+10 HLD Pulse Width  
5
5
110  
nS  
nS  
9, 10,  
11  
tHAD=3/4tC Rising Edge on  
160  
200  
116  
9, 10,  
11  
+85  
HLD to Rising  
Edge on HLDA  
tHAE = tC  
+ 100  
Falling Edge on  
HLD to Falling  
Edge on HLDA  
5, 9  
nS  
nS  
nS  
nS  
9, 10,  
11  
tBF=1/2tC  
+ 66  
BUS Float After  
Falling Edge on  
HLDA  
5
5
5
9, 10,  
11  
tBE=1/2tC  
+ 66  
BUS Enable From  
Rising Edge of  
HLDA  
116  
10  
9, 10,  
11  
tUAS  
Address Setup  
Time to Falling  
Edge of URD  
9, 10,  
11  
6
MILITARY DATA SHEET  
MNHPC16003-20-X REV 0A0  
Electrical Characteristics  
AC PARAMETERS(Continued)  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: Vcc = 4.5V and 5.5V  
PIN-  
NAME  
SUB-  
SYMBOL  
tUAH  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
10  
MAX UNIT  
GROUPS  
Address Hold Time  
From Rising Edge  
of URD  
5
nS  
9, 10,  
11  
tRPW  
tOE  
URD Pulse Width  
5
5
5
100  
nS  
9, 10,  
11  
URD Falling Edge  
to Data Out Vaild  
60  
70  
nS  
nS  
9, 10,  
11  
tDRDY  
RDRDY Delay From  
Rising Edge of  
URD  
9, 10,  
11  
tWDW  
tUDS  
UWR Pulse Width  
5
5
40  
10  
nS  
nS  
9, 10,  
11  
Data Invalid  
Before Trailing  
Edge of UWR  
9, 10,  
11  
tUDH  
tA  
Data In Hold  
After Rising Edge  
of UWR  
5
5
20  
nS  
nS  
9, 10,  
11  
WRRDY Delay From  
Rising Edge of  
UWR  
70  
9, 10,  
11  
Note 1: PORT A Vih test limit includes 700mV offset caused by output loads being on during  
Data Drive Time.  
Note 2: PORT A Vil test limit includes 400mV offset caused by output loads being on during  
Data Drive Time  
Note 3: Verified at initial qual only  
Note 4: Tested in functional patterns. Not directly measured  
Note 5: CL=70pF. AC testing inputs are driven at Vih for a logic 1 and Vil for a logic 0.  
Output timing measurements are made at 2.0V for a logic 1 and 0.8V for a logic 0.  
Note 6: Icc1,Icc2,Icc3 measured with no external drive(Ioh=Iol=0,Iih=Iil=0). Icc1 measured  
with RESET=Vss. Icc3 measured with NMI=Vcc, CKI driven to Vih1 and Vil1, with rise  
and fall times less than 10nS.  
Note 7: These AC characteristics are guaranteed with external clock drive on CKI having 50%  
duty cycle and with less than 15pF load on CKO with rise and fall times (tCKIR and  
tCKIL) on CKI input less than 2.5nS.  
Note 8: WS = tWAIT*number of pre-programmed wait states. Min and Max values are calculated  
from Max operating frequency, Tc = 20MHz, with one wait state programmed.  
Note 9: tHAE is spec'd for case with HLD falling edge occurring at the latest time it can be  
accepted during the present CPU cycle being executed. If HLD falling edge occurs  
later, tHAE as long as (3tC + 4WS + 72tC +90) may occur depending on the following  
CPU instruction cycles, its wait state and ready input.  
7
MNHPC16003-20-X REV 0A0  
Burn-in/QCI Electrical End-Point Tests  
OP#  
Operation description  
Sub-Groups  
1,2,9,10  
01 (When Required) for Group C and D  
Graphics and Diagrams  
GRAPHICS#  
DESCRIPTION  
5864HRA1  
P000006A  
U68CRB  
PIN GRID ARRAY, CERAMIC, 68 PIN (B/I CKT)  
PIN GRID ARRAY, CERAMIC, 68 PIN (PIN OUT)  
PIN GRID ARRAY, CERAMIC, 68 PIN (P/P DWG)  
See attached graphics following this page.  
8
9 8 7 6 5 4 3 2 16867666564636261  
10 60  
I7  
I6  
D0  
D1  
D2  
D3  
EI  
CKO  
I0  
I1  
9 7 5 3 1 67656361  
10118 6 4 2 6866646260  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
ST1  
ST2  
1213  
1415  
1617  
1819  
2021  
2223  
2425  
5958  
5756  
5554  
5352  
5150  
4948  
4746  
RESET  
A0  
A1  
TOP  
D4  
D5  
D6  
D7  
EXM  
P0  
P1  
P2  
P3  
NC  
A2  
A3  
A4  
VIEW  
A5  
A6  
A7  
RDY/HLD  
CK2  
DGND  
2628303234363840424544  
272931333537394143  
2728293031323334353637383940414243  
HPC003U20/883, HPC083XXX/U/883  
HPC004U20/883, HPC064XXX/U/883  
CONNECTION DIAGRAM  
68 - LEAD PGA (TOP VIEW)  
P000006A  

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