GRM188R71H103KA01D_技术文档

User's Guide

SLAU443–May 2012

EEG Front-End Performance Demonstration Kit

This user's guide describes the characteristics, operation, and use of the ADS1299EEG-FE. This EVM is

an evaluation module for the ADS1299, an eight-channel, 24-bit, low-power; integrated analog front-end

(AFE) designed for electroencephalography (EEG) applications. The ADS1299ECG-FE is intended for

prototyping and evaluation. This user's guide includes a complete circuit description, schematic diagram,

and bill of materials.

The following related documents are available through the Texas Instruments web site at www.ti.com.

Device

Literature Number

ADS1299

SBAS499

Contents

1

2

ADS1299EEG-FE Overview ............................................................................................... 4

1.1

1.2

Important Disclaimer Information ................................................................................ 4

Information about Cautions and Warnings ..................................................................... 4

Overview ..................................................................................................................... 5

2.1

2.2

2.3

2.4

2.5

Introduction ......................................................................................................... 5

Supported Features ................................................................................................ 5

Features Not Supported in Current Version .................................................................... 5

ADS1299EEG-FE Hardware ..................................................................................... 5

Factory Default Jumper Settings ................................................................................. 6

3

4

Software Installation ........................................................................................................ 7

3.1

3.2

3.3

Minimum Requirements ........................................................................................... 7

Installing the Software ............................................................................................. 7

Install the ADS1299 EVM Hardware Drivers ................................................................. 10

ADS1299EEG-FE Daughter Card Hardware Introduction ........................................................... 13

4.1

4.2

4.3

4.4

4.5

4.6

Power Supply ..................................................................................................... 14

Clock ............................................................................................................... 15

Reference .......................................................................................................... 16

Accessing ADS1299 Analog Signals .......................................................................... 16

Accessing ADS1299 Digital Signals ........................................................................... 16

Analog Inputs ..................................................................................................... 17

5

Using the Software: ADS1299 Control Registers and GUI .......................................................... 18

5.1

5.2

5.3

5.4

5.5

5.6

Overview and Features .......................................................................................... 18

Global Channel Registers ....................................................................................... 19

Channel Control Registers ...................................................................................... 19

GPIO and Other Registers ...................................................................................... 23

Lead-Off and BIAS Registers ................................................................................... 23

Register Map ...................................................................................................... 26

6

7

ADS1299EEG-FE Analysis Tools ....................................................................................... 27

6.1

6.2

6.3

Scope Tab ......................................................................................................... 27

Histogram Tool .................................................................................................... 28

FFT Tool ........................................................................................................... 29

EEG Specific Features .................................................................................................... 32

Reference Signal and Patient Bias Signal .................................................................... 32

7.1

SPI is a trademark of Motorola.

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7.2

7.3

Lead-Off Detection ............................................................................................... 36

External Calibration/Test Signals ............................................................................... 40

8

9

Test Options on the EVM ................................................................................................. 43

8.1

8.2

8.3

8.4

8.5

8.6

On Chip (ADS1299) Input Short ................................................................................ 43

External Input Short with 5K Resistor .......................................................................... 44

Noise with Common Reference on Negative Inputs ......................................................... 46

Noise with Buffered Common Reference Input ............................................................... 48

Internally Generated Test Signal and Other Multiplexer Inputs ............................................ 49

Arbitrary Input Signal ............................................................................................. 49

Bill of Materials, Layouts and Schematics ............................................................................. 50

9.1

9.2

9.3

9.4

ADS1299EEG-FE Front-End Board Schematics ............................................................. 50

Printed Circuit Board Layout .................................................................................... 53

Bill of Materials .................................................................................................... 57

ADS1299EEG-FE Power-Supply Recommendations ....................................................... 59

List of Figures

1

ADS1299EEG-FE Kit.......................................................................................................

Executable to Run ADS1299 Software Installation.....................................................................

Initialization of ADS1299EEG-FE.........................................................................................

License Agreement .........................................................................................................

Installation Process .........................................................................................................

USBStyx Driver Preinstallation............................................................................................

6

7

8

9

2

3

4

5

6

7

Completion of ADS1299 Software Installation......................................................................... 10

New Hardware Wizard.................................................................................................... 10

New Hardware Wizard Screen 3 ........................................................................................ 11

Completion of the Initial USB Drive ..................................................................................... 11

Second 'New Hardware" Wizard ........................................................................................ 12

Install the USBStyx Driver................................................................................................ 12

ADS1299 EEG-FE Front End Block Diagram ......................................................................... 14

Input Configurations Supported by the EEG-FE a) Differential Inputs b) Single ended inputs.................. 17

File Save Option Under 'Save' Tab ..................................................................................... 18

Channel Registers GUI for Global Registers .......................................................................... 19

Input Multiplexer for a Single Channel (MAIN = [000 or 110 or 111]) .............................................. 20

Channel Control Registers GUI Panel.................................................................................. 20

Register Bit for SRB1 Routing ........................................................................................... 21

Internal Test Signals ...................................................................................................... 21

Simplified Diode Arrangement ........................................................................................... 22

Eight Channel Read of Internal Temperature Data ................................................................... 22

GPIO Control Register GUI Panel....................................................................................... 23

LOFF_STATP and LOFF_STATN Comparators ...................................................................... 24

LOFF_SENSP and LOFF_SENSN Registers GUI Panel ............................................................ 24

Lead-Off Status Indicator................................................................................................. 25

BIAS_SENSP and BIAS_SENSN GUI Panel.......................................................................... 26

Device Register Settings ................................................................................................. 26

Scope Tool Features...................................................................................................... 27

Zoom Option on the Waveform Examination Tool .................................................................... 28

Histogram Bins for Input Short Noise................................................................................... 29

Analysis : FFT Graph of Input Short Test .............................................................................. 30

Analysis : FFT : AC Analysis Parameters : Windowing Options .................................................... 31

Analysis : FFT : FFT Analysis : Input Short Condition................................................................ 31

Changing the User-Defined Dynamic Range for Channel 1 ......................................................... 32

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9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

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36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

Dedicated Reference and Bias Electrode .............................................................................. 33

Programmable reference and bias electrode .......................................................................... 34

Settings for Normal Electrode............................................................................................ 35

Configuring BIASREF and Bias Drive Buffer .......................................................................... 35

Setting up the Bias Drive Loop .......................................................................................... 36

Setting the LOFF Register Bits .......................................................................................... 37

Configuring the Lead Off Comparator .................................................................................. 37

Lead off Status Registers ................................................................................................ 37

Scope tab for Impedance Measurement at 31.25Hz ................................................................. 38

FFT Analysis for Impedance Measurement at 31.25Hz.............................................................. 39

Scope Tab for Impedance Measurement at fDR/4 (DR = 4ksps) ................................................... 40

Multiplexer Setting for Calibration with Electrode Disconnected .................................................... 41

Multiplexer Setting with Positive Electrode Connected to Test Signal ............................................. 42

Multiplexer Setting with Both Electrodes Connected to Test Signal................................................ 42

Channel Setting for Input Short Test.................................................................................... 43

Global Register Settings for Input Short Test.......................................................................... 43

Scope Tab for Input Short Test.......................................................................................... 44

Global Register Settings for External Input Short Test ............................................................... 45

Scope Showing Noise for Input Short with 5k Resistors ............................................................. 45

MISC1 Register Setting for SRB1....................................................................................... 46

Noise with Negative Input Connected to SRB1 Pin................................................................... 47

Noise with OPA376 in SRB1 Path ...................................................................................... 48

Scope Tab with Sinusoidal Inputs on AIN1 ............................................................................ 49

ADS1299EEG-FC Schematic ........................................................................................... 50

ADS1299EEG-FC Jumper Schematic ................................................................................. 51

ECG Power Supplies ..................................................................................................... 52

External Reference Drivers (Not Installed) ............................................................................ 53

ECG MDK Board Interface Adapter..................................................................................... 53

ADS1299EEG-FE Top Assembly ....................................................................................... 54

ADS1299EEG-FE Top Layer ............................................................................................ 54

ADS1299EEG-FE Internal Layer (1).................................................................................... 55

ADS1299EEG-FE Internal Layer (2).................................................................................... 55

ADS1299EEG-FE Bottom Layer ........................................................................................ 56

ADS1299EEG-FE Bottom Assembly.................................................................................... 56

Recommended Power Supply for ADS1299EEG-FE................................................................. 59

List of Tables

1

2

3

4

5

6

7

8

9

10

Factory Default Jumper Settings..........................................................................................

6

Power Supply Test Points................................................................................................ 15

Analog Supply Configurations ........................................................................................... 15

Digital Supply Configurations ............................................................................................ 15

Clock Jumper Options .................................................................................................... 15

External Reference Jumper Options.................................................................................... 16

Test Signals ................................................................................................................ 16

Serial Interface Pin Out................................................................................................... 16

Dedicated Reference Drive Options through REF_ELEC............................................................ 33

Bill of Materials............................................................................................................. 57

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ADS1299EEG-FE Overview

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1

ADS1299EEG-FE Overview

1.1 Important Disclaimer Information

CAUTION

Notice: The ADS1299EEG-FE is intended for feasibility and evaluation testing

only in laboratory and development environments. This product is not for

diagnostic use.

The ADS1299EEG-FE is to be used only under these conditions:

•

The ADS1299EEG-FE is intended only for electrical evaluation of the features of the ADS1299 device

in a laboratory, simulation, or development environment.

The ADS1299EEG-FE is not intended for direct interface with a patient, patient diagnostics, or with a

defibrillator.

The ADS1299EEG-FE is intended for development purposes ONLY. It is not intended to be used as all

or part of an end-equipment application.

The ADS1299EEG-FE should be used only by qualified engineers and technicians who are familiar

with the risks associated with handling electrical and mechanical components, systems, and

subsystems.

•

You are responsible for the safety of yourself, your fellow employees and contractors, and your co-

workers when using or handling the ADS1299EEG-FE. Furthermore, you are fully responsible for the

contact interface between the human body and electronics; consequently, you are responsible for

preventing electrical hazards such as shock, electrostatic discharge, and electrical overstress of

electric circuit components.

1.2 Information about Cautions and Warnings

This document contains caution statements. The information in a caution statement is provided for your

protection. Be sure to read each caution carefully.

CAUTION

This is an example of a caution statement. A caution statement describes a

situation that could potentially damage your software or equipment.

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Overview

2

Overview

2.1 Introduction

The ADS1299EEG-FE is intended for evaluating the ADS1299 low-power, low noise 24-bit, simultaneously

sampling, eight-channel front-end for EEG applications. The digital SPI™ control interface is provided by

the MMB0 Modular EVM motherboard (Rev. D or higher) that connects to the ADS1299EEG FE

evaluation board (Rev A). The ADS1299EEG-FE (see Figure 1) is NOT a reference design for EEG

applications; rather, its purpose is to expedite evaluation and system development. The output of the

ADS1299 yields a raw, unfiltered EEG signal.

The MMB0 motherboard allows the ADS1299EEG-FE to be connected to the computer via an available

USB port. This manual shows how to use the MMB0 as part of the ADS1299EEG-FE, but does not

provide technical details about the MMB0 itself.

Throughout this document, the abbreviation EVM and the term evaluation module are synonymous with

the ADS1299EEG-FE.

2.2 Supported Features

Hardware Features:

•

Configurable for bipolar or unipolar supply operation

Configurable for internal and external clock and reference via jumper settings

Configurable for dc-coupled inputs

External bias electrode drive

Option to provide a common reference to all channels negative terminals.

Option to select any electrode as reference electrode

Option to choose any electrode as bias electrode

External shield drive amplifier

Software Features:

•

Analysis tools including a virtual oscilloscope, histogram, FFT.

Data export for post-processing of raw EEG data

2.3 Features Not Supported in Current Version

NOTE:

The following features are NOT SUPPORTED by the current version of the evaluation kit.

•

Real-time data processing

AC lead-off detection filters

2.4 ADS1299EEG-FE Hardware

Figure 1 shows the hardware included in the ADS1299EEG-FE kit. Contact the factory if any component is

missing. Also, it is highly recommended that you check the TI website at http://www.ti.com to verify that

you have the latest software.

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Overview

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Figure 1. ADS1299EEG-FE Kit

The complete kit includes the following items:

•

ADS1299EEG FE printed circuit board (PCB), Rev A

MMB0 (Modular EVM motherboard, Rev D or higher)

Universal ac to dc wall adapter, 120V to 240V ac to +6V dc

2.5 Factory Default Jumper Settings

Table 1. Factory Default Jumper Settings

Jumper Name Settings

Comment

JP1

JP2

Not Installed

Used for programmable bias drive.

Unipolar analog supply (AVDD = 5V)

Related to external reference generation circuitry

5V supply to board

2-3

JP3

Not Installed

JP4

1-2

JP5

Not Installed

Option to provide hardware PWDN signal.

BIAS_ELEC to onboard midsupply

JP6

1-2

JP7

1-2

Route REF_ELEC to buffer input (buffer output is not used by default)

Route REF_ELEC directly to SRB1

Related to shield drive circuitry

JP8

1-2

JP17

JP18

JP19

JP20

JP21

JP22

JP23

JP24

Not Installed

2-3

1-2

2-3

1-2

2-3

Clock from Oscillator on the EVM

Power for Oscillator on the EVM

Unipolar supply (AVSS = 0V)

CLKSEL = 0

Digital supply (DVDD =3.3)

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Software Installation

Table 1. Factory Default Jumper Settings (continued)

Jumper Name Settings

Comment

JP25

1-2/ 3-4/5-6

– BIAS_ELEC connected to all INPs

– BIAS_ELEC connected to all INMs

– BIAS_ELEC shorted to REF_ELEC which connects to SRB1

connect jumpers on all channels

J6

5-6/ 7-8/ 9-10/ … 32-34 / 35-36

3

Software Installation

3.1 Minimum Requirements

Before installing the software that is intended for use with the EVM kit, verify that your PC meets the

minimum requirements outlined in this section.

3.1.1

Required Setup for ADS1299EEG-FE Software

Install the software on a PC-compatible computer that meets these specifications:

•

Pentium III®/ Celeron® processor, 866MHz or equivalent

Minimum 256MB of RAM (512MB or greater recommended)

USB 1.1-compatible input

Hard disk drive with at least 200MB free space

Microsoft® Windows® XP operating system with SP2 (Windows Vista and Windows 7 are NOT

supported at this time)

•

Mouse or other pointing device

1280 x 960 minimum display resolution

3.2 Installing the Software

CAUTION

Do not connect the ADS1299EEG-FE hardware before installing the software

on a suitable PC. Failure to observe this caution may cause Microsoft Windows

to not recognize the ADS1299EEG-FE.

The latest software is available from the TI web site at www.ti.com\ads1299. Check the ADS1299 Product

Folder on the TI web site regularly for updated versions.

To install the ADS1299 software, click on the executable shown in Figure 2. Then follow the prompts

illustrated in Figure 3 through Figure 7.

Figure 2. Executable to Run ADS1299 Software Installation

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Figure 3. Initialization of ADS1299EEG-FE

You must accept the license agreement (shown in Figure 4) before you can proceed with the installation.

Figure 4. License Agreement

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Software Installation

Figure 5. Installation Process

Figure 6. USBStyx Driver Preinstallation

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Figure 7. Completion of ADS1299 Software Installation

3.3 Install the ADS1299 EVM Hardware Drivers

Apply power to the MMB0 using the supplied wall mount power supply and connect the MMB0 to your PC

via any available USB port. There are two USB drivers which will be installed. Follow the steps shown in

the figures below to install the USB drivers.

Figure 8. New Hardware Wizard

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Software Installation

Figure 9. New Hardware Wizard Screen 3

Click Next and allow the wizard to find and install the driver.

Figure 10. Completion of the Initial USB Drive

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3.3.1

Initial Launch of the ADS1299EEG FE Software

Launch ADS1299EEG FE software from the program menu. The software will load and begin downloading

firmware to the processor on data capture card (MMB0). Once the firmware is loaded and running, it will

cause the USB to re-enumerate.

Figure 11. Second 'New Hardware" Wizard

Click Next

Figure 12. Install the USBStyx Driver

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ADS1299EEG-FE Daughter Card Hardware Introduction

By this time the ADS1299EEG FE software will have prompted the user an with error message. Click ‘OK’.

It may be necessary to close the program, power cycle the ADS1299EEG FE and restart the program.

This process may need to be done again should you plug the ADS1299ECG FE into a different USB port

on your computer.

4

ADS1299EEG-FE Daughter Card Hardware Introduction

CAUTION

Many of the components on the ADS1299EEG-FE are susceptible to damage

by electrostatic discharge (ESD). Customers are advised to observe proper

ESD handling procedures when unpacking and handling the EVM, including the

use of a grounded wrist strap, bootstraps, or mats at an approved ESD

workstation. An electrostatic smock and safety glasses should also be worn.

The ADS1299 ECG front-end evaluation board is configured to be used with the TI MMB0 data converter

evaluation platform. The key features of the ADS1299 system on a chip (SOC) are:

•

Eight integrated INAs and eight 24-bit high-resolution ADCs

Low channel noise of 1uVpp for 65Hz bandwidth

Low power consumption (5mW/channel)

Data rates of 250SPS to 16kSPS

5V unipolar or bipolar analog supply, 1.8V to 3.6V digital supply.

DC /AC Lead off detection

On-chip oscillator

On-chip bias amplifier

Versatile MUX to enable programmable reference and bias electrode

SPI data interface

The ADS1299EEG-FE can be used to evaluate the performance of ADS1299 chip. Users can provide any

type of signal directly to the ADS1299 through a variety of hardware jumper settings (J6, JP25). External

support circuits are provided for testing purposes such as external references, clocks, lead-off resistors,

and shield drive amplifiers.

Figure 13 shows the functional block diagram with important jumper names for the EVM.

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Figure 13. ADS1299 EEG-FE Front End Block Diagram

The ADS1299EEG-FE board is a four-layer circuit board. The board layout is provided in Section 9; the

schematics are appended to this document. The following sections explain some of the hardware settings

possible with the EVM for evaluating the ADS1299 under various test conditions.

4.1 Power Supply

The EEG front-end EVM mounts on the MMB0 EVM with connectors J2, J3 and J4. The main power

supplies (+5V, +3V and +1.8V) for the front-end board are supplied by the host board (MMB0) through

connector J4. All other power supplies needed for the front-end board are generated on board by power

management devices. The EVM is shipped in +5V unipolar supply configuration.

The ADS1299 can operate from +5.0V analog supply (AVDD/AVSS) and +1.8V to +3.0V digital supply

(DVDD). A bipolar analog supply (±2.5V) can be used as well. The analog power consumption of the front-

end board can be measured by the current flowing through the JP2 jumper and JP20 jumper. The

ADS1299 can be powered down by shorting jumper JP5.

Test points TP5, TP6, TP7, TP8, TP9, TP10, and TP14 are provided to verify that the host power supplies

are correct. The corresponding voltages are shown in Table 2.

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ADS1299EEG-FE Daughter Card Hardware Introduction

Table 2. Power Supply Test Points

Test Point

TP7

Voltage

+5.0V

+1.8V

+3.3V

+5.0V

+2.5V

–2.5V

GND

TP9

TP10

TP5

TP13

TP6

TP8

The front-end board must be properly configured in order to achieve the various power-supply schemes.

The default power-supply setting for the ADS1299EEG-FE is a unipolar analog supply of 5V and DVDD of

either +3V or +1.8V. Table 3 shows the board and component configurations for each analog power-

supply scheme; Table 4 shows the board configurations for the digital supply.

Table 3. Analog Supply Configurations

Unipolar Analog Supply

5V

Bipolar Analog Supply

Power Supplies

±2.5V

1-2

JP2 (AVDD)

JP20 (AVSS)

U8

2-3 (default)

1-2 (default)

Don’t Care

2-3

TPS72325

TPS73225

U9

Don’t Care

Table 4. Digital Supply Configurations

DVDD

+3.0V

+1.8V

JP24

2-3 (default)

1-2

4.2 Clock

The ADS1299 has an on-chip oscillator circuit that generates a 2.048MHz clock (nominal). This clock can

vary by ±5% over temperature. For applications that require higher accuracy, the ADS1299 can also

accept an external clock signal. The ADS1299EEG-FE provides an option to test both internal and

external clock configurations. It also provides an option to generate the external clock from either the

onboard oscillator or from an external clock source.

The onboard oscillator is powered by the DVDD supply of the ADS1299. Care must be taken to ensure

that the external oscillator can operate either with +1.8V or +3.0V, depending on the DVDD supply

configuration. Table 5 shows the jumper settings for the three options for the ADS1299 clocks.

Table 5. Clock Jumper Options

ADS1299 Clock

JP18

Internal Clock from the ADS1299

Not Installed

Clock from Oscillator on the EVM

External Clock Source

1-2

2-3 (default)

1-2

JP19

Don’t Care

J3– pin 17

Don’t Care

External Clock Source

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A 2.048MHz oscillator available for +3V and +1.8V DVDD is the FXO-HC735-2.048MHz and SiT8002AC-

34-18E-2.048, respectively. The EVM is shipped with the external oscillator enabled.

4.3 Reference

The ADS1299 has an on-chip internal reference circuit that provides reference voltages to the device.

Alternatively, the internal reference can be powered down and VREFP can be applied externally. This

configuration is achieved with the external reference generator (U3) and driver buffer. The EVM has the

footprints for the necessary circuitry, but the components are not installed at the factory.

The external reference voltage can be set to 4.096V. Measure TP3 to make sure the external reference is

correct. The setting for the external reference is described in Table 6.

Table 6. External Reference Jumper Options

Internal Reference

VREF = 4.5V

External Reference

VREFP = 4.096V

Installed

ADS1299 Reference

JP3

Not Installed

The software uses the VREF value entered in the Global Registers control tab (refer to Section 5.2) to

calculate the input-referred voltage value for all the tests. The default value is 4.5V. If any other value is

used, the user must update this field in the Global Registers control tab.

4.4 Accessing ADS1299 Analog Signals

Some ADS1299 output signals are provided as test points for probing purposes through J5. Table 7 lists

the various test signals with the corresponding test points.

Table 7. Test Signals

Signal

RESERVE

GPIO4

J5 Pin Number

Signal

1

3

5

7

9

2

4

RESERVE

PWDNB

6

GPIO3

8

Daisy_in

AGND

10

RESERVE

4.5 Accessing ADS1299 Digital Signals

The ADS1299 digital signals (including SPI interface signals, some GPIO signals, and some of the control

signals) are available at connector J3. These signals are used to interface to the MMB0 board DSP. The

pin out for this connector is given in Table 8.

Table 8. Serial Interface Pin Out

Signal

START/CS

CLK

J3 Pin Number

Signal

CLKSEL

GND

1

3

2

4

NC

5

6

GPIO1

RESETB

GND

CS

7

8

NC

9

10

12

14

16

18

20

DIN

11

13

15

17

19

GPIO2

NC/START

SCL

DOUT

DRDYB

EXT_CLK

NC

GND

SDA

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ADS1299EEG-FE Daughter Card Hardware Introduction

4.6 Analog Inputs

The ADS1299EEG-FE is designed so that it can be used as a eight channel data acquisition board.

Arbitrary input signals can be fed to the ADS1299 by feeding the signal directly at connector J6. Figure 14

shows the input configurations that are available in the EVM.

Figure 14. Input Configurations Supported by the EEG-FE a) Differential Inputs b) Single ended inputs

4.6.1

Differential Inputs

To digitize eight differential inputs,

1. Set all jumpers to factory defaults as described in Section 2.5.

2. Remove jumpers from pin 7-36 of J6.

3. Provide the differential inputs on the even pins 8-36 of J6.

While used with differential inputs, care needs to be taken to ensure that the analog inputs are within the

input common mode range of the PGA. If the input differential signal is centered around 0V, the ADS1299

needs to be operated with a bipolar supply. Refer to Section 4.1 for details on setting the EVM to operate

with a bipolar supply.

4.6.2

Single Ended Inputs

For single ended inputs the measurement can be done with respect to the voltage applied to the SRB1 pin

of the ADS1299. To digitize eight single ended inputs,

1. Set all jumpers to factory defaults as described in

2. Remove jumpers from pin 7-36 of J6.

3. Short pin 5 and 6 of JP6. Set the SRB1 bit in the MISC1 register to route the SRB1 pin to the negative

input of the channels (refer to Section 8.3 for details). This will route BIAS_ELEC (mid supply) to the

negative inputs of the channels through the SRB1 pin.

4. Provide the Single ended inputs to pins 36, 32, 28, 24, 20, 16, 12, 8 of J6 for channels 1-8

respectively.

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Apart from providing the option to feed inputs directly at the jumper (for general purpose data acquisition),

the ADS1299 EVM provides multiple configurations specific to the EEG application. These configurations

are explained in detail in Section 7.

5

Using the Software: ADS1299 Control Registers and GUI

Before starting to use the EVM software, there is one important feature that users should be aware of. The

software GUI contains a Save tab that allows all data from any combination of channels to be saved in a

given directory location with notes to describe the saved data. Figure 15 shows the Save tab options.

Figure 15. File Save Option Under 'Save' Tab

5.1 Overview and Features

This section provides a quick overview of the various features and functions of the ADS1299EEG-FE

software package.

There are four primary tabs across the left side of the GUI:

•

About tab: Provides information about the EVM and software version revisions.

ADC Register tab: Includes all of the control registers for the ADS1299, in a series of related sub-tabs:

–

Channel Registers tab

LOFF and BIAS tab

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–

GPIO and Other Registers tab

Register Map tab

•

Analysis tab: Provides different ways to analyze captured data in the time or frequency domain, with a

series of related sub-tabs:

–

Scope tab

FFT tab

Histogram tab

•

Save tab: Provides options for saving data

5.2 Global Channel Registers

The first section under the Channel Registers→Global Channel Registers tab allows the user to

manipulate the entire ADS1299 configuration and lead-off registers. The Global Channel Registers box

includes Configuration Register 1 (controls daisy-chain/MRB mode, clock connection, and data rate);

Configuration Register 2 (controls internal test source amplitude and frequency); Configuration Register 3

(controls the reference buffer power-up/-down processes, the reference voltage, the bias drive

enable/disable, and the bias reference); and the Lead-Off Control Register (controls the comparator

threshold and the magnitude and frequency of the lead-off signal). shows the GUI panel to manipulate

these registers and the respective settings for each.

Figure 16. Channel Registers GUI for Global Registers

5.3 Channel Control Registers

The second section under the Channel Registers tab is the Channel Control Registers box. This panel

allows the user to uniquely configure the front-end MUX for each channel. Additionally, at the top of the

Channel Control Registers box is the option to globally set all channels to the same setting. The channel-

specific MUX is illustrated in Figure 17. The panel snapshot for the channel control registers is shown in

Figure 18. Figure 19 shows the register bit to control the switches which connect all channels negative

input to SRB1 pin. This bit is located in “GPIO and other registers” tab.

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Figure 17. Input Multiplexer for a Single Channel (MAIN = [000 or 110 or 111])

Figure 18. Channel Control Registers GUI Panel

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Figure 19. Register Bit for SRB1 Routing

5.3.1

Internal Test Signals Input

Configuration Register 2 controls the signal amplitude and frequency of an internally-generated square

wave test signals. The primary purpose of this test signal is to verify the functionality of the front-end MUX,

the PGA, and the ADC. The test signals may be viewed on the Analysis→Scope tab, as Figure 20 shows.

Detailed instructions for using the Analysis→Scope tab is provided in Section 6.1.1.

Figure 20. Internal Test Signals

5.3.2

Temperature Sensor and the Scope Tab

The internal temperature sensor on the ADS1299 is shown in . When the internal MUX is routed to the

temperature sensor input, the output voltage of the ADC may be converted to a temperature value, using

Equation 1.

(1)

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Figure 21. Simplified Diode Arrangement

The output voltage corresponding to a given temperature can be read selecting the Temperature Sensor

option on the Channel Control Registers GUI (see Figure 17) and verified using the Analysis→Scope tab

as shown in Figure 22. The number 0.146V (on the y-axis) can be calculated as a temperature using

Equation 1:

Temperature = (0.146 – 0.145300) / 0.00049 + 25 = 26.4°C

It should be noted that the temperature sensor input cannot be used with a gain setting of 24 as it will

saturate the PGA output.

Figure 22. Eight Channel Read of Internal Temperature Data

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5.3.3

5.3.4

5.3.5

Normal Electrode Input

The Normal electrode input on the MUX routes the inputs (VINP and VINN) differentially to the internal

PGA, as Figure 17 illustrates. An exception is if the SRB1 bit is set high. If channel is in Normal electrode

mode and SRB1 bit is set high the signal on SRB1 pin is routed to negative inputs of all channels instead

of VINN inputs.

MV_DDInput and the Scope Tab

The MV_DDinput option allows the measurement of the supply voltage V_S= (AV_DD+ AV_SS)/2 for channels 1,

2, 5, 6, 7, and 8; however, the supply voltage for channel 3 and 4 will be DV_DD/4. As an example, in

bipolar supply mode, AV_DD= 3.0V and AV_SS= –2.5V. Therefore, with the PGA gain = 1, the output voltage

measured by the ADC will be approximately 0.25V.

Bias Measurement

This measurement takes the voltage at the BIASIN pin and measures it on the PGA with respect to

(AVDD + AVSS)/2 or BIASREF. This option can be used to give a calibration/test signal to ADS1299

device without connecting the calibration/test signal to the electrodes. The positive signal can be applied

to BIASIN pin and the negative input can be applied to the BIASREF pin. More details on this can be

found in Section 7.3.

5.3.6

Bias Positive Electrode Drive and Bias Negative Electrode

This option can be used to have a selectable bias electrode. This option routes the signal on BIASIN pin

to any of positive or negative pins of the channel inputs.

5.4 GPIO and Other Registers

The GPIO and Other Registers tab, located under the Analysis tab, includes controls for GPIO1 through

GPIO4, SRB1 control, pulse mode control and lead off comparators power down. The GPIO registers

control four general-purpose I/O pins. Figure 23 illustrates the GPIO Control Register GUI panel.

Figure 23. GPIO Control Register GUI Panel

5.5 Lead-Off and BIAS Registers

The Lead-Off Detection and Current Control Registers and the Bias Derivation Control Registers are

located under the ADC Register→LOFF and BIAS tab.

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5.5.1

Lead-Off Sense (LOFF_SENSP and LOFF_SENSN) Registers

These registers enable lead-off detection for both the positive and negative channels. Figure 24 describes

the 4-bit DAC settings to configure the lead-off threshold. Note that the LOFF_FLIPx bits change the

direction of the lead-off current if this option is selected. Figure 24 illustrates the connections from the

positive and negative inputs to the lead-off comparators. Figure 25 shows the respective GUI panel on the

EVM software.

Figure 24. LOFF_STATP and LOFF_STATN Comparators

Figure 25. LOFF_SENSP and LOFF_SENSN Registers GUI Panel

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5.5.2

Lead-Off Status Registers (LOFF_STATP and LOFF STATN)

These registers store the output of the lead-off comparator that corresponds with each input. When a lead

is disconnected, the corresponding register bit activates low. The GUI for this feature is enabled by

clicking in the upper right-hand corner of the EVM software on the Show/Poll Lead-Off Status button.

Pressing this button causes a pop-up box that shows the status of the lead-off registers. The GUI shows

when a lead is disconnected by turning its bit from green to red. Figure 26 illustrates the Lead-Off Status

Registers GUI controls.

Figure 26. Lead-Off Status Indicator

5.5.3

Bias Drive Derivation Control Registers

The Bias Drive Derivation Control Registers enable the user to set any combination of positive and/or

negative electrodes to derive the BIAS voltage that is fed to the internal bias drive amplifier. Figure 27

shows the corresponding GUI controls. The details about bias drive can be found in Section 5.5.

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Figure 27. BIAS_SENSP and BIAS_SENSN GUI Panel

5.6 Register Map

The Register Map→ Device Registers tab is a helpful debug feature that allows the user to view the state

of all the internal registers. This tab is illustrated in Figure 28.

Figure 28. Device Register Settings

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ADS1299EEG-FE Analysis Tools

6

ADS1299EEG-FE Analysis Tools

Under the Analysis tab in the ADS1299EEG-FE GUI software, there are four different analysis tools

shown that enable a detailed examination of the signals selected by the front-end MUX:

•

Scope

Analysis

Histogram

FFT

These tools are detailed in the following subsections.

6.1 Scope Tab

6.1.1

Using the Analysis→Scope Tool

The Scope tool (available under the Analysis tab) is a very useful means of examining the exact amplitude

of the measured input signals from each channel. Additionally, users can determine the noise contribution

from each channel at a given resolution, and review the sampling rate, the PGA gain, and the input signal

amplitude. Figure 29 illustrates the Scope tool features.

Figure 29. Scope Tool Features

Waveform Examination Tool

6.1.2

The waveform examination tool allows the user to zoom in either on all channels simultaneously or on a

single channel. Figure 30 shows an example of the waveform examination tool with the magnifying glass

zoomed in on 90 samples.

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Figure 30. Zoom Option on the Waveform Examination Tool

6.2 Histogram Tool

The Histogram tool is located under the Analysis→Histogram tab.

6.2.1

Using the Analysis→Histogram Tool

The Analysis→Histogram tool is used primarily to view the bin separation of the different amplitudes of the

EEG waveform harmonics. Figure 31 illustrates the histogram output for input short on all channels. The

same Signal Zoom analysis may be used on the histogram plots for a more detailed examination of the

amplitude bins. The Analysis table gives the mean of the input signal and also the rms and peak-to-peak

value of the signal on each channel.

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Figure 31. Histogram Bins for Input Short Noise

6.3 FFT Tool

The FFT tool is located under the Analysis→FFT tab.

6.3.1

Using the Analysis→FFT Tool

The Analysis→FFT tool allows the user to examine the channel-specific spectrum as well as typical

figures of merit such as SNR, THD, ENOB, and CMRR. Each feature is numbered below and described in

detail in the following subsections. Figure 32 illustrates an Analysis→FFT plot for input short configuration.

The explanation of different tabs is explained below.

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Figure 32. Analysis : FFT Graph of Input Short Test

Coherent Frequency Calculator: 1

Coherent sampling in an FFT is defined as F_AIN/F_SAMPLE= N_WINDOW/N_TOTAL, where:

•

F_AINis the input frequency

_FSAMPLEis the sampling frequency of the ADS1299

N_WINDOWis the number of odd integer cycles during a given sampling period

N_TOTALis the number of data points (in powers of 2) that is used to create the FFT If the conditions for

coherent sampling can be met, the FFT results for a periodic signal will be optimized. The Ideal A_IN

Frequency is a value that is calculated based on the sampling rate, such that the coherent sampling

criteria can be met.

AC Analysis Parameters: 2

This section of the tool allows the user to dictate the number of harmonics, dc leakage bins, harmonic

leakage bins, and fundamental leakage bins that are used in the creation of various histograms. Pressing

the Windowing button, illustrated in Figure 33, allows the user to evaluate the FFT graph under a variety

of different windows. Note that pressing the Reference button toggles between dBFS (decibels, full-scale)

and dBc (decibels to carrier).

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Figure 33. Analysis : FFT : AC Analysis Parameters : Windowing Options

FFT Analysis: 3

Pressing the FFT Analysis button pulls up the window shown in Figure 34. This window can be useful

because the different tabulated figures of merit can show more detailed information about the channel-to-

channel noise.

Figure 34. Analysis : FFT : FFT Analysis : Input Short Condition

User-Defined Dynamic Range: 4

This section enables the user to examine the SNR of a specific channel within a given frequency band

defined by Low Frequency and High Frequency. The SNR displayed in this window will also show under

the Dynamic Range heading as Figure 35 illustrates.

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Figure 35. Changing the User-Defined Dynamic Range for Channel 1

Input Amplitude: 5

This field is a user input that is important for accurately calculating the CMRR of each channel.

7

EEG Specific Features

This section describes some of the EEG specific features supported by the EVM, including the

reference/patient bias signals, lead off detection and calibration.

7.1 Reference Signal and Patient Bias Signal

A typical EEG system has multiple electrodes (32 up to 256, hereby called as the “normal electrodes”)

connected to the scalp that are used to acquire EEG signals. In addition to these electrode signals, an

EEG system also uses two additional signals, a reference signal and a patient bias signal. The reference

signal is used as the reference for the single ended EEG measurements. The patient bias signal is used

for biasing the patient to set the common mode of the EEG signals (typically mid supply).

Dedicated reference and patient bias electrodes

Many EEG systems have two dedicated electrodes, one used as the reference signal for the EEG

measurement (hereby called as the “reference electrode”) and the other used for the patient bias signal

(hereby called as the “bias electrode”). The EVM has two signals (BIAS_ELEC, REF_ELEC) available at

the connector JP81 that correspond to these two electrodes. The BIAS_DRV signal is similar to the

BIAS_ELEC, but appears as a separate signal at JP80. In future versions of the EVM, BIAS_DRV will be

multiplexed through a jumper to BIAS_ELEC.

Programmable reference and patient bias electrodes

Certain EEG systems provide the flexibility to be able to route the reference and/or the patient bias signals

through any of the normal electrodes.

The internal multiplexer of the ADS1299 provides ample flexibility for

(a) Choosing the voltage applied to these electrodes (Fixed or closed loop),

(b) Being able to route the reference and patient bias signals to either the dedicated electrode or any other

normal electrode.

7.1.1

Using the Dedicated Reference and Patient Bias Electrodes

This is the simplest option for electrode connection and is illustrated in . One dedicated electrode is

chosen as a bias electrode and a potential is applied to it to bias the patient at about mid-supply voltage.

Similarly a fixed electrode is chosen as the reference electrode and all the other electrodes are measured

with respect to this electrode. Below we discuss different options available on the EVM board to connect

the bias electrode BIAS_ELEC/BIAS_DRV and reference electrode REF_ELEC.

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Figure 36. Dedicated Reference and Bias Electrode

Reference : The reference electrode (REF_ELEC) input is used to drive the negative inputs of the

channel through SRB1 pin on ADS1299 device. The reference electrode is connected to the negative

inputs of all the channels. This leads to increased leakage current on the reference electrode since current

of all the channels gets added. The EVM provides an option to buffer the reference electrode to reduce

the leakage. The disadvantage of the buffered approach is the additional noise of the buffer amplifier. The

table below shows the jumper settings for the two options.

Table 9. Dedicated Reference Drive Options through

REF_ELEC

JP7

Don’t care

1-2

JP8

1-2

2-3

Un Buffered

Buffered

Bias : There is an option to provide the bias to a fixed electrode either through BIAS_ELEC or through

BIAS_DRV. BIAS_ELEC option needs an external amplifier U11 to buffer the mid supply. For the

BIAS_DRV option the buffer is built inside the ADS1299 chip. The BIAS_DRV option also helps in

improving common mode rejection by implementing a feedback loop. The details on selecting the inputs

for bias drive are discussed in Section 5.5.3 and Section 7.1.3.

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7.1.2

Programmable Reference and Bias Electrodes

The multiplexer in ADS1299 allows any electrode to be chosen as the bias electrode or reference

electrode. This is illustrated in Figure 37.

Figure 37. Programmable reference and bias electrode

The reference electrode selection is done using SRB2 pin. The SRB2 bit in CHxSET register is set high

for the electrode chosen as reference. This reference is routed out on SRB2 pin and can be routed to

SRB1 pin as a reference for all other channels. On the EVM, a jumper between pin 2 and pin 3 of JP7 and

JP8 is needed for this configuration. In Figure 37, the channel 1 electrode is selected as a reference

electrode and is routed out to SRB2 pin.

The bias selection is done using BIASIN pin. The voltage in this pin can be routed to positive input of any

channel by writing MUX = 110 on the CHxSET register. On the EVM a jumper between pin 2 and pin 3 of

JP6 is required, to route the mid supply to BIASIN. In the illustration in Figure 37 channel 7 is used as a

bias electrode.

7.1.3

Biasing the Patient with a Feedback Loop

There are two options on the EVM board to bias the patient. First option is to use onboard BIAS_ELEC

signal to drive the patient as explained in the earlier section. Second option, which is described below, is

to drive the body with BIAS_DRV signal generated by ADS1299 chip. The advantage of using BIAS_DRV

signal is that it takes advantage of feedback loop to get better common mode rejection. The bandwidth of

the BIAS loop is determined by R8 (390kΩ) and C20 (10nF). Users can change these values to set the

bandwidth based on the specific application. The stability of the loop is determined by the user’s specific

system. Therefore, optimization may be needed on the feedback component values to ensure stability if

additional filtering components and long cables are added before the ADS1299EEG-FE.

The ADS1299 offers full flexibility by letting the user select any combination of the electrodes to generate

the bias voltage. Refer to the ADS1299 data sheet (SBAS499) for more details.

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The reference voltage for the on-chip right leg drive can be driven externally. The on-chip voltage is set to

mid-supply. If the application requires the common mode to be set to any other voltage, this configuration

can be accomplished by setting the appropriate bit in the Configuration 3 Register. The external BIASREF

voltage is set by resistor R1 and adjustable resistor R2.

The following procedure needs to be applied to activate the Bias drive circuitry:

Step 1. Set the inputs to Normal Electrode, refer Figure 38

To Next Chans

INT_TEST

TESTP

ADS1299 Mux

Mux[2:0] =101

Mux[2:0] =100

Mux[2:0] =011

TEMPP

0.75 x VDD

From

LOFFP

CHxSET[3] =1

MAIN

VINP

To PGAP

Mux[2:0] =110

Mux[2:0] = 010

AND BIAS_MEAS

Mux[2:0] = 001

(VREFP+VREFN)

2

Mux[2:0] =111

Mux[2:0] = 001

MAIN AND SRB1

VINN

To PGAN

From

LOFFM

BIASREF_INT=1

BIASREF_INT=0

MAIN AND SRB1

(AVDD+AVSS)

2

Mux[2:0] =010 AND

BIAS_MEAS

Mux[2:0] =011

Mux[2:0] =100

0.25 x VDD

TEMPM

Mux[2:0] =101

INT_TEST

TESTM

NOTE:

MAIN = Mux[2:0] =000 OR Mux[2:0] = 111OR Mux[2:0] = 110

TEST

AC

Figure 38. Settings for Normal Electrode

Step 2. Turn on the bias drive buffer and set the internal bias drive reference; refer to Figure 39.

Figure 39. Configuring BIASREF and Bias Drive Buffer

Step 3. Select the electrodes to be chosen for the bias drive loop. In this case, the channel 1 and 2

input signals are used (as Figure 40 shows).

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Figure 40. Setting up the Bias Drive Loop

Once these steps are completed, measure and verify that the voltage on either side of R8 is close to mid-

supply. This measurement confirms whether the Bias drive loop is functional. Apart from the BIAS_DRV

signal, the ADS1299EEG-FE also offers an option to drive the cable shield. The EEG cable shield signal

can be connected to BIAS_SHD. The jumper (1-2) on JP17 must be shorted to enable the shield drive.

The footprints for the components needed for the shield drive circuitry are available on the board. But the

components are not installed at the factory.

7.2 Lead-Off Detection

The ADS1299 provides multiple schemes to implement the lead-off detection function. These schemes

include current source at dc, at 7.8Hz, 31.2Hz or at f_DR/4. There is also a wide range on the amplitude of

currents available. Refer to the ADS1299 product data sheet (SBAS499) for additional details.

While attempting to use the lead-off detection, care must be taken to analyze the input signal. If the input

signal is dc-coupled, the dc lead-off scheme can be used. If the input signal is ac-coupled, the ac lead-off

scheme must be used. When using the dc lead-off scheme, be sure to bias the patient to set the input

common-mode before activating lead-off detection.

7.2.1

DC Lead-Off

At board power-up, the firmware sets the appropriate registers so that dc lead-off is selected. In the event

of a reset signal, the register values default to the device default settings. In such a scenario, follow this

procedure to reactivate the lead-off circuitry.

Step 1. Make sure the input is dc-coupled and that the bias drive circuit is operational, as explained

in Section 7.1.3

Step 2. Choose the lead-off scheme by setting the respective bits in the LOFF register (in the LOFF

control tab). Select the DC Lead-Off Detect, 6.25nA, Current Source scheme, and set the

comparator threshold to 95%. Select the appropriate inputs for lead-off detection by clicking

the bits of the LOFF_SENSP and LOFF_SENSN Registers. The LOFF tab should appear as

shown in Figure 41.

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Figure 41. Setting the LOFF Register Bits

Step 3. Turn on the lead-off comparator by setting the bit in the Configuration 4 Register in the Global

Registers control tab, as Figure 42 shows.

Figure 42. Configuring the Lead Off Comparator

Step 4. The software has an option where the LOFF_STATP and LOFF_STATM Registers are

continuously polled (set the Read Status Registers switch as shown in shown in Figure 43).

This option allows the user to see the lead-off detection scheme work in real time. Figure 44

shows a case for which only positive electrodes are connected.

Figure 43. Lead off Status Registers

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7.2.2

AC Lead-Off Detection

AC lead off detection can be used in three ways

1. To measure electrode impedance with inband excitation for one time use at electrode placement.

2. To simultaneously measure electrode impedance with EEG, by using out of band excitation.

3. To detect if a lead is off for an AC coupled input.

These options are explained below.

In band Electrode impedance measurement

ADS1299 provides two frequency options (7.8Hz and 31.25Hz) to measure the electrode impedance

within the bandwidth of interest for EEG. There are four amplitude of current source (I_Leadoff) options

available 6nA, 24nA, 6µA and 24µA. The electrode impedance measurement at these frequencies cannot

be done simultaneously with EEG measurements. The voltage developed at the -inputs depends on the

impedance on each electrode and the current used for lead-off detection. If we denote the source

impedance on INP pin as Z_inpand the source impedance on INM pin as Z_inmthe peak to peak voltage

developed on channel input is 2×(I_Leadoff×Z_inp+ I_Leadoff×_Zinm).

As an example Figure 44 shows the snapshot of the scope with 5K impedance on each source with 6µA

of lead-off current at 31.25Hz. We expect a theoretical peak to peak voltage of 120mV. The observed

peak-to-peak voltage is 128mV which is within the tolerance specification of current source. The results

can also be analyzed in frequency domain using the FFT analysis tab as shown in Figure 45. The

magnitude of the fundamental component will be directly proportional to the electrode impedance being

measured.

Figure 44. Scope tab for Impedance Measurement at 31.25Hz

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Figure 45. FFT Analysis for Impedance Measurement at 31.25Hz

Out of band Lead off detection

ADS1299 also provides option to do electrode impedance measurement at frequencies outside the EEG

bandwidth of interest. The frequency for this AC current source is set at f_DR/4. For example to do an AC

lead-off detection at 1 kHz the data rate for the device must be set at 4Ksps. These measurements can be

done concurrently with the EEG measurement. Figure 46 shows the fft result of AC lead off detection at

fDR/4 with data rate of 4Ksps. The impedance component is present at 1KHz and must be bandpass

filtered. The EEG information is at low frequencies and the data must be low pass filtered to extract the

information. It is recommended to use only nA range current sources for concurrent measurement of EEG

and impedance. For µA range the noise from the current source will be too large and it may swamp the

EEG signal.

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Figure 46. Scope Tab for Impedance Measurement at fDR/4 (DR = 4ksps)

7.3 External Calibration/Test Signals

ADS1299 generates a square wave test signal that can be used to check the functionality of the signal

chain (Refer to the datasheet for details). It also gives the user an option to provide external test signals

for calibration. For evaluation purposes with the EVM, the test signals can be provided directly to the

jumpers of the corresponding signals. SRB1 (pin2 of JP8), SRB2 (pin3 of JP7), BIASIN (Pin3 of JP6),

BIASREF (does not appear at a jumper, needs to be soldered to one side of R5).

7.3.1

Channel Inputs Disconnected

It may sometimes be required to provide a calibration or test signal to ADS1299 channel without the signal

being routed to the channel input pins (or electrodes). This can be accomplished by applying the positive

test signal to BIASIN pin and the negative test signal to BIASREF pin. The channel multiplexer must be

set as 010, BIASREF_INT bit in Config 3 register must be set to 0 to choose external BIASREF and

BIAS_MEAS bit in Config 3 must be set to 1. These multiplexer settings are illustrated in Figure 47.

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Figure 47. Multiplexer Setting for Calibration with Electrode Disconnected

7.3.2

Channel Inputs Connected

It may sometimes be required to provide a calibration or test signal to ADS1299 device with the positive

input connected to the pin or electrode. This can be accomplished by connecting the positive test signal to

SRB2 pin and the negative test signal to SRB1 pin. The channel input multiplexer must be set for Normal

Electrode (000), SRB2 switch must be closed and SRB1 switch must be closed. This multiplexer setting is

illustrated in Figure 48.

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Figure 48. Multiplexer Setting with Positive Electrode Connected to Test Signal

If it is desired to have both the input pins connected during calibration or test, the following connections

must be made. The positive test signal must be tied to SRB2 pin and the negative test signal must tie to

BIASIN pin. The channel multiplexer must be set for 111 and the SRB2 switch must be closed. This

multiplexer setting is illustrated in Figure 49.

Figure 49. Multiplexer Setting with Both Electrodes Connected to Test Signal

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Test Options on the EVM

8

Test Options on the EVM

8.1 On Chip (ADS1299) Input Short

The channel input can be shorted internally by setting the input multiplexer of the individual channel to

001. The global registers must be set as shown in Figure 51. The channel control registers must be set as

shown in Figure 50. This test gives the noise in the channel. It also gives the offset in the channel. The

result can be seen in the analysis tab. Figure 52 shows a snapshot of the scope for internal input short

with gain setting of 24. The channel offset in this example is 23uV and noise is less than 1µVpp. 5000pts

at 500sps is taken there by giving data for 10 seconds.

Figure 50. Channel Setting for Input Short Test

Figure 51. Global Register Settings for Input Short Test

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Figure 52. Scope Tab for Input Short Test

8.2 External Input Short with 5K Resistor

There is an option on board to tie the positive and negative input of the channel to a common voltage

(VCM) on BIAS_ELEC through 5K resistors. The following jumper settings are needed for this test. On

JP6 short pin 1 and pin 2. On JP25 short (1-2) and (2-3). The connecter J6 must have jumpers across

from left to right to connect the inputs to the ADS1299 channels. The noise from U11 which is used to

generate the BIAS_ELEC appears as common mode noise for this test and is rejected. Same is true for

noise from resistor R10 in BIAS_ELEC path. The only noise source present are two 5K resistors in the

input path and the channel noise. This test is useful to measure the effect of input bias current on noise.

The PGA in ADS1299 has CMOS input and thus has negligible current noise. The input bias current is as

a result of chopping the PGA to remove flicker noise. This bias current doesn’t manifest itself as noise and

appears like a DC offset in presence of 5K input impedance. The Channel control registers must be

programmed as shown in Figure 53. The results in the analysis tab are shown in Figure 54. The average

peak-to-peak noise for this test is 1.27µV. The increase in noise is due to the noise from 5K resistors. The

two 5K resistors contribute about 0.67µVpp in 65Hz bandwidth.

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Figure 53. Global Register Settings for External Input Short Test

Figure 54. Scope Showing Noise for Input Short with 5k Resistors

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8.3 Noise with Common Reference on Negative Inputs

There is an option in ADS1299 to connect all the channels negative inputs to a common reference. This

can be accomplished by giving a signal on SRB1 pin and setting the bit SRB1 bit in MISC1 register. There

is an option on board to test out the channel noise performance with this setting. On JP81 a jumper on (3-

4) and (5-6) is needed. On JP8 a jumper (1-2) is required. These settings routes the common mode

voltage VCM on BIAS_ELEC to all the positive inputs. It also connects BIAS_ELEC to REF_ELEC via R11

(5K). REF_ELEC is connected to SRB1 pin on ADS1299. The noise in this test includes noise of two 5K

resistors and the channel noise. The SRB1 control switch must be set as shown in Figure 55.The

snapshot of the scope in the analysis tab is shown in Figure 56. The average peak-to-peak noise for this

test is 1.28µV.

Figure 55. MISC1 Register Setting for SRB1

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Figure 56. Noise with Negative Input Connected to SRB1 Pin

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8.4 Noise with Buffered Common Reference Input

Connecting all the negative inputs to one reference electrode can lead to excessive leakage current on the

electrode. The typical leakage current on ADS1299 channel is 200pA. So for a 16 channel system total

leakage may be as large as 3.2nA. This number will become progressively worse as channel count is

increased. If the leakage number is not acceptable there is an option to buffer the common reference input

before connected it to all the negative inputs of the channel. On JP81 jumpers (3-4) and (5-6) are

required. On JP8 a jumper (2-3) is required and on JP7 a jumper (1-2) is needed. The GUI settings are

same as in Figure 56. Figure 57 shows a snapshot of the noise with SRB1 driven by a buffered reference.

The drawback of using the buffer in the SRB1 path is increased noise. The noise contributors in these

settings are two 5k resistors, op amp U4 and ADS1299 channel. As can be seen from the Figure 57 the

noise with this approach is larger than noise in previous three approaches. At present OPA376 is installed

on board for U4. A lower noise op amp can be used if needed.

Figure 57. Noise with OPA376 in SRB1 Path

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Test Options on the EVM

8.5 Internally Generated Test Signal and Other Multiplexer Inputs

ADS1299 internally generates a test signal that can be used for signal integrity check. Also the multiplexer

provides options to measure supply voltage, temperature, etc. Details of these inputs can be found in

Section 5.3.

8.6 Arbitrary Input Signal

Any input signal can be fed to the device on connector J6 as described in Section 4.6. Figure 58 shows

the results obtained when a single ended sinusoidal signal is applied to AIN1 by following the steps

described in Section 4.6.2.

Figure 58. Scope Tab with Sinusoidal Inputs on AIN1

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Bill of Materials, Layouts and Schematics

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9

Bill of Materials, Layouts and Schematics

This section contains the complete bill of materials, printed circuit board (PCB) layouts, and schematic

diagrams for the ADS1299EEG-FE.

NOTE: Board layouts are not to scale. These are intended to show how the board is laid out; do not

use for manufacturing ADS1299EEG-FE PCBs.

9.1 ADS1299EEG-FE Front-End Board Schematics

Figure 59 through Figure 63 shown the schematic diagrams of the ADS1299EEG-FE.

AVDD

C21

NI

AVDD

AGND

2

3

U2

NI

JP17

R18

NI

R4

NI

6

U11_6

1

3

R1

U11_3

BIAS_SHD

4

BIAS_SHD

U11A

NI

R5

NI

AVSS

AVDD

JP1

C22

NI

BIAS_ELEC

AGND

R2

NI

AVSS

R3

0

BIAS_DRV

C3

C20

R8

392K

2

3

R16

NI

0.01uF

6

U4_6

AVSS

R17

NI

U4_3

1uF

C13

AVSS

U4A

NI

VCAP3

AVDD

0.1uF

AVSS

C23

1uF

C76

1uF

C77

1uF

Optional 8-MSOP driver

AVDD

U1

ADS1299

DVDD

AGND

R23

2M

JP6

2

3

64

1

2

3

4

5

6

7

8

52

49

50

32

51

48

47

46

43

44

45

40

39

37

38

34

33

CLKSEL

RESERVED

IN8N

IN8P

IN7N

IN7P

IN6N

IN6P

IN5N

IN5P

IN4N

IN4P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

RESV1

CLKSEL

DGND

DVDD

AVSS

DGND

DVDD

/DRDY

GPIO4

DOUT

GPIO2

GPIO3

SCLK

/CS

CLKSEL

R15

U11_6

6

AIN8N

U11_3

0

AIN8P

AIN7N

AIN7P

AIN6N

AIN6P

AIN5N

AIN5P

AIN4N

AIN4P

AIN3N

AIN3P

AIN2N

AIN2P

AIN1N

AIN1P

U11

OPA376

R24

2M

SPI_DRDY

GPIO4

SPI_OUT

GPIO2

GPIO3

DVDD

SPI_DRDY

GPIO4

SPI_OUT

GPIO2

GPIO3

BIAS_ELEC

REF_ELEC

BIAS_ELEC

REF_ELEC

C24

1uF

R75

10K

9

AVSS

10

11

12

13

14

15

16

31

SPI_CLK

SPI_CS

SPI_CLK

SPI_CS

CLK

SPI_START

SPI_IN

START

DIN

DGND

SPI_START

SPI_IN

JP19

DVDD

C97 AVDD

1uF

C11

1uF

OSC1

VDD

AGND

4

3

1

2

E/D

JP8

R25

SRB1

SRB2

DVDD

0

C98

NI

2

Output GND

R14

0

JP7

6

U4_6

R6

10K

R7

10K

R13

U4_3

3

CLK

JP18

AVDD

HC735-2.048MHZ

0

U4

OPA376

AGND

C6

C16

C7

NI

C19

NI

C8

NI

C15

NI

C99

VREFP

C95

0.1uF

/RESET

GPIO1

VREFP

/RESET

GPIO1

EXT_CLK

1uF

0.1uF

C10

1uF AVSS

/PWDN

DAISY_IN

TP3

/PWDN

DAISY_IN

10uF

AVSS

AGND

C1

JP5

1uF

AVDD

DVDD

AVSS

J5

C33

NI

C9

C2

AGND

C4

C14

C17

1uF

C18

C12

C5

TP1

TP2

TP11

TP12

2

4

6

8

10

1

3

5

7

9

100uF

1uF

AVSS

1uF

0.1uF

1uF

GPIO4

GPIO3

/PWDN

DAISY_IN

AGND

AVSS

AGND

NI

AGND

Figure 59. ADS1299EEG-FC Schematic

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Bill of Materials, Layouts and Schematics

R80

AIN8N

4.99K

C80

4.7nF

AGND

C81

4.7nF

4.99K

AIN8P

R81

R82

AIN7N

4.99K

C82

4.7nF

AGND

C83

4.7nF

4.99K

AIN7P

R83

R84

AIN6N

4.99K

C84

4.7nF

AGND

C85

4.7nF

4.99K

AIN6P

R85

R86

AIN5N

R12

4.99K

J6

4.99K

C86

BIAS_SHD

1

2

4

6

8

10

4.7nF

AIN1

3

5

7

9

AGND

1

C87

4.7nF

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

4.99K

AIN5P

R87

AGND

R88

AIN4N

4.99K

C88

4.7nF

AGND

C89

4.7nF

4.99K

AIN4P

R89

36PIN_IDC

R90

AIN3N

4.99K

C90

4.7nF

AGND

JP25

C91

4.7nF

1

3

5

2

4

6

R10

4.99K

BIAS_ELEC

REF_ELEC

4.99K

AIN3P

R91

R11

4.99K

R92

AIN2N

4.99K

C92

C75

4.7nF

AGND

JP81 Setting

C93

4.7nF

AGND

1) External Input Short to VCM

Jumper on (1-2), (3-4)

4.99K

AIN2P

R93

2) Ain+ to VCM, VCM drives SRB1

Jumper on (3-4), (5-6)

R94

AIN1N

3) Ain- to VCM and Ain+ to SMA

Jumper on (1-2)

4.99K

C72

4.7nF

4) Ain+ signal through header, VCM drives SRB1

Jumper on (5-6)

AGND

C73

4.7nF

VCM: DC Bias from BIAS_ELEC

4.99K

AIN1P

R95

Figure 60. ADS1299EEG-FC Jumper Schematic

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Bill of Materials, Layouts and Schematics

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C48

1uF

TP4

VCC_5v

U6

OUT

L1

L2

2

1

IN

VCC_-5v

3.3uH

C45

C46

C47

1uF

C49

1uF

C50

C51

10uF

AGND

TPS60403

AGND

TP5

+5.0V

JP2

AVDD

C57

0.1uF

TP13

U9

IN

L5

1

3

5

+2.5V

OUT

3.3uH

C58

1uF

C59

C60

C61

2.2uF

10uF

EN

R56

AGND

NI

AGND

2

4

GND

NR/FB

C62

1uF

TPS73225

AGND

R57

NI

AGND

TP6

U8

IN

VCC_-5v

C63

L4

2

3

5

-2.5V

OUT

3.3uH

C64

C65

C66

JP20

AVSS

2.2uF

AGND

2.2uF

10uF

EN

R52

NI

AGND

1

4

GND

NR/FB

TPS72325

C67

0.01uF

AGND

R53

NI

AGND

Figure 61. ECG Power Supplies

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Bill of Materials, Layouts and Schematics

R50

C40

AVDD

NI

C41 NI

AGND

U3

NI

2

3

U5

JP3

NI

R51

NI

6

VREFP

R49

NI

AVDD

1

2

3

4

N/C

R47

NI

R48

NI

6

5

VIN

OUT

C35

NI

TEMP

GND

C34

C38

NI

C39

NI

C42 NI

TRIM

NI

C43

NI

AVSS

AGND

AVSS

Figure 62. External Reference Drivers (Not Installed)

DVDD

C71

C70

100uF

0.1uF

R67

10K

AGND

J4

J2

JP23

CLKSEL

2

4

6

8

10

1

3

5

7

9

TP9

VCC_1.8V

J3

TP7

1

2

4

6

8

10

1

2

4

6

8

10

JP24

3

5

7

9

JP21

VCC_5v

SPI_CLK

3

5

7

9

JP4

TP10

VCC_3.3V

SPI_CS

GPIO1

/RESET

TP8

C68

100uF

C69

0.1uF

11 12

13 14

15 16

17 18

19 20

SPI_IN

11 12

13 14

15 16

17 18

19 20

GPIO2

SPI_OUT

SPI_DRDY

EXT_CLK

VCC_3.3V

C94

0.1uF

VCC_3.3V

U10

8

6

5

7

1

2

3

4

R68

R69

R70

Dummy Connector

NI

JP22

VCC

SCL

SDA

WP

A0

A1

A2

GND

SPI_START

SCL

AGND

SDA

R74

0

24AA256-I/ST

R71 R72 R73

0

AGND

NOTE: Populate J2, J3, and J4 female connectors from the bottom

Figure 63. ECG MDK Board Interface Adapter

9.2 Printed Circuit Board Layout

Figure 64 through Figure 69 show the ADS1299EEG-FE PCB layout.

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Figure 64. ADS1299EEG-FE Top Assembly

Figure 65. ADS1299EEG-FE Top Layer

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Bill of Materials, Layouts and Schematics

Figure 66. ADS1299EEG-FE Internal Layer (1)

Figure 67. ADS1299EEG-FE Internal Layer (2)

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Figure 68. ADS1299EEG-FE Bottom Layer

Figure 69. ADS1299EEG-FE Bottom Assembly

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9.4 ADS1299EEG-FE Power-Supply Recommendations

Figure 70 shows a +6V power-supply cable (not provided in the EVM kit) connected to a battery pack with

four 1.5V batteries connected in series. Connecting to a wall-powered source (provided in the EVM kit)

makes the ADS1299EEG-FE more susceptible to 50Hz/60Hz noise pickup; therefore, for best

performance, it is recommended to power the ADS1299EEG-FE with a battery source. This configuration

minimizes the amount of noise pickup seen at the digitized output of the ADS1299.

Figure 70. Recommended Power Supply for ADS1299EEG-FE

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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS

Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims

arising from the handling or use of the goods.

Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from

the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO

BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF

MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH

ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL

DAMAGES.

Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This

notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety

programs, please visit www.ti.com/esh or contact TI.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or

combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and

therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,

software performance, or infringement of patents or services described herein.

REGULATORY COMPLIANCE INFORMATION

As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal

Communications Commission (FCC) and Industry Canada (IC) rules.

For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,

DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer

use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing

devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency

interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will

be required to take whatever measures may be required to correct this interference.

General Statement for EVMs including a radio

User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and

power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local

laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this

radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and

unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory

authorities, which is responsibility of user including its acceptable authorization.

For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant

Caution

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause

harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the

equipment.

FCC Interference Statement for Class A EVM devices

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial

environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the

instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to

cause harmful interference in which case the user will be required to correct the interference at his own expense.

FCC Interference Statement for Class B EVM devices

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment

generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause

harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If

this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and

on, the user is encouraged to try to correct the interference by one or more of the following measures:

•

Reorient or relocate the receiving antenna.

Increase the separation between the equipment and receiver.

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help.

For EVMs annotated as IC – INDUSTRY CANADA Compliant

This Class A or B digital apparatus complies with Canadian ICES-003.

Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the

equipment.

Concerning EVMs including radio transmitters

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this

device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired

operation of the device.

Concerning EVMs including detachable antennas

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain

approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should

be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.

This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum

permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain

greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.

Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de

l'utilisateur pour actionner l'équipement.

Concernant les EVMs avec appareils radio

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est

autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout

brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain

maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à

l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente

(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.

Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel

d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans

cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.

SPACER

【Important Notice for Users of this Product in Japan】

This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan

If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:

1. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and

Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of

Japan,

2. Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this

product, or

3. Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with

respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note

that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.

Texas Instruments Japan Limited

(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan

http://www.tij.co.jp

【ご使用にあたっての注】

本開発キットは技術基準適合証明を受けておりません。

本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。

1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。

2. 実験局の免許を取得後ご使用いただく。

3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

ꢀꢀꢀ上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。

日本テキサス・インスツルメンツ株式会社

東京都新宿区西新宿６丁目２４番１号

西新宿三井ビル

http://www.tij.co.jp

SPACER

EVALUATION BOARD/KIT/MODULE (EVM)

WARNINGS, RESTRICTIONS AND DISCLAIMERS

For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished

electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in

laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks

associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end

product.

Your Sole Responsibility and Risk. You acknowledge, represent and agree that:

1. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug

Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,

affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.

2. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable

regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,

contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)

between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to

minimize the risk of electrical shock hazard.

3. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even

if the EVM should fail to perform as described or expected.

4. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.

Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the

user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and

environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact

a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the

specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or

interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the

load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures

greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include

but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the

EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please

be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable

in electronic measurement and diagnostics normally found in development environments should use these EVMs.

Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives

harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in

connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims

arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.

Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such

as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices

which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate

Assurance and Indemnity Agreement.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265